2 * ARM mach-virt emulation
4 * Copyright (c) 2013 Linaro Limited
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
18 * Emulate a virtual board which works by passing Linux all the information
19 * it needs about what devices are present via the device tree.
20 * There are some restrictions about what we can do here:
21 * + we can only present devices whose Linux drivers will work based
22 * purely on the device tree with no platform data at all
23 * + we want to present a very stripped-down minimalist platform,
24 * both because this reduces the security attack surface from the guest
25 * and also because it reduces our exposure to being broken when
26 * the kernel updates its device tree bindings and requires further
27 * information in a device binding that we aren't providing.
28 * This is essentially the same approach kvmtool uses.
31 #include "qemu/osdep.h"
32 #include "qapi/error.h"
33 #include "hw/sysbus.h"
34 #include "hw/arm/arm.h"
35 #include "hw/arm/primecell.h"
36 #include "hw/arm/virt.h"
37 #include "hw/devices.h"
39 #include "sysemu/block-backend.h"
40 #include "sysemu/device_tree.h"
41 #include "sysemu/numa.h"
42 #include "sysemu/sysemu.h"
43 #include "sysemu/kvm.h"
44 #include "hw/boards.h"
45 #include "hw/compat.h"
46 #include "hw/loader.h"
47 #include "exec/address-spaces.h"
48 #include "qemu/bitops.h"
49 #include "qemu/error-report.h"
50 #include "hw/pci-host/gpex.h"
51 #include "hw/arm/virt-acpi-build.h"
52 #include "hw/arm/sysbus-fdt.h"
53 #include "hw/platform-bus.h"
54 #include "hw/arm/fdt.h"
55 #include "hw/intc/arm_gic.h"
56 #include "hw/intc/arm_gicv3_common.h"
58 #include "hw/smbios/smbios.h"
59 #include "qapi/visitor.h"
60 #include "standard-headers/linux/input.h"
62 /* Number of external interrupt lines to configure the GIC with */
65 #define PLATFORM_BUS_NUM_IRQS 64
67 static ARMPlatformBusSystemParams platform_bus_params
;
71 bool disallow_affinity_adjustment
;
81 struct arm_boot_info bootinfo
;
82 const MemMapEntry
*memmap
;
87 uint32_t clock_phandle
;
93 #define TYPE_VIRT_MACHINE MACHINE_TYPE_NAME("virt")
94 #define VIRT_MACHINE(obj) \
95 OBJECT_CHECK(VirtMachineState, (obj), TYPE_VIRT_MACHINE)
96 #define VIRT_MACHINE_GET_CLASS(obj) \
97 OBJECT_GET_CLASS(VirtMachineClass, obj, TYPE_VIRT_MACHINE)
98 #define VIRT_MACHINE_CLASS(klass) \
99 OBJECT_CLASS_CHECK(VirtMachineClass, klass, TYPE_VIRT_MACHINE)
102 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
103 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
106 MachineClass *mc = MACHINE_CLASS(oc); \
107 virt_machine_##major##_##minor##_options(mc); \
108 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \
110 mc->alias = "virt"; \
113 static const TypeInfo machvirt_##major##_##minor##_info = { \
114 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
115 .parent = TYPE_VIRT_MACHINE, \
116 .instance_init = virt_##major##_##minor##_instance_init, \
117 .class_init = virt_##major##_##minor##_class_init, \
119 static void machvirt_machine_##major##_##minor##_init(void) \
121 type_register_static(&machvirt_##major##_##minor##_info); \
123 type_init(machvirt_machine_##major##_##minor##_init);
125 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
126 DEFINE_VIRT_MACHINE_LATEST(major, minor, true)
127 #define DEFINE_VIRT_MACHINE(major, minor) \
128 DEFINE_VIRT_MACHINE_LATEST(major, minor, false)
131 /* RAM limit in GB. Since VIRT_MEM starts at the 1GB mark, this means
132 * RAM can go up to the 256GB mark, leaving 256GB of the physical
133 * address space unallocated and free for future use between 256G and 512G.
134 * If we need to provide more RAM to VMs in the future then we need to:
135 * * allocate a second bank of RAM starting at 2TB and working up
136 * * fix the DT and ACPI table generation code in QEMU to correctly
137 * report two split lumps of RAM to the guest
138 * * fix KVM in the host kernel to allow guests with >40 bit address spaces
139 * (We don't want to fill all the way up to 512GB with RAM because
140 * we might want it for non-RAM purposes later. Conversely it seems
141 * reasonable to assume that anybody configuring a VM with a quarter
142 * of a terabyte of RAM will be doing it on a host with more than a
143 * terabyte of physical address space.)
145 #define RAMLIMIT_GB 255
146 #define RAMLIMIT_BYTES (RAMLIMIT_GB * 1024ULL * 1024 * 1024)
148 /* Addresses and sizes of our components.
149 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
150 * 128MB..256MB is used for miscellaneous device I/O.
151 * 256MB..1GB is reserved for possible future PCI support (ie where the
152 * PCI memory window will go if we add a PCI host controller).
153 * 1GB and up is RAM (which may happily spill over into the
154 * high memory region beyond 4GB).
155 * This represents a compromise between how much RAM can be given to
156 * a 32 bit VM and leaving space for expansion and in particular for PCI.
157 * Note that devices should generally be placed at multiples of 0x10000,
158 * to accommodate guests using 64K pages.
160 static const MemMapEntry a15memmap
[] = {
161 /* Space up to 0x8000000 is reserved for a boot ROM */
162 [VIRT_FLASH
] = { 0, 0x08000000 },
163 [VIRT_CPUPERIPHS
] = { 0x08000000, 0x00020000 },
164 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
165 [VIRT_GIC_DIST
] = { 0x08000000, 0x00010000 },
166 [VIRT_GIC_CPU
] = { 0x08010000, 0x00010000 },
167 [VIRT_GIC_V2M
] = { 0x08020000, 0x00001000 },
168 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
169 [VIRT_GIC_ITS
] = { 0x08080000, 0x00020000 },
170 /* This redistributor space allows up to 2*64kB*123 CPUs */
171 [VIRT_GIC_REDIST
] = { 0x080A0000, 0x00F60000 },
172 [VIRT_UART
] = { 0x09000000, 0x00001000 },
173 [VIRT_RTC
] = { 0x09010000, 0x00001000 },
174 [VIRT_FW_CFG
] = { 0x09020000, 0x00000018 },
175 [VIRT_GPIO
] = { 0x09030000, 0x00001000 },
176 [VIRT_SECURE_UART
] = { 0x09040000, 0x00001000 },
177 [VIRT_MMIO
] = { 0x0a000000, 0x00000200 },
178 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
179 [VIRT_PLATFORM_BUS
] = { 0x0c000000, 0x02000000 },
180 [VIRT_SECURE_MEM
] = { 0x0e000000, 0x01000000 },
181 [VIRT_PCIE_MMIO
] = { 0x10000000, 0x2eff0000 },
182 [VIRT_PCIE_PIO
] = { 0x3eff0000, 0x00010000 },
183 [VIRT_PCIE_ECAM
] = { 0x3f000000, 0x01000000 },
184 [VIRT_MEM
] = { 0x40000000, RAMLIMIT_BYTES
},
185 /* Second PCIe window, 512GB wide at the 512GB boundary */
186 [VIRT_PCIE_MMIO_HIGH
] = { 0x8000000000ULL
, 0x8000000000ULL
},
189 static const int a15irqmap
[] = {
192 [VIRT_PCIE
] = 3, /* ... to 6 */
194 [VIRT_SECURE_UART
] = 8,
195 [VIRT_MMIO
] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
196 [VIRT_GIC_V2M
] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
197 [VIRT_PLATFORM_BUS
] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
200 static const char *valid_cpus
[] = {
208 static bool cpuname_valid(const char *cpu
)
212 for (i
= 0; i
< ARRAY_SIZE(valid_cpus
); i
++) {
213 if (strcmp(cpu
, valid_cpus
[i
]) == 0) {
220 static void create_fdt(VirtMachineState
*vms
)
222 void *fdt
= create_device_tree(&vms
->fdt_size
);
225 error_report("create_device_tree() failed");
232 qemu_fdt_setprop_string(fdt
, "/", "compatible", "linux,dummy-virt");
233 qemu_fdt_setprop_cell(fdt
, "/", "#address-cells", 0x2);
234 qemu_fdt_setprop_cell(fdt
, "/", "#size-cells", 0x2);
237 * /chosen and /memory nodes must exist for load_dtb
238 * to fill in necessary properties later
240 qemu_fdt_add_subnode(fdt
, "/chosen");
241 qemu_fdt_add_subnode(fdt
, "/memory");
242 qemu_fdt_setprop_string(fdt
, "/memory", "device_type", "memory");
244 /* Clock node, for the benefit of the UART. The kernel device tree
245 * binding documentation claims the PL011 node clock properties are
246 * optional but in practice if you omit them the kernel refuses to
247 * probe for the device.
249 vms
->clock_phandle
= qemu_fdt_alloc_phandle(fdt
);
250 qemu_fdt_add_subnode(fdt
, "/apb-pclk");
251 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "compatible", "fixed-clock");
252 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "#clock-cells", 0x0);
253 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "clock-frequency", 24000000);
254 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "clock-output-names",
256 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "phandle", vms
->clock_phandle
);
260 static void fdt_add_psci_node(const VirtMachineState
*vms
)
262 uint32_t cpu_suspend_fn
;
266 void *fdt
= vms
->fdt
;
267 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(0));
269 if (!vms
->using_psci
) {
273 qemu_fdt_add_subnode(fdt
, "/psci");
274 if (armcpu
->psci_version
== 2) {
275 const char comp
[] = "arm,psci-0.2\0arm,psci";
276 qemu_fdt_setprop(fdt
, "/psci", "compatible", comp
, sizeof(comp
));
278 cpu_off_fn
= QEMU_PSCI_0_2_FN_CPU_OFF
;
279 if (arm_feature(&armcpu
->env
, ARM_FEATURE_AARCH64
)) {
280 cpu_suspend_fn
= QEMU_PSCI_0_2_FN64_CPU_SUSPEND
;
281 cpu_on_fn
= QEMU_PSCI_0_2_FN64_CPU_ON
;
282 migrate_fn
= QEMU_PSCI_0_2_FN64_MIGRATE
;
284 cpu_suspend_fn
= QEMU_PSCI_0_2_FN_CPU_SUSPEND
;
285 cpu_on_fn
= QEMU_PSCI_0_2_FN_CPU_ON
;
286 migrate_fn
= QEMU_PSCI_0_2_FN_MIGRATE
;
289 qemu_fdt_setprop_string(fdt
, "/psci", "compatible", "arm,psci");
291 cpu_suspend_fn
= QEMU_PSCI_0_1_FN_CPU_SUSPEND
;
292 cpu_off_fn
= QEMU_PSCI_0_1_FN_CPU_OFF
;
293 cpu_on_fn
= QEMU_PSCI_0_1_FN_CPU_ON
;
294 migrate_fn
= QEMU_PSCI_0_1_FN_MIGRATE
;
297 /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer
298 * to the instruction that should be used to invoke PSCI functions.
299 * However, the device tree binding uses 'method' instead, so that is
300 * what we should use here.
302 qemu_fdt_setprop_string(fdt
, "/psci", "method", "hvc");
304 qemu_fdt_setprop_cell(fdt
, "/psci", "cpu_suspend", cpu_suspend_fn
);
305 qemu_fdt_setprop_cell(fdt
, "/psci", "cpu_off", cpu_off_fn
);
306 qemu_fdt_setprop_cell(fdt
, "/psci", "cpu_on", cpu_on_fn
);
307 qemu_fdt_setprop_cell(fdt
, "/psci", "migrate", migrate_fn
);
310 static void fdt_add_timer_nodes(const VirtMachineState
*vms
, int gictype
)
312 /* Note that on A15 h/w these interrupts are level-triggered,
313 * but for the GIC implementation provided by both QEMU and KVM
314 * they are edge-triggered.
317 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
;
320 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
321 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
322 (1 << vms
->smp_cpus
) - 1);
325 qemu_fdt_add_subnode(vms
->fdt
, "/timer");
327 armcpu
= ARM_CPU(qemu_get_cpu(0));
328 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
329 const char compat
[] = "arm,armv8-timer\0arm,armv7-timer";
330 qemu_fdt_setprop(vms
->fdt
, "/timer", "compatible",
331 compat
, sizeof(compat
));
333 qemu_fdt_setprop_string(vms
->fdt
, "/timer", "compatible",
336 qemu_fdt_setprop(vms
->fdt
, "/timer", "always-on", NULL
, 0);
337 qemu_fdt_setprop_cells(vms
->fdt
, "/timer", "interrupts",
338 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_S_EL1_IRQ
, irqflags
,
339 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL1_IRQ
, irqflags
,
340 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_VIRT_IRQ
, irqflags
,
341 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL2_IRQ
, irqflags
);
344 static void fdt_add_cpu_nodes(const VirtMachineState
*vms
)
351 * From Documentation/devicetree/bindings/arm/cpus.txt
352 * On ARM v8 64-bit systems value should be set to 2,
353 * that corresponds to the MPIDR_EL1 register size.
354 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
355 * in the system, #address-cells can be set to 1, since
356 * MPIDR_EL1[63:32] bits are not used for CPUs
359 * Here we actually don't know whether our system is 32- or 64-bit one.
360 * The simplest way to go is to examine affinity IDs of all our CPUs. If
361 * at least one of them has Aff3 populated, we set #address-cells to 2.
363 for (cpu
= 0; cpu
< vms
->smp_cpus
; cpu
++) {
364 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
366 if (armcpu
->mp_affinity
& ARM_AFF3_MASK
) {
372 qemu_fdt_add_subnode(vms
->fdt
, "/cpus");
373 qemu_fdt_setprop_cell(vms
->fdt
, "/cpus", "#address-cells", addr_cells
);
374 qemu_fdt_setprop_cell(vms
->fdt
, "/cpus", "#size-cells", 0x0);
376 for (cpu
= vms
->smp_cpus
- 1; cpu
>= 0; cpu
--) {
377 char *nodename
= g_strdup_printf("/cpus/cpu@%d", cpu
);
378 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
380 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
381 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "device_type", "cpu");
382 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible",
383 armcpu
->dtb_compatible
);
385 if (vms
->using_psci
&& vms
->smp_cpus
> 1) {
386 qemu_fdt_setprop_string(vms
->fdt
, nodename
,
387 "enable-method", "psci");
390 if (addr_cells
== 2) {
391 qemu_fdt_setprop_u64(vms
->fdt
, nodename
, "reg",
392 armcpu
->mp_affinity
);
394 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "reg",
395 armcpu
->mp_affinity
);
398 i
= numa_get_node_for_cpu(cpu
);
399 if (i
< nb_numa_nodes
) {
400 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "numa-node-id", i
);
407 static void fdt_add_its_gic_node(VirtMachineState
*vms
)
409 vms
->msi_phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
410 qemu_fdt_add_subnode(vms
->fdt
, "/intc/its");
411 qemu_fdt_setprop_string(vms
->fdt
, "/intc/its", "compatible",
413 qemu_fdt_setprop(vms
->fdt
, "/intc/its", "msi-controller", NULL
, 0);
414 qemu_fdt_setprop_sized_cells(vms
->fdt
, "/intc/its", "reg",
415 2, vms
->memmap
[VIRT_GIC_ITS
].base
,
416 2, vms
->memmap
[VIRT_GIC_ITS
].size
);
417 qemu_fdt_setprop_cell(vms
->fdt
, "/intc/its", "phandle", vms
->msi_phandle
);
420 static void fdt_add_v2m_gic_node(VirtMachineState
*vms
)
422 vms
->msi_phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
423 qemu_fdt_add_subnode(vms
->fdt
, "/intc/v2m");
424 qemu_fdt_setprop_string(vms
->fdt
, "/intc/v2m", "compatible",
425 "arm,gic-v2m-frame");
426 qemu_fdt_setprop(vms
->fdt
, "/intc/v2m", "msi-controller", NULL
, 0);
427 qemu_fdt_setprop_sized_cells(vms
->fdt
, "/intc/v2m", "reg",
428 2, vms
->memmap
[VIRT_GIC_V2M
].base
,
429 2, vms
->memmap
[VIRT_GIC_V2M
].size
);
430 qemu_fdt_setprop_cell(vms
->fdt
, "/intc/v2m", "phandle", vms
->msi_phandle
);
433 static void fdt_add_gic_node(VirtMachineState
*vms
, int type
)
435 vms
->gic_phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
436 qemu_fdt_setprop_cell(vms
->fdt
, "/", "interrupt-parent", vms
->gic_phandle
);
438 qemu_fdt_add_subnode(vms
->fdt
, "/intc");
439 qemu_fdt_setprop_cell(vms
->fdt
, "/intc", "#interrupt-cells", 3);
440 qemu_fdt_setprop(vms
->fdt
, "/intc", "interrupt-controller", NULL
, 0);
441 qemu_fdt_setprop_cell(vms
->fdt
, "/intc", "#address-cells", 0x2);
442 qemu_fdt_setprop_cell(vms
->fdt
, "/intc", "#size-cells", 0x2);
443 qemu_fdt_setprop(vms
->fdt
, "/intc", "ranges", NULL
, 0);
445 qemu_fdt_setprop_string(vms
->fdt
, "/intc", "compatible",
447 qemu_fdt_setprop_sized_cells(vms
->fdt
, "/intc", "reg",
448 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
449 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
450 2, vms
->memmap
[VIRT_GIC_REDIST
].base
,
451 2, vms
->memmap
[VIRT_GIC_REDIST
].size
);
453 /* 'cortex-a15-gic' means 'GIC v2' */
454 qemu_fdt_setprop_string(vms
->fdt
, "/intc", "compatible",
455 "arm,cortex-a15-gic");
456 qemu_fdt_setprop_sized_cells(vms
->fdt
, "/intc", "reg",
457 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
458 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
459 2, vms
->memmap
[VIRT_GIC_CPU
].base
,
460 2, vms
->memmap
[VIRT_GIC_CPU
].size
);
463 qemu_fdt_setprop_cell(vms
->fdt
, "/intc", "phandle", vms
->gic_phandle
);
466 static void fdt_add_pmu_nodes(const VirtMachineState
*vms
, int gictype
)
470 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
473 armcpu
= ARM_CPU(cpu
);
474 if (!arm_feature(&armcpu
->env
, ARM_FEATURE_PMU
) ||
475 !kvm_arm_pmu_create(cpu
, PPI(VIRTUAL_PMU_IRQ
))) {
481 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
482 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
483 (1 << vms
->smp_cpus
) - 1);
486 armcpu
= ARM_CPU(qemu_get_cpu(0));
487 qemu_fdt_add_subnode(vms
->fdt
, "/pmu");
488 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
489 const char compat
[] = "arm,armv8-pmuv3";
490 qemu_fdt_setprop(vms
->fdt
, "/pmu", "compatible",
491 compat
, sizeof(compat
));
492 qemu_fdt_setprop_cells(vms
->fdt
, "/pmu", "interrupts",
493 GIC_FDT_IRQ_TYPE_PPI
, VIRTUAL_PMU_IRQ
, irqflags
);
497 static void create_its(VirtMachineState
*vms
, DeviceState
*gicdev
)
499 const char *itsclass
= its_class_name();
503 /* Do nothing if not supported */
507 dev
= qdev_create(NULL
, itsclass
);
509 object_property_set_link(OBJECT(dev
), OBJECT(gicdev
), "parent-gicv3",
511 qdev_init_nofail(dev
);
512 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_GIC_ITS
].base
);
514 fdt_add_its_gic_node(vms
);
517 static void create_v2m(VirtMachineState
*vms
, qemu_irq
*pic
)
520 int irq
= vms
->irqmap
[VIRT_GIC_V2M
];
523 dev
= qdev_create(NULL
, "arm-gicv2m");
524 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_GIC_V2M
].base
);
525 qdev_prop_set_uint32(dev
, "base-spi", irq
);
526 qdev_prop_set_uint32(dev
, "num-spi", NUM_GICV2M_SPIS
);
527 qdev_init_nofail(dev
);
529 for (i
= 0; i
< NUM_GICV2M_SPIS
; i
++) {
530 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
, pic
[irq
+ i
]);
533 fdt_add_v2m_gic_node(vms
);
536 static void create_gic(VirtMachineState
*vms
, qemu_irq
*pic
, int type
,
537 bool secure
, bool no_its
)
539 /* We create a standalone GIC */
541 SysBusDevice
*gicbusdev
;
545 gictype
= (type
== 3) ? gicv3_class_name() : gic_class_name();
547 gicdev
= qdev_create(NULL
, gictype
);
548 qdev_prop_set_uint32(gicdev
, "revision", type
);
549 qdev_prop_set_uint32(gicdev
, "num-cpu", smp_cpus
);
550 /* Note that the num-irq property counts both internal and external
551 * interrupts; there are always 32 of the former (mandated by GIC spec).
553 qdev_prop_set_uint32(gicdev
, "num-irq", NUM_IRQS
+ 32);
554 if (!kvm_irqchip_in_kernel()) {
555 qdev_prop_set_bit(gicdev
, "has-security-extensions", secure
);
557 qdev_init_nofail(gicdev
);
558 gicbusdev
= SYS_BUS_DEVICE(gicdev
);
559 sysbus_mmio_map(gicbusdev
, 0, vms
->memmap
[VIRT_GIC_DIST
].base
);
561 sysbus_mmio_map(gicbusdev
, 1, vms
->memmap
[VIRT_GIC_REDIST
].base
);
563 sysbus_mmio_map(gicbusdev
, 1, vms
->memmap
[VIRT_GIC_CPU
].base
);
566 /* Wire the outputs from each CPU's generic timer to the
567 * appropriate GIC PPI inputs, and the GIC's IRQ output to
568 * the CPU's IRQ input.
570 for (i
= 0; i
< smp_cpus
; i
++) {
571 DeviceState
*cpudev
= DEVICE(qemu_get_cpu(i
));
572 int ppibase
= NUM_IRQS
+ i
* GIC_INTERNAL
+ GIC_NR_SGIS
;
574 /* Mapping from the output timer irq lines from the CPU to the
575 * GIC PPI inputs we use for the virt board.
577 const int timer_irq
[] = {
578 [GTIMER_PHYS
] = ARCH_TIMER_NS_EL1_IRQ
,
579 [GTIMER_VIRT
] = ARCH_TIMER_VIRT_IRQ
,
580 [GTIMER_HYP
] = ARCH_TIMER_NS_EL2_IRQ
,
581 [GTIMER_SEC
] = ARCH_TIMER_S_EL1_IRQ
,
584 for (irq
= 0; irq
< ARRAY_SIZE(timer_irq
); irq
++) {
585 qdev_connect_gpio_out(cpudev
, irq
,
586 qdev_get_gpio_in(gicdev
,
587 ppibase
+ timer_irq
[irq
]));
590 sysbus_connect_irq(gicbusdev
, i
, qdev_get_gpio_in(cpudev
, ARM_CPU_IRQ
));
591 sysbus_connect_irq(gicbusdev
, i
+ smp_cpus
,
592 qdev_get_gpio_in(cpudev
, ARM_CPU_FIQ
));
595 for (i
= 0; i
< NUM_IRQS
; i
++) {
596 pic
[i
] = qdev_get_gpio_in(gicdev
, i
);
599 fdt_add_gic_node(vms
, type
);
601 if (type
== 3 && !no_its
) {
602 create_its(vms
, gicdev
);
603 } else if (type
== 2) {
604 create_v2m(vms
, pic
);
608 static void create_uart(const VirtMachineState
*vms
, qemu_irq
*pic
, int uart
,
609 MemoryRegion
*mem
, CharDriverState
*chr
)
612 hwaddr base
= vms
->memmap
[uart
].base
;
613 hwaddr size
= vms
->memmap
[uart
].size
;
614 int irq
= vms
->irqmap
[uart
];
615 const char compat
[] = "arm,pl011\0arm,primecell";
616 const char clocknames
[] = "uartclk\0apb_pclk";
617 DeviceState
*dev
= qdev_create(NULL
, "pl011");
618 SysBusDevice
*s
= SYS_BUS_DEVICE(dev
);
620 qdev_prop_set_chr(dev
, "chardev", chr
);
621 qdev_init_nofail(dev
);
622 memory_region_add_subregion(mem
, base
,
623 sysbus_mmio_get_region(s
, 0));
624 sysbus_connect_irq(s
, 0, pic
[irq
]);
626 nodename
= g_strdup_printf("/pl011@%" PRIx64
, base
);
627 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
628 /* Note that we can't use setprop_string because of the embedded NUL */
629 qemu_fdt_setprop(vms
->fdt
, nodename
, "compatible",
630 compat
, sizeof(compat
));
631 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
633 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
634 GIC_FDT_IRQ_TYPE_SPI
, irq
,
635 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
636 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "clocks",
637 vms
->clock_phandle
, vms
->clock_phandle
);
638 qemu_fdt_setprop(vms
->fdt
, nodename
, "clock-names",
639 clocknames
, sizeof(clocknames
));
641 if (uart
== VIRT_UART
) {
642 qemu_fdt_setprop_string(vms
->fdt
, "/chosen", "stdout-path", nodename
);
644 /* Mark as not usable by the normal world */
645 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "status", "disabled");
646 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "secure-status", "okay");
652 static void create_rtc(const VirtMachineState
*vms
, qemu_irq
*pic
)
655 hwaddr base
= vms
->memmap
[VIRT_RTC
].base
;
656 hwaddr size
= vms
->memmap
[VIRT_RTC
].size
;
657 int irq
= vms
->irqmap
[VIRT_RTC
];
658 const char compat
[] = "arm,pl031\0arm,primecell";
660 sysbus_create_simple("pl031", base
, pic
[irq
]);
662 nodename
= g_strdup_printf("/pl031@%" PRIx64
, base
);
663 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
664 qemu_fdt_setprop(vms
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
665 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
667 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
668 GIC_FDT_IRQ_TYPE_SPI
, irq
,
669 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
670 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "clocks", vms
->clock_phandle
);
671 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "clock-names", "apb_pclk");
675 static DeviceState
*gpio_key_dev
;
676 static void virt_powerdown_req(Notifier
*n
, void *opaque
)
678 /* use gpio Pin 3 for power button event */
679 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev
, 0), 1);
682 static Notifier virt_system_powerdown_notifier
= {
683 .notify
= virt_powerdown_req
686 static void create_gpio(const VirtMachineState
*vms
, qemu_irq
*pic
)
689 DeviceState
*pl061_dev
;
690 hwaddr base
= vms
->memmap
[VIRT_GPIO
].base
;
691 hwaddr size
= vms
->memmap
[VIRT_GPIO
].size
;
692 int irq
= vms
->irqmap
[VIRT_GPIO
];
693 const char compat
[] = "arm,pl061\0arm,primecell";
695 pl061_dev
= sysbus_create_simple("pl061", base
, pic
[irq
]);
697 uint32_t phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
698 nodename
= g_strdup_printf("/pl061@%" PRIx64
, base
);
699 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
700 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
702 qemu_fdt_setprop(vms
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
703 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#gpio-cells", 2);
704 qemu_fdt_setprop(vms
->fdt
, nodename
, "gpio-controller", NULL
, 0);
705 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
706 GIC_FDT_IRQ_TYPE_SPI
, irq
,
707 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
708 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "clocks", vms
->clock_phandle
);
709 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "clock-names", "apb_pclk");
710 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "phandle", phandle
);
712 gpio_key_dev
= sysbus_create_simple("gpio-key", -1,
713 qdev_get_gpio_in(pl061_dev
, 3));
714 qemu_fdt_add_subnode(vms
->fdt
, "/gpio-keys");
715 qemu_fdt_setprop_string(vms
->fdt
, "/gpio-keys", "compatible", "gpio-keys");
716 qemu_fdt_setprop_cell(vms
->fdt
, "/gpio-keys", "#size-cells", 0);
717 qemu_fdt_setprop_cell(vms
->fdt
, "/gpio-keys", "#address-cells", 1);
719 qemu_fdt_add_subnode(vms
->fdt
, "/gpio-keys/poweroff");
720 qemu_fdt_setprop_string(vms
->fdt
, "/gpio-keys/poweroff",
721 "label", "GPIO Key Poweroff");
722 qemu_fdt_setprop_cell(vms
->fdt
, "/gpio-keys/poweroff", "linux,code",
724 qemu_fdt_setprop_cells(vms
->fdt
, "/gpio-keys/poweroff",
725 "gpios", phandle
, 3, 0);
727 /* connect powerdown request */
728 qemu_register_powerdown_notifier(&virt_system_powerdown_notifier
);
733 static void create_virtio_devices(const VirtMachineState
*vms
, qemu_irq
*pic
)
736 hwaddr size
= vms
->memmap
[VIRT_MMIO
].size
;
738 /* We create the transports in forwards order. Since qbus_realize()
739 * prepends (not appends) new child buses, the incrementing loop below will
740 * create a list of virtio-mmio buses with decreasing base addresses.
742 * When a -device option is processed from the command line,
743 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
744 * order. The upshot is that -device options in increasing command line
745 * order are mapped to virtio-mmio buses with decreasing base addresses.
747 * When this code was originally written, that arrangement ensured that the
748 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
749 * the first -device on the command line. (The end-to-end order is a
750 * function of this loop, qbus_realize(), qbus_find_recursive(), and the
751 * guest kernel's name-to-address assignment strategy.)
753 * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
754 * the message, if not necessarily the code, of commit 70161ff336.
755 * Therefore the loop now establishes the inverse of the original intent.
757 * Unfortunately, we can't counteract the kernel change by reversing the
758 * loop; it would break existing command lines.
760 * In any case, the kernel makes no guarantee about the stability of
761 * enumeration order of virtio devices (as demonstrated by it changing
762 * between kernel versions). For reliable and stable identification
763 * of disks users must use UUIDs or similar mechanisms.
765 for (i
= 0; i
< NUM_VIRTIO_TRANSPORTS
; i
++) {
766 int irq
= vms
->irqmap
[VIRT_MMIO
] + i
;
767 hwaddr base
= vms
->memmap
[VIRT_MMIO
].base
+ i
* size
;
769 sysbus_create_simple("virtio-mmio", base
, pic
[irq
]);
772 /* We add dtb nodes in reverse order so that they appear in the finished
773 * device tree lowest address first.
775 * Note that this mapping is independent of the loop above. The previous
776 * loop influences virtio device to virtio transport assignment, whereas
777 * this loop controls how virtio transports are laid out in the dtb.
779 for (i
= NUM_VIRTIO_TRANSPORTS
- 1; i
>= 0; i
--) {
781 int irq
= vms
->irqmap
[VIRT_MMIO
] + i
;
782 hwaddr base
= vms
->memmap
[VIRT_MMIO
].base
+ i
* size
;
784 nodename
= g_strdup_printf("/virtio_mmio@%" PRIx64
, base
);
785 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
786 qemu_fdt_setprop_string(vms
->fdt
, nodename
,
787 "compatible", "virtio,mmio");
788 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
790 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
791 GIC_FDT_IRQ_TYPE_SPI
, irq
,
792 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
797 static void create_one_flash(const char *name
, hwaddr flashbase
,
798 hwaddr flashsize
, const char *file
,
799 MemoryRegion
*sysmem
)
801 /* Create and map a single flash device. We use the same
802 * parameters as the flash devices on the Versatile Express board.
804 DriveInfo
*dinfo
= drive_get_next(IF_PFLASH
);
805 DeviceState
*dev
= qdev_create(NULL
, "cfi.pflash01");
806 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
807 const uint64_t sectorlength
= 256 * 1024;
810 qdev_prop_set_drive(dev
, "drive", blk_by_legacy_dinfo(dinfo
),
814 qdev_prop_set_uint32(dev
, "num-blocks", flashsize
/ sectorlength
);
815 qdev_prop_set_uint64(dev
, "sector-length", sectorlength
);
816 qdev_prop_set_uint8(dev
, "width", 4);
817 qdev_prop_set_uint8(dev
, "device-width", 2);
818 qdev_prop_set_bit(dev
, "big-endian", false);
819 qdev_prop_set_uint16(dev
, "id0", 0x89);
820 qdev_prop_set_uint16(dev
, "id1", 0x18);
821 qdev_prop_set_uint16(dev
, "id2", 0x00);
822 qdev_prop_set_uint16(dev
, "id3", 0x00);
823 qdev_prop_set_string(dev
, "name", name
);
824 qdev_init_nofail(dev
);
826 memory_region_add_subregion(sysmem
, flashbase
,
827 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0));
833 if (drive_get(IF_PFLASH
, 0, 0)) {
834 error_report("The contents of the first flash device may be "
835 "specified with -bios or with -drive if=pflash... "
836 "but you cannot use both options at once");
839 fn
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, file
);
841 error_report("Could not find ROM image '%s'", file
);
844 image_size
= load_image_mr(fn
, sysbus_mmio_get_region(sbd
, 0));
846 if (image_size
< 0) {
847 error_report("Could not load ROM image '%s'", file
);
853 static void create_flash(const VirtMachineState
*vms
,
854 MemoryRegion
*sysmem
,
855 MemoryRegion
*secure_sysmem
)
857 /* Create two flash devices to fill the VIRT_FLASH space in the memmap.
858 * Any file passed via -bios goes in the first of these.
859 * sysmem is the system memory space. secure_sysmem is the secure view
860 * of the system, and the first flash device should be made visible only
861 * there. The second flash device is visible to both secure and nonsecure.
862 * If sysmem == secure_sysmem this means there is no separate Secure
863 * address space and both flash devices are generally visible.
865 hwaddr flashsize
= vms
->memmap
[VIRT_FLASH
].size
/ 2;
866 hwaddr flashbase
= vms
->memmap
[VIRT_FLASH
].base
;
869 create_one_flash("virt.flash0", flashbase
, flashsize
,
870 bios_name
, secure_sysmem
);
871 create_one_flash("virt.flash1", flashbase
+ flashsize
, flashsize
,
874 if (sysmem
== secure_sysmem
) {
875 /* Report both flash devices as a single node in the DT */
876 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
877 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
878 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible", "cfi-flash");
879 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
880 2, flashbase
, 2, flashsize
,
881 2, flashbase
+ flashsize
, 2, flashsize
);
882 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "bank-width", 4);
885 /* Report the devices as separate nodes so we can mark one as
886 * only visible to the secure world.
888 nodename
= g_strdup_printf("/secflash@%" PRIx64
, flashbase
);
889 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
890 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible", "cfi-flash");
891 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
892 2, flashbase
, 2, flashsize
);
893 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "bank-width", 4);
894 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "status", "disabled");
895 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "secure-status", "okay");
898 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
899 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
900 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible", "cfi-flash");
901 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
902 2, flashbase
+ flashsize
, 2, flashsize
);
903 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "bank-width", 4);
908 static void create_fw_cfg(const VirtMachineState
*vms
, AddressSpace
*as
)
910 hwaddr base
= vms
->memmap
[VIRT_FW_CFG
].base
;
911 hwaddr size
= vms
->memmap
[VIRT_FW_CFG
].size
;
915 fw_cfg
= fw_cfg_init_mem_wide(base
+ 8, base
, 8, base
+ 16, as
);
916 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, (uint16_t)smp_cpus
);
918 nodename
= g_strdup_printf("/fw-cfg@%" PRIx64
, base
);
919 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
920 qemu_fdt_setprop_string(vms
->fdt
, nodename
,
921 "compatible", "qemu,fw-cfg-mmio");
922 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
927 static void create_pcie_irq_map(const VirtMachineState
*vms
,
928 uint32_t gic_phandle
,
929 int first_irq
, const char *nodename
)
932 uint32_t full_irq_map
[4 * 4 * 10] = { 0 };
933 uint32_t *irq_map
= full_irq_map
;
935 for (devfn
= 0; devfn
<= 0x18; devfn
+= 0x8) {
936 for (pin
= 0; pin
< 4; pin
++) {
937 int irq_type
= GIC_FDT_IRQ_TYPE_SPI
;
938 int irq_nr
= first_irq
+ ((pin
+ PCI_SLOT(devfn
)) % PCI_NUM_PINS
);
939 int irq_level
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
943 devfn
<< 8, 0, 0, /* devfn */
944 pin
+ 1, /* PCI pin */
945 gic_phandle
, 0, 0, irq_type
, irq_nr
, irq_level
}; /* GIC irq */
947 /* Convert map to big endian */
948 for (i
= 0; i
< 10; i
++) {
949 irq_map
[i
] = cpu_to_be32(map
[i
]);
955 qemu_fdt_setprop(vms
->fdt
, nodename
, "interrupt-map",
956 full_irq_map
, sizeof(full_irq_map
));
958 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupt-map-mask",
959 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */
963 static void create_pcie(const VirtMachineState
*vms
, qemu_irq
*pic
,
966 hwaddr base_mmio
= vms
->memmap
[VIRT_PCIE_MMIO
].base
;
967 hwaddr size_mmio
= vms
->memmap
[VIRT_PCIE_MMIO
].size
;
968 hwaddr base_mmio_high
= vms
->memmap
[VIRT_PCIE_MMIO_HIGH
].base
;
969 hwaddr size_mmio_high
= vms
->memmap
[VIRT_PCIE_MMIO_HIGH
].size
;
970 hwaddr base_pio
= vms
->memmap
[VIRT_PCIE_PIO
].base
;
971 hwaddr size_pio
= vms
->memmap
[VIRT_PCIE_PIO
].size
;
972 hwaddr base_ecam
= vms
->memmap
[VIRT_PCIE_ECAM
].base
;
973 hwaddr size_ecam
= vms
->memmap
[VIRT_PCIE_ECAM
].size
;
974 hwaddr base
= base_mmio
;
975 int nr_pcie_buses
= size_ecam
/ PCIE_MMCFG_SIZE_MIN
;
976 int irq
= vms
->irqmap
[VIRT_PCIE
];
977 MemoryRegion
*mmio_alias
;
978 MemoryRegion
*mmio_reg
;
979 MemoryRegion
*ecam_alias
;
980 MemoryRegion
*ecam_reg
;
986 dev
= qdev_create(NULL
, TYPE_GPEX_HOST
);
987 qdev_init_nofail(dev
);
989 /* Map only the first size_ecam bytes of ECAM space */
990 ecam_alias
= g_new0(MemoryRegion
, 1);
991 ecam_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0);
992 memory_region_init_alias(ecam_alias
, OBJECT(dev
), "pcie-ecam",
993 ecam_reg
, 0, size_ecam
);
994 memory_region_add_subregion(get_system_memory(), base_ecam
, ecam_alias
);
996 /* Map the MMIO window into system address space so as to expose
997 * the section of PCI MMIO space which starts at the same base address
998 * (ie 1:1 mapping for that part of PCI MMIO space visible through
1001 mmio_alias
= g_new0(MemoryRegion
, 1);
1002 mmio_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 1);
1003 memory_region_init_alias(mmio_alias
, OBJECT(dev
), "pcie-mmio",
1004 mmio_reg
, base_mmio
, size_mmio
);
1005 memory_region_add_subregion(get_system_memory(), base_mmio
, mmio_alias
);
1008 /* Map high MMIO space */
1009 MemoryRegion
*high_mmio_alias
= g_new0(MemoryRegion
, 1);
1011 memory_region_init_alias(high_mmio_alias
, OBJECT(dev
), "pcie-mmio-high",
1012 mmio_reg
, base_mmio_high
, size_mmio_high
);
1013 memory_region_add_subregion(get_system_memory(), base_mmio_high
,
1017 /* Map IO port space */
1018 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 2, base_pio
);
1020 for (i
= 0; i
< GPEX_NUM_IRQS
; i
++) {
1021 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
, pic
[irq
+ i
]);
1024 pci
= PCI_HOST_BRIDGE(dev
);
1026 for (i
= 0; i
< nb_nics
; i
++) {
1027 NICInfo
*nd
= &nd_table
[i
];
1030 nd
->model
= g_strdup("virtio");
1033 pci_nic_init_nofail(nd
, pci
->bus
, nd
->model
, NULL
);
1037 nodename
= g_strdup_printf("/pcie@%" PRIx64
, base
);
1038 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
1039 qemu_fdt_setprop_string(vms
->fdt
, nodename
,
1040 "compatible", "pci-host-ecam-generic");
1041 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "device_type", "pci");
1042 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#address-cells", 3);
1043 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#size-cells", 2);
1044 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "bus-range", 0,
1046 qemu_fdt_setprop(vms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1048 if (vms
->msi_phandle
) {
1049 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "msi-parent",
1053 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
1054 2, base_ecam
, 2, size_ecam
);
1057 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "ranges",
1058 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1059 2, base_pio
, 2, size_pio
,
1060 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1061 2, base_mmio
, 2, size_mmio
,
1062 1, FDT_PCI_RANGE_MMIO_64BIT
,
1064 2, base_mmio_high
, 2, size_mmio_high
);
1066 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "ranges",
1067 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1068 2, base_pio
, 2, size_pio
,
1069 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1070 2, base_mmio
, 2, size_mmio
);
1073 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#interrupt-cells", 1);
1074 create_pcie_irq_map(vms
, vms
->gic_phandle
, irq
, nodename
);
1079 static void create_platform_bus(VirtMachineState
*vms
, qemu_irq
*pic
)
1084 ARMPlatformBusFDTParams
*fdt_params
= g_new(ARMPlatformBusFDTParams
, 1);
1085 MemoryRegion
*sysmem
= get_system_memory();
1087 platform_bus_params
.platform_bus_base
= vms
->memmap
[VIRT_PLATFORM_BUS
].base
;
1088 platform_bus_params
.platform_bus_size
= vms
->memmap
[VIRT_PLATFORM_BUS
].size
;
1089 platform_bus_params
.platform_bus_first_irq
= vms
->irqmap
[VIRT_PLATFORM_BUS
];
1090 platform_bus_params
.platform_bus_num_irqs
= PLATFORM_BUS_NUM_IRQS
;
1092 fdt_params
->system_params
= &platform_bus_params
;
1093 fdt_params
->binfo
= &vms
->bootinfo
;
1094 fdt_params
->intc
= "/intc";
1096 * register a machine init done notifier that creates the device tree
1097 * nodes of the platform bus and its children dynamic sysbus devices
1099 arm_register_platform_bus_fdt_creator(fdt_params
);
1101 dev
= qdev_create(NULL
, TYPE_PLATFORM_BUS_DEVICE
);
1102 dev
->id
= TYPE_PLATFORM_BUS_DEVICE
;
1103 qdev_prop_set_uint32(dev
, "num_irqs",
1104 platform_bus_params
.platform_bus_num_irqs
);
1105 qdev_prop_set_uint32(dev
, "mmio_size",
1106 platform_bus_params
.platform_bus_size
);
1107 qdev_init_nofail(dev
);
1108 s
= SYS_BUS_DEVICE(dev
);
1110 for (i
= 0; i
< platform_bus_params
.platform_bus_num_irqs
; i
++) {
1111 int irqn
= platform_bus_params
.platform_bus_first_irq
+ i
;
1112 sysbus_connect_irq(s
, i
, pic
[irqn
]);
1115 memory_region_add_subregion(sysmem
,
1116 platform_bus_params
.platform_bus_base
,
1117 sysbus_mmio_get_region(s
, 0));
1120 static void create_secure_ram(VirtMachineState
*vms
,
1121 MemoryRegion
*secure_sysmem
)
1123 MemoryRegion
*secram
= g_new(MemoryRegion
, 1);
1125 hwaddr base
= vms
->memmap
[VIRT_SECURE_MEM
].base
;
1126 hwaddr size
= vms
->memmap
[VIRT_SECURE_MEM
].size
;
1128 memory_region_init_ram(secram
, NULL
, "virt.secure-ram", size
, &error_fatal
);
1129 vmstate_register_ram_global(secram
);
1130 memory_region_add_subregion(secure_sysmem
, base
, secram
);
1132 nodename
= g_strdup_printf("/secram@%" PRIx64
, base
);
1133 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
1134 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "device_type", "memory");
1135 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg", 2, base
, 2, size
);
1136 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "status", "disabled");
1137 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "secure-status", "okay");
1142 static void *machvirt_dtb(const struct arm_boot_info
*binfo
, int *fdt_size
)
1144 const VirtMachineState
*board
= container_of(binfo
, VirtMachineState
,
1147 *fdt_size
= board
->fdt_size
;
1151 static void virt_build_smbios(VirtGuestInfo
*guest_info
)
1153 FWCfgState
*fw_cfg
= guest_info
->fw_cfg
;
1154 uint8_t *smbios_tables
, *smbios_anchor
;
1155 size_t smbios_tables_len
, smbios_anchor_len
;
1156 const char *product
= "QEMU Virtual Machine";
1162 if (kvm_enabled()) {
1163 product
= "KVM Virtual Machine";
1166 smbios_set_defaults("QEMU", product
,
1167 "1.0", false, true, SMBIOS_ENTRY_POINT_30
);
1169 smbios_get_tables(NULL
, 0, &smbios_tables
, &smbios_tables_len
,
1170 &smbios_anchor
, &smbios_anchor_len
);
1172 if (smbios_anchor
) {
1173 fw_cfg_add_file(fw_cfg
, "etc/smbios/smbios-tables",
1174 smbios_tables
, smbios_tables_len
);
1175 fw_cfg_add_file(fw_cfg
, "etc/smbios/smbios-anchor",
1176 smbios_anchor
, smbios_anchor_len
);
1181 void virt_guest_info_machine_done(Notifier
*notifier
, void *data
)
1183 VirtGuestInfoState
*guest_info_state
= container_of(notifier
,
1184 VirtGuestInfoState
, machine_done
);
1185 virt_acpi_setup(&guest_info_state
->info
);
1186 virt_build_smbios(&guest_info_state
->info
);
1189 static void machvirt_init(MachineState
*machine
)
1191 VirtMachineState
*vms
= VIRT_MACHINE(machine
);
1192 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(machine
);
1193 qemu_irq pic
[NUM_IRQS
];
1194 MemoryRegion
*sysmem
= get_system_memory();
1195 MemoryRegion
*secure_sysmem
= NULL
;
1196 int gic_version
= vms
->gic_version
;
1197 int n
, virt_max_cpus
;
1198 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
1199 const char *cpu_model
= machine
->cpu_model
;
1200 VirtGuestInfoState
*guest_info_state
= g_malloc0(sizeof *guest_info_state
);
1201 VirtGuestInfo
*guest_info
= &guest_info_state
->info
;
1204 const char *typename
;
1207 bool firmware_loaded
= bios_name
|| drive_get(IF_PFLASH
, 0, 0);
1211 cpu_model
= "cortex-a15";
1214 /* We can probe only here because during property set
1215 * KVM is not available yet
1218 if (!kvm_enabled()) {
1219 error_report("gic-version=host requires KVM");
1223 gic_version
= kvm_arm_vgic_probe();
1225 error_report("Unable to determine GIC version supported by host");
1230 /* Separate the actual CPU model name from any appended features */
1231 cpustr
= g_strsplit(cpu_model
, ",", 2);
1233 if (!cpuname_valid(cpustr
[0])) {
1234 error_report("mach-virt: CPU %s not supported", cpustr
[0]);
1238 /* If we have an EL3 boot ROM then the assumption is that it will
1239 * implement PSCI itself, so disable QEMU's internal implementation
1240 * so it doesn't get in the way. Instead of starting secondary
1241 * CPUs in PSCI powerdown state we will start them all running and
1242 * let the boot ROM sort them out.
1243 * The usual case is that we do use QEMU's PSCI implementation.
1245 vms
->using_psci
= !(vms
->secure
&& firmware_loaded
);
1247 /* The maximum number of CPUs depends on the GIC version, or on how
1248 * many redistributors we can fit into the memory map.
1250 if (gic_version
== 3) {
1251 virt_max_cpus
= vms
->memmap
[VIRT_GIC_REDIST
].size
/ 0x20000;
1252 clustersz
= GICV3_TARGETLIST_BITS
;
1254 virt_max_cpus
= GIC_NCPU
;
1255 clustersz
= GIC_TARGETLIST_BITS
;
1258 if (max_cpus
> virt_max_cpus
) {
1259 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
1260 "supported by machine 'mach-virt' (%d)",
1261 max_cpus
, virt_max_cpus
);
1265 vms
->smp_cpus
= smp_cpus
;
1267 if (machine
->ram_size
> vms
->memmap
[VIRT_MEM
].size
) {
1268 error_report("mach-virt: cannot model more than %dGB RAM", RAMLIMIT_GB
);
1273 if (kvm_enabled()) {
1274 error_report("mach-virt: KVM does not support Security extensions");
1278 /* The Secure view of the world is the same as the NonSecure,
1279 * but with a few extra devices. Create it as a container region
1280 * containing the system memory at low priority; any secure-only
1281 * devices go in at higher priority and take precedence.
1283 secure_sysmem
= g_new(MemoryRegion
, 1);
1284 memory_region_init(secure_sysmem
, OBJECT(machine
), "secure-memory",
1286 memory_region_add_subregion_overlap(secure_sysmem
, 0, sysmem
, -1);
1291 oc
= cpu_class_by_name(TYPE_ARM_CPU
, cpustr
[0]);
1293 error_report("Unable to find CPU definition");
1296 typename
= object_class_get_name(oc
);
1298 /* convert -smp CPU options specified by the user into global props */
1300 cc
->parse_features(typename
, cpustr
[1], &err
);
1303 error_report_err(err
);
1307 for (n
= 0; n
< smp_cpus
; n
++) {
1308 Object
*cpuobj
= object_new(typename
);
1309 if (!vmc
->disallow_affinity_adjustment
) {
1310 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the
1311 * GIC's target-list limitations. 32-bit KVM hosts currently
1312 * always create clusters of 4 CPUs, but that is expected to
1313 * change when they gain support for gicv3. When KVM is enabled
1314 * it will override the changes we make here, therefore our
1315 * purposes are to make TCG consistent (with 64-bit KVM hosts)
1316 * and to improve SGI efficiency.
1318 uint8_t aff1
= n
/ clustersz
;
1319 uint8_t aff0
= n
% clustersz
;
1320 object_property_set_int(cpuobj
, (aff1
<< ARM_AFF1_SHIFT
) | aff0
,
1321 "mp-affinity", NULL
);
1325 object_property_set_bool(cpuobj
, false, "has_el3", NULL
);
1328 if (vms
->using_psci
) {
1329 object_property_set_int(cpuobj
, QEMU_PSCI_CONDUIT_HVC
,
1330 "psci-conduit", NULL
);
1332 /* Secondary CPUs start in PSCI powered-down state */
1334 object_property_set_bool(cpuobj
, true,
1335 "start-powered-off", NULL
);
1339 if (vmc
->no_pmu
&& object_property_find(cpuobj
, "pmu", NULL
)) {
1340 object_property_set_bool(cpuobj
, false, "pmu", NULL
);
1343 if (object_property_find(cpuobj
, "reset-cbar", NULL
)) {
1344 object_property_set_int(cpuobj
, vms
->memmap
[VIRT_CPUPERIPHS
].base
,
1345 "reset-cbar", &error_abort
);
1348 object_property_set_link(cpuobj
, OBJECT(sysmem
), "memory",
1351 object_property_set_link(cpuobj
, OBJECT(secure_sysmem
),
1352 "secure-memory", &error_abort
);
1355 object_property_set_bool(cpuobj
, true, "realized", NULL
);
1357 fdt_add_timer_nodes(vms
, gic_version
);
1358 fdt_add_cpu_nodes(vms
);
1359 fdt_add_psci_node(vms
);
1361 memory_region_allocate_system_memory(ram
, NULL
, "mach-virt.ram",
1363 memory_region_add_subregion(sysmem
, vms
->memmap
[VIRT_MEM
].base
, ram
);
1365 create_flash(vms
, sysmem
, secure_sysmem
? secure_sysmem
: sysmem
);
1367 create_gic(vms
, pic
, gic_version
, vms
->secure
, vmc
->no_its
);
1369 fdt_add_pmu_nodes(vms
, gic_version
);
1371 create_uart(vms
, pic
, VIRT_UART
, sysmem
, serial_hds
[0]);
1374 create_secure_ram(vms
, secure_sysmem
);
1375 create_uart(vms
, pic
, VIRT_SECURE_UART
, secure_sysmem
, serial_hds
[1]);
1378 create_rtc(vms
, pic
);
1380 create_pcie(vms
, pic
, vms
->highmem
);
1382 create_gpio(vms
, pic
);
1384 /* Create mmio transports, so the user can create virtio backends
1385 * (which will be automatically plugged in to the transports). If
1386 * no backend is created the transport will just sit harmlessly idle.
1388 create_virtio_devices(vms
, pic
);
1390 create_fw_cfg(vms
, &address_space_memory
);
1391 rom_set_fw(fw_cfg_find());
1393 guest_info
->smp_cpus
= smp_cpus
;
1394 guest_info
->fw_cfg
= fw_cfg_find();
1395 guest_info
->memmap
= vms
->memmap
;
1396 guest_info
->irqmap
= vms
->irqmap
;
1397 guest_info
->use_highmem
= vms
->highmem
;
1398 guest_info
->gic_version
= gic_version
;
1399 guest_info
->no_its
= vmc
->no_its
;
1400 guest_info_state
->machine_done
.notify
= virt_guest_info_machine_done
;
1401 qemu_add_machine_init_done_notifier(&guest_info_state
->machine_done
);
1403 vms
->bootinfo
.ram_size
= machine
->ram_size
;
1404 vms
->bootinfo
.kernel_filename
= machine
->kernel_filename
;
1405 vms
->bootinfo
.kernel_cmdline
= machine
->kernel_cmdline
;
1406 vms
->bootinfo
.initrd_filename
= machine
->initrd_filename
;
1407 vms
->bootinfo
.nb_cpus
= smp_cpus
;
1408 vms
->bootinfo
.board_id
= -1;
1409 vms
->bootinfo
.loader_start
= vms
->memmap
[VIRT_MEM
].base
;
1410 vms
->bootinfo
.get_dtb
= machvirt_dtb
;
1411 vms
->bootinfo
.firmware_loaded
= firmware_loaded
;
1412 arm_load_kernel(ARM_CPU(first_cpu
), &vms
->bootinfo
);
1415 * arm_load_kernel machine init done notifier registration must
1416 * happen before the platform_bus_create call. In this latter,
1417 * another notifier is registered which adds platform bus nodes.
1418 * Notifiers are executed in registration reverse order.
1420 create_platform_bus(vms
, pic
);
1423 static bool virt_get_secure(Object
*obj
, Error
**errp
)
1425 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1430 static void virt_set_secure(Object
*obj
, bool value
, Error
**errp
)
1432 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1434 vms
->secure
= value
;
1437 static bool virt_get_highmem(Object
*obj
, Error
**errp
)
1439 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1441 return vms
->highmem
;
1444 static void virt_set_highmem(Object
*obj
, bool value
, Error
**errp
)
1446 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1448 vms
->highmem
= value
;
1451 static char *virt_get_gic_version(Object
*obj
, Error
**errp
)
1453 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1454 const char *val
= vms
->gic_version
== 3 ? "3" : "2";
1456 return g_strdup(val
);
1459 static void virt_set_gic_version(Object
*obj
, const char *value
, Error
**errp
)
1461 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1463 if (!strcmp(value
, "3")) {
1464 vms
->gic_version
= 3;
1465 } else if (!strcmp(value
, "2")) {
1466 vms
->gic_version
= 2;
1467 } else if (!strcmp(value
, "host")) {
1468 vms
->gic_version
= 0; /* Will probe later */
1470 error_setg(errp
, "Invalid gic-version value");
1471 error_append_hint(errp
, "Valid values are 3, 2, host.\n");
1475 static void virt_machine_class_init(ObjectClass
*oc
, void *data
)
1477 MachineClass
*mc
= MACHINE_CLASS(oc
);
1479 mc
->init
= machvirt_init
;
1480 /* Start max_cpus at the maximum QEMU supports. We'll further restrict
1481 * it later in machvirt_init, where we have more information about the
1482 * configuration of the particular instance.
1485 mc
->has_dynamic_sysbus
= true;
1486 mc
->block_default_type
= IF_VIRTIO
;
1488 mc
->pci_allow_0_address
= true;
1489 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */
1490 mc
->minimum_page_bits
= 12;
1493 static const TypeInfo virt_machine_info
= {
1494 .name
= TYPE_VIRT_MACHINE
,
1495 .parent
= TYPE_MACHINE
,
1497 .instance_size
= sizeof(VirtMachineState
),
1498 .class_size
= sizeof(VirtMachineClass
),
1499 .class_init
= virt_machine_class_init
,
1502 static void machvirt_machine_init(void)
1504 type_register_static(&virt_machine_info
);
1506 type_init(machvirt_machine_init
);
1508 static void virt_2_9_instance_init(Object
*obj
)
1510 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1512 /* EL3 is disabled by default on virt: this makes us consistent
1513 * between KVM and TCG for this board, and it also allows us to
1514 * boot UEFI blobs which assume no TrustZone support.
1516 vms
->secure
= false;
1517 object_property_add_bool(obj
, "secure", virt_get_secure
,
1518 virt_set_secure
, NULL
);
1519 object_property_set_description(obj
, "secure",
1520 "Set on/off to enable/disable the ARM "
1521 "Security Extensions (TrustZone)",
1524 /* High memory is enabled by default */
1525 vms
->highmem
= true;
1526 object_property_add_bool(obj
, "highmem", virt_get_highmem
,
1527 virt_set_highmem
, NULL
);
1528 object_property_set_description(obj
, "highmem",
1529 "Set on/off to enable/disable using "
1530 "physical address space above 32 bits",
1532 /* Default GIC type is v2 */
1533 vms
->gic_version
= 2;
1534 object_property_add_str(obj
, "gic-version", virt_get_gic_version
,
1535 virt_set_gic_version
, NULL
);
1536 object_property_set_description(obj
, "gic-version",
1538 "Valid values are 2, 3 and host", NULL
);
1540 vms
->memmap
= a15memmap
;
1541 vms
->irqmap
= a15irqmap
;
1544 static void virt_machine_2_9_options(MachineClass
*mc
)
1547 DEFINE_VIRT_MACHINE_AS_LATEST(2, 9)
1549 #define VIRT_COMPAT_2_8 \
1552 static void virt_2_8_instance_init(Object
*obj
)
1554 virt_2_9_instance_init(obj
);
1557 static void virt_machine_2_8_options(MachineClass
*mc
)
1559 virt_machine_2_9_options(mc
);
1560 SET_MACHINE_COMPAT(mc
, VIRT_COMPAT_2_8
);
1562 DEFINE_VIRT_MACHINE(2, 8)
1564 #define VIRT_COMPAT_2_7 \
1567 static void virt_2_7_instance_init(Object
*obj
)
1569 virt_2_8_instance_init(obj
);
1572 static void virt_machine_2_7_options(MachineClass
*mc
)
1574 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
1576 virt_machine_2_8_options(mc
);
1577 SET_MACHINE_COMPAT(mc
, VIRT_COMPAT_2_7
);
1578 /* ITS was introduced with 2.8 */
1580 /* Stick with 1K pages for migration compatibility */
1581 mc
->minimum_page_bits
= 0;
1583 DEFINE_VIRT_MACHINE(2, 7)
1585 #define VIRT_COMPAT_2_6 \
1588 static void virt_2_6_instance_init(Object
*obj
)
1590 virt_2_7_instance_init(obj
);
1593 static void virt_machine_2_6_options(MachineClass
*mc
)
1595 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
1597 virt_machine_2_7_options(mc
);
1598 SET_MACHINE_COMPAT(mc
, VIRT_COMPAT_2_6
);
1599 vmc
->disallow_affinity_adjustment
= true;
1600 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */
1603 DEFINE_VIRT_MACHINE(2, 6)