target/riscv/cpu.h

   1 /*
   2  * QEMU RISC-V CPU
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  * Copyright (c) 2017-2018 SiFive, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2 or later, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef RISCV_CPU_H
  21 #define RISCV_CPU_H
  22
  23 #include "hw/core/cpu.h"
  24 #include "exec/cpu-defs.h"
  25 #include "fpu/softfloat-types.h"
  26
  27 #define TCG_GUEST_DEFAULT_MO 0
  28
  29 #define TYPE_RISCV_CPU "riscv-cpu"
  30
  31 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
  32 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
  33 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
  34
  35 #define TYPE_RISCV_CPU_ANY              RISCV_CPU_TYPE_NAME("any")
  36 #define TYPE_RISCV_CPU_BASE32           RISCV_CPU_TYPE_NAME("rv32")
  37 #define TYPE_RISCV_CPU_BASE64           RISCV_CPU_TYPE_NAME("rv64")
  38 #define TYPE_RISCV_CPU_SIFIVE_E31       RISCV_CPU_TYPE_NAME("sifive-e31")
  39 #define TYPE_RISCV_CPU_SIFIVE_E51       RISCV_CPU_TYPE_NAME("sifive-e51")
  40 #define TYPE_RISCV_CPU_SIFIVE_U34       RISCV_CPU_TYPE_NAME("sifive-u34")
  41 #define TYPE_RISCV_CPU_SIFIVE_U54       RISCV_CPU_TYPE_NAME("sifive-u54")
  42 /* Deprecated */
  43 #define TYPE_RISCV_CPU_RV32IMACU_NOMMU  RISCV_CPU_TYPE_NAME("rv32imacu-nommu")
  44 #define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1")
  45 #define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0")
  46 #define TYPE_RISCV_CPU_RV64IMACU_NOMMU  RISCV_CPU_TYPE_NAME("rv64imacu-nommu")
  47 #define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9.1")
  48 #define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0")
  49
  50 #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
  51 #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
  52
  53 #if defined(TARGET_RISCV32)
  54 #define RVXLEN RV32
  55 #elif defined(TARGET_RISCV64)
  56 #define RVXLEN RV64
  57 #endif
  58
  59 #define RV(x) ((target_ulong)1 << (x - 'A'))
  60
  61 #define RVI RV('I')
  62 #define RVE RV('E') /* E and I are mutually exclusive */
  63 #define RVM RV('M')
  64 #define RVA RV('A')
  65 #define RVF RV('F')
  66 #define RVD RV('D')
  67 #define RVC RV('C')
  68 #define RVS RV('S')
  69 #define RVU RV('U')
  70 #define RVH RV('H')
  71
  72 /* S extension denotes that Supervisor mode exists, however it is possible
  73    to have a core that support S mode but does not have an MMU and there
  74    is currently no bit in misa to indicate whether an MMU exists or not
  75    so a cpu features bitfield is required, likewise for optional PMP support */
  76 enum {
  77     RISCV_FEATURE_MMU,
  78     RISCV_FEATURE_PMP,
  79     RISCV_FEATURE_MISA
  80 };
  81
  82 #define PRIV_VERSION_1_09_1 0x00010901
  83 #define PRIV_VERSION_1_10_0 0x00011000
  84 #define PRIV_VERSION_1_11_0 0x00011100
  85
  86 #define TRANSLATE_PMP_FAIL 2
  87 #define TRANSLATE_FAIL 1
  88 #define TRANSLATE_SUCCESS 0
  89 #define MMU_USER_IDX 3
  90
  91 #define MAX_RISCV_PMPS (16)
  92
  93 typedef struct CPURISCVState CPURISCVState;
  94
  95 #include "pmp.h"
  96
  97 struct CPURISCVState {
  98     target_ulong gpr[32];
  99     uint64_t fpr[32]; /* assume both F and D extensions */
 100     target_ulong pc;
 101     target_ulong load_res;
 102     target_ulong load_val;
 103
 104     target_ulong frm;
 105
 106     target_ulong badaddr;
 107
 108     target_ulong priv_ver;
 109     target_ulong misa;
 110     target_ulong misa_mask;
 111
 112     uint32_t features;
 113
 114 #ifdef CONFIG_USER_ONLY
 115     uint32_t elf_flags;
 116 #endif
 117
 118 #ifndef CONFIG_USER_ONLY
 119     target_ulong priv;
 120     /* This contains QEMU specific information about the virt state. */
 121     target_ulong virt;
 122     target_ulong resetvec;
 123
 124     target_ulong mhartid;
 125     target_ulong mstatus;
 126
 127     target_ulong mip;
 128     uint32_t miclaim;
 129
 130     target_ulong mie;
 131     target_ulong mideleg;
 132
 133     target_ulong sptbr;  /* until: priv-1.9.1 */
 134     target_ulong satp;   /* since: priv-1.10.0 */
 135     target_ulong sbadaddr;
 136     target_ulong mbadaddr;
 137     target_ulong medeleg;
 138
 139     target_ulong stvec;
 140     target_ulong sepc;
 141     target_ulong scause;
 142
 143     target_ulong mtvec;
 144     target_ulong mepc;
 145     target_ulong mcause;
 146     target_ulong mtval;  /* since: priv-1.10.0 */
 147
 148     /* Hypervisor CSRs */
 149     target_ulong hstatus;
 150     target_ulong hedeleg;
 151     target_ulong hideleg;
 152     target_ulong hcounteren;
 153     target_ulong htval;
 154     target_ulong htinst;
 155     target_ulong hgatp;
 156
 157     /* Virtual CSRs */
 158     target_ulong vsstatus;
 159     target_ulong vstvec;
 160     target_ulong vsscratch;
 161     target_ulong vsepc;
 162     target_ulong vscause;
 163     target_ulong vstval;
 164     target_ulong vsatp;
 165
 166     target_ulong mtval2;
 167     target_ulong mtinst;
 168
 169     target_ulong scounteren;
 170     target_ulong mcounteren;
 171
 172     target_ulong sscratch;
 173     target_ulong mscratch;
 174
 175     /* temporary htif regs */
 176     uint64_t mfromhost;
 177     uint64_t mtohost;
 178     uint64_t timecmp;
 179
 180     /* physical memory protection */
 181     pmp_table_t pmp_state;
 182
 183     /* True if in debugger mode.  */
 184     bool debugger;
 185 #endif
 186
 187     float_status fp_status;
 188
 189     /* Fields from here on are preserved across CPU reset. */
 190     QEMUTimer *timer; /* Internal timer */
 191 };
 192
 193 #define RISCV_CPU_CLASS(klass) \
 194     OBJECT_CLASS_CHECK(RISCVCPUClass, (klass), TYPE_RISCV_CPU)
 195 #define RISCV_CPU(obj) \
 196     OBJECT_CHECK(RISCVCPU, (obj), TYPE_RISCV_CPU)
 197 #define RISCV_CPU_GET_CLASS(obj) \
 198     OBJECT_GET_CLASS(RISCVCPUClass, (obj), TYPE_RISCV_CPU)
 199
 200 /**
 201  * RISCVCPUClass:
 202  * @parent_realize: The parent class' realize handler.
 203  * @parent_reset: The parent class' reset handler.
 204  *
 205  * A RISCV CPU model.
 206  */
 207 typedef struct RISCVCPUClass {
 208     /*< private >*/
 209     CPUClass parent_class;
 210     /*< public >*/
 211     DeviceRealize parent_realize;
 212     void (*parent_reset)(CPUState *cpu);
 213 } RISCVCPUClass;
 214
 215 /**
 216  * RISCVCPU:
 217  * @env: #CPURISCVState
 218  *
 219  * A RISCV CPU.
 220  */
 221 typedef struct RISCVCPU {
 222     /*< private >*/
 223     CPUState parent_obj;
 224     /*< public >*/
 225     CPUNegativeOffsetState neg;
 226     CPURISCVState env;
 227
 228     /* Configuration Settings */
 229     struct {
 230         bool ext_i;
 231         bool ext_e;
 232         bool ext_g;
 233         bool ext_m;
 234         bool ext_a;
 235         bool ext_f;
 236         bool ext_d;
 237         bool ext_c;
 238         bool ext_s;
 239         bool ext_u;
 240         bool ext_counters;
 241         bool ext_ifencei;
 242         bool ext_icsr;
 243
 244         char *priv_spec;
 245         char *user_spec;
 246         bool mmu;
 247         bool pmp;
 248     } cfg;
 249 } RISCVCPU;
 250
 251 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
 252 {
 253     return (env->misa & ext) != 0;
 254 }
 255
 256 static inline bool riscv_feature(CPURISCVState *env, int feature)
 257 {
 258     return env->features & (1ULL << feature);
 259 }
 260
 261 #include "cpu_user.h"
 262 #include "cpu_bits.h"
 263
 264 extern const char * const riscv_int_regnames[];
 265 extern const char * const riscv_fpr_regnames[];
 266 extern const char * const riscv_excp_names[];
 267 extern const char * const riscv_intr_names[];
 268
 269 void riscv_cpu_do_interrupt(CPUState *cpu);
 270 int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
 271 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 272 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
 273 bool riscv_cpu_fp_enabled(CPURISCVState *env);
 274 bool riscv_cpu_virt_enabled(CPURISCVState *env);
 275 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
 276 bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env);
 277 void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable);
 278 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
 279 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 280 void  riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
 281                                     MMUAccessType access_type, int mmu_idx,
 282                                     uintptr_t retaddr);
 283 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 284                         MMUAccessType access_type, int mmu_idx,
 285                         bool probe, uintptr_t retaddr);
 286 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
 287                                      vaddr addr, unsigned size,
 288                                      MMUAccessType access_type,
 289                                      int mmu_idx, MemTxAttrs attrs,
 290                                      MemTxResult response, uintptr_t retaddr);
 291 char *riscv_isa_string(RISCVCPU *cpu);
 292 void riscv_cpu_list(void);
 293
 294 #define cpu_signal_handler riscv_cpu_signal_handler
 295 #define cpu_list riscv_cpu_list
 296 #define cpu_mmu_index riscv_cpu_mmu_index
 297
 298 #ifndef CONFIG_USER_ONLY
 299 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts);
 300 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
 301 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
 302 #endif
 303 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
 304
 305 void riscv_translate_init(void);
 306 int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
 307 void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
 308                                          uint32_t exception, uintptr_t pc);
 309
 310 target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
 311 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
 312
 313 #define TB_FLAGS_MMU_MASK   3
 314 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS
 315
 316 static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
 317                                         target_ulong *cs_base, uint32_t *flags)
 318 {
 319     *pc = env->pc;
 320     *cs_base = 0;
 321 #ifdef CONFIG_USER_ONLY
 322     *flags = TB_FLAGS_MSTATUS_FS;
 323 #else
 324     *flags = cpu_mmu_index(env, 0) | (env->mstatus & MSTATUS_FS);
 325 #endif
 326 }
 327
 328 int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
 329                 target_ulong new_value, target_ulong write_mask);
 330 int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value,
 331                       target_ulong new_value, target_ulong write_mask);
 332
 333 static inline void riscv_csr_write(CPURISCVState *env, int csrno,
 334                                    target_ulong val)
 335 {
 336     riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS));
 337 }
 338
 339 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
 340 {
 341     target_ulong val = 0;
 342     riscv_csrrw(env, csrno, &val, 0, 0);
 343     return val;
 344 }
 345
 346 typedef int (*riscv_csr_predicate_fn)(CPURISCVState *env, int csrno);
 347 typedef int (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,
 348     target_ulong *ret_value);
 349 typedef int (*riscv_csr_write_fn)(CPURISCVState *env, int csrno,
 350     target_ulong new_value);
 351 typedef int (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
 352     target_ulong *ret_value, target_ulong new_value, target_ulong write_mask);
 353
 354 typedef struct {
 355     riscv_csr_predicate_fn predicate;
 356     riscv_csr_read_fn read;
 357     riscv_csr_write_fn write;
 358     riscv_csr_op_fn op;
 359 } riscv_csr_operations;
 360
 361 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
 362 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
 363
 364 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
 365
 366 typedef CPURISCVState CPUArchState;
 367 typedef RISCVCPU ArchCPU;
 368
 369 #include "exec/cpu-all.h"
 370
 371 #endif /* RISCV_CPU_H */