hw/arm/xlnx-zynqmp.c

   1 /*
   2  * Xilinx Zynq MPSoC emulation
   3  *
   4  * Copyright (C) 2015 Xilinx Inc
   5  * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  15  * for more details.
  16  */
  17
  18 #include "qemu/osdep.h"
  19 #include "qapi/error.h"
  20 #include "qemu-common.h"
  21 #include "cpu.h"
  22 #include "hw/arm/xlnx-zynqmp.h"
  23 #include "hw/intc/arm_gic_common.h"
  24 #include "exec/address-spaces.h"
  25 #include "sysemu/kvm.h"
  26 #include "kvm_arm.h"
  27
  28 #define GIC_NUM_SPI_INTR 160
  29
  30 #define ARM_PHYS_TIMER_PPI  30
  31 #define ARM_VIRT_TIMER_PPI  27
  32
  33 #define GEM_REVISION        0x40070106
  34
  35 #define GIC_BASE_ADDR       0xf9000000
  36 #define GIC_DIST_ADDR       0xf9010000
  37 #define GIC_CPU_ADDR        0xf9020000
  38
  39 #define SATA_INTR           133
  40 #define SATA_ADDR           0xFD0C0000
  41 #define SATA_NUM_PORTS      2
  42
  43 #define QSPI_ADDR           0xff0f0000
  44 #define LQSPI_ADDR          0xc0000000
  45 #define QSPI_IRQ            15
  46
  47 #define DP_ADDR             0xfd4a0000
  48 #define DP_IRQ              113
  49
  50 #define DPDMA_ADDR          0xfd4c0000
  51 #define DPDMA_IRQ           116
  52
  53 #define IPI_ADDR            0xFF300000
  54 #define IPI_IRQ             64
  55
  56 #define RTC_ADDR            0xffa60000
  57 #define RTC_IRQ             26
  58
  59 #define SDHCI_CAPABILITIES  0x280737ec6481 /* Datasheet: UG1085 (v1.7) */
  60
  61 static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
  62     0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
  63 };
  64
  65 static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = {
  66     57, 59, 61, 63,
  67 };
  68
  69 static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = {
  70     0xFF000000, 0xFF010000,
  71 };
  72
  73 static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
  74     21, 22,
  75 };
  76
  77 static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = {
  78     0xFF160000, 0xFF170000,
  79 };
  80
  81 static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = {
  82     48, 49,
  83 };
  84
  85 static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = {
  86     0xFF040000, 0xFF050000,
  87 };
  88
  89 static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = {
  90     19, 20,
  91 };
  92
  93 static const uint64_t gdma_ch_addr[XLNX_ZYNQMP_NUM_GDMA_CH] = {
  94     0xFD500000, 0xFD510000, 0xFD520000, 0xFD530000,
  95     0xFD540000, 0xFD550000, 0xFD560000, 0xFD570000
  96 };
  97
  98 static const int gdma_ch_intr[XLNX_ZYNQMP_NUM_GDMA_CH] = {
  99     124, 125, 126, 127, 128, 129, 130, 131
 100 };
 101
 102 static const uint64_t adma_ch_addr[XLNX_ZYNQMP_NUM_ADMA_CH] = {
 103     0xFFA80000, 0xFFA90000, 0xFFAA0000, 0xFFAB0000,
 104     0xFFAC0000, 0xFFAD0000, 0xFFAE0000, 0xFFAF0000
 105 };
 106
 107 static const int adma_ch_intr[XLNX_ZYNQMP_NUM_ADMA_CH] = {
 108     77, 78, 79, 80, 81, 82, 83, 84
 109 };
 110
 111 typedef struct XlnxZynqMPGICRegion {
 112     int region_index;
 113     uint32_t address;
 114 } XlnxZynqMPGICRegion;
 115
 116 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = {
 117     { .region_index = 0, .address = GIC_DIST_ADDR, },
 118     { .region_index = 1, .address = GIC_CPU_ADDR,  },
 119 };
 120
 121 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
 122 {
 123     return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index;
 124 }
 125
 126 static void xlnx_zynqmp_create_rpu(XlnxZynqMPState *s, const char *boot_cpu,
 127                                    Error **errp)
 128 {
 129     Error *err = NULL;
 130     int i;
 131     int num_rpus = MIN(smp_cpus - XLNX_ZYNQMP_NUM_APU_CPUS, XLNX_ZYNQMP_NUM_RPU_CPUS);
 132
 133     for (i = 0; i < num_rpus; i++) {
 134         char *name;
 135
 136         object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]),
 137                           "cortex-r5f-" TYPE_ARM_CPU);
 138         object_property_add_child(OBJECT(s), "rpu-cpu[*]",
 139                                   OBJECT(&s->rpu_cpu[i]), &error_abort);
 140
 141         name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i]));
 142         if (strcmp(name, boot_cpu)) {
 143             /* Secondary CPUs start in PSCI powered-down state */
 144             object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true,
 145                                      "start-powered-off", &error_abort);
 146         } else {
 147             s->boot_cpu_ptr = &s->rpu_cpu[i];
 148         }
 149         g_free(name);
 150
 151         object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs",
 152                                  &error_abort);
 153         object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "realized",
 154                                  &err);
 155         if (err) {
 156             error_propagate(errp, err);
 157             return;
 158         }
 159     }
 160 }
 161
 162 static void xlnx_zynqmp_init(Object *obj)
 163 {
 164     XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
 165     int i;
 166     int num_apus = MIN(smp_cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
 167
 168     for (i = 0; i < num_apus; i++) {
 169         object_initialize_child(obj, "apu-cpu[*]", &s->apu_cpu[i],
 170                                 sizeof(s->apu_cpu[i]),
 171                                 "cortex-a53-" TYPE_ARM_CPU, &error_abort, NULL);
 172     }
 173
 174     sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic),
 175                           gic_class_name());
 176
 177     for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
 178         sysbus_init_child_obj(obj, "gem[*]", &s->gem[i], sizeof(s->gem[i]),
 179                               TYPE_CADENCE_GEM);
 180     }
 181
 182     for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
 183         sysbus_init_child_obj(obj, "uart[*]", &s->uart[i], sizeof(s->uart[i]),
 184                               TYPE_CADENCE_UART);
 185     }
 186
 187     sysbus_init_child_obj(obj, "sata", &s->sata, sizeof(s->sata),
 188                           TYPE_SYSBUS_AHCI);
 189
 190     for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
 191         sysbus_init_child_obj(obj, "sdhci[*]", &s->sdhci[i],
 192                               sizeof(s->sdhci[i]), TYPE_SYSBUS_SDHCI);
 193     }
 194
 195     for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
 196         sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]),
 197                               TYPE_XILINX_SPIPS);
 198     }
 199
 200     sysbus_init_child_obj(obj, "qspi", &s->qspi, sizeof(s->qspi),
 201                           TYPE_XLNX_ZYNQMP_QSPIPS);
 202
 203     sysbus_init_child_obj(obj, "xxxdp", &s->dp, sizeof(s->dp), TYPE_XLNX_DP);
 204
 205     sysbus_init_child_obj(obj, "dp-dma", &s->dpdma, sizeof(s->dpdma),
 206                           TYPE_XLNX_DPDMA);
 207
 208     sysbus_init_child_obj(obj, "ipi", &s->ipi, sizeof(s->ipi),
 209                           TYPE_XLNX_ZYNQMP_IPI);
 210
 211     sysbus_init_child_obj(obj, "rtc", &s->rtc, sizeof(s->rtc),
 212                           TYPE_XLNX_ZYNQMP_RTC);
 213
 214     for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
 215         sysbus_init_child_obj(obj, "gdma[*]", &s->gdma[i], sizeof(s->gdma[i]),
 216                               TYPE_XLNX_ZDMA);
 217     }
 218
 219     for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) {
 220         sysbus_init_child_obj(obj, "adma[*]", &s->adma[i], sizeof(s->adma[i]),
 221                               TYPE_XLNX_ZDMA);
 222     }
 223 }
 224
 225 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
 226 {
 227     XlnxZynqMPState *s = XLNX_ZYNQMP(dev);
 228     MemoryRegion *system_memory = get_system_memory();
 229     uint8_t i;
 230     uint64_t ram_size;
 231     int num_apus = MIN(smp_cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
 232     const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]";
 233     ram_addr_t ddr_low_size, ddr_high_size;
 234     qemu_irq gic_spi[GIC_NUM_SPI_INTR];
 235     Error *err = NULL;
 236
 237     ram_size = memory_region_size(s->ddr_ram);
 238
 239     /* Create the DDR Memory Regions. User friendly checks should happen at
 240      * the board level
 241      */
 242     if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) {
 243         /* The RAM size is above the maximum available for the low DDR.
 244          * Create the high DDR memory region as well.
 245          */
 246         assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE);
 247         ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
 248         ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
 249
 250         memory_region_init_alias(&s->ddr_ram_high, NULL,
 251                                  "ddr-ram-high", s->ddr_ram,
 252                                   ddr_low_size, ddr_high_size);
 253         memory_region_add_subregion(get_system_memory(),
 254                                     XLNX_ZYNQMP_HIGH_RAM_START,
 255                                     &s->ddr_ram_high);
 256     } else {
 257         /* RAM must be non-zero */
 258         assert(ram_size);
 259         ddr_low_size = ram_size;
 260     }
 261
 262     memory_region_init_alias(&s->ddr_ram_low, NULL,
 263                              "ddr-ram-low", s->ddr_ram,
 264                               0, ddr_low_size);
 265     memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low);
 266
 267     /* Create the four OCM banks */
 268     for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) {
 269         char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i);
 270
 271         memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name,
 272                                XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal);
 273         memory_region_add_subregion(get_system_memory(),
 274                                     XLNX_ZYNQMP_OCM_RAM_0_ADDRESS +
 275                                         i * XLNX_ZYNQMP_OCM_RAM_SIZE,
 276                                     &s->ocm_ram[i]);
 277
 278         g_free(ocm_name);
 279     }
 280
 281     qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
 282     qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
 283     qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus);
 284
 285     /* Realize APUs before realizing the GIC. KVM requires this.  */
 286     for (i = 0; i < num_apus; i++) {
 287         char *name;
 288
 289         object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC,
 290                                 "psci-conduit", &error_abort);
 291
 292         name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i]));
 293         if (strcmp(name, boot_cpu)) {
 294             /* Secondary CPUs start in PSCI powered-down state */
 295             object_property_set_bool(OBJECT(&s->apu_cpu[i]), true,
 296                                      "start-powered-off", &error_abort);
 297         } else {
 298             s->boot_cpu_ptr = &s->apu_cpu[i];
 299         }
 300         g_free(name);
 301
 302         object_property_set_bool(OBJECT(&s->apu_cpu[i]),
 303                                  s->secure, "has_el3", NULL);
 304         object_property_set_bool(OBJECT(&s->apu_cpu[i]),
 305                                  s->virt, "has_el2", NULL);
 306         object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR,
 307                                 "reset-cbar", &error_abort);
 308         object_property_set_int(OBJECT(&s->apu_cpu[i]), num_apus,
 309                                 "core-count", &error_abort);
 310         object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized",
 311                                  &err);
 312         if (err) {
 313             error_propagate(errp, err);
 314             return;
 315         }
 316     }
 317
 318     object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
 319     if (err) {
 320         error_propagate(errp, err);
 321         return;
 322     }
 323
 324     assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS);
 325     for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) {
 326         SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic);
 327         const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i];
 328         MemoryRegion *mr = sysbus_mmio_get_region(gic, r->region_index);
 329         uint32_t addr = r->address;
 330         int j;
 331
 332         sysbus_mmio_map(gic, r->region_index, addr);
 333
 334         for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) {
 335             MemoryRegion *alias = &s->gic_mr[i][j];
 336
 337             addr += XLNX_ZYNQMP_GIC_REGION_SIZE;
 338             memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr,
 339                                      0, XLNX_ZYNQMP_GIC_REGION_SIZE);
 340             memory_region_add_subregion(system_memory, addr, alias);
 341         }
 342     }
 343
 344     for (i = 0; i < num_apus; i++) {
 345         qemu_irq irq;
 346
 347         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
 348                            qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
 349                                             ARM_CPU_IRQ));
 350         irq = qdev_get_gpio_in(DEVICE(&s->gic),
 351                                arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
 352         qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 0, irq);
 353         irq = qdev_get_gpio_in(DEVICE(&s->gic),
 354                                arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
 355         qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 1, irq);
 356     }
 357
 358     if (s->has_rpu) {
 359         info_report("The 'has_rpu' property is no longer required, to use the "
 360                     "RPUs just use -smp 6.");
 361     }
 362
 363     xlnx_zynqmp_create_rpu(s, boot_cpu, &err);
 364     if (err) {
 365         error_propagate(errp, err);
 366         return;
 367     }
 368
 369     if (!s->boot_cpu_ptr) {
 370         error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu);
 371         return;
 372     }
 373
 374     for (i = 0; i < GIC_NUM_SPI_INTR; i++) {
 375         gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i);
 376     }
 377
 378     for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
 379         NICInfo *nd = &nd_table[i];
 380
 381         if (nd->used) {
 382             qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
 383             qdev_set_nic_properties(DEVICE(&s->gem[i]), nd);
 384         }
 385         object_property_set_int(OBJECT(&s->gem[i]), GEM_REVISION, "revision",
 386                                 &error_abort);
 387         object_property_set_int(OBJECT(&s->gem[i]), 2, "num-priority-queues",
 388                                 &error_abort);
 389         object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err);
 390         if (err) {
 391             error_propagate(errp, err);
 392             return;
 393         }
 394         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]);
 395         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0,
 396                            gic_spi[gem_intr[i]]);
 397     }
 398
 399     for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
 400         qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
 401         object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
 402         if (err) {
 403             error_propagate(errp, err);
 404             return;
 405         }
 406         sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]);
 407         sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
 408                            gic_spi[uart_intr[i]]);
 409     }
 410
 411     object_property_set_int(OBJECT(&s->sata), SATA_NUM_PORTS, "num-ports",
 412                             &error_abort);
 413     object_property_set_bool(OBJECT(&s->sata), true, "realized", &err);
 414     if (err) {
 415         error_propagate(errp, err);
 416         return;
 417     }
 418
 419     sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR);
 420     sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);
 421
 422     for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
 423         char *bus_name = g_strdup_printf("sd-bus%d", i);
 424         SysBusDevice *sbd = SYS_BUS_DEVICE(&s->sdhci[i]);
 425         Object *sdhci = OBJECT(&s->sdhci[i]);
 426
 427         /* Compatible with:
 428          * - SD Host Controller Specification Version 3.00
 429          * - SDIO Specification Version 3.0
 430          * - eMMC Specification Version 4.51
 431          */
 432         object_property_set_uint(sdhci, 3, "sd-spec-version", &err);
 433         object_property_set_uint(sdhci, SDHCI_CAPABILITIES, "capareg", &err);
 434         object_property_set_uint(sdhci, UHS_I, "uhs", &err);
 435         object_property_set_bool(sdhci, true, "realized", &err);
 436         if (err) {
 437             error_propagate(errp, err);
 438             return;
 439         }
 440         sysbus_mmio_map(sbd, 0, sdhci_addr[i]);
 441         sysbus_connect_irq(sbd, 0, gic_spi[sdhci_intr[i]]);
 442
 443         /* Alias controller SD bus to the SoC itself */
 444         object_property_add_alias(OBJECT(s), bus_name, sdhci, "sd-bus",
 445                                   &error_abort);
 446         g_free(bus_name);
 447     }
 448
 449     for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
 450         gchar *bus_name;
 451
 452         object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
 453
 454         sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
 455         sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
 456                            gic_spi[spi_intr[i]]);
 457
 458         /* Alias controller SPI bus to the SoC itself */
 459         bus_name = g_strdup_printf("spi%d", i);
 460         object_property_add_alias(OBJECT(s), bus_name,
 461                                   OBJECT(&s->spi[i]), "spi0",
 462                                   &error_abort);
 463         g_free(bus_name);
 464     }
 465
 466     object_property_set_bool(OBJECT(&s->qspi), true, "realized", &err);
 467     sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR);
 468     sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR);
 469     sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0, gic_spi[QSPI_IRQ]);
 470
 471     for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_BUS; i++) {
 472         gchar *bus_name;
 473         gchar *target_bus;
 474
 475         /* Alias controller SPI bus to the SoC itself */
 476         bus_name = g_strdup_printf("qspi%d", i);
 477         target_bus = g_strdup_printf("spi%d", i);
 478         object_property_add_alias(OBJECT(s), bus_name,
 479                                   OBJECT(&s->qspi), target_bus,
 480                                   &error_abort);
 481         g_free(bus_name);
 482         g_free(target_bus);
 483     }
 484
 485     object_property_set_bool(OBJECT(&s->dp), true, "realized", &err);
 486     if (err) {
 487         error_propagate(errp, err);
 488         return;
 489     }
 490     sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR);
 491     sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]);
 492
 493     object_property_set_bool(OBJECT(&s->dpdma), true, "realized", &err);
 494     if (err) {
 495         error_propagate(errp, err);
 496         return;
 497     }
 498     object_property_set_link(OBJECT(&s->dp), OBJECT(&s->dpdma), "dpdma",
 499                              &error_abort);
 500     sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR);
 501     sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]);
 502
 503     object_property_set_bool(OBJECT(&s->ipi), true, "realized", &err);
 504     if (err) {
 505         error_propagate(errp, err);
 506         return;
 507     }
 508     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi), 0, IPI_ADDR);
 509     sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi), 0, gic_spi[IPI_IRQ]);
 510
 511     object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err);
 512     if (err) {
 513         error_propagate(errp, err);
 514         return;
 515     }
 516     sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR);
 517     sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]);
 518
 519     for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
 520         object_property_set_uint(OBJECT(&s->gdma[i]), 128, "bus-width", &err);
 521         object_property_set_bool(OBJECT(&s->gdma[i]), true, "realized", &err);
 522         if (err) {
 523             error_propagate(errp, err);
 524             return;
 525         }
 526
 527         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gdma[i]), 0, gdma_ch_addr[i]);
 528         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gdma[i]), 0,
 529                            gic_spi[gdma_ch_intr[i]]);
 530     }
 531
 532     for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) {
 533         object_property_set_bool(OBJECT(&s->adma[i]), true, "realized", &err);
 534         if (err) {
 535             error_propagate(errp, err);
 536             return;
 537         }
 538
 539         sysbus_mmio_map(SYS_BUS_DEVICE(&s->adma[i]), 0, adma_ch_addr[i]);
 540         sysbus_connect_irq(SYS_BUS_DEVICE(&s->adma[i]), 0,
 541                            gic_spi[adma_ch_intr[i]]);
 542     }
 543 }
 544
 545 static Property xlnx_zynqmp_props[] = {
 546     DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu),
 547     DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false),
 548     DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState, virt, false),
 549     DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false),
 550     DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION,
 551                      MemoryRegion *),
 552     DEFINE_PROP_END_OF_LIST()
 553 };
 554
 555 static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data)
 556 {
 557     DeviceClass *dc = DEVICE_CLASS(oc);
 558
 559     dc->props = xlnx_zynqmp_props;
 560     dc->realize = xlnx_zynqmp_realize;
 561     /* Reason: Uses serial_hd in realize function, thus can't be used twice */
 562     dc->user_creatable = false;
 563 }
 564
 565 static const TypeInfo xlnx_zynqmp_type_info = {
 566     .name = TYPE_XLNX_ZYNQMP,
 567     .parent = TYPE_DEVICE,
 568     .instance_size = sizeof(XlnxZynqMPState),
 569     .instance_init = xlnx_zynqmp_init,
 570     .class_init = xlnx_zynqmp_class_init,
 571 };
 572
 573 static void xlnx_zynqmp_register_types(void)
 574 {
 575     type_register_static(&xlnx_zynqmp_type_info);
 576 }
 577
 578 type_init(xlnx_zynqmp_register_types)