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hw/sd: sd: Bypass the RCA check for CMD13 in SPI mode
[qemu/ar7.git] / hw / block / m25p80.c
blob0412d3e7f4076dbf2c3dafb143abe5dde3e994de
1 /*
2 * ST M25P80 emulator. Emulate all SPI flash devices based on the m25p80 command
3 * set. Known devices table current as of Jun/2012 and taken from linux.
4 * See drivers/mtd/devices/m25p80.c.
5 *
6 * Copyright (C) 2011 Edgar E. Iglesias <edgar.iglesias@gmail.com>
7 * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
8 * Copyright (C) 2012 PetaLogix
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 or
13 * (at your option) a later version of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 */
23
24 #include "qemu/osdep.h"
25 #include "qemu/units.h"
26 #include "sysemu/block-backend.h"
27 #include "hw/qdev-properties.h"
28 #include "hw/qdev-properties-system.h"
29 #include "hw/ssi/ssi.h"
30 #include "migration/vmstate.h"
31 #include "qemu/bitops.h"
32 #include "qemu/log.h"
33 #include "qemu/module.h"
34 #include "qemu/error-report.h"
35 #include "qapi/error.h"
36 #include "trace.h"
37 #include "qom/object.h"
38
39 /* Fields for FlashPartInfo->flags */
40
41 /* erase capabilities */
42 #define ER_4K 1
43 #define ER_32K 2
44 /* set to allow the page program command to write 0s back to 1. Useful for
45 * modelling EEPROM with SPI flash command set
46 */
47 #define EEPROM 0x100
48
49 /* 16 MiB max in 3 byte address mode */
50 #define MAX_3BYTES_SIZE 0x1000000
51
52 #define SPI_NOR_MAX_ID_LEN 6
53
54 typedef struct FlashPartInfo {
55 const char *part_name;
56 /*
57 * This array stores the ID bytes.
58 * The first three bytes are the JEDIC ID.
59 * JEDEC ID zero means "no ID" (mostly older chips).
60 */
61 uint8_t id[SPI_NOR_MAX_ID_LEN];
62 uint8_t id_len;
63 /* there is confusion between manufacturers as to what a sector is. In this
64 * device model, a "sector" is the size that is erased by the ERASE_SECTOR
65 * command (opcode 0xd8).
66 */
67 uint32_t sector_size;
68 uint32_t n_sectors;
69 uint32_t page_size;
70 uint16_t flags;
71 /*
72 * Big sized spi nor are often stacked devices, thus sometime
73 * replace chip erase with die erase.
74 * This field inform how many die is in the chip.
75 */
76 uint8_t die_cnt;
77 } FlashPartInfo;
78
79 /* adapted from linux */
80 /* Used when the "_ext_id" is two bytes at most */
81 #define INFO(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\
82 .part_name = _part_name,\
83 .id = {\
84 ((_jedec_id) >> 16) & 0xff,\
85 ((_jedec_id) >> 8) & 0xff,\
86 (_jedec_id) & 0xff,\
87 ((_ext_id) >> 8) & 0xff,\
88 (_ext_id) & 0xff,\
89 },\
90 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\
91 .sector_size = (_sector_size),\
92 .n_sectors = (_n_sectors),\
93 .page_size = 256,\
94 .flags = (_flags),\
95 .die_cnt = 0
96
97 #define INFO6(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\
98 .part_name = _part_name,\
99 .id = {\
100 ((_jedec_id) >> 16) & 0xff,\
101 ((_jedec_id) >> 8) & 0xff,\
102 (_jedec_id) & 0xff,\
103 ((_ext_id) >> 16) & 0xff,\
104 ((_ext_id) >> 8) & 0xff,\
105 (_ext_id) & 0xff,\
106 },\
107 .id_len = 6,\
108 .sector_size = (_sector_size),\
109 .n_sectors = (_n_sectors),\
110 .page_size = 256,\
111 .flags = (_flags),\
112 .die_cnt = 0
113
114 #define INFO_STACKED(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors,\
115 _flags, _die_cnt)\
116 .part_name = _part_name,\
117 .id = {\
118 ((_jedec_id) >> 16) & 0xff,\
119 ((_jedec_id) >> 8) & 0xff,\
120 (_jedec_id) & 0xff,\
121 ((_ext_id) >> 8) & 0xff,\
122 (_ext_id) & 0xff,\
123 },\
124 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\
125 .sector_size = (_sector_size),\
126 .n_sectors = (_n_sectors),\
127 .page_size = 256,\
128 .flags = (_flags),\
129 .die_cnt = _die_cnt
130
131 #define JEDEC_NUMONYX 0x20
132 #define JEDEC_WINBOND 0xEF
133 #define JEDEC_SPANSION 0x01
134
135 /* Numonyx (Micron) Configuration register macros */
136 #define VCFG_DUMMY 0x1
137 #define VCFG_WRAP_SEQUENTIAL 0x2
138 #define NVCFG_XIP_MODE_DISABLED (7 << 9)
139 #define NVCFG_XIP_MODE_MASK (7 << 9)
140 #define VCFG_XIP_MODE_DISABLED (1 << 3)
141 #define CFG_DUMMY_CLK_LEN 4
142 #define NVCFG_DUMMY_CLK_POS 12
143 #define VCFG_DUMMY_CLK_POS 4
144 #define EVCFG_OUT_DRIVER_STRENGTH_DEF 7
145 #define EVCFG_VPP_ACCELERATOR (1 << 3)
146 #define EVCFG_RESET_HOLD_ENABLED (1 << 4)
147 #define NVCFG_DUAL_IO_MASK (1 << 2)
148 #define EVCFG_DUAL_IO_DISABLED (1 << 6)
149 #define NVCFG_QUAD_IO_MASK (1 << 3)
150 #define EVCFG_QUAD_IO_DISABLED (1 << 7)
151 #define NVCFG_4BYTE_ADDR_MASK (1 << 0)
152 #define NVCFG_LOWER_SEGMENT_MASK (1 << 1)
153
154 /* Numonyx (Micron) Flag Status Register macros */
155 #define FSR_4BYTE_ADDR_MODE_ENABLED 0x1
156 #define FSR_FLASH_READY (1 << 7)
157
158 /* Spansion configuration registers macros. */
159 #define SPANSION_QUAD_CFG_POS 0
160 #define SPANSION_QUAD_CFG_LEN 1
161 #define SPANSION_DUMMY_CLK_POS 0
162 #define SPANSION_DUMMY_CLK_LEN 4
163 #define SPANSION_ADDR_LEN_POS 7
164 #define SPANSION_ADDR_LEN_LEN 1
165
166 /*
167 * Spansion read mode command length in bytes,
168 * the mode is currently not supported.
169 */
170
171 #define SPANSION_CONTINUOUS_READ_MODE_CMD_LEN 1
172 #define WINBOND_CONTINUOUS_READ_MODE_CMD_LEN 1
173
174 static const FlashPartInfo known_devices[] = {
175 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
176 { INFO("at25fs010", 0x1f6601, 0, 32 << 10, 4, ER_4K) },
177 { INFO("at25fs040", 0x1f6604, 0, 64 << 10, 8, ER_4K) },
178
179 { INFO("at25df041a", 0x1f4401, 0, 64 << 10, 8, ER_4K) },
180 { INFO("at25df321a", 0x1f4701, 0, 64 << 10, 64, ER_4K) },
181 { INFO("at25df641", 0x1f4800, 0, 64 << 10, 128, ER_4K) },
182
183 { INFO("at26f004", 0x1f0400, 0, 64 << 10, 8, ER_4K) },
184 { INFO("at26df081a", 0x1f4501, 0, 64 << 10, 16, ER_4K) },
185 { INFO("at26df161a", 0x1f4601, 0, 64 << 10, 32, ER_4K) },
186 { INFO("at26df321", 0x1f4700, 0, 64 << 10, 64, ER_4K) },
187
188 { INFO("at45db081d", 0x1f2500, 0, 64 << 10, 16, ER_4K) },
189
190 /* Atmel EEPROMS - it is assumed, that don't care bit in command
191 * is set to 0. Block protection is not supported.
192 */
193 { INFO("at25128a-nonjedec", 0x0, 0, 1, 131072, EEPROM) },
194 { INFO("at25256a-nonjedec", 0x0, 0, 1, 262144, EEPROM) },
195
196 /* EON -- en25xxx */
197 { INFO("en25f32", 0x1c3116, 0, 64 << 10, 64, ER_4K) },
198 { INFO("en25p32", 0x1c2016, 0, 64 << 10, 64, 0) },
199 { INFO("en25q32b", 0x1c3016, 0, 64 << 10, 64, 0) },
200 { INFO("en25p64", 0x1c2017, 0, 64 << 10, 128, 0) },
201 { INFO("en25q64", 0x1c3017, 0, 64 << 10, 128, ER_4K) },
202
203 /* GigaDevice */
204 { INFO("gd25q32", 0xc84016, 0, 64 << 10, 64, ER_4K) },
205 { INFO("gd25q64", 0xc84017, 0, 64 << 10, 128, ER_4K) },
206
207 /* Intel/Numonyx -- xxxs33b */
208 { INFO("160s33b", 0x898911, 0, 64 << 10, 32, 0) },
209 { INFO("320s33b", 0x898912, 0, 64 << 10, 64, 0) },
210 { INFO("640s33b", 0x898913, 0, 64 << 10, 128, 0) },
211 { INFO("n25q064", 0x20ba17, 0, 64 << 10, 128, 0) },
212
213 /* Macronix */
214 { INFO("mx25l2005a", 0xc22012, 0, 64 << 10, 4, ER_4K) },
215 { INFO("mx25l4005a", 0xc22013, 0, 64 << 10, 8, ER_4K) },
216 { INFO("mx25l8005", 0xc22014, 0, 64 << 10, 16, 0) },
217 { INFO("mx25l1606e", 0xc22015, 0, 64 << 10, 32, ER_4K) },
218 { INFO("mx25l3205d", 0xc22016, 0, 64 << 10, 64, 0) },
219 { INFO("mx25l6405d", 0xc22017, 0, 64 << 10, 128, 0) },
220 { INFO("mx25l12805d", 0xc22018, 0, 64 << 10, 256, 0) },
221 { INFO("mx25l12855e", 0xc22618, 0, 64 << 10, 256, 0) },
222 { INFO6("mx25l25635e", 0xc22019, 0xc22019, 64 << 10, 512, 0) },
223 { INFO("mx25l25655e", 0xc22619, 0, 64 << 10, 512, 0) },
224 { INFO("mx66l51235f", 0xc2201a, 0, 64 << 10, 1024, ER_4K | ER_32K) },
225 { INFO("mx66u51235f", 0xc2253a, 0, 64 << 10, 1024, ER_4K | ER_32K) },
226 { INFO("mx66u1g45g", 0xc2253b, 0, 64 << 10, 2048, ER_4K | ER_32K) },
227 { INFO("mx66l1g45g", 0xc2201b, 0, 64 << 10, 2048, ER_4K | ER_32K) },
228
229 /* Micron */
230 { INFO("n25q032a11", 0x20bb16, 0, 64 << 10, 64, ER_4K) },
231 { INFO("n25q032a13", 0x20ba16, 0, 64 << 10, 64, ER_4K) },
232 { INFO("n25q064a11", 0x20bb17, 0, 64 << 10, 128, ER_4K) },
233 { INFO("n25q064a13", 0x20ba17, 0, 64 << 10, 128, ER_4K) },
234 { INFO("n25q128a11", 0x20bb18, 0, 64 << 10, 256, ER_4K) },
235 { INFO("n25q128a13", 0x20ba18, 0, 64 << 10, 256, ER_4K) },
236 { INFO("n25q256a11", 0x20bb19, 0, 64 << 10, 512, ER_4K) },
237 { INFO("n25q256a13", 0x20ba19, 0, 64 << 10, 512, ER_4K) },
238 { INFO("n25q512a11", 0x20bb20, 0, 64 << 10, 1024, ER_4K) },
239 { INFO("n25q512a13", 0x20ba20, 0, 64 << 10, 1024, ER_4K) },
240 { INFO("n25q128", 0x20ba18, 0, 64 << 10, 256, 0) },
241 { INFO("n25q256a", 0x20ba19, 0, 64 << 10, 512, ER_4K) },
242 { INFO("n25q512a", 0x20ba20, 0, 64 << 10, 1024, ER_4K) },
243 { INFO("n25q512ax3", 0x20ba20, 0x1000, 64 << 10, 1024, ER_4K) },
244 { INFO("mt25ql512ab", 0x20ba20, 0x1044, 64 << 10, 1024, ER_4K | ER_32K) },
245 { INFO_STACKED("n25q00", 0x20ba21, 0x1000, 64 << 10, 2048, ER_4K, 4) },
246 { INFO_STACKED("n25q00a", 0x20bb21, 0x1000, 64 << 10, 2048, ER_4K, 4) },
247 { INFO_STACKED("mt25ql01g", 0x20ba21, 0x1040, 64 << 10, 2048, ER_4K, 2) },
248 { INFO_STACKED("mt25qu01g", 0x20bb21, 0x1040, 64 << 10, 2048, ER_4K, 2) },
249
250 /* Spansion -- single (large) sector size only, at least
251 * for the chips listed here (without boot sectors).
252 */
253 { INFO("s25sl032p", 0x010215, 0x4d00, 64 << 10, 64, ER_4K) },
254 { INFO("s25sl064p", 0x010216, 0x4d00, 64 << 10, 128, ER_4K) },
255 { INFO("s25fl256s0", 0x010219, 0x4d00, 256 << 10, 128, 0) },
256 { INFO("s25fl256s1", 0x010219, 0x4d01, 64 << 10, 512, 0) },
257 { INFO6("s25fl512s", 0x010220, 0x4d0080, 256 << 10, 256, 0) },
258 { INFO6("s70fl01gs", 0x010221, 0x4d0080, 256 << 10, 512, 0) },
259 { INFO("s25sl12800", 0x012018, 0x0300, 256 << 10, 64, 0) },
260 { INFO("s25sl12801", 0x012018, 0x0301, 64 << 10, 256, 0) },
261 { INFO("s25fl129p0", 0x012018, 0x4d00, 256 << 10, 64, 0) },
262 { INFO("s25fl129p1", 0x012018, 0x4d01, 64 << 10, 256, 0) },
263 { INFO("s25sl004a", 0x010212, 0, 64 << 10, 8, 0) },
264 { INFO("s25sl008a", 0x010213, 0, 64 << 10, 16, 0) },
265 { INFO("s25sl016a", 0x010214, 0, 64 << 10, 32, 0) },
266 { INFO("s25sl032a", 0x010215, 0, 64 << 10, 64, 0) },
267 { INFO("s25sl064a", 0x010216, 0, 64 << 10, 128, 0) },
268 { INFO("s25fl016k", 0xef4015, 0, 64 << 10, 32, ER_4K | ER_32K) },
269 { INFO("s25fl064k", 0xef4017, 0, 64 << 10, 128, ER_4K | ER_32K) },
270
271 /* Spansion -- boot sectors support */
272 { INFO6("s25fs512s", 0x010220, 0x4d0081, 256 << 10, 256, 0) },
273 { INFO6("s70fs01gs", 0x010221, 0x4d0081, 256 << 10, 512, 0) },
274
275 /* SST -- large erase sizes are "overlays", "sectors" are 4<< 10 */
276 { INFO("sst25vf040b", 0xbf258d, 0, 64 << 10, 8, ER_4K) },
277 { INFO("sst25vf080b", 0xbf258e, 0, 64 << 10, 16, ER_4K) },
278 { INFO("sst25vf016b", 0xbf2541, 0, 64 << 10, 32, ER_4K) },
279 { INFO("sst25vf032b", 0xbf254a, 0, 64 << 10, 64, ER_4K) },
280 { INFO("sst25wf512", 0xbf2501, 0, 64 << 10, 1, ER_4K) },
281 { INFO("sst25wf010", 0xbf2502, 0, 64 << 10, 2, ER_4K) },
282 { INFO("sst25wf020", 0xbf2503, 0, 64 << 10, 4, ER_4K) },
283 { INFO("sst25wf040", 0xbf2504, 0, 64 << 10, 8, ER_4K) },
284 { INFO("sst25wf080", 0xbf2505, 0, 64 << 10, 16, ER_4K) },
285
286 /* ST Microelectronics -- newer production may have feature updates */
287 { INFO("m25p05", 0x202010, 0, 32 << 10, 2, 0) },
288 { INFO("m25p10", 0x202011, 0, 32 << 10, 4, 0) },
289 { INFO("m25p20", 0x202012, 0, 64 << 10, 4, 0) },
290 { INFO("m25p40", 0x202013, 0, 64 << 10, 8, 0) },
291 { INFO("m25p80", 0x202014, 0, 64 << 10, 16, 0) },
292 { INFO("m25p16", 0x202015, 0, 64 << 10, 32, 0) },
293 { INFO("m25p32", 0x202016, 0, 64 << 10, 64, 0) },
294 { INFO("m25p64", 0x202017, 0, 64 << 10, 128, 0) },
295 { INFO("m25p128", 0x202018, 0, 256 << 10, 64, 0) },
296 { INFO("n25q032", 0x20ba16, 0, 64 << 10, 64, 0) },
297
298 { INFO("m45pe10", 0x204011, 0, 64 << 10, 2, 0) },
299 { INFO("m45pe80", 0x204014, 0, 64 << 10, 16, 0) },
300 { INFO("m45pe16", 0x204015, 0, 64 << 10, 32, 0) },
301
302 { INFO("m25pe20", 0x208012, 0, 64 << 10, 4, 0) },
303 { INFO("m25pe80", 0x208014, 0, 64 << 10, 16, 0) },
304 { INFO("m25pe16", 0x208015, 0, 64 << 10, 32, ER_4K) },
305
306 { INFO("m25px32", 0x207116, 0, 64 << 10, 64, ER_4K) },
307 { INFO("m25px32-s0", 0x207316, 0, 64 << 10, 64, ER_4K) },
308 { INFO("m25px32-s1", 0x206316, 0, 64 << 10, 64, ER_4K) },
309 { INFO("m25px64", 0x207117, 0, 64 << 10, 128, 0) },
310
311 /* Winbond -- w25x "blocks" are 64k, "sectors" are 4KiB */
312 { INFO("w25x10", 0xef3011, 0, 64 << 10, 2, ER_4K) },
313 { INFO("w25x20", 0xef3012, 0, 64 << 10, 4, ER_4K) },
314 { INFO("w25x40", 0xef3013, 0, 64 << 10, 8, ER_4K) },
315 { INFO("w25x80", 0xef3014, 0, 64 << 10, 16, ER_4K) },
316 { INFO("w25x16", 0xef3015, 0, 64 << 10, 32, ER_4K) },
317 { INFO("w25x32", 0xef3016, 0, 64 << 10, 64, ER_4K) },
318 { INFO("w25q32", 0xef4016, 0, 64 << 10, 64, ER_4K) },
319 { INFO("w25q32dw", 0xef6016, 0, 64 << 10, 64, ER_4K) },
320 { INFO("w25x64", 0xef3017, 0, 64 << 10, 128, ER_4K) },
321 { INFO("w25q64", 0xef4017, 0, 64 << 10, 128, ER_4K) },
322 { INFO("w25q80", 0xef5014, 0, 64 << 10, 16, ER_4K) },
323 { INFO("w25q80bl", 0xef4014, 0, 64 << 10, 16, ER_4K) },
324 { INFO("w25q256", 0xef4019, 0, 64 << 10, 512, ER_4K) },
325 { INFO("w25q512jv", 0xef4020, 0, 64 << 10, 1024, ER_4K) },
326 };
327
328 typedef enum {
329 NOP = 0,
330 WRSR = 0x1,
331 WRDI = 0x4,
332 RDSR = 0x5,
333 WREN = 0x6,
334 BRRD = 0x16,
335 BRWR = 0x17,
336 JEDEC_READ = 0x9f,
337 BULK_ERASE_60 = 0x60,
338 BULK_ERASE = 0xc7,
339 READ_FSR = 0x70,
340 RDCR = 0x15,
341
342 READ = 0x03,
343 READ4 = 0x13,
344 FAST_READ = 0x0b,
345 FAST_READ4 = 0x0c,
346 DOR = 0x3b,
347 DOR4 = 0x3c,
348 QOR = 0x6b,
349 QOR4 = 0x6c,
350 DIOR = 0xbb,
351 DIOR4 = 0xbc,
352 QIOR = 0xeb,
353 QIOR4 = 0xec,
354
355 PP = 0x02,
356 PP4 = 0x12,
357 PP4_4 = 0x3e,
358 DPP = 0xa2,
359 QPP = 0x32,
360 QPP_4 = 0x34,
361 RDID_90 = 0x90,
362 RDID_AB = 0xab,
363 AAI_WP = 0xad,
364
365 ERASE_4K = 0x20,
366 ERASE4_4K = 0x21,
367 ERASE_32K = 0x52,
368 ERASE4_32K = 0x5c,
369 ERASE_SECTOR = 0xd8,
370 ERASE4_SECTOR = 0xdc,
371
372 EN_4BYTE_ADDR = 0xB7,
373 EX_4BYTE_ADDR = 0xE9,
374
375 EXTEND_ADDR_READ = 0xC8,
376 EXTEND_ADDR_WRITE = 0xC5,
377
378 RESET_ENABLE = 0x66,
379 RESET_MEMORY = 0x99,
380
381 /*
382 * Micron: 0x35 - enable QPI
383 * Spansion: 0x35 - read control register
384 */
385 RDCR_EQIO = 0x35,
386 RSTQIO = 0xf5,
387
388 RNVCR = 0xB5,
389 WNVCR = 0xB1,
390
391 RVCR = 0x85,
392 WVCR = 0x81,
393
394 REVCR = 0x65,
395 WEVCR = 0x61,
396
397 DIE_ERASE = 0xC4,
398 } FlashCMD;
399
400 typedef enum {
401 STATE_IDLE,
402 STATE_PAGE_PROGRAM,
403 STATE_READ,
404 STATE_COLLECTING_DATA,
405 STATE_COLLECTING_VAR_LEN_DATA,
406 STATE_READING_DATA,
407 } CMDState;
408
409 typedef enum {
410 MAN_SPANSION,
411 MAN_MACRONIX,
412 MAN_NUMONYX,
413 MAN_WINBOND,
414 MAN_SST,
415 MAN_GENERIC,
416 } Manufacturer;
417
418 typedef enum {
419 MODE_STD = 0,
420 MODE_DIO = 1,
421 MODE_QIO = 2
422 } SPIMode;
423
424 #define M25P80_INTERNAL_DATA_BUFFER_SZ 16
425
426 struct Flash {
427 SSIPeripheral parent_obj;
428
429 BlockBackend *blk;
430
431 uint8_t *storage;
432 uint32_t size;
433 int page_size;
434
435 uint8_t state;
436 uint8_t data[M25P80_INTERNAL_DATA_BUFFER_SZ];
437 uint32_t len;
438 uint32_t pos;
439 bool data_read_loop;
440 uint8_t needed_bytes;
441 uint8_t cmd_in_progress;
442 uint32_t cur_addr;
443 uint32_t nonvolatile_cfg;
444 /* Configuration register for Macronix */
445 uint32_t volatile_cfg;
446 uint32_t enh_volatile_cfg;
447 /* Spansion cfg registers. */
448 uint8_t spansion_cr1nv;
449 uint8_t spansion_cr2nv;
450 uint8_t spansion_cr3nv;
451 uint8_t spansion_cr4nv;
452 uint8_t spansion_cr1v;
453 uint8_t spansion_cr2v;
454 uint8_t spansion_cr3v;
455 uint8_t spansion_cr4v;
456 bool write_enable;
457 bool four_bytes_address_mode;
458 bool reset_enable;
459 bool quad_enable;
460 bool aai_enable;
461 uint8_t ear;
462
463 int64_t dirty_page;
464
465 const FlashPartInfo *pi;
466
467 };
468
469 struct M25P80Class {
470 SSIPeripheralClass parent_class;
471 FlashPartInfo *pi;
472 };
473
474 #define TYPE_M25P80 "m25p80-generic"
475 OBJECT_DECLARE_TYPE(Flash, M25P80Class, M25P80)
476
477 static inline Manufacturer get_man(Flash *s)
478 {
479 switch (s->pi->id[0]) {
480 case 0x20:
481 return MAN_NUMONYX;
482 case 0xEF:
483 return MAN_WINBOND;
484 case 0x01:
485 return MAN_SPANSION;
486 case 0xC2:
487 return MAN_MACRONIX;
488 case 0xBF:
489 return MAN_SST;
490 default:
491 return MAN_GENERIC;
492 }
493 }
494
495 static void blk_sync_complete(void *opaque, int ret)
496 {
497 QEMUIOVector *iov = opaque;
498
499 qemu_iovec_destroy(iov);
500 g_free(iov);
501
502 /* do nothing. Masters do not directly interact with the backing store,
503 * only the working copy so no mutexing required.
504 */
505 }
506
507 static void flash_sync_page(Flash *s, int page)
508 {
509 QEMUIOVector *iov;
510
511 if (!s->blk || !blk_is_writable(s->blk)) {
512 return;
513 }
514
515 iov = g_new(QEMUIOVector, 1);
516 qemu_iovec_init(iov, 1);
517 qemu_iovec_add(iov, s->storage + page * s->pi->page_size,
518 s->pi->page_size);
519 blk_aio_pwritev(s->blk, page * s->pi->page_size, iov, 0,
520 blk_sync_complete, iov);
521 }
522
523 static inline void flash_sync_area(Flash *s, int64_t off, int64_t len)
524 {
525 QEMUIOVector *iov;
526
527 if (!s->blk || !blk_is_writable(s->blk)) {
528 return;
529 }
530
531 assert(!(len % BDRV_SECTOR_SIZE));
532 iov = g_new(QEMUIOVector, 1);
533 qemu_iovec_init(iov, 1);
534 qemu_iovec_add(iov, s->storage + off, len);
535 blk_aio_pwritev(s->blk, off, iov, 0, blk_sync_complete, iov);
536 }
537
538 static void flash_erase(Flash *s, int offset, FlashCMD cmd)
539 {
540 uint32_t len;
541 uint8_t capa_to_assert = 0;
542
543 switch (cmd) {
544 case ERASE_4K:
545 case ERASE4_4K:
546 len = 4 * KiB;
547 capa_to_assert = ER_4K;
548 break;
549 case ERASE_32K:
550 case ERASE4_32K:
551 len = 32 * KiB;
552 capa_to_assert = ER_32K;
553 break;
554 case ERASE_SECTOR:
555 case ERASE4_SECTOR:
556 len = s->pi->sector_size;
557 break;
558 case BULK_ERASE:
559 len = s->size;
560 break;
561 case DIE_ERASE:
562 if (s->pi->die_cnt) {
563 len = s->size / s->pi->die_cnt;
564 offset = offset & (~(len - 1));
565 } else {
566 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: die erase is not supported"
567 " by device\n");
568 return;
569 }
570 break;
571 default:
572 abort();
573 }
574
575 trace_m25p80_flash_erase(s, offset, len);
576
577 if ((s->pi->flags & capa_to_assert) != capa_to_assert) {
578 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %d erase size not supported by"
579 " device\n", len);
580 }
581
582 if (!s->write_enable) {
583 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: erase with write protect!\n");
584 return;
585 }
586 memset(s->storage + offset, 0xff, len);
587 flash_sync_area(s, offset, len);
588 }
589
590 static inline void flash_sync_dirty(Flash *s, int64_t newpage)
591 {
592 if (s->dirty_page >= 0 && s->dirty_page != newpage) {
593 flash_sync_page(s, s->dirty_page);
594 s->dirty_page = newpage;
595 }
596 }
597
598 static inline
599 void flash_write8(Flash *s, uint32_t addr, uint8_t data)
600 {
601 uint32_t page = addr / s->pi->page_size;
602 uint8_t prev = s->storage[s->cur_addr];
603
604 if (!s->write_enable) {
605 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write protect!\n");
606 return;
607 }
608
609 if ((prev ^ data) & data) {
610 trace_m25p80_programming_zero_to_one(s, addr, prev, data);
611 }
612
613 if (s->pi->flags & EEPROM) {
614 s->storage[s->cur_addr] = data;
615 } else {
616 s->storage[s->cur_addr] &= data;
617 }
618
619 flash_sync_dirty(s, page);
620 s->dirty_page = page;
621 }
622
623 static inline int get_addr_length(Flash *s)
624 {
625 /* check if eeprom is in use */
626 if (s->pi->flags == EEPROM) {
627 return 2;
628 }
629
630 switch (s->cmd_in_progress) {
631 case PP4:
632 case PP4_4:
633 case QPP_4:
634 case READ4:
635 case QIOR4:
636 case ERASE4_4K:
637 case ERASE4_32K:
638 case ERASE4_SECTOR:
639 case FAST_READ4:
640 case DOR4:
641 case QOR4:
642 case DIOR4:
643 return 4;
644 default:
645 return s->four_bytes_address_mode ? 4 : 3;
646 }
647 }
648
649 static void complete_collecting_data(Flash *s)
650 {
651 int i, n;
652
653 n = get_addr_length(s);
654 s->cur_addr = (n == 3 ? s->ear : 0);
655 for (i = 0; i < n; ++i) {
656 s->cur_addr <<= 8;
657 s->cur_addr |= s->data[i];
658 }
659
660 s->cur_addr &= s->size - 1;
661
662 s->state = STATE_IDLE;
663
664 trace_m25p80_complete_collecting(s, s->cmd_in_progress, n, s->ear,
665 s->cur_addr);
666
667 switch (s->cmd_in_progress) {
668 case DPP:
669 case QPP:
670 case QPP_4:
671 case PP:
672 case PP4:
673 case PP4_4:
674 s->state = STATE_PAGE_PROGRAM;
675 break;
676 case AAI_WP:
677 /* AAI programming starts from the even address */
678 s->cur_addr &= ~BIT(0);
679 s->state = STATE_PAGE_PROGRAM;
680 break;
681 case READ:
682 case READ4:
683 case FAST_READ:
684 case FAST_READ4:
685 case DOR:
686 case DOR4:
687 case QOR:
688 case QOR4:
689 case DIOR:
690 case DIOR4:
691 case QIOR:
692 case QIOR4:
693 s->state = STATE_READ;
694 break;
695 case ERASE_4K:
696 case ERASE4_4K:
697 case ERASE_32K:
698 case ERASE4_32K:
699 case ERASE_SECTOR:
700 case ERASE4_SECTOR:
701 case DIE_ERASE:
702 flash_erase(s, s->cur_addr, s->cmd_in_progress);
703 break;
704 case WRSR:
705 switch (get_man(s)) {
706 case MAN_SPANSION:
707 s->quad_enable = !!(s->data[1] & 0x02);
708 break;
709 case MAN_MACRONIX:
710 s->quad_enable = extract32(s->data[0], 6, 1);
711 if (s->len > 1) {
712 s->volatile_cfg = s->data[1];
713 s->four_bytes_address_mode = extract32(s->data[1], 5, 1);
714 }
715 break;
716 default:
717 break;
718 }
719 if (s->write_enable) {
720 s->write_enable = false;
721 }
722 break;
723 case BRWR:
724 case EXTEND_ADDR_WRITE:
725 s->ear = s->data[0];
726 break;
727 case WNVCR:
728 s->nonvolatile_cfg = s->data[0] | (s->data[1] << 8);
729 break;
730 case WVCR:
731 s->volatile_cfg = s->data[0];
732 break;
733 case WEVCR:
734 s->enh_volatile_cfg = s->data[0];
735 break;
736 case RDID_90:
737 case RDID_AB:
738 if (get_man(s) == MAN_SST) {
739 if (s->cur_addr <= 1) {
740 if (s->cur_addr) {
741 s->data[0] = s->pi->id[2];
742 s->data[1] = s->pi->id[0];
743 } else {
744 s->data[0] = s->pi->id[0];
745 s->data[1] = s->pi->id[2];
746 }
747 s->pos = 0;
748 s->len = 2;
749 s->data_read_loop = true;
750 s->state = STATE_READING_DATA;
751 } else {
752 qemu_log_mask(LOG_GUEST_ERROR,
753 "M25P80: Invalid read id address\n");
754 }
755 } else {
756 qemu_log_mask(LOG_GUEST_ERROR,
757 "M25P80: Read id (command 0x90/0xAB) is not supported"
758 " by device\n");
759 }
760 break;
761 default:
762 break;
763 }
764 }
765
766 static void reset_memory(Flash *s)
767 {
768 s->cmd_in_progress = NOP;
769 s->cur_addr = 0;
770 s->ear = 0;
771 s->four_bytes_address_mode = false;
772 s->len = 0;
773 s->needed_bytes = 0;
774 s->pos = 0;
775 s->state = STATE_IDLE;
776 s->write_enable = false;
777 s->reset_enable = false;
778 s->quad_enable = false;
779 s->aai_enable = false;
780
781 switch (get_man(s)) {
782 case MAN_NUMONYX:
783 s->volatile_cfg = 0;
784 s->volatile_cfg |= VCFG_DUMMY;
785 s->volatile_cfg |= VCFG_WRAP_SEQUENTIAL;
786 if ((s->nonvolatile_cfg & NVCFG_XIP_MODE_MASK)
787 == NVCFG_XIP_MODE_DISABLED) {
788 s->volatile_cfg |= VCFG_XIP_MODE_DISABLED;
789 }
790 s->volatile_cfg |= deposit32(s->volatile_cfg,
791 VCFG_DUMMY_CLK_POS,
792 CFG_DUMMY_CLK_LEN,
793 extract32(s->nonvolatile_cfg,
794 NVCFG_DUMMY_CLK_POS,
795 CFG_DUMMY_CLK_LEN)
796 );
797
798 s->enh_volatile_cfg = 0;
799 s->enh_volatile_cfg |= EVCFG_OUT_DRIVER_STRENGTH_DEF;
800 s->enh_volatile_cfg |= EVCFG_VPP_ACCELERATOR;
801 s->enh_volatile_cfg |= EVCFG_RESET_HOLD_ENABLED;
802 if (s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK) {
803 s->enh_volatile_cfg |= EVCFG_DUAL_IO_DISABLED;
804 }
805 if (s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK) {
806 s->enh_volatile_cfg |= EVCFG_QUAD_IO_DISABLED;
807 }
808 if (!(s->nonvolatile_cfg & NVCFG_4BYTE_ADDR_MASK)) {
809 s->four_bytes_address_mode = true;
810 }
811 if (!(s->nonvolatile_cfg & NVCFG_LOWER_SEGMENT_MASK)) {
812 s->ear = s->size / MAX_3BYTES_SIZE - 1;
813 }
814 break;
815 case MAN_MACRONIX:
816 s->volatile_cfg = 0x7;
817 break;
818 case MAN_SPANSION:
819 s->spansion_cr1v = s->spansion_cr1nv;
820 s->spansion_cr2v = s->spansion_cr2nv;
821 s->spansion_cr3v = s->spansion_cr3nv;
822 s->spansion_cr4v = s->spansion_cr4nv;
823 s->quad_enable = extract32(s->spansion_cr1v,
824 SPANSION_QUAD_CFG_POS,
825 SPANSION_QUAD_CFG_LEN
826 );
827 s->four_bytes_address_mode = extract32(s->spansion_cr2v,
828 SPANSION_ADDR_LEN_POS,
829 SPANSION_ADDR_LEN_LEN
830 );
831 break;
832 default:
833 break;
834 }
835
836 trace_m25p80_reset_done(s);
837 }
838
839 static uint8_t numonyx_mode(Flash *s)
840 {
841 if (!(s->enh_volatile_cfg & EVCFG_QUAD_IO_DISABLED)) {
842 return MODE_QIO;
843 } else if (!(s->enh_volatile_cfg & EVCFG_DUAL_IO_DISABLED)) {
844 return MODE_DIO;
845 } else {
846 return MODE_STD;
847 }
848 }
849
850 static uint8_t numonyx_extract_cfg_num_dummies(Flash *s)
851 {
852 uint8_t num_dummies;
853 uint8_t mode;
854 assert(get_man(s) == MAN_NUMONYX);
855
856 mode = numonyx_mode(s);
857 num_dummies = extract32(s->volatile_cfg, 4, 4);
858
859 if (num_dummies == 0x0 || num_dummies == 0xf) {
860 switch (s->cmd_in_progress) {
861 case QIOR:
862 case QIOR4:
863 num_dummies = 10;
864 break;
865 default:
866 num_dummies = (mode == MODE_QIO) ? 10 : 8;
867 break;
868 }
869 }
870
871 return num_dummies;
872 }
873
874 static void decode_fast_read_cmd(Flash *s)
875 {
876 s->needed_bytes = get_addr_length(s);
877 switch (get_man(s)) {
878 /* Dummy cycles - modeled with bytes writes instead of bits */
879 case MAN_WINBOND:
880 s->needed_bytes += 8;
881 break;
882 case MAN_NUMONYX:
883 s->needed_bytes += numonyx_extract_cfg_num_dummies(s);
884 break;
885 case MAN_MACRONIX:
886 if (extract32(s->volatile_cfg, 6, 2) == 1) {
887 s->needed_bytes += 6;
888 } else {
889 s->needed_bytes += 8;
890 }
891 break;
892 case MAN_SPANSION:
893 s->needed_bytes += extract32(s->spansion_cr2v,
894 SPANSION_DUMMY_CLK_POS,
895 SPANSION_DUMMY_CLK_LEN
896 );
897 break;
898 default:
899 break;
900 }
901 s->pos = 0;
902 s->len = 0;
903 s->state = STATE_COLLECTING_DATA;
904 }
905
906 static void decode_dio_read_cmd(Flash *s)
907 {
908 s->needed_bytes = get_addr_length(s);
909 /* Dummy cycles modeled with bytes writes instead of bits */
910 switch (get_man(s)) {
911 case MAN_WINBOND:
912 s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN;
913 break;
914 case MAN_SPANSION:
915 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN;
916 s->needed_bytes += extract32(s->spansion_cr2v,
917 SPANSION_DUMMY_CLK_POS,
918 SPANSION_DUMMY_CLK_LEN
919 );
920 break;
921 case MAN_NUMONYX:
922 s->needed_bytes += numonyx_extract_cfg_num_dummies(s);
923 break;
924 case MAN_MACRONIX:
925 switch (extract32(s->volatile_cfg, 6, 2)) {
926 case 1:
927 s->needed_bytes += 6;
928 break;
929 case 2:
930 s->needed_bytes += 8;
931 break;
932 default:
933 s->needed_bytes += 4;
934 break;
935 }
936 break;
937 default:
938 break;
939 }
940 s->pos = 0;
941 s->len = 0;
942 s->state = STATE_COLLECTING_DATA;
943 }
944
945 static void decode_qio_read_cmd(Flash *s)
946 {
947 s->needed_bytes = get_addr_length(s);
948 /* Dummy cycles modeled with bytes writes instead of bits */
949 switch (get_man(s)) {
950 case MAN_WINBOND:
951 s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN;
952 s->needed_bytes += 4;
953 break;
954 case MAN_SPANSION:
955 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN;
956 s->needed_bytes += extract32(s->spansion_cr2v,
957 SPANSION_DUMMY_CLK_POS,
958 SPANSION_DUMMY_CLK_LEN
959 );
960 break;
961 case MAN_NUMONYX:
962 s->needed_bytes += numonyx_extract_cfg_num_dummies(s);
963 break;
964 case MAN_MACRONIX:
965 switch (extract32(s->volatile_cfg, 6, 2)) {
966 case 1:
967 s->needed_bytes += 4;
968 break;
969 case 2:
970 s->needed_bytes += 8;
971 break;
972 default:
973 s->needed_bytes += 6;
974 break;
975 }
976 break;
977 default:
978 break;
979 }
980 s->pos = 0;
981 s->len = 0;
982 s->state = STATE_COLLECTING_DATA;
983 }
984
985 static bool is_valid_aai_cmd(uint32_t cmd)
986 {
987 return cmd == AAI_WP || cmd == WRDI || cmd == RDSR;
988 }
989
990 static void decode_new_cmd(Flash *s, uint32_t value)
991 {
992 int i;
993
994 s->cmd_in_progress = value;
995 trace_m25p80_command_decoded(s, value);
996
997 if (value != RESET_MEMORY) {
998 s->reset_enable = false;
999 }
1000
1001 if (get_man(s) == MAN_SST && s->aai_enable && !is_valid_aai_cmd(value)) {
1002 qemu_log_mask(LOG_GUEST_ERROR,
1003 "M25P80: Invalid cmd within AAI programming sequence");
1004 }
1005
1006 switch (value) {
1007
1008 case ERASE_4K:
1009 case ERASE4_4K:
1010 case ERASE_32K:
1011 case ERASE4_32K:
1012 case ERASE_SECTOR:
1013 case ERASE4_SECTOR:
1014 case PP:
1015 case PP4:
1016 case DIE_ERASE:
1017 case RDID_90:
1018 case RDID_AB:
1019 s->needed_bytes = get_addr_length(s);
1020 s->pos = 0;
1021 s->len = 0;
1022 s->state = STATE_COLLECTING_DATA;
1023 break;
1024 case READ:
1025 case READ4:
1026 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) == MODE_STD) {
1027 s->needed_bytes = get_addr_length(s);
1028 s->pos = 0;
1029 s->len = 0;
1030 s->state = STATE_COLLECTING_DATA;
1031 } else {
1032 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
1033 "DIO or QIO mode\n", s->cmd_in_progress);
1034 }
1035 break;
1036 case DPP:
1037 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) {
1038 s->needed_bytes = get_addr_length(s);
1039 s->pos = 0;
1040 s->len = 0;
1041 s->state = STATE_COLLECTING_DATA;
1042 } else {
1043 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
1044 "QIO mode\n", s->cmd_in_progress);
1045 }
1046 break;
1047 case QPP:
1048 case QPP_4:
1049 case PP4_4:
1050 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) {
1051 s->needed_bytes = get_addr_length(s);
1052 s->pos = 0;
1053 s->len = 0;
1054 s->state = STATE_COLLECTING_DATA;
1055 } else {
1056 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
1057 "DIO mode\n", s->cmd_in_progress);
1058 }
1059 break;
1060
1061 case FAST_READ:
1062 case FAST_READ4:
1063 decode_fast_read_cmd(s);
1064 break;
1065 case DOR:
1066 case DOR4:
1067 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) {
1068 decode_fast_read_cmd(s);
1069 } else {
1070 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
1071 "QIO mode\n", s->cmd_in_progress);
1072 }
1073 break;
1074 case QOR:
1075 case QOR4:
1076 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) {
1077 decode_fast_read_cmd(s);
1078 } else {
1079 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
1080 "DIO mode\n", s->cmd_in_progress);
1081 }
1082 break;
1083
1084 case DIOR:
1085 case DIOR4:
1086 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) {
1087 decode_dio_read_cmd(s);
1088 } else {
1089 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
1090 "QIO mode\n", s->cmd_in_progress);
1091 }
1092 break;
1093
1094 case QIOR:
1095 case QIOR4:
1096 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) {
1097 decode_qio_read_cmd(s);
1098 } else {
1099 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
1100 "DIO mode\n", s->cmd_in_progress);
1101 }
1102 break;
1103
1104 case WRSR:
1105 if (s->write_enable) {
1106 switch (get_man(s)) {
1107 case MAN_SPANSION:
1108 s->needed_bytes = 2;
1109 s->state = STATE_COLLECTING_DATA;
1110 break;
1111 case MAN_MACRONIX:
1112 s->needed_bytes = 2;
1113 s->state = STATE_COLLECTING_VAR_LEN_DATA;
1114 break;
1115 default:
1116 s->needed_bytes = 1;
1117 s->state = STATE_COLLECTING_DATA;
1118 }
1119 s->pos = 0;
1120 }
1121 break;
1122
1123 case WRDI:
1124 s->write_enable = false;
1125 if (get_man(s) == MAN_SST) {
1126 s->aai_enable = false;
1127 }
1128 break;
1129 case WREN:
1130 s->write_enable = true;
1131 break;
1132
1133 case RDSR:
1134 s->data[0] = (!!s->write_enable) << 1;
1135 if (get_man(s) == MAN_MACRONIX) {
1136 s->data[0] |= (!!s->quad_enable) << 6;
1137 }
1138 if (get_man(s) == MAN_SST) {
1139 s->data[0] |= (!!s->aai_enable) << 6;
1140 }
1141
1142 s->pos = 0;
1143 s->len = 1;
1144 s->data_read_loop = true;
1145 s->state = STATE_READING_DATA;
1146 break;
1147
1148 case READ_FSR:
1149 s->data[0] = FSR_FLASH_READY;
1150 if (s->four_bytes_address_mode) {
1151 s->data[0] |= FSR_4BYTE_ADDR_MODE_ENABLED;
1152 }
1153 s->pos = 0;
1154 s->len = 1;
1155 s->data_read_loop = true;
1156 s->state = STATE_READING_DATA;
1157 break;
1158
1159 case JEDEC_READ:
1160 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) == MODE_STD) {
1161 trace_m25p80_populated_jedec(s);
1162 for (i = 0; i < s->pi->id_len; i++) {
1163 s->data[i] = s->pi->id[i];
1164 }
1165 for (; i < SPI_NOR_MAX_ID_LEN; i++) {
1166 s->data[i] = 0;
1167 }
1168
1169 s->len = SPI_NOR_MAX_ID_LEN;
1170 s->pos = 0;
1171 s->state = STATE_READING_DATA;
1172 } else {
1173 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute JEDEC read "
1174 "in DIO or QIO mode\n");
1175 }
1176 break;
1177
1178 case RDCR:
1179 s->data[0] = s->volatile_cfg & 0xFF;
1180 s->data[0] |= (!!s->four_bytes_address_mode) << 5;
1181 s->pos = 0;
1182 s->len = 1;
1183 s->state = STATE_READING_DATA;
1184 break;
1185
1186 case BULK_ERASE_60:
1187 case BULK_ERASE:
1188 if (s->write_enable) {
1189 trace_m25p80_chip_erase(s);
1190 flash_erase(s, 0, BULK_ERASE);
1191 } else {
1192 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: chip erase with write "
1193 "protect!\n");
1194 }
1195 break;
1196 case NOP:
1197 break;
1198 case EN_4BYTE_ADDR:
1199 s->four_bytes_address_mode = true;
1200 break;
1201 case EX_4BYTE_ADDR:
1202 s->four_bytes_address_mode = false;
1203 break;
1204 case BRRD:
1205 case EXTEND_ADDR_READ:
1206 s->data[0] = s->ear;
1207 s->pos = 0;
1208 s->len = 1;
1209 s->state = STATE_READING_DATA;
1210 break;
1211 case BRWR:
1212 case EXTEND_ADDR_WRITE:
1213 if (s->write_enable) {
1214 s->needed_bytes = 1;
1215 s->pos = 0;
1216 s->len = 0;
1217 s->state = STATE_COLLECTING_DATA;
1218 }
1219 break;
1220 case RNVCR:
1221 s->data[0] = s->nonvolatile_cfg & 0xFF;
1222 s->data[1] = (s->nonvolatile_cfg >> 8) & 0xFF;
1223 s->pos = 0;
1224 s->len = 2;
1225 s->state = STATE_READING_DATA;
1226 break;
1227 case WNVCR:
1228 if (s->write_enable && get_man(s) == MAN_NUMONYX) {
1229 s->needed_bytes = 2;
1230 s->pos = 0;
1231 s->len = 0;
1232 s->state = STATE_COLLECTING_DATA;
1233 }
1234 break;
1235 case RVCR:
1236 s->data[0] = s->volatile_cfg & 0xFF;
1237 s->pos = 0;
1238 s->len = 1;
1239 s->state = STATE_READING_DATA;
1240 break;
1241 case WVCR:
1242 if (s->write_enable) {
1243 s->needed_bytes = 1;
1244 s->pos = 0;
1245 s->len = 0;
1246 s->state = STATE_COLLECTING_DATA;
1247 }
1248 break;
1249 case REVCR:
1250 s->data[0] = s->enh_volatile_cfg & 0xFF;
1251 s->pos = 0;
1252 s->len = 1;
1253 s->state = STATE_READING_DATA;
1254 break;
1255 case WEVCR:
1256 if (s->write_enable) {
1257 s->needed_bytes = 1;
1258 s->pos = 0;
1259 s->len = 0;
1260 s->state = STATE_COLLECTING_DATA;
1261 }
1262 break;
1263 case RESET_ENABLE:
1264 s->reset_enable = true;
1265 break;
1266 case RESET_MEMORY:
1267 if (s->reset_enable) {
1268 reset_memory(s);
1269 }
1270 break;
1271 case RDCR_EQIO:
1272 switch (get_man(s)) {
1273 case MAN_SPANSION:
1274 s->data[0] = (!!s->quad_enable) << 1;
1275 s->pos = 0;
1276 s->len = 1;
1277 s->state = STATE_READING_DATA;
1278 break;
1279 case MAN_MACRONIX:
1280 s->quad_enable = true;
1281 break;
1282 default:
1283 break;
1284 }
1285 break;
1286 case RSTQIO:
1287 s->quad_enable = false;
1288 break;
1289 case AAI_WP:
1290 if (get_man(s) == MAN_SST) {
1291 if (s->write_enable) {
1292 if (s->aai_enable) {
1293 s->state = STATE_PAGE_PROGRAM;
1294 } else {
1295 s->aai_enable = true;
1296 s->needed_bytes = get_addr_length(s);
1297 s->state = STATE_COLLECTING_DATA;
1298 }
1299 } else {
1300 qemu_log_mask(LOG_GUEST_ERROR,
1301 "M25P80: AAI_WP with write protect\n");
1302 }
1303 } else {
1304 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value);
1305 }
1306 break;
1307 default:
1308 s->pos = 0;
1309 s->len = 1;
1310 s->state = STATE_READING_DATA;
1311 s->data_read_loop = true;
1312 s->data[0] = 0;
1313 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value);
1314 break;
1315 }
1316 }
1317
1318 static int m25p80_cs(SSIPeripheral *ss, bool select)
1319 {
1320 Flash *s = M25P80(ss);
1321
1322 if (select) {
1323 if (s->state == STATE_COLLECTING_VAR_LEN_DATA) {
1324 complete_collecting_data(s);
1325 }
1326 s->len = 0;
1327 s->pos = 0;
1328 s->state = STATE_IDLE;
1329 flash_sync_dirty(s, -1);
1330 s->data_read_loop = false;
1331 }
1332
1333 trace_m25p80_select(s, select ? "de" : "");
1334
1335 return 0;
1336 }
1337
1338 static uint32_t m25p80_transfer8(SSIPeripheral *ss, uint32_t tx)
1339 {
1340 Flash *s = M25P80(ss);
1341 uint32_t r = 0;
1342
1343 trace_m25p80_transfer(s, s->state, s->len, s->needed_bytes, s->pos,
1344 s->cur_addr, (uint8_t)tx);
1345
1346 switch (s->state) {
1347
1348 case STATE_PAGE_PROGRAM:
1349 trace_m25p80_page_program(s, s->cur_addr, (uint8_t)tx);
1350 flash_write8(s, s->cur_addr, (uint8_t)tx);
1351 s->cur_addr = (s->cur_addr + 1) & (s->size - 1);
1352
1353 if (get_man(s) == MAN_SST && s->aai_enable && s->cur_addr == 0) {
1354 /*
1355 * There is no wrap mode during AAI programming once the highest
1356 * unprotected memory address is reached. The Write-Enable-Latch
1357 * bit is automatically reset, and AAI programming mode aborts.
1358 */
1359 s->write_enable = false;
1360 s->aai_enable = false;
1361 }
1362
1363 break;
1364
1365 case STATE_READ:
1366 r = s->storage[s->cur_addr];
1367 trace_m25p80_read_byte(s, s->cur_addr, (uint8_t)r);
1368 s->cur_addr = (s->cur_addr + 1) & (s->size - 1);
1369 break;
1370
1371 case STATE_COLLECTING_DATA:
1372 case STATE_COLLECTING_VAR_LEN_DATA:
1373
1374 if (s->len >= M25P80_INTERNAL_DATA_BUFFER_SZ) {
1375 qemu_log_mask(LOG_GUEST_ERROR,
1376 "M25P80: Write overrun internal data buffer. "
1377 "SPI controller (QEMU emulator or guest driver) "
1378 "is misbehaving\n");
1379 s->len = s->pos = 0;
1380 s->state = STATE_IDLE;
1381 break;
1382 }
1383
1384 s->data[s->len] = (uint8_t)tx;
1385 s->len++;
1386
1387 if (s->len == s->needed_bytes) {
1388 complete_collecting_data(s);
1389 }
1390 break;
1391
1392 case STATE_READING_DATA:
1393
1394 if (s->pos >= M25P80_INTERNAL_DATA_BUFFER_SZ) {
1395 qemu_log_mask(LOG_GUEST_ERROR,
1396 "M25P80: Read overrun internal data buffer. "
1397 "SPI controller (QEMU emulator or guest driver) "
1398 "is misbehaving\n");
1399 s->len = s->pos = 0;
1400 s->state = STATE_IDLE;
1401 break;
1402 }
1403
1404 r = s->data[s->pos];
1405 trace_m25p80_read_data(s, s->pos, (uint8_t)r);
1406 s->pos++;
1407 if (s->pos == s->len) {
1408 s->pos = 0;
1409 if (!s->data_read_loop) {
1410 s->state = STATE_IDLE;
1411 }
1412 }
1413 break;
1414
1415 default:
1416 case STATE_IDLE:
1417 decode_new_cmd(s, (uint8_t)tx);
1418 break;
1419 }
1420
1421 return r;
1422 }
1423
1424 static void m25p80_realize(SSIPeripheral *ss, Error **errp)
1425 {
1426 Flash *s = M25P80(ss);
1427 M25P80Class *mc = M25P80_GET_CLASS(s);
1428 int ret;
1429
1430 s->pi = mc->pi;
1431
1432 s->size = s->pi->sector_size * s->pi->n_sectors;
1433 s->dirty_page = -1;
1434
1435 if (s->blk) {
1436 uint64_t perm = BLK_PERM_CONSISTENT_READ |
1437 (blk_supports_write_perm(s->blk) ? BLK_PERM_WRITE : 0);
1438 ret = blk_set_perm(s->blk, perm, BLK_PERM_ALL, errp);
1439 if (ret < 0) {
1440 return;
1441 }
1442
1443 trace_m25p80_binding(s);
1444 s->storage = blk_blockalign(s->blk, s->size);
1445
1446 if (blk_pread(s->blk, 0, s->storage, s->size) != s->size) {
1447 error_setg(errp, "failed to read the initial flash content");
1448 return;
1449 }
1450 } else {
1451 trace_m25p80_binding_no_bdrv(s);
1452 s->storage = blk_blockalign(NULL, s->size);
1453 memset(s->storage, 0xFF, s->size);
1454 }
1455 }
1456
1457 static void m25p80_reset(DeviceState *d)
1458 {
1459 Flash *s = M25P80(d);
1460
1461 reset_memory(s);
1462 }
1463
1464 static int m25p80_pre_save(void *opaque)
1465 {
1466 flash_sync_dirty((Flash *)opaque, -1);
1467
1468 return 0;
1469 }
1470
1471 static Property m25p80_properties[] = {
1472 /* This is default value for Micron flash */
1473 DEFINE_PROP_UINT32("nonvolatile-cfg", Flash, nonvolatile_cfg, 0x8FFF),
1474 DEFINE_PROP_UINT8("spansion-cr1nv", Flash, spansion_cr1nv, 0x0),
1475 DEFINE_PROP_UINT8("spansion-cr2nv", Flash, spansion_cr2nv, 0x8),
1476 DEFINE_PROP_UINT8("spansion-cr3nv", Flash, spansion_cr3nv, 0x2),
1477 DEFINE_PROP_UINT8("spansion-cr4nv", Flash, spansion_cr4nv, 0x10),
1478 DEFINE_PROP_DRIVE("drive", Flash, blk),
1479 DEFINE_PROP_END_OF_LIST(),
1480 };
1481
1482 static int m25p80_pre_load(void *opaque)
1483 {
1484 Flash *s = (Flash *)opaque;
1485
1486 s->data_read_loop = false;
1487 return 0;
1488 }
1489
1490 static bool m25p80_data_read_loop_needed(void *opaque)
1491 {
1492 Flash *s = (Flash *)opaque;
1493
1494 return s->data_read_loop;
1495 }
1496
1497 static const VMStateDescription vmstate_m25p80_data_read_loop = {
1498 .name = "m25p80/data_read_loop",
1499 .version_id = 1,
1500 .minimum_version_id = 1,
1501 .needed = m25p80_data_read_loop_needed,
1502 .fields = (VMStateField[]) {
1503 VMSTATE_BOOL(data_read_loop, Flash),
1504 VMSTATE_END_OF_LIST()
1505 }
1506 };
1507
1508 static bool m25p80_aai_enable_needed(void *opaque)
1509 {
1510 Flash *s = (Flash *)opaque;
1511
1512 return s->aai_enable;
1513 }
1514
1515 static const VMStateDescription vmstate_m25p80_aai_enable = {
1516 .name = "m25p80/aai_enable",
1517 .version_id = 1,
1518 .minimum_version_id = 1,
1519 .needed = m25p80_aai_enable_needed,
1520 .fields = (VMStateField[]) {
1521 VMSTATE_BOOL(aai_enable, Flash),
1522 VMSTATE_END_OF_LIST()
1523 }
1524 };
1525
1526 static const VMStateDescription vmstate_m25p80 = {
1527 .name = "m25p80",
1528 .version_id = 0,
1529 .minimum_version_id = 0,
1530 .pre_save = m25p80_pre_save,
1531 .pre_load = m25p80_pre_load,
1532 .fields = (VMStateField[]) {
1533 VMSTATE_UINT8(state, Flash),
1534 VMSTATE_UINT8_ARRAY(data, Flash, M25P80_INTERNAL_DATA_BUFFER_SZ),
1535 VMSTATE_UINT32(len, Flash),
1536 VMSTATE_UINT32(pos, Flash),
1537 VMSTATE_UINT8(needed_bytes, Flash),
1538 VMSTATE_UINT8(cmd_in_progress, Flash),
1539 VMSTATE_UINT32(cur_addr, Flash),
1540 VMSTATE_BOOL(write_enable, Flash),
1541 VMSTATE_BOOL(reset_enable, Flash),
1542 VMSTATE_UINT8(ear, Flash),
1543 VMSTATE_BOOL(four_bytes_address_mode, Flash),
1544 VMSTATE_UINT32(nonvolatile_cfg, Flash),
1545 VMSTATE_UINT32(volatile_cfg, Flash),
1546 VMSTATE_UINT32(enh_volatile_cfg, Flash),
1547 VMSTATE_BOOL(quad_enable, Flash),
1548 VMSTATE_UINT8(spansion_cr1nv, Flash),
1549 VMSTATE_UINT8(spansion_cr2nv, Flash),
1550 VMSTATE_UINT8(spansion_cr3nv, Flash),
1551 VMSTATE_UINT8(spansion_cr4nv, Flash),
1552 VMSTATE_END_OF_LIST()
1553 },
1554 .subsections = (const VMStateDescription * []) {
1555 &vmstate_m25p80_data_read_loop,
1556 &vmstate_m25p80_aai_enable,
1557 NULL
1558 }
1559 };
1560
1561 static void m25p80_class_init(ObjectClass *klass, void *data)
1562 {
1563 DeviceClass *dc = DEVICE_CLASS(klass);
1564 SSIPeripheralClass *k = SSI_PERIPHERAL_CLASS(klass);
1565 M25P80Class *mc = M25P80_CLASS(klass);
1566
1567 k->realize = m25p80_realize;
1568 k->transfer = m25p80_transfer8;
1569 k->set_cs = m25p80_cs;
1570 k->cs_polarity = SSI_CS_LOW;
1571 dc->vmsd = &vmstate_m25p80;
1572 device_class_set_props(dc, m25p80_properties);
1573 dc->reset = m25p80_reset;
1574 mc->pi = data;
1575 }
1576
1577 static const TypeInfo m25p80_info = {
1578 .name = TYPE_M25P80,
1579 .parent = TYPE_SSI_PERIPHERAL,
1580 .instance_size = sizeof(Flash),
1581 .class_size = sizeof(M25P80Class),
1582 .abstract = true,
1583 };
1584
1585 static void m25p80_register_types(void)
1586 {
1587 int i;
1588
1589 type_register_static(&m25p80_info);
1590 for (i = 0; i < ARRAY_SIZE(known_devices); ++i) {
1591 TypeInfo ti = {
1592 .name = known_devices[i].part_name,
1593 .parent = TYPE_M25P80,
1594 .class_init = m25p80_class_init,
1595 .class_data = (void *)&known_devices[i],
1596 };
1597 type_register(&ti);
1598 }
1599 }
1600
1601 type_init(m25p80_register_types)
AR7 emulation for QEMU