target/arm/kvm32.c

   1 /*
   2  * ARM implementation of KVM hooks, 32 bit specific code.
   3  *
   4  * Copyright Christoffer Dall 2009-2010
   5  *
   6  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   7  * See the COPYING file in the top-level directory.
   8  *
   9  */
  10
  11 #include "qemu/osdep.h"
  12 #include <sys/ioctl.h>
  13
  14 #include <linux/kvm.h>
  15
  16 #include "qemu-common.h"
  17 #include "cpu.h"
  18 #include "qemu/timer.h"
  19 #include "sysemu/kvm.h"
  20 #include "kvm_arm.h"
  21 #include "internals.h"
  22 #include "qemu/log.h"
  23
  24 static inline void set_feature(uint64_t *features, int feature)
  25 {
  26     *features |= 1ULL << feature;
  27 }
  28
  29 static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id)
  30 {
  31     struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)pret };
  32
  33     assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32);
  34     return ioctl(fd, KVM_GET_ONE_REG, &idreg);
  35 }
  36
  37 bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
  38 {
  39     /* Identify the feature bits corresponding to the host CPU, and
  40      * fill out the ARMHostCPUClass fields accordingly. To do this
  41      * we have to create a scratch VM, create a single CPU inside it,
  42      * and then query that CPU for the relevant ID registers.
  43      */
  44     int err = 0, fdarray[3];
  45     uint32_t midr, id_pfr0;
  46     uint64_t features = 0;
  47
  48     /* Old kernels may not know about the PREFERRED_TARGET ioctl: however
  49      * we know these will only support creating one kind of guest CPU,
  50      * which is its preferred CPU type.
  51      */
  52     static const uint32_t cpus_to_try[] = {
  53         QEMU_KVM_ARM_TARGET_CORTEX_A15,
  54         QEMU_KVM_ARM_TARGET_NONE
  55     };
  56     /*
  57      * target = -1 informs kvm_arm_create_scratch_host_vcpu()
  58      * to use the preferred target
  59      */
  60     struct kvm_vcpu_init init = { .target = -1, };
  61
  62     if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) {
  63         return false;
  64     }
  65
  66     ahcf->target = init.target;
  67
  68     /* This is not strictly blessed by the device tree binding docs yet,
  69      * but in practice the kernel does not care about this string so
  70      * there is no point maintaining an KVM_ARM_TARGET_* -> string table.
  71      */
  72     ahcf->dtb_compatible = "arm,arm-v7";
  73
  74     err |= read_sys_reg32(fdarray[2], &midr, ARM_CP15_REG32(0, 0, 0, 0));
  75     err |= read_sys_reg32(fdarray[2], &id_pfr0, ARM_CP15_REG32(0, 0, 1, 0));
  76
  77     err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0,
  78                           ARM_CP15_REG32(0, 0, 2, 0));
  79     err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1,
  80                           ARM_CP15_REG32(0, 0, 2, 1));
  81     err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2,
  82                           ARM_CP15_REG32(0, 0, 2, 2));
  83     err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3,
  84                           ARM_CP15_REG32(0, 0, 2, 3));
  85     err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4,
  86                           ARM_CP15_REG32(0, 0, 2, 4));
  87     err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5,
  88                           ARM_CP15_REG32(0, 0, 2, 5));
  89     if (read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6,
  90                        ARM_CP15_REG32(0, 0, 2, 7))) {
  91         /*
  92          * Older kernels don't support reading ID_ISAR6. This register was
  93          * only introduced in ARMv8, so we can assume that it is zero on a
  94          * CPU that a kernel this old is running on.
  95          */
  96         ahcf->isar.id_isar6 = 0;
  97     }
  98
  99     err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0,
 100                           KVM_REG_ARM | KVM_REG_SIZE_U32 |
 101                           KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR0);
 102     err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1,
 103                           KVM_REG_ARM | KVM_REG_SIZE_U32 |
 104                           KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1);
 105     /*
 106      * FIXME: There is not yet a way to read MVFR2.
 107      * Fortunately there is not yet anything in there that affects migration.
 108      */
 109
 110     kvm_arm_destroy_scratch_host_vcpu(fdarray);
 111
 112     if (err < 0) {
 113         return false;
 114     }
 115
 116     /* Now we've retrieved all the register information we can
 117      * set the feature bits based on the ID register fields.
 118      * We can assume any KVM supporting CPU is at least a v7
 119      * with VFPv3, virtualization extensions, and the generic
 120      * timers; this in turn implies most of the other feature
 121      * bits, but a few must be tested.
 122      */
 123     set_feature(&features, ARM_FEATURE_V7VE);
 124     set_feature(&features, ARM_FEATURE_VFP3);
 125     set_feature(&features, ARM_FEATURE_GENERIC_TIMER);
 126
 127     if (extract32(id_pfr0, 12, 4) == 1) {
 128         set_feature(&features, ARM_FEATURE_THUMB2EE);
 129     }
 130     if (extract32(ahcf->isar.mvfr1, 12, 4) == 1) {
 131         set_feature(&features, ARM_FEATURE_NEON);
 132     }
 133     if (extract32(ahcf->isar.mvfr1, 28, 4) == 1) {
 134         /* FMAC support implies VFPv4 */
 135         set_feature(&features, ARM_FEATURE_VFP4);
 136     }
 137
 138     ahcf->features = features;
 139
 140     return true;
 141 }
 142
 143 bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx)
 144 {
 145     /* Return true if the regidx is a register we should synchronize
 146      * via the cpreg_tuples array (ie is not a core reg we sync by
 147      * hand in kvm_arch_get/put_registers())
 148      */
 149     switch (regidx & KVM_REG_ARM_COPROC_MASK) {
 150     case KVM_REG_ARM_CORE:
 151     case KVM_REG_ARM_VFP:
 152         return false;
 153     default:
 154         return true;
 155     }
 156 }
 157
 158 typedef struct CPRegStateLevel {
 159     uint64_t regidx;
 160     int level;
 161 } CPRegStateLevel;
 162
 163 /* All coprocessor registers not listed in the following table are assumed to
 164  * be of the level KVM_PUT_RUNTIME_STATE. If a register should be written less
 165  * often, you must add it to this table with a state of either
 166  * KVM_PUT_RESET_STATE or KVM_PUT_FULL_STATE.
 167  */
 168 static const CPRegStateLevel non_runtime_cpregs[] = {
 169     { KVM_REG_ARM_TIMER_CNT, KVM_PUT_FULL_STATE },
 170 };
 171
 172 int kvm_arm_cpreg_level(uint64_t regidx)
 173 {
 174     int i;
 175
 176     for (i = 0; i < ARRAY_SIZE(non_runtime_cpregs); i++) {
 177         const CPRegStateLevel *l = &non_runtime_cpregs[i];
 178         if (l->regidx == regidx) {
 179             return l->level;
 180         }
 181     }
 182
 183     return KVM_PUT_RUNTIME_STATE;
 184 }
 185
 186 #define ARM_CPU_ID_MPIDR       0, 0, 0, 5
 187
 188 int kvm_arch_init_vcpu(CPUState *cs)
 189 {
 190     int ret;
 191     uint64_t v;
 192     uint32_t mpidr;
 193     struct kvm_one_reg r;
 194     ARMCPU *cpu = ARM_CPU(cs);
 195
 196     if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE) {
 197         fprintf(stderr, "KVM is not supported for this guest CPU type\n");
 198         return -EINVAL;
 199     }
 200
 201     /* Determine init features for this CPU */
 202     memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features));
 203     if (cpu->start_powered_off) {
 204         cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_POWER_OFF;
 205     }
 206     if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PSCI_0_2)) {
 207         cpu->psci_version = 2;
 208         cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PSCI_0_2;
 209     }
 210
 211     /* Do KVM_ARM_VCPU_INIT ioctl */
 212     ret = kvm_arm_vcpu_init(cs);
 213     if (ret) {
 214         return ret;
 215     }
 216
 217     /* Query the kernel to make sure it supports 32 VFP
 218      * registers: QEMU's "cortex-a15" CPU is always a
 219      * VFP-D32 core. The simplest way to do this is just
 220      * to attempt to read register d31.
 221      */
 222     r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP | 31;
 223     r.addr = (uintptr_t)(&v);
 224     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 225     if (ret == -ENOENT) {
 226         return -EINVAL;
 227     }
 228
 229     /*
 230      * When KVM is in use, PSCI is emulated in-kernel and not by qemu.
 231      * Currently KVM has its own idea about MPIDR assignment, so we
 232      * override our defaults with what we get from KVM.
 233      */
 234     ret = kvm_get_one_reg(cs, ARM_CP15_REG32(ARM_CPU_ID_MPIDR), &mpidr);
 235     if (ret) {
 236         return ret;
 237     }
 238     cpu->mp_affinity = mpidr & ARM32_AFFINITY_MASK;
 239
 240     /* Check whether userspace can specify guest syndrome value */
 241     kvm_arm_init_serror_injection(cs);
 242
 243     return kvm_arm_init_cpreg_list(cpu);
 244 }
 245
 246 int kvm_arch_destroy_vcpu(CPUState *cs)
 247 {
 248         return 0;
 249 }
 250
 251 typedef struct Reg {
 252     uint64_t id;
 253     int offset;
 254 } Reg;
 255
 256 #define COREREG(KERNELNAME, QEMUFIELD)                       \
 257     {                                                        \
 258         KVM_REG_ARM | KVM_REG_SIZE_U32 |                     \
 259         KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(KERNELNAME), \
 260         offsetof(CPUARMState, QEMUFIELD)                     \
 261     }
 262
 263 #define VFPSYSREG(R)                                       \
 264     {                                                      \
 265         KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP | \
 266         KVM_REG_ARM_VFP_##R,                               \
 267         offsetof(CPUARMState, vfp.xregs[ARM_VFP_##R])      \
 268     }
 269
 270 /* Like COREREG, but handle fields which are in a uint64_t in CPUARMState. */
 271 #define COREREG64(KERNELNAME, QEMUFIELD)                     \
 272     {                                                        \
 273         KVM_REG_ARM | KVM_REG_SIZE_U32 |                     \
 274         KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(KERNELNAME), \
 275         offsetoflow32(CPUARMState, QEMUFIELD)                \
 276     }
 277
 278 static const Reg regs[] = {
 279     /* R0_usr .. R14_usr */
 280     COREREG(usr_regs.uregs[0], regs[0]),
 281     COREREG(usr_regs.uregs[1], regs[1]),
 282     COREREG(usr_regs.uregs[2], regs[2]),
 283     COREREG(usr_regs.uregs[3], regs[3]),
 284     COREREG(usr_regs.uregs[4], regs[4]),
 285     COREREG(usr_regs.uregs[5], regs[5]),
 286     COREREG(usr_regs.uregs[6], regs[6]),
 287     COREREG(usr_regs.uregs[7], regs[7]),
 288     COREREG(usr_regs.uregs[8], usr_regs[0]),
 289     COREREG(usr_regs.uregs[9], usr_regs[1]),
 290     COREREG(usr_regs.uregs[10], usr_regs[2]),
 291     COREREG(usr_regs.uregs[11], usr_regs[3]),
 292     COREREG(usr_regs.uregs[12], usr_regs[4]),
 293     COREREG(usr_regs.uregs[13], banked_r13[BANK_USRSYS]),
 294     COREREG(usr_regs.uregs[14], banked_r14[BANK_USRSYS]),
 295     /* R13, R14, SPSR for SVC, ABT, UND, IRQ banks */
 296     COREREG(svc_regs[0], banked_r13[BANK_SVC]),
 297     COREREG(svc_regs[1], banked_r14[BANK_SVC]),
 298     COREREG64(svc_regs[2], banked_spsr[BANK_SVC]),
 299     COREREG(abt_regs[0], banked_r13[BANK_ABT]),
 300     COREREG(abt_regs[1], banked_r14[BANK_ABT]),
 301     COREREG64(abt_regs[2], banked_spsr[BANK_ABT]),
 302     COREREG(und_regs[0], banked_r13[BANK_UND]),
 303     COREREG(und_regs[1], banked_r14[BANK_UND]),
 304     COREREG64(und_regs[2], banked_spsr[BANK_UND]),
 305     COREREG(irq_regs[0], banked_r13[BANK_IRQ]),
 306     COREREG(irq_regs[1], banked_r14[BANK_IRQ]),
 307     COREREG64(irq_regs[2], banked_spsr[BANK_IRQ]),
 308     /* R8_fiq .. R14_fiq and SPSR_fiq */
 309     COREREG(fiq_regs[0], fiq_regs[0]),
 310     COREREG(fiq_regs[1], fiq_regs[1]),
 311     COREREG(fiq_regs[2], fiq_regs[2]),
 312     COREREG(fiq_regs[3], fiq_regs[3]),
 313     COREREG(fiq_regs[4], fiq_regs[4]),
 314     COREREG(fiq_regs[5], banked_r13[BANK_FIQ]),
 315     COREREG(fiq_regs[6], banked_r14[BANK_FIQ]),
 316     COREREG64(fiq_regs[7], banked_spsr[BANK_FIQ]),
 317     /* R15 */
 318     COREREG(usr_regs.uregs[15], regs[15]),
 319     /* VFP system registers */
 320     VFPSYSREG(FPSID),
 321     VFPSYSREG(MVFR1),
 322     VFPSYSREG(MVFR0),
 323     VFPSYSREG(FPEXC),
 324     VFPSYSREG(FPINST),
 325     VFPSYSREG(FPINST2),
 326 };
 327
 328 int kvm_arch_put_registers(CPUState *cs, int level)
 329 {
 330     ARMCPU *cpu = ARM_CPU(cs);
 331     CPUARMState *env = &cpu->env;
 332     struct kvm_one_reg r;
 333     int mode, bn;
 334     int ret, i;
 335     uint32_t cpsr, fpscr;
 336
 337     /* Make sure the banked regs are properly set */
 338     mode = env->uncached_cpsr & CPSR_M;
 339     bn = bank_number(mode);
 340     if (mode == ARM_CPU_MODE_FIQ) {
 341         memcpy(env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
 342     } else {
 343         memcpy(env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
 344     }
 345     env->banked_r13[bn] = env->regs[13];
 346     env->banked_spsr[bn] = env->spsr;
 347     env->banked_r14[r14_bank_number(mode)] = env->regs[14];
 348
 349     /* Now we can safely copy stuff down to the kernel */
 350     for (i = 0; i < ARRAY_SIZE(regs); i++) {
 351         r.id = regs[i].id;
 352         r.addr = (uintptr_t)(env) + regs[i].offset;
 353         ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
 354         if (ret) {
 355             return ret;
 356         }
 357     }
 358
 359     /* Special cases which aren't a single CPUARMState field */
 360     cpsr = cpsr_read(env);
 361     r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 |
 362         KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(usr_regs.ARM_cpsr);
 363     r.addr = (uintptr_t)(&cpsr);
 364     ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
 365     if (ret) {
 366         return ret;
 367     }
 368
 369     /* VFP registers */
 370     r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP;
 371     for (i = 0; i < 32; i++) {
 372         r.addr = (uintptr_t)aa32_vfp_dreg(env, i);
 373         ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
 374         if (ret) {
 375             return ret;
 376         }
 377         r.id++;
 378     }
 379
 380     r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP |
 381         KVM_REG_ARM_VFP_FPSCR;
 382     fpscr = vfp_get_fpscr(env);
 383     r.addr = (uintptr_t)&fpscr;
 384     ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
 385     if (ret) {
 386         return ret;
 387     }
 388
 389     ret = kvm_put_vcpu_events(cpu);
 390     if (ret) {
 391         return ret;
 392     }
 393
 394     write_cpustate_to_list(cpu, true);
 395
 396     if (!write_list_to_kvmstate(cpu, level)) {
 397         return EINVAL;
 398     }
 399
 400     kvm_arm_sync_mpstate_to_kvm(cpu);
 401
 402     return ret;
 403 }
 404
 405 int kvm_arch_get_registers(CPUState *cs)
 406 {
 407     ARMCPU *cpu = ARM_CPU(cs);
 408     CPUARMState *env = &cpu->env;
 409     struct kvm_one_reg r;
 410     int mode, bn;
 411     int ret, i;
 412     uint32_t cpsr, fpscr;
 413
 414     for (i = 0; i < ARRAY_SIZE(regs); i++) {
 415         r.id = regs[i].id;
 416         r.addr = (uintptr_t)(env) + regs[i].offset;
 417         ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 418         if (ret) {
 419             return ret;
 420         }
 421     }
 422
 423     /* Special cases which aren't a single CPUARMState field */
 424     r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 |
 425         KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(usr_regs.ARM_cpsr);
 426     r.addr = (uintptr_t)(&cpsr);
 427     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 428     if (ret) {
 429         return ret;
 430     }
 431     cpsr_write(env, cpsr, 0xffffffff, CPSRWriteRaw);
 432
 433     /* Make sure the current mode regs are properly set */
 434     mode = env->uncached_cpsr & CPSR_M;
 435     bn = bank_number(mode);
 436     if (mode == ARM_CPU_MODE_FIQ) {
 437         memcpy(env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
 438     } else {
 439         memcpy(env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
 440     }
 441     env->regs[13] = env->banked_r13[bn];
 442     env->spsr = env->banked_spsr[bn];
 443     env->regs[14] = env->banked_r14[r14_bank_number(mode)];
 444
 445     /* VFP registers */
 446     r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP;
 447     for (i = 0; i < 32; i++) {
 448         r.addr = (uintptr_t)aa32_vfp_dreg(env, i);
 449         ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 450         if (ret) {
 451             return ret;
 452         }
 453         r.id++;
 454     }
 455
 456     r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP |
 457         KVM_REG_ARM_VFP_FPSCR;
 458     r.addr = (uintptr_t)&fpscr;
 459     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 460     if (ret) {
 461         return ret;
 462     }
 463     vfp_set_fpscr(env, fpscr);
 464
 465     ret = kvm_get_vcpu_events(cpu);
 466     if (ret) {
 467         return ret;
 468     }
 469
 470     if (!write_kvmstate_to_list(cpu)) {
 471         return EINVAL;
 472     }
 473     /* Note that it's OK to have registers which aren't in CPUState,
 474      * so we can ignore a failure return here.
 475      */
 476     write_list_to_cpustate(cpu);
 477
 478     kvm_arm_sync_mpstate_to_qemu(cpu);
 479
 480     return 0;
 481 }
 482
 483 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
 484 {
 485     qemu_log_mask(LOG_UNIMP, "%s: guest debug not yet implemented\n", __func__);
 486     return -EINVAL;
 487 }
 488
 489 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
 490 {
 491     qemu_log_mask(LOG_UNIMP, "%s: guest debug not yet implemented\n", __func__);
 492     return -EINVAL;
 493 }
 494
 495 bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit)
 496 {
 497     qemu_log_mask(LOG_UNIMP, "%s: guest debug not yet implemented\n", __func__);
 498     return false;
 499 }
 500
 501 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
 502                                   target_ulong len, int type)
 503 {
 504     qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
 505     return -EINVAL;
 506 }
 507
 508 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
 509                                   target_ulong len, int type)
 510 {
 511     qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
 512     return -EINVAL;
 513 }
 514
 515 void kvm_arch_remove_all_hw_breakpoints(void)
 516 {
 517     qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
 518 }
 519
 520 void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr)
 521 {
 522     qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
 523 }
 524
 525 bool kvm_arm_hw_debug_active(CPUState *cs)
 526 {
 527     return false;
 528 }
 529
 530 void kvm_arm_pmu_set_irq(CPUState *cs, int irq)
 531 {
 532     qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
 533 }
 534
 535 void kvm_arm_pmu_init(CPUState *cs)
 536 {
 537     qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
 538 }