2 * OpenRISC system instructions helper routines
4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
5 * Zhizhou Zhang <etouzh@gmail.com>
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
23 #include "exec/exec-all.h"
24 #include "exec/helper-proto.h"
25 #include "exception.h"
26 #include "sysemu/sysemu.h"
27 #ifndef CONFIG_USER_ONLY
28 #include "hw/boards.h"
31 #define TO_SPR(group, number) (((group) << 11) + (number))
33 void HELPER(mtspr
)(CPUOpenRISCState
*env
, target_ulong spr
, target_ulong rb
)
35 #ifndef CONFIG_USER_ONLY
36 OpenRISCCPU
*cpu
= env_archcpu(env
);
37 CPUState
*cs
= env_cpu(env
);
43 #ifndef CONFIG_USER_ONLY
44 case TO_SPR(0, 11): /* EVBAR */
48 case TO_SPR(0, 16): /* NPC */
49 cpu_restore_state(cs
, GETPC(), true);
50 /* ??? Mirror or1ksim in not trashing delayed branch state
51 when "jumping" to the current instruction. */
59 case TO_SPR(0, 17): /* SR */
63 case TO_SPR(0, 32): /* EPCR */
67 case TO_SPR(0, 48): /* EEAR */
71 case TO_SPR(0, 64): /* ESR */
75 case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */
77 env
->shadow_gpr
[idx
/ 32][idx
% 32] = rb
;
80 case TO_SPR(1, 512) ... TO_SPR(1, 512 + TLB_SIZE
- 1): /* DTLBW0MR 0-127 */
81 idx
= spr
- TO_SPR(1, 512);
82 mr
= env
->tlb
.dtlb
[idx
].mr
;
84 tlb_flush_page(cs
, mr
& TARGET_PAGE_MASK
);
87 tlb_flush_page(cs
, rb
& TARGET_PAGE_MASK
);
89 env
->tlb
.dtlb
[idx
].mr
= rb
;
91 case TO_SPR(1, 640) ... TO_SPR(1, 640 + TLB_SIZE
- 1): /* DTLBW0TR 0-127 */
92 idx
= spr
- TO_SPR(1, 640);
93 env
->tlb
.dtlb
[idx
].tr
= rb
;
95 case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */
96 case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */
97 case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
98 case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
99 case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
100 case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
103 case TO_SPR(2, 512) ... TO_SPR(2, 512 + TLB_SIZE
- 1): /* ITLBW0MR 0-127 */
104 idx
= spr
- TO_SPR(2, 512);
105 mr
= env
->tlb
.itlb
[idx
].mr
;
107 tlb_flush_page(cs
, mr
& TARGET_PAGE_MASK
);
110 tlb_flush_page(cs
, rb
& TARGET_PAGE_MASK
);
112 env
->tlb
.itlb
[idx
].mr
= rb
;
114 case TO_SPR(2, 640) ... TO_SPR(2, 640 + TLB_SIZE
- 1): /* ITLBW0TR 0-127 */
115 idx
= spr
- TO_SPR(2, 640);
116 env
->tlb
.itlb
[idx
].tr
= rb
;
118 case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */
119 case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */
120 case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
121 case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
122 case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
123 case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
126 case TO_SPR(5, 1): /* MACLO */
127 env
->mac
= deposit64(env
->mac
, 0, 32, rb
);
129 case TO_SPR(5, 2): /* MACHI */
130 env
->mac
= deposit64(env
->mac
, 32, 32, rb
);
132 case TO_SPR(8, 0): /* PMR */
134 if (env
->pmr
& PMR_DME
|| env
->pmr
& PMR_SME
) {
135 cpu_restore_state(cs
, GETPC(), true);
138 raise_exception(cpu
, EXCP_HALTED
);
141 case TO_SPR(9, 0): /* PICMR */
144 case TO_SPR(9, 2): /* PICSR */
147 case TO_SPR(10, 0): /* TTMR */
149 if ((env
->ttmr
& TTMR_M
) ^ (rb
& TTMR_M
)) {
150 switch (rb
& TTMR_M
) {
152 cpu_openrisc_count_stop(cpu
);
157 cpu_openrisc_count_start(cpu
);
164 int ip
= env
->ttmr
& TTMR_IP
;
166 if (rb
& TTMR_IP
) { /* Keep IP bit. */
167 env
->ttmr
= (rb
& ~TTMR_IP
) | ip
;
168 } else { /* Clear IP bit. */
169 env
->ttmr
= rb
& ~TTMR_IP
;
170 cs
->interrupt_request
&= ~CPU_INTERRUPT_TIMER
;
173 cpu_openrisc_timer_update(cpu
);
177 case TO_SPR(10, 1): /* TTCR */
178 cpu_openrisc_count_set(cpu
, rb
);
179 cpu_openrisc_timer_update(cpu
);
183 case TO_SPR(0, 20): /* FPCSR */
184 cpu_set_fpcsr(env
, rb
);
189 target_ulong
HELPER(mfspr
)(CPUOpenRISCState
*env
, target_ulong rd
,
192 #ifndef CONFIG_USER_ONLY
193 MachineState
*ms
= MACHINE(qdev_get_machine());
194 OpenRISCCPU
*cpu
= env_archcpu(env
);
195 CPUState
*cs
= env_cpu(env
);
200 #ifndef CONFIG_USER_ONLY
201 case TO_SPR(0, 0): /* VR */
204 case TO_SPR(0, 1): /* UPR */
207 case TO_SPR(0, 2): /* CPUCFGR */
210 case TO_SPR(0, 3): /* DMMUCFGR */
211 return env
->dmmucfgr
;
213 case TO_SPR(0, 4): /* IMMUCFGR */
214 return env
->immucfgr
;
216 case TO_SPR(0, 9): /* VR2 */
219 case TO_SPR(0, 10): /* AVR */
222 case TO_SPR(0, 11): /* EVBAR */
225 case TO_SPR(0, 16): /* NPC (equals PC) */
226 cpu_restore_state(cs
, GETPC(), false);
229 case TO_SPR(0, 17): /* SR */
230 return cpu_get_sr(env
);
232 case TO_SPR(0, 18): /* PPC */
233 cpu_restore_state(cs
, GETPC(), false);
236 case TO_SPR(0, 32): /* EPCR */
239 case TO_SPR(0, 48): /* EEAR */
242 case TO_SPR(0, 64): /* ESR */
245 case TO_SPR(0, 128): /* COREID */
246 return cpu
->parent_obj
.cpu_index
;
248 case TO_SPR(0, 129): /* NUMCORES */
249 return ms
->smp
.max_cpus
;
251 case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */
253 return env
->shadow_gpr
[idx
/ 32][idx
% 32];
255 case TO_SPR(1, 512) ... TO_SPR(1, 512 + TLB_SIZE
- 1): /* DTLBW0MR 0-127 */
256 idx
= spr
- TO_SPR(1, 512);
257 return env
->tlb
.dtlb
[idx
].mr
;
259 case TO_SPR(1, 640) ... TO_SPR(1, 640 + TLB_SIZE
- 1): /* DTLBW0TR 0-127 */
260 idx
= spr
- TO_SPR(1, 640);
261 return env
->tlb
.dtlb
[idx
].tr
;
263 case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */
264 case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */
265 case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
266 case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
267 case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
268 case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
271 case TO_SPR(2, 512) ... TO_SPR(2, 512 + TLB_SIZE
- 1): /* ITLBW0MR 0-127 */
272 idx
= spr
- TO_SPR(2, 512);
273 return env
->tlb
.itlb
[idx
].mr
;
275 case TO_SPR(2, 640) ... TO_SPR(2, 640 + TLB_SIZE
- 1): /* ITLBW0TR 0-127 */
276 idx
= spr
- TO_SPR(2, 640);
277 return env
->tlb
.itlb
[idx
].tr
;
279 case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */
280 case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */
281 case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
282 case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
283 case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
284 case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
287 case TO_SPR(5, 1): /* MACLO */
288 return (uint32_t)env
->mac
;
290 case TO_SPR(5, 2): /* MACHI */
291 return env
->mac
>> 32;
294 case TO_SPR(8, 0): /* PMR */
297 case TO_SPR(9, 0): /* PICMR */
300 case TO_SPR(9, 2): /* PICSR */
303 case TO_SPR(10, 0): /* TTMR */
306 case TO_SPR(10, 1): /* TTCR */
307 cpu_openrisc_count_update(cpu
);
308 return cpu_openrisc_count_get(cpu
);
311 case TO_SPR(0, 20): /* FPCSR */
315 /* for rd is passed in, if rd unchanged, just keep it back. */