2 * LatticeMico32 virtual CPU header.
4 * Copyright (c) 2010 Michael Walle <michael@walle.cc>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
23 #define TARGET_LONG_BITS 32
25 #define CPUArchState struct CPULM32State
27 #include "qemu-common.h"
29 #include "exec/cpu-defs.h"
31 typedef struct CPULM32State CPULM32State
;
33 #define NB_MMU_MODES 1
34 #define TARGET_PAGE_BITS 12
35 static inline int cpu_mmu_index(CPULM32State
*env
, bool ifetch
)
40 #define TARGET_PHYS_ADDR_SPACE_BITS 32
41 #define TARGET_VIRT_ADDR_SPACE_BITS 32
43 /* Exceptions indices */
57 R_R0
= 0, R_R1
, R_R2
, R_R3
, R_R4
, R_R5
, R_R6
, R_R7
, R_R8
, R_R9
, R_R10
,
58 R_R11
, R_R12
, R_R13
, R_R14
, R_R15
, R_R16
, R_R17
, R_R18
, R_R19
, R_R20
,
59 R_R21
, R_R22
, R_R23
, R_R24
, R_R25
, R_R26
, R_R27
, R_R28
, R_R29
, R_R30
,
63 /* Register aliases */
135 LM32_FEATURE_MULTIPLY
= 1,
136 LM32_FEATURE_DIVIDE
= 2,
137 LM32_FEATURE_SHIFT
= 4,
138 LM32_FEATURE_SIGN_EXTEND
= 8,
139 LM32_FEATURE_I_CACHE
= 16,
140 LM32_FEATURE_D_CACHE
= 32,
141 LM32_FEATURE_CYCLE_COUNT
= 64,
145 LM32_FLAG_IGNORE_MSB
= 1,
148 struct CPULM32State
{
149 /* general registers */
152 /* special registers */
153 uint32_t pc
; /* program counter */
154 uint32_t ie
; /* interrupt enable */
155 uint32_t icc
; /* instruction cache control */
156 uint32_t dcc
; /* data cache control */
157 uint32_t cc
; /* cycle counter */
158 uint32_t cfg
; /* configuration */
160 /* debug registers */
161 uint32_t dc
; /* debug control */
162 uint32_t bp
[4]; /* breakpoints */
163 uint32_t wp
[4]; /* watchpoints */
165 struct CPUBreakpoint
*cpu_breakpoint
[4];
166 struct CPUWatchpoint
*cpu_watchpoint
[4];
168 /* Fields up to this point are cleared by a CPU reset */
169 struct {} end_reset_fields
;
173 /* Fields from here on are preserved across CPU reset. */
174 uint32_t eba
; /* exception base address */
175 uint32_t deba
; /* debug exception base address */
177 /* interrupt controller handle for callbacks */
178 DeviceState
*pic_state
;
179 /* JTAG UART handle for callbacks */
180 DeviceState
*juart_state
;
182 /* processor core features */
189 * @env: #CPULM32State
191 * A LatticeMico32 CPU.
201 uint8_t num_interrupts
;
202 uint8_t num_breakpoints
;
203 uint8_t num_watchpoints
;
207 static inline LM32CPU
*lm32_env_get_cpu(CPULM32State
*env
)
209 return container_of(env
, LM32CPU
, env
);
212 #define ENV_GET_CPU(e) CPU(lm32_env_get_cpu(e))
214 #define ENV_OFFSET offsetof(LM32CPU, env)
216 #ifndef CONFIG_USER_ONLY
217 extern const struct VMStateDescription vmstate_lm32_cpu
;
220 void lm32_cpu_do_interrupt(CPUState
*cpu
);
221 bool lm32_cpu_exec_interrupt(CPUState
*cs
, int int_req
);
222 void lm32_cpu_dump_state(CPUState
*cpu
, FILE *f
, fprintf_function cpu_fprintf
,
224 hwaddr
lm32_cpu_get_phys_page_debug(CPUState
*cpu
, vaddr addr
);
225 int lm32_cpu_gdb_read_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
226 int lm32_cpu_gdb_write_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
229 LM32_WP_DISABLED
= 0,
235 static inline lm32_wp_t
lm32_wp_type(uint32_t dc
, int idx
)
238 return (dc
>> (idx
+1)*2) & 0x3;
241 /* you can call this signal handler from your SIGBUS and SIGSEGV
242 signal handlers to inform the virtual CPU of exceptions. non zero
243 is returned if the signal was handled by the virtual CPU. */
244 int cpu_lm32_signal_handler(int host_signum
, void *pinfo
,
246 void lm32_cpu_list(FILE *f
, fprintf_function cpu_fprintf
);
247 void lm32_translate_init(void);
248 void cpu_lm32_set_phys_msb_ignore(CPULM32State
*env
, int value
);
249 void QEMU_NORETURN
raise_exception(CPULM32State
*env
, int index
);
250 void lm32_debug_excp_handler(CPUState
*cs
);
251 void lm32_breakpoint_insert(CPULM32State
*env
, int index
, target_ulong address
);
252 void lm32_breakpoint_remove(CPULM32State
*env
, int index
);
253 void lm32_watchpoint_insert(CPULM32State
*env
, int index
, target_ulong address
,
255 void lm32_watchpoint_remove(CPULM32State
*env
, int index
);
256 bool lm32_cpu_do_semihosting(CPUState
*cs
);
258 #define cpu_init(cpu_model) cpu_generic_init(TYPE_LM32_CPU, cpu_model)
260 #define LM32_CPU_TYPE_SUFFIX "-" TYPE_LM32_CPU
261 #define LM32_CPU_TYPE_NAME(model) model LM32_CPU_TYPE_SUFFIX
263 #define cpu_list lm32_cpu_list
264 #define cpu_signal_handler cpu_lm32_signal_handler
266 int lm32_cpu_handle_mmu_fault(CPUState
*cpu
, vaddr address
, int size
, int rw
,
269 #include "exec/cpu-all.h"
271 static inline void cpu_get_tb_cpu_state(CPULM32State
*env
, target_ulong
*pc
,
272 target_ulong
*cs_base
, uint32_t *flags
)