hw/intc/apic_common.c

   1 /*
   2  *  APIC support - common bits of emulated and KVM kernel model
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *  Copyright (c) 2011      Jan Kiszka, Siemens AG
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qemu/error-report.h"
  23 #include "qemu/module.h"
  24 #include "qapi/error.h"
  25 #include "cpu.h"
  26 #include "qapi/visitor.h"
  27 #include "hw/i386/apic.h"
  28 #include "hw/i386/apic_internal.h"
  29 #include "trace.h"
  30 #include "sysemu/hax.h"
  31 #include "sysemu/kvm.h"
  32 #include "hw/qdev.h"
  33 #include "hw/sysbus.h"
  34
  35 static int apic_irq_delivered;
  36 bool apic_report_tpr_access;
  37
  38 void cpu_set_apic_base(DeviceState *dev, uint64_t val)
  39 {
  40     trace_cpu_set_apic_base(val);
  41
  42     if (dev) {
  43         APICCommonState *s = APIC_COMMON(dev);
  44         APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
  45         /* switching to x2APIC, reset possibly modified xAPIC ID */
  46         if (!(s->apicbase & MSR_IA32_APICBASE_EXTD) &&
  47             (val & MSR_IA32_APICBASE_EXTD)) {
  48             s->id = s->initial_apic_id;
  49         }
  50         info->set_base(s, val);
  51     }
  52 }
  53
  54 uint64_t cpu_get_apic_base(DeviceState *dev)
  55 {
  56     if (dev) {
  57         APICCommonState *s = APIC_COMMON(dev);
  58         trace_cpu_get_apic_base((uint64_t)s->apicbase);
  59         return s->apicbase;
  60     } else {
  61         trace_cpu_get_apic_base(MSR_IA32_APICBASE_BSP);
  62         return MSR_IA32_APICBASE_BSP;
  63     }
  64 }
  65
  66 void cpu_set_apic_tpr(DeviceState *dev, uint8_t val)
  67 {
  68     APICCommonState *s;
  69     APICCommonClass *info;
  70
  71     if (!dev) {
  72         return;
  73     }
  74
  75     s = APIC_COMMON(dev);
  76     info = APIC_COMMON_GET_CLASS(s);
  77
  78     info->set_tpr(s, val);
  79 }
  80
  81 uint8_t cpu_get_apic_tpr(DeviceState *dev)
  82 {
  83     APICCommonState *s;
  84     APICCommonClass *info;
  85
  86     if (!dev) {
  87         return 0;
  88     }
  89
  90     s = APIC_COMMON(dev);
  91     info = APIC_COMMON_GET_CLASS(s);
  92
  93     return info->get_tpr(s);
  94 }
  95
  96 void apic_enable_tpr_access_reporting(DeviceState *dev, bool enable)
  97 {
  98     APICCommonState *s = APIC_COMMON(dev);
  99     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 100
 101     apic_report_tpr_access = enable;
 102     if (info->enable_tpr_reporting) {
 103         info->enable_tpr_reporting(s, enable);
 104     }
 105 }
 106
 107 void apic_enable_vapic(DeviceState *dev, hwaddr paddr)
 108 {
 109     APICCommonState *s = APIC_COMMON(dev);
 110     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 111
 112     s->vapic_paddr = paddr;
 113     info->vapic_base_update(s);
 114 }
 115
 116 void apic_handle_tpr_access_report(DeviceState *dev, target_ulong ip,
 117                                    TPRAccess access)
 118 {
 119     APICCommonState *s = APIC_COMMON(dev);
 120
 121     vapic_report_tpr_access(s->vapic, CPU(s->cpu), ip, access);
 122 }
 123
 124 void apic_report_irq_delivered(int delivered)
 125 {
 126     apic_irq_delivered += delivered;
 127
 128     trace_apic_report_irq_delivered(apic_irq_delivered);
 129 }
 130
 131 void apic_reset_irq_delivered(void)
 132 {
 133     /* Copy this into a local variable to encourage gcc to emit a plain
 134      * register for a sys/sdt.h marker.  For details on this workaround, see:
 135      * https://sourceware.org/bugzilla/show_bug.cgi?id=13296
 136      */
 137     volatile int a_i_d = apic_irq_delivered;
 138     trace_apic_reset_irq_delivered(a_i_d);
 139
 140     apic_irq_delivered = 0;
 141 }
 142
 143 int apic_get_irq_delivered(void)
 144 {
 145     trace_apic_get_irq_delivered(apic_irq_delivered);
 146
 147     return apic_irq_delivered;
 148 }
 149
 150 void apic_deliver_nmi(DeviceState *dev)
 151 {
 152     APICCommonState *s = APIC_COMMON(dev);
 153     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 154
 155     info->external_nmi(s);
 156 }
 157
 158 bool apic_next_timer(APICCommonState *s, int64_t current_time)
 159 {
 160     int64_t d;
 161
 162     /* We need to store the timer state separately to support APIC
 163      * implementations that maintain a non-QEMU timer, e.g. inside the
 164      * host kernel. This open-coded state allows us to migrate between
 165      * both models. */
 166     s->timer_expiry = -1;
 167
 168     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED) {
 169         return false;
 170     }
 171
 172     d = (current_time - s->initial_count_load_time) >> s->count_shift;
 173
 174     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 175         if (!s->initial_count) {
 176             return false;
 177         }
 178         d = ((d / ((uint64_t)s->initial_count + 1)) + 1) *
 179             ((uint64_t)s->initial_count + 1);
 180     } else {
 181         if (d >= s->initial_count) {
 182             return false;
 183         }
 184         d = (uint64_t)s->initial_count + 1;
 185     }
 186     s->next_time = s->initial_count_load_time + (d << s->count_shift);
 187     s->timer_expiry = s->next_time;
 188     return true;
 189 }
 190
 191 void apic_init_reset(DeviceState *dev)
 192 {
 193     APICCommonState *s;
 194     APICCommonClass *info;
 195     int i;
 196
 197     if (!dev) {
 198         return;
 199     }
 200     s = APIC_COMMON(dev);
 201     s->tpr = 0;
 202     s->spurious_vec = 0xff;
 203     s->log_dest = 0;
 204     s->dest_mode = 0xf;
 205     memset(s->isr, 0, sizeof(s->isr));
 206     memset(s->tmr, 0, sizeof(s->tmr));
 207     memset(s->irr, 0, sizeof(s->irr));
 208     for (i = 0; i < APIC_LVT_NB; i++) {
 209         s->lvt[i] = APIC_LVT_MASKED;
 210     }
 211     s->esr = 0;
 212     memset(s->icr, 0, sizeof(s->icr));
 213     s->divide_conf = 0;
 214     s->count_shift = 0;
 215     s->initial_count = 0;
 216     s->initial_count_load_time = 0;
 217     s->next_time = 0;
 218     s->wait_for_sipi = !cpu_is_bsp(s->cpu);
 219
 220     if (s->timer) {
 221         timer_del(s->timer);
 222     }
 223     s->timer_expiry = -1;
 224
 225     info = APIC_COMMON_GET_CLASS(s);
 226     if (info->reset) {
 227         info->reset(s);
 228     }
 229 }
 230
 231 void apic_designate_bsp(DeviceState *dev, bool bsp)
 232 {
 233     if (dev == NULL) {
 234         return;
 235     }
 236
 237     APICCommonState *s = APIC_COMMON(dev);
 238     if (bsp) {
 239         s->apicbase |= MSR_IA32_APICBASE_BSP;
 240     } else {
 241         s->apicbase &= ~MSR_IA32_APICBASE_BSP;
 242     }
 243 }
 244
 245 static void apic_reset_common(DeviceState *dev)
 246 {
 247     APICCommonState *s = APIC_COMMON(dev);
 248     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 249     uint32_t bsp;
 250
 251     bsp = s->apicbase & MSR_IA32_APICBASE_BSP;
 252     s->apicbase = APIC_DEFAULT_ADDRESS | bsp | MSR_IA32_APICBASE_ENABLE;
 253     s->id = s->initial_apic_id;
 254
 255     apic_reset_irq_delivered();
 256
 257     s->vapic_paddr = 0;
 258     info->vapic_base_update(s);
 259
 260     apic_init_reset(dev);
 261 }
 262
 263 /* This function is only used for old state version 1 and 2 */
 264 static int apic_load_old(QEMUFile *f, void *opaque, int version_id)
 265 {
 266     APICCommonState *s = opaque;
 267     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 268     int i;
 269
 270     if (version_id > 2) {
 271         return -EINVAL;
 272     }
 273
 274     /* XXX: what if the base changes? (registered memory regions) */
 275     qemu_get_be32s(f, &s->apicbase);
 276     qemu_get_8s(f, &s->id);
 277     qemu_get_8s(f, &s->arb_id);
 278     qemu_get_8s(f, &s->tpr);
 279     qemu_get_be32s(f, &s->spurious_vec);
 280     qemu_get_8s(f, &s->log_dest);
 281     qemu_get_8s(f, &s->dest_mode);
 282     for (i = 0; i < 8; i++) {
 283         qemu_get_be32s(f, &s->isr[i]);
 284         qemu_get_be32s(f, &s->tmr[i]);
 285         qemu_get_be32s(f, &s->irr[i]);
 286     }
 287     for (i = 0; i < APIC_LVT_NB; i++) {
 288         qemu_get_be32s(f, &s->lvt[i]);
 289     }
 290     qemu_get_be32s(f, &s->esr);
 291     qemu_get_be32s(f, &s->icr[0]);
 292     qemu_get_be32s(f, &s->icr[1]);
 293     qemu_get_be32s(f, &s->divide_conf);
 294     s->count_shift = qemu_get_be32(f);
 295     qemu_get_be32s(f, &s->initial_count);
 296     s->initial_count_load_time = qemu_get_be64(f);
 297     s->next_time = qemu_get_be64(f);
 298
 299     if (version_id >= 2) {
 300         s->timer_expiry = qemu_get_be64(f);
 301     }
 302
 303     if (info->post_load) {
 304         info->post_load(s);
 305     }
 306     return 0;
 307 }
 308
 309 static const VMStateDescription vmstate_apic_common;
 310
 311 static void apic_common_realize(DeviceState *dev, Error **errp)
 312 {
 313     APICCommonState *s = APIC_COMMON(dev);
 314     APICCommonClass *info;
 315     static DeviceState *vapic;
 316     int instance_id = s->id;
 317
 318     info = APIC_COMMON_GET_CLASS(s);
 319     info->realize(dev, errp);
 320
 321     /* Note: We need at least 1M to map the VAPIC option ROM */
 322     if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK &&
 323         !hax_enabled() && ram_size >= 1024 * 1024) {
 324         vapic = sysbus_create_simple("kvmvapic", -1, NULL);
 325     }
 326     s->vapic = vapic;
 327     if (apic_report_tpr_access && info->enable_tpr_reporting) {
 328         info->enable_tpr_reporting(s, true);
 329     }
 330
 331     if (s->legacy_instance_id) {
 332         instance_id = -1;
 333     }
 334     vmstate_register_with_alias_id(NULL, instance_id, &vmstate_apic_common,
 335                                    s, -1, 0, NULL);
 336 }
 337
 338 static void apic_common_unrealize(DeviceState *dev, Error **errp)
 339 {
 340     APICCommonState *s = APIC_COMMON(dev);
 341     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 342
 343     vmstate_unregister(NULL, &vmstate_apic_common, s);
 344     info->unrealize(dev, errp);
 345
 346     if (apic_report_tpr_access && info->enable_tpr_reporting) {
 347         info->enable_tpr_reporting(s, false);
 348     }
 349 }
 350
 351 static int apic_pre_load(void *opaque)
 352 {
 353     APICCommonState *s = APIC_COMMON(opaque);
 354
 355     /* The default is !cpu_is_bsp(s->cpu), but the common value is 0
 356      * so that's what apic_common_sipi_needed checks for.  Reset to
 357      * the value that is assumed when the apic_sipi subsection is
 358      * absent.
 359      */
 360     s->wait_for_sipi = 0;
 361     return 0;
 362 }
 363
 364 static int apic_dispatch_pre_save(void *opaque)
 365 {
 366     APICCommonState *s = APIC_COMMON(opaque);
 367     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 368
 369     if (info->pre_save) {
 370         info->pre_save(s);
 371     }
 372
 373     return 0;
 374 }
 375
 376 static int apic_dispatch_post_load(void *opaque, int version_id)
 377 {
 378     APICCommonState *s = APIC_COMMON(opaque);
 379     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 380
 381     if (info->post_load) {
 382         info->post_load(s);
 383     }
 384     return 0;
 385 }
 386
 387 static bool apic_common_sipi_needed(void *opaque)
 388 {
 389     APICCommonState *s = APIC_COMMON(opaque);
 390     return s->wait_for_sipi != 0;
 391 }
 392
 393 static const VMStateDescription vmstate_apic_common_sipi = {
 394     .name = "apic_sipi",
 395     .version_id = 1,
 396     .minimum_version_id = 1,
 397     .needed = apic_common_sipi_needed,
 398     .fields = (VMStateField[]) {
 399         VMSTATE_INT32(sipi_vector, APICCommonState),
 400         VMSTATE_INT32(wait_for_sipi, APICCommonState),
 401         VMSTATE_END_OF_LIST()
 402     }
 403 };
 404
 405 static const VMStateDescription vmstate_apic_common = {
 406     .name = "apic",
 407     .version_id = 3,
 408     .minimum_version_id = 3,
 409     .minimum_version_id_old = 1,
 410     .load_state_old = apic_load_old,
 411     .pre_load = apic_pre_load,
 412     .pre_save = apic_dispatch_pre_save,
 413     .post_load = apic_dispatch_post_load,
 414     .fields = (VMStateField[]) {
 415         VMSTATE_UINT32(apicbase, APICCommonState),
 416         VMSTATE_UINT8(id, APICCommonState),
 417         VMSTATE_UINT8(arb_id, APICCommonState),
 418         VMSTATE_UINT8(tpr, APICCommonState),
 419         VMSTATE_UINT32(spurious_vec, APICCommonState),
 420         VMSTATE_UINT8(log_dest, APICCommonState),
 421         VMSTATE_UINT8(dest_mode, APICCommonState),
 422         VMSTATE_UINT32_ARRAY(isr, APICCommonState, 8),
 423         VMSTATE_UINT32_ARRAY(tmr, APICCommonState, 8),
 424         VMSTATE_UINT32_ARRAY(irr, APICCommonState, 8),
 425         VMSTATE_UINT32_ARRAY(lvt, APICCommonState, APIC_LVT_NB),
 426         VMSTATE_UINT32(esr, APICCommonState),
 427         VMSTATE_UINT32_ARRAY(icr, APICCommonState, 2),
 428         VMSTATE_UINT32(divide_conf, APICCommonState),
 429         VMSTATE_INT32(count_shift, APICCommonState),
 430         VMSTATE_UINT32(initial_count, APICCommonState),
 431         VMSTATE_INT64(initial_count_load_time, APICCommonState),
 432         VMSTATE_INT64(next_time, APICCommonState),
 433         VMSTATE_INT64(timer_expiry,
 434                       APICCommonState), /* open-coded timer state */
 435         VMSTATE_END_OF_LIST()
 436     },
 437     .subsections = (const VMStateDescription*[]) {
 438         &vmstate_apic_common_sipi,
 439         NULL
 440     }
 441 };
 442
 443 static Property apic_properties_common[] = {
 444     DEFINE_PROP_UINT8("version", APICCommonState, version, 0x14),
 445     DEFINE_PROP_BIT("vapic", APICCommonState, vapic_control, VAPIC_ENABLE_BIT,
 446                     true),
 447     DEFINE_PROP_BOOL("legacy-instance-id", APICCommonState, legacy_instance_id,
 448                      false),
 449     DEFINE_PROP_END_OF_LIST(),
 450 };
 451
 452 static void apic_common_get_id(Object *obj, Visitor *v, const char *name,
 453                                void *opaque, Error **errp)
 454 {
 455     APICCommonState *s = APIC_COMMON(obj);
 456     uint32_t value;
 457
 458     value = s->apicbase & MSR_IA32_APICBASE_EXTD ? s->initial_apic_id : s->id;
 459     visit_type_uint32(v, name, &value, errp);
 460 }
 461
 462 static void apic_common_set_id(Object *obj, Visitor *v, const char *name,
 463                                void *opaque, Error **errp)
 464 {
 465     APICCommonState *s = APIC_COMMON(obj);
 466     DeviceState *dev = DEVICE(obj);
 467     Error *local_err = NULL;
 468     uint32_t value;
 469
 470     if (dev->realized) {
 471         qdev_prop_set_after_realize(dev, name, errp);
 472         return;
 473     }
 474
 475     visit_type_uint32(v, name, &value, &local_err);
 476     if (local_err) {
 477         error_propagate(errp, local_err);
 478         return;
 479     }
 480
 481     s->initial_apic_id = value;
 482     s->id = (uint8_t)value;
 483 }
 484
 485 static void apic_common_initfn(Object *obj)
 486 {
 487     APICCommonState *s = APIC_COMMON(obj);
 488
 489     s->id = s->initial_apic_id = -1;
 490     object_property_add(obj, "id", "uint32",
 491                         apic_common_get_id,
 492                         apic_common_set_id, NULL, NULL, NULL);
 493 }
 494
 495 static void apic_common_class_init(ObjectClass *klass, void *data)
 496 {
 497     DeviceClass *dc = DEVICE_CLASS(klass);
 498
 499     dc->reset = apic_reset_common;
 500     dc->props = apic_properties_common;
 501     dc->realize = apic_common_realize;
 502     dc->unrealize = apic_common_unrealize;
 503     /*
 504      * Reason: APIC and CPU need to be wired up by
 505      * x86_cpu_apic_create()
 506      */
 507     dc->user_creatable = false;
 508 }
 509
 510 static const TypeInfo apic_common_type = {
 511     .name = TYPE_APIC_COMMON,
 512     .parent = TYPE_DEVICE,
 513     .instance_size = sizeof(APICCommonState),
 514     .instance_init = apic_common_initfn,
 515     .class_size = sizeof(APICCommonClass),
 516     .class_init = apic_common_class_init,
 517     .abstract = true,
 518 };
 519
 520 static void apic_common_register_types(void)
 521 {
 522     type_register_static(&apic_common_type);
 523 }
 524
 525 type_init(apic_common_register_types)