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hw/bt: Remove HCIInfo from "qemu/typedefs.h"
[qemu/ar7.git] / hw / ppc / pnv.c
blobd84acef55b691900c2b92e7e9c04b4f8707bb3b4
1 /*
2 * QEMU PowerPC PowerNV machine model
3 *
4 * Copyright (c) 2016, IBM Corporation.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu/units.h"
22 #include "qapi/error.h"
23 #include "sysemu/sysemu.h"
24 #include "sysemu/numa.h"
25 #include "sysemu/cpus.h"
26 #include "hw/hw.h"
27 #include "target/ppc/cpu.h"
28 #include "qemu/log.h"
29 #include "hw/ppc/fdt.h"
30 #include "hw/ppc/ppc.h"
31 #include "hw/ppc/pnv.h"
32 #include "hw/ppc/pnv_core.h"
33 #include "hw/loader.h"
34 #include "exec/address-spaces.h"
35 #include "qapi/visitor.h"
36 #include "monitor/monitor.h"
37 #include "hw/intc/intc.h"
38 #include "hw/ipmi/ipmi.h"
39 #include "target/ppc/mmu-hash64.h"
40
41 #include "hw/ppc/xics.h"
42 #include "hw/ppc/pnv_xscom.h"
43
44 #include "hw/isa/isa.h"
45 #include "hw/char/serial.h"
46 #include "hw/timer/mc146818rtc.h"
47
48 #include <libfdt.h>
49
50 #define FDT_MAX_SIZE 0x00100000
51
52 #define FW_FILE_NAME "skiboot.lid"
53 #define FW_LOAD_ADDR 0x0
54 #define FW_MAX_SIZE 0x00400000
55
56 #define KERNEL_LOAD_ADDR 0x20000000
57 #define INITRD_LOAD_ADDR 0x60000000
58
59 static const char *pnv_chip_core_typename(const PnvChip *o)
60 {
61 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o)));
62 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX);
63 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type);
64 const char *core_type = object_class_get_name(object_class_by_name(s));
65 g_free(s);
66 return core_type;
67 }
68
69 /*
70 * On Power Systems E880 (POWER8), the max cpus (threads) should be :
71 * 4 * 4 sockets * 12 cores * 8 threads = 1536
72 * Let's make it 2^11
73 */
74 #define MAX_CPUS 2048
75
76 /*
77 * Memory nodes are created by hostboot, one for each range of memory
78 * that has a different "affinity". In practice, it means one range
79 * per chip.
80 */
81 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size)
82 {
83 char *mem_name;
84 uint64_t mem_reg_property[2];
85 int off;
86
87 mem_reg_property[0] = cpu_to_be64(start);
88 mem_reg_property[1] = cpu_to_be64(size);
89
90 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start);
91 off = fdt_add_subnode(fdt, 0, mem_name);
92 g_free(mem_name);
93
94 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
95 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
96 sizeof(mem_reg_property))));
97 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id)));
98 }
99
100 static int get_cpus_node(void *fdt)
101 {
102 int cpus_offset = fdt_path_offset(fdt, "/cpus");
103
104 if (cpus_offset < 0) {
105 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
106 if (cpus_offset) {
107 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
108 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
109 }
110 }
111 _FDT(cpus_offset);
112 return cpus_offset;
113 }
114
115 /*
116 * The PowerNV cores (and threads) need to use real HW ids and not an
117 * incremental index like it has been done on other platforms. This HW
118 * id is stored in the CPU PIR, it is used to create cpu nodes in the
119 * device tree, used in XSCOM to address cores and in interrupt
120 * servers.
121 */
122 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
123 {
124 PowerPCCPU *cpu = pc->threads[0];
125 CPUState *cs = CPU(cpu);
126 DeviceClass *dc = DEVICE_GET_CLASS(cs);
127 int smt_threads = CPU_CORE(pc)->nr_threads;
128 CPUPPCState *env = &cpu->env;
129 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
130 uint32_t servers_prop[smt_threads];
131 int i;
132 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
133 0xffffffff, 0xffffffff};
134 uint32_t tbfreq = PNV_TIMEBASE_FREQ;
135 uint32_t cpufreq = 1000000000;
136 uint32_t page_sizes_prop[64];
137 size_t page_sizes_prop_size;
138 const uint8_t pa_features[] = { 24, 0,
139 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
140 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
141 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
142 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
143 int offset;
144 char *nodename;
145 int cpus_offset = get_cpus_node(fdt);
146
147 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir);
148 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
149 _FDT(offset);
150 g_free(nodename);
151
152 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id)));
153
154 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir)));
155 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir)));
156 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
157
158 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
159 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
160 env->dcache_line_size)));
161 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
162 env->dcache_line_size)));
163 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
164 env->icache_line_size)));
165 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
166 env->icache_line_size)));
167
168 if (pcc->l1_dcache_size) {
169 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
170 pcc->l1_dcache_size)));
171 } else {
172 warn_report("Unknown L1 dcache size for cpu");
173 }
174 if (pcc->l1_icache_size) {
175 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
176 pcc->l1_icache_size)));
177 } else {
178 warn_report("Unknown L1 icache size for cpu");
179 }
180
181 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
182 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
183 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size)));
184 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
185 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
186
187 if (env->spr_cb[SPR_PURR].oea_read) {
188 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
189 }
190
191 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) {
192 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
193 segs, sizeof(segs))));
194 }
195
196 /* Advertise VMX/VSX (vector extensions) if available
197 * 0 / no property == no vector extensions
198 * 1 == VMX / Altivec available
199 * 2 == VSX available */
200 if (env->insns_flags & PPC_ALTIVEC) {
201 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
202
203 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
204 }
205
206 /* Advertise DFP (Decimal Floating Point) if available
207 * 0 / no property == no DFP
208 * 1 == DFP available */
209 if (env->insns_flags2 & PPC2_DFP) {
210 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
211 }
212
213 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
214 sizeof(page_sizes_prop));
215 if (page_sizes_prop_size) {
216 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
217 page_sizes_prop, page_sizes_prop_size)));
218 }
219
220 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
221 pa_features, sizeof(pa_features))));
222
223 /* Build interrupt servers properties */
224 for (i = 0; i < smt_threads; i++) {
225 servers_prop[i] = cpu_to_be32(pc->pir + i);
226 }
227 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
228 servers_prop, sizeof(servers_prop))));
229 }
230
231 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir,
232 uint32_t nr_threads)
233 {
234 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12);
235 char *name;
236 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp";
237 uint32_t irange[2], i, rsize;
238 uint64_t *reg;
239 int offset;
240
241 irange[0] = cpu_to_be32(pir);
242 irange[1] = cpu_to_be32(nr_threads);
243
244 rsize = sizeof(uint64_t) * 2 * nr_threads;
245 reg = g_malloc(rsize);
246 for (i = 0; i < nr_threads; i++) {
247 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000));
248 reg[i * 2 + 1] = cpu_to_be64(0x1000);
249 }
250
251 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr);
252 offset = fdt_add_subnode(fdt, 0, name);
253 _FDT(offset);
254 g_free(name);
255
256 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat))));
257 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize)));
258 _FDT((fdt_setprop_string(fdt, offset, "device_type",
259 "PowerPC-External-Interrupt-Presentation")));
260 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0)));
261 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges",
262 irange, sizeof(irange))));
263 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1)));
264 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0)));
265 g_free(reg);
266 }
267
268 static void pnv_dt_chip(PnvChip *chip, void *fdt)
269 {
270 const char *typename = pnv_chip_core_typename(chip);
271 size_t typesize = object_type_get_instance_size(typename);
272 int i;
273
274 pnv_dt_xscom(chip, fdt, 0);
275
276 for (i = 0; i < chip->nr_cores; i++) {
277 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize);
278
279 pnv_dt_core(chip, pnv_core, fdt);
280
281 /* Interrupt Control Presenters (ICP). One per core. */
282 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads);
283 }
284
285 if (chip->ram_size) {
286 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
287 }
288 }
289
290 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off)
291 {
292 uint32_t io_base = d->ioport_id;
293 uint32_t io_regs[] = {
294 cpu_to_be32(1),
295 cpu_to_be32(io_base),
296 cpu_to_be32(2)
297 };
298 char *name;
299 int node;
300
301 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
302 node = fdt_add_subnode(fdt, lpc_off, name);
303 _FDT(node);
304 g_free(name);
305
306 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
307 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00")));
308 }
309
310 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off)
311 {
312 const char compatible[] = "ns16550\0pnpPNP,501";
313 uint32_t io_base = d->ioport_id;
314 uint32_t io_regs[] = {
315 cpu_to_be32(1),
316 cpu_to_be32(io_base),
317 cpu_to_be32(8)
318 };
319 char *name;
320 int node;
321
322 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
323 node = fdt_add_subnode(fdt, lpc_off, name);
324 _FDT(node);
325 g_free(name);
326
327 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
328 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
329 sizeof(compatible))));
330
331 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200)));
332 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200)));
333 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0])));
334 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
335 fdt_get_phandle(fdt, lpc_off))));
336
337 /* This is needed by Linux */
338 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial")));
339 }
340
341 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off)
342 {
343 const char compatible[] = "bt\0ipmi-bt";
344 uint32_t io_base;
345 uint32_t io_regs[] = {
346 cpu_to_be32(1),
347 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */
348 cpu_to_be32(3)
349 };
350 uint32_t irq;
351 char *name;
352 int node;
353
354 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal);
355 io_regs[1] = cpu_to_be32(io_base);
356
357 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal);
358
359 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
360 node = fdt_add_subnode(fdt, lpc_off, name);
361 _FDT(node);
362 g_free(name);
363
364 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
365 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
366 sizeof(compatible))));
367
368 /* Mark it as reserved to avoid Linux trying to claim it */
369 _FDT((fdt_setprop_string(fdt, node, "status", "reserved")));
370 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq)));
371 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
372 fdt_get_phandle(fdt, lpc_off))));
373 }
374
375 typedef struct ForeachPopulateArgs {
376 void *fdt;
377 int offset;
378 } ForeachPopulateArgs;
379
380 static int pnv_dt_isa_device(DeviceState *dev, void *opaque)
381 {
382 ForeachPopulateArgs *args = opaque;
383 ISADevice *d = ISA_DEVICE(dev);
384
385 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) {
386 pnv_dt_rtc(d, args->fdt, args->offset);
387 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) {
388 pnv_dt_serial(d, args->fdt, args->offset);
389 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) {
390 pnv_dt_ipmi_bt(d, args->fdt, args->offset);
391 } else {
392 error_report("unknown isa device %s@i%x", qdev_fw_name(dev),
393 d->ioport_id);
394 }
395
396 return 0;
397 }
398
399 static int pnv_chip_isa_offset(PnvChip *chip, void *fdt)
400 {
401 char *name;
402 int offset;
403
404 name = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x",
405 (uint64_t) PNV_XSCOM_BASE(chip), PNV_XSCOM_LPC_BASE);
406 offset = fdt_path_offset(fdt, name);
407 g_free(name);
408 return offset;
409 }
410
411 /* The default LPC bus of a multichip system is on chip 0. It's
412 * recognized by the firmware (skiboot) using a "primary" property.
413 */
414 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt)
415 {
416 int isa_offset = pnv_chip_isa_offset(pnv->chips[0], fdt);
417 ForeachPopulateArgs args = {
418 .fdt = fdt,
419 .offset = isa_offset,
420 };
421
422 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0)));
423
424 /* ISA devices are not necessarily parented to the ISA bus so we
425 * can not use object_child_foreach() */
426 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL,
427 &args);
428 }
429
430 static void *pnv_dt_create(MachineState *machine)
431 {
432 const char plat_compat[] = "qemu,powernv\0ibm,powernv";
433 PnvMachineState *pnv = PNV_MACHINE(machine);
434 void *fdt;
435 char *buf;
436 int off;
437 int i;
438
439 fdt = g_malloc0(FDT_MAX_SIZE);
440 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
441
442 /* Root node */
443 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2)));
444 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2)));
445 _FDT((fdt_setprop_string(fdt, 0, "model",
446 "IBM PowerNV (emulated by qemu)")));
447 _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat,
448 sizeof(plat_compat))));
449
450 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
451 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf)));
452 if (qemu_uuid_set) {
453 _FDT((fdt_property_string(fdt, "system-id", buf)));
454 }
455 g_free(buf);
456
457 off = fdt_add_subnode(fdt, 0, "chosen");
458 if (machine->kernel_cmdline) {
459 _FDT((fdt_setprop_string(fdt, off, "bootargs",
460 machine->kernel_cmdline)));
461 }
462
463 if (pnv->initrd_size) {
464 uint32_t start_prop = cpu_to_be32(pnv->initrd_base);
465 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size);
466
467 _FDT((fdt_setprop(fdt, off, "linux,initrd-start",
468 &start_prop, sizeof(start_prop))));
469 _FDT((fdt_setprop(fdt, off, "linux,initrd-end",
470 &end_prop, sizeof(end_prop))));
471 }
472
473 /* Populate device tree for each chip */
474 for (i = 0; i < pnv->num_chips; i++) {
475 pnv_dt_chip(pnv->chips[i], fdt);
476 }
477
478 /* Populate ISA devices on chip 0 */
479 pnv_dt_isa(pnv, fdt);
480
481 if (pnv->bmc) {
482 pnv_dt_bmc_sensors(pnv->bmc, fdt);
483 }
484
485 return fdt;
486 }
487
488 static void pnv_powerdown_notify(Notifier *n, void *opaque)
489 {
490 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
491
492 if (pnv->bmc) {
493 pnv_bmc_powerdown(pnv->bmc);
494 }
495 }
496
497 static void pnv_reset(void)
498 {
499 MachineState *machine = MACHINE(qdev_get_machine());
500 PnvMachineState *pnv = PNV_MACHINE(machine);
501 void *fdt;
502 Object *obj;
503
504 qemu_devices_reset();
505
506 /* OpenPOWER systems have a BMC, which can be defined on the
507 * command line with:
508 *
509 * -device ipmi-bmc-sim,id=bmc0
510 *
511 * This is the internal simulator but it could also be an external
512 * BMC.
513 */
514 obj = object_resolve_path_type("", "ipmi-bmc-sim", NULL);
515 if (obj) {
516 pnv->bmc = IPMI_BMC(obj);
517 }
518
519 fdt = pnv_dt_create(machine);
520
521 /* Pack resulting tree */
522 _FDT((fdt_pack(fdt)));
523
524 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt));
525 }
526
527 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp)
528 {
529 Pnv8Chip *chip8 = PNV8_CHIP(chip);
530 return pnv_lpc_isa_create(&chip8->lpc, true, errp);
531 }
532
533 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp)
534 {
535 Pnv8Chip *chip8 = PNV8_CHIP(chip);
536 return pnv_lpc_isa_create(&chip8->lpc, false, errp);
537 }
538
539 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp)
540 {
541 return NULL;
542 }
543
544 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp)
545 {
546 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp);
547 }
548
549 static void pnv_init(MachineState *machine)
550 {
551 PnvMachineState *pnv = PNV_MACHINE(machine);
552 MemoryRegion *ram;
553 char *fw_filename;
554 long fw_size;
555 int i;
556 char *chip_typename;
557
558 /* allocate RAM */
559 if (machine->ram_size < (1 * GiB)) {
560 warn_report("skiboot may not work with < 1GB of RAM");
561 }
562
563 ram = g_new(MemoryRegion, 1);
564 memory_region_allocate_system_memory(ram, NULL, "pnv.ram",
565 machine->ram_size);
566 memory_region_add_subregion(get_system_memory(), 0, ram);
567
568 /* load skiboot firmware */
569 if (bios_name == NULL) {
570 bios_name = FW_FILE_NAME;
571 }
572
573 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
574 if (!fw_filename) {
575 error_report("Could not find OPAL firmware '%s'", bios_name);
576 exit(1);
577 }
578
579 fw_size = load_image_targphys(fw_filename, FW_LOAD_ADDR, FW_MAX_SIZE);
580 if (fw_size < 0) {
581 error_report("Could not load OPAL firmware '%s'", fw_filename);
582 exit(1);
583 }
584 g_free(fw_filename);
585
586 /* load kernel */
587 if (machine->kernel_filename) {
588 long kernel_size;
589
590 kernel_size = load_image_targphys(machine->kernel_filename,
591 KERNEL_LOAD_ADDR, 0x2000000);
592 if (kernel_size < 0) {
593 error_report("Could not load kernel '%s'",
594 machine->kernel_filename);
595 exit(1);
596 }
597 }
598
599 /* load initrd */
600 if (machine->initrd_filename) {
601 pnv->initrd_base = INITRD_LOAD_ADDR;
602 pnv->initrd_size = load_image_targphys(machine->initrd_filename,
603 pnv->initrd_base, 0x10000000); /* 128MB max */
604 if (pnv->initrd_size < 0) {
605 error_report("Could not load initial ram disk '%s'",
606 machine->initrd_filename);
607 exit(1);
608 }
609 }
610
611 /* Create the processor chips */
612 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
613 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"),
614 i, machine->cpu_type);
615 if (!object_class_by_name(chip_typename)) {
616 error_report("invalid CPU model '%.*s' for %s machine",
617 i, machine->cpu_type, MACHINE_GET_CLASS(machine)->name);
618 exit(1);
619 }
620
621 pnv->chips = g_new0(PnvChip *, pnv->num_chips);
622 for (i = 0; i < pnv->num_chips; i++) {
623 char chip_name[32];
624 Object *chip = object_new(chip_typename);
625
626 pnv->chips[i] = PNV_CHIP(chip);
627
628 /* TODO: put all the memory in one node on chip 0 until we find a
629 * way to specify different ranges for each chip
630 */
631 if (i == 0) {
632 object_property_set_int(chip, machine->ram_size, "ram-size",
633 &error_fatal);
634 }
635
636 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i));
637 object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal);
638 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id",
639 &error_fatal);
640 object_property_set_int(chip, smp_cores, "nr-cores", &error_fatal);
641 object_property_set_bool(chip, true, "realized", &error_fatal);
642 }
643 g_free(chip_typename);
644
645 /* Instantiate ISA bus on chip 0 */
646 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal);
647
648 /* Create serial port */
649 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS);
650
651 /* Create an RTC ISA device too */
652 mc146818_rtc_init(pnv->isa_bus, 2000, NULL);
653
654 /* OpenPOWER systems use a IPMI SEL Event message to notify the
655 * host to powerdown */
656 pnv->powerdown_notifier.notify = pnv_powerdown_notify;
657 qemu_register_powerdown_notifier(&pnv->powerdown_notifier);
658 }
659
660 /*
661 * 0:21 Reserved - Read as zeros
662 * 22:24 Chip ID
663 * 25:28 Core number
664 * 29:31 Thread ID
665 */
666 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id)
667 {
668 return (chip->chip_id << 7) | (core_id << 3);
669 }
670
671 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu,
672 Error **errp)
673 {
674 Error *local_err = NULL;
675 Object *obj;
676
677 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, XICS_FABRIC(qdev_get_machine()),
678 &local_err);
679 if (local_err) {
680 error_propagate(errp, local_err);
681 return;
682 }
683
684 cpu->icp = ICP(obj);
685 }
686
687 /*
688 * 0:48 Reserved - Read as zeroes
689 * 49:52 Node ID
690 * 53:55 Chip ID
691 * 56 Reserved - Read as zero
692 * 57:61 Core number
693 * 62:63 Thread ID
694 *
695 * We only care about the lower bits. uint32_t is fine for the moment.
696 */
697 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id)
698 {
699 return (chip->chip_id << 8) | (core_id << 2);
700 }
701
702 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu,
703 Error **errp)
704 {
705 return;
706 }
707
708 /* Allowed core identifiers on a POWER8 Processor Chip :
709 *
710 * <EX0 reserved>
711 * EX1 - Venice only
712 * EX2 - Venice only
713 * EX3 - Venice only
714 * EX4
715 * EX5
716 * EX6
717 * <EX7,8 reserved> <reserved>
718 * EX9 - Venice only
719 * EX10 - Venice only
720 * EX11 - Venice only
721 * EX12
722 * EX13
723 * EX14
724 * <EX15 reserved>
725 */
726 #define POWER8E_CORE_MASK (0x7070ull)
727 #define POWER8_CORE_MASK (0x7e7eull)
728
729 /*
730 * POWER9 has 24 cores, ids starting at 0x0
731 */
732 #define POWER9_CORE_MASK (0xffffffffffffffull)
733
734 static void pnv_chip_power8_instance_init(Object *obj)
735 {
736 Pnv8Chip *chip8 = PNV8_CHIP(obj);
737
738 object_initialize(&chip8->psi, sizeof(chip8->psi), TYPE_PNV_PSI);
739 object_property_add_child(obj, "psi", OBJECT(&chip8->psi), NULL);
740 object_property_add_const_link(OBJECT(&chip8->psi), "xics",
741 OBJECT(qdev_get_machine()), &error_abort);
742
743 object_initialize(&chip8->lpc, sizeof(chip8->lpc), TYPE_PNV_LPC);
744 object_property_add_child(obj, "lpc", OBJECT(&chip8->lpc), NULL);
745 object_property_add_const_link(OBJECT(&chip8->lpc), "psi",
746 OBJECT(&chip8->psi), &error_abort);
747
748 object_initialize(&chip8->occ, sizeof(chip8->occ), TYPE_PNV_OCC);
749 object_property_add_child(obj, "occ", OBJECT(&chip8->occ), NULL);
750 object_property_add_const_link(OBJECT(&chip8->occ), "psi",
751 OBJECT(&chip8->psi), &error_abort);
752 }
753
754 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
755 {
756 PnvChip *chip = PNV_CHIP(chip8);
757 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
758 const char *typename = pnv_chip_core_typename(chip);
759 size_t typesize = object_type_get_instance_size(typename);
760 int i, j;
761 char *name;
762 XICSFabric *xi = XICS_FABRIC(qdev_get_machine());
763
764 name = g_strdup_printf("icp-%x", chip->chip_id);
765 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE);
766 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio);
767 g_free(name);
768
769 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip));
770
771 /* Map the ICP registers for each thread */
772 for (i = 0; i < chip->nr_cores; i++) {
773 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize);
774 int core_hwid = CPU_CORE(pnv_core)->core_id;
775
776 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) {
777 uint32_t pir = pcc->core_pir(chip, core_hwid) + j;
778 PnvICPState *icp = PNV_ICP(xics_icp_get(xi, pir));
779
780 memory_region_add_subregion(&chip8->icp_mmio, pir << 12,
781 &icp->mmio);
782 }
783 }
784 }
785
786 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
787 {
788 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
789 PnvChip *chip = PNV_CHIP(dev);
790 Pnv8Chip *chip8 = PNV8_CHIP(dev);
791 Error *local_err = NULL;
792
793 pcc->parent_realize(dev, &local_err);
794 if (local_err) {
795 error_propagate(errp, local_err);
796 return;
797 }
798
799 /* Processor Service Interface (PSI) Host Bridge */
800 object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip),
801 "bar", &error_fatal);
802 object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local_err);
803 if (local_err) {
804 error_propagate(errp, local_err);
805 return;
806 }
807 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, &chip8->psi.xscom_regs);
808
809 /* Create LPC controller */
810 object_property_set_bool(OBJECT(&chip8->lpc), true, "realized",
811 &error_fatal);
812 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs);
813
814 /* Interrupt Management Area. This is the memory region holding
815 * all the Interrupt Control Presenter (ICP) registers */
816 pnv_chip_icp_realize(chip8, &local_err);
817 if (local_err) {
818 error_propagate(errp, local_err);
819 return;
820 }
821
822 /* Create the simplified OCC model */
823 object_property_set_bool(OBJECT(&chip8->occ), true, "realized", &local_err);
824 if (local_err) {
825 error_propagate(errp, local_err);
826 return;
827 }
828 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs);
829 }
830
831 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
832 {
833 DeviceClass *dc = DEVICE_CLASS(klass);
834 PnvChipClass *k = PNV_CHIP_CLASS(klass);
835
836 k->chip_type = PNV_CHIP_POWER8E;
837 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */
838 k->cores_mask = POWER8E_CORE_MASK;
839 k->core_pir = pnv_chip_core_pir_p8;
840 k->intc_create = pnv_chip_power8_intc_create;
841 k->isa_create = pnv_chip_power8_isa_create;
842 k->xscom_base = 0x003fc0000000000ull;
843 dc->desc = "PowerNV Chip POWER8E";
844
845 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
846 &k->parent_realize);
847 }
848
849 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
850 {
851 DeviceClass *dc = DEVICE_CLASS(klass);
852 PnvChipClass *k = PNV_CHIP_CLASS(klass);
853
854 k->chip_type = PNV_CHIP_POWER8;
855 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
856 k->cores_mask = POWER8_CORE_MASK;
857 k->core_pir = pnv_chip_core_pir_p8;
858 k->intc_create = pnv_chip_power8_intc_create;
859 k->isa_create = pnv_chip_power8_isa_create;
860 k->xscom_base = 0x003fc0000000000ull;
861 dc->desc = "PowerNV Chip POWER8";
862
863 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
864 &k->parent_realize);
865 }
866
867 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
868 {
869 DeviceClass *dc = DEVICE_CLASS(klass);
870 PnvChipClass *k = PNV_CHIP_CLASS(klass);
871
872 k->chip_type = PNV_CHIP_POWER8NVL;
873 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */
874 k->cores_mask = POWER8_CORE_MASK;
875 k->core_pir = pnv_chip_core_pir_p8;
876 k->intc_create = pnv_chip_power8_intc_create;
877 k->isa_create = pnv_chip_power8nvl_isa_create;
878 k->xscom_base = 0x003fc0000000000ull;
879 dc->desc = "PowerNV Chip POWER8NVL";
880
881 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
882 &k->parent_realize);
883 }
884
885 static void pnv_chip_power9_instance_init(Object *obj)
886 {
887 }
888
889 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
890 {
891 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
892 Error *local_err = NULL;
893
894 pcc->parent_realize(dev, &local_err);
895 if (local_err) {
896 error_propagate(errp, local_err);
897 return;
898 }
899 }
900
901 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
902 {
903 DeviceClass *dc = DEVICE_CLASS(klass);
904 PnvChipClass *k = PNV_CHIP_CLASS(klass);
905
906 k->chip_type = PNV_CHIP_POWER9;
907 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */
908 k->cores_mask = POWER9_CORE_MASK;
909 k->core_pir = pnv_chip_core_pir_p9;
910 k->intc_create = pnv_chip_power9_intc_create;
911 k->isa_create = pnv_chip_power9_isa_create;
912 k->xscom_base = 0x00603fc00000000ull;
913 dc->desc = "PowerNV Chip POWER9";
914
915 device_class_set_parent_realize(dc, pnv_chip_power9_realize,
916 &k->parent_realize);
917 }
918
919 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp)
920 {
921 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
922 int cores_max;
923
924 /*
925 * No custom mask for this chip, let's use the default one from *
926 * the chip class
927 */
928 if (!chip->cores_mask) {
929 chip->cores_mask = pcc->cores_mask;
930 }
931
932 /* filter alien core ids ! some are reserved */
933 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) {
934 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !",
935 chip->cores_mask);
936 return;
937 }
938 chip->cores_mask &= pcc->cores_mask;
939
940 /* now that we have a sane layout, let check the number of cores */
941 cores_max = ctpop64(chip->cores_mask);
942 if (chip->nr_cores > cores_max) {
943 error_setg(errp, "warning: too many cores for chip ! Limit is %d",
944 cores_max);
945 return;
946 }
947 }
948
949 static void pnv_chip_instance_init(Object *obj)
950 {
951 PNV_CHIP(obj)->xscom_base = PNV_CHIP_GET_CLASS(obj)->xscom_base;
952 }
953
954 static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
955 {
956 Error *error = NULL;
957 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
958 const char *typename = pnv_chip_core_typename(chip);
959 size_t typesize = object_type_get_instance_size(typename);
960 int i, core_hwid;
961
962 if (!object_class_by_name(typename)) {
963 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename);
964 return;
965 }
966
967 /* Cores */
968 pnv_chip_core_sanitize(chip, &error);
969 if (error) {
970 error_propagate(errp, error);
971 return;
972 }
973
974 chip->cores = g_malloc0(typesize * chip->nr_cores);
975
976 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8)
977 && (i < chip->nr_cores); core_hwid++) {
978 char core_name[32];
979 void *pnv_core = chip->cores + i * typesize;
980 uint64_t xscom_core_base;
981
982 if (!(chip->cores_mask & (1ull << core_hwid))) {
983 continue;
984 }
985
986 object_initialize(pnv_core, typesize, typename);
987 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid);
988 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core),
989 &error_fatal);
990 object_property_set_int(OBJECT(pnv_core), smp_threads, "nr-threads",
991 &error_fatal);
992 object_property_set_int(OBJECT(pnv_core), core_hwid,
993 CPU_CORE_PROP_CORE_ID, &error_fatal);
994 object_property_set_int(OBJECT(pnv_core),
995 pcc->core_pir(chip, core_hwid),
996 "pir", &error_fatal);
997 object_property_add_const_link(OBJECT(pnv_core), "chip",
998 OBJECT(chip), &error_fatal);
999 object_property_set_bool(OBJECT(pnv_core), true, "realized",
1000 &error_fatal);
1001 object_unref(OBJECT(pnv_core));
1002
1003 /* Each core has an XSCOM MMIO region */
1004 if (!pnv_chip_is_power9(chip)) {
1005 xscom_core_base = PNV_XSCOM_EX_BASE(core_hwid);
1006 } else {
1007 xscom_core_base = PNV_XSCOM_P9_EC_BASE(core_hwid);
1008 }
1009
1010 pnv_xscom_add_subregion(chip, xscom_core_base,
1011 &PNV_CORE(pnv_core)->xscom_regs);
1012 i++;
1013 }
1014 }
1015
1016 static void pnv_chip_realize(DeviceState *dev, Error **errp)
1017 {
1018 PnvChip *chip = PNV_CHIP(dev);
1019 Error *error = NULL;
1020
1021 /* XSCOM bridge */
1022 pnv_xscom_realize(chip, &error);
1023 if (error) {
1024 error_propagate(errp, error);
1025 return;
1026 }
1027 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip));
1028
1029 /* Cores */
1030 pnv_chip_core_realize(chip, &error);
1031 if (error) {
1032 error_propagate(errp, error);
1033 return;
1034 }
1035 }
1036
1037 static Property pnv_chip_properties[] = {
1038 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0),
1039 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0),
1040 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0),
1041 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1),
1042 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
1043 DEFINE_PROP_END_OF_LIST(),
1044 };
1045
1046 static void pnv_chip_class_init(ObjectClass *klass, void *data)
1047 {
1048 DeviceClass *dc = DEVICE_CLASS(klass);
1049
1050 set_bit(DEVICE_CATEGORY_CPU, dc->categories);
1051 dc->realize = pnv_chip_realize;
1052 dc->props = pnv_chip_properties;
1053 dc->desc = "PowerNV Chip";
1054 }
1055
1056 static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
1057 {
1058 PnvMachineState *pnv = PNV_MACHINE(xi);
1059 int i;
1060
1061 for (i = 0; i < pnv->num_chips; i++) {
1062 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
1063
1064 if (ics_valid_irq(&chip8->psi.ics, irq)) {
1065 return &chip8->psi.ics;
1066 }
1067 }
1068 return NULL;
1069 }
1070
1071 static void pnv_ics_resend(XICSFabric *xi)
1072 {
1073 PnvMachineState *pnv = PNV_MACHINE(xi);
1074 int i;
1075
1076 for (i = 0; i < pnv->num_chips; i++) {
1077 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
1078 ics_resend(&chip8->psi.ics);
1079 }
1080 }
1081
1082 static PowerPCCPU *ppc_get_vcpu_by_pir(int pir)
1083 {
1084 CPUState *cs;
1085
1086 CPU_FOREACH(cs) {
1087 PowerPCCPU *cpu = POWERPC_CPU(cs);
1088 CPUPPCState *env = &cpu->env;
1089
1090 if (env->spr_cb[SPR_PIR].default_value == pir) {
1091 return cpu;
1092 }
1093 }
1094
1095 return NULL;
1096 }
1097
1098 static ICPState *pnv_icp_get(XICSFabric *xi, int pir)
1099 {
1100 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir);
1101
1102 return cpu ? cpu->icp : NULL;
1103 }
1104
1105 static void pnv_pic_print_info(InterruptStatsProvider *obj,
1106 Monitor *mon)
1107 {
1108 PnvMachineState *pnv = PNV_MACHINE(obj);
1109 int i;
1110 CPUState *cs;
1111
1112 CPU_FOREACH(cs) {
1113 PowerPCCPU *cpu = POWERPC_CPU(cs);
1114
1115 icp_pic_print_info(cpu->icp, mon);
1116 }
1117
1118 for (i = 0; i < pnv->num_chips; i++) {
1119 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
1120 ics_pic_print_info(&chip8->psi.ics, mon);
1121 }
1122 }
1123
1124 static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name,
1125 void *opaque, Error **errp)
1126 {
1127 visit_type_uint32(v, name, &PNV_MACHINE(obj)->num_chips, errp);
1128 }
1129
1130 static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name,
1131 void *opaque, Error **errp)
1132 {
1133 PnvMachineState *pnv = PNV_MACHINE(obj);
1134 uint32_t num_chips;
1135 Error *local_err = NULL;
1136
1137 visit_type_uint32(v, name, &num_chips, &local_err);
1138 if (local_err) {
1139 error_propagate(errp, local_err);
1140 return;
1141 }
1142
1143 /*
1144 * TODO: should we decide on how many chips we can create based
1145 * on #cores and Venice vs. Murano vs. Naples chip type etc...,
1146 */
1147 if (!is_power_of_2(num_chips) || num_chips > 4) {
1148 error_setg(errp, "invalid number of chips: '%d'", num_chips);
1149 return;
1150 }
1151
1152 pnv->num_chips = num_chips;
1153 }
1154
1155 static void pnv_machine_instance_init(Object *obj)
1156 {
1157 PnvMachineState *pnv = PNV_MACHINE(obj);
1158 pnv->num_chips = 1;
1159 }
1160
1161 static void pnv_machine_class_props_init(ObjectClass *oc)
1162 {
1163 object_class_property_add(oc, "num-chips", "uint32",
1164 pnv_get_num_chips, pnv_set_num_chips,
1165 NULL, NULL, NULL);
1166 object_class_property_set_description(oc, "num-chips",
1167 "Specifies the number of processor chips",
1168 NULL);
1169 }
1170
1171 static void pnv_machine_class_init(ObjectClass *oc, void *data)
1172 {
1173 MachineClass *mc = MACHINE_CLASS(oc);
1174 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
1175 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
1176
1177 mc->desc = "IBM PowerNV (Non-Virtualized)";
1178 mc->init = pnv_init;
1179 mc->reset = pnv_reset;
1180 mc->max_cpus = MAX_CPUS;
1181 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
1182 mc->block_default_type = IF_IDE; /* Pnv provides a AHCI device for
1183 * storage */
1184 mc->no_parallel = 1;
1185 mc->default_boot_order = NULL;
1186 mc->default_ram_size = 1 * GiB;
1187 xic->icp_get = pnv_icp_get;
1188 xic->ics_get = pnv_ics_get;
1189 xic->ics_resend = pnv_ics_resend;
1190 ispc->print_info = pnv_pic_print_info;
1191
1192 pnv_machine_class_props_init(oc);
1193 }
1194
1195 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \
1196 { \
1197 .name = type, \
1198 .class_init = class_initfn, \
1199 .parent = TYPE_PNV8_CHIP, \
1200 }
1201
1202 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \
1203 { \
1204 .name = type, \
1205 .class_init = class_initfn, \
1206 .parent = TYPE_PNV9_CHIP, \
1207 }
1208
1209 static const TypeInfo types[] = {
1210 {
1211 .name = TYPE_PNV_MACHINE,
1212 .parent = TYPE_MACHINE,
1213 .instance_size = sizeof(PnvMachineState),
1214 .instance_init = pnv_machine_instance_init,
1215 .class_init = pnv_machine_class_init,
1216 .interfaces = (InterfaceInfo[]) {
1217 { TYPE_XICS_FABRIC },
1218 { TYPE_INTERRUPT_STATS_PROVIDER },
1219 { },
1220 },
1221 },
1222 {
1223 .name = TYPE_PNV_CHIP,
1224 .parent = TYPE_SYS_BUS_DEVICE,
1225 .class_init = pnv_chip_class_init,
1226 .instance_init = pnv_chip_instance_init,
1227 .instance_size = sizeof(PnvChip),
1228 .class_size = sizeof(PnvChipClass),
1229 .abstract = true,
1230 },
1231
1232 /*
1233 * P9 chip and variants
1234 */
1235 {
1236 .name = TYPE_PNV9_CHIP,
1237 .parent = TYPE_PNV_CHIP,
1238 .instance_init = pnv_chip_power9_instance_init,
1239 .instance_size = sizeof(Pnv9Chip),
1240 },
1241 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init),
1242
1243 /*
1244 * P8 chip and variants
1245 */
1246 {
1247 .name = TYPE_PNV8_CHIP,
1248 .parent = TYPE_PNV_CHIP,
1249 .instance_init = pnv_chip_power8_instance_init,
1250 .instance_size = sizeof(Pnv8Chip),
1251 },
1252 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init),
1253 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init),
1254 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL,
1255 pnv_chip_power8nvl_class_init),
1256 };
1257
1258 DEFINE_TYPES(types)
AR7 emulation for QEMU