hw/intc/apic_common.c

   1 /*
   2  *  APIC support - common bits of emulated and KVM kernel model
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *  Copyright (c) 2011      Jan Kiszka, Siemens AG
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  19  */
  20 #include "qemu/osdep.h"
  21 #include "qemu/error-report.h"
  22 #include "qapi/error.h"
  23 #include "qemu-common.h"
  24 #include "cpu.h"
  25 #include "qapi/visitor.h"
  26 #include "hw/i386/apic.h"
  27 #include "hw/i386/apic_internal.h"
  28 #include "trace.h"
  29 #include "sysemu/hax.h"
  30 #include "sysemu/kvm.h"
  31 #include "hw/qdev.h"
  32 #include "hw/sysbus.h"
  33
  34 static int apic_irq_delivered;
  35 bool apic_report_tpr_access;
  36
  37 void cpu_set_apic_base(DeviceState *dev, uint64_t val)
  38 {
  39     trace_cpu_set_apic_base(val);
  40
  41     if (dev) {
  42         APICCommonState *s = APIC_COMMON(dev);
  43         APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
  44         /* switching to x2APIC, reset possibly modified xAPIC ID */
  45         if (!(s->apicbase & MSR_IA32_APICBASE_EXTD) &&
  46             (val & MSR_IA32_APICBASE_EXTD)) {
  47             s->id = s->initial_apic_id;
  48         }
  49         info->set_base(s, val);
  50     }
  51 }
  52
  53 uint64_t cpu_get_apic_base(DeviceState *dev)
  54 {
  55     if (dev) {
  56         APICCommonState *s = APIC_COMMON(dev);
  57         trace_cpu_get_apic_base((uint64_t)s->apicbase);
  58         return s->apicbase;
  59     } else {
  60         trace_cpu_get_apic_base(MSR_IA32_APICBASE_BSP);
  61         return MSR_IA32_APICBASE_BSP;
  62     }
  63 }
  64
  65 void cpu_set_apic_tpr(DeviceState *dev, uint8_t val)
  66 {
  67     APICCommonState *s;
  68     APICCommonClass *info;
  69
  70     if (!dev) {
  71         return;
  72     }
  73
  74     s = APIC_COMMON(dev);
  75     info = APIC_COMMON_GET_CLASS(s);
  76
  77     info->set_tpr(s, val);
  78 }
  79
  80 uint8_t cpu_get_apic_tpr(DeviceState *dev)
  81 {
  82     APICCommonState *s;
  83     APICCommonClass *info;
  84
  85     if (!dev) {
  86         return 0;
  87     }
  88
  89     s = APIC_COMMON(dev);
  90     info = APIC_COMMON_GET_CLASS(s);
  91
  92     return info->get_tpr(s);
  93 }
  94
  95 void apic_enable_tpr_access_reporting(DeviceState *dev, bool enable)
  96 {
  97     APICCommonState *s = APIC_COMMON(dev);
  98     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
  99
 100     apic_report_tpr_access = enable;
 101     if (info->enable_tpr_reporting) {
 102         info->enable_tpr_reporting(s, enable);
 103     }
 104 }
 105
 106 void apic_enable_vapic(DeviceState *dev, hwaddr paddr)
 107 {
 108     APICCommonState *s = APIC_COMMON(dev);
 109     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 110
 111     s->vapic_paddr = paddr;
 112     info->vapic_base_update(s);
 113 }
 114
 115 void apic_handle_tpr_access_report(DeviceState *dev, target_ulong ip,
 116                                    TPRAccess access)
 117 {
 118     APICCommonState *s = APIC_COMMON(dev);
 119
 120     vapic_report_tpr_access(s->vapic, CPU(s->cpu), ip, access);
 121 }
 122
 123 void apic_report_irq_delivered(int delivered)
 124 {
 125     apic_irq_delivered += delivered;
 126
 127     trace_apic_report_irq_delivered(apic_irq_delivered);
 128 }
 129
 130 void apic_reset_irq_delivered(void)
 131 {
 132     /* Copy this into a local variable to encourage gcc to emit a plain
 133      * register for a sys/sdt.h marker.  For details on this workaround, see:
 134      * https://sourceware.org/bugzilla/show_bug.cgi?id=13296
 135      */
 136     volatile int a_i_d = apic_irq_delivered;
 137     trace_apic_reset_irq_delivered(a_i_d);
 138
 139     apic_irq_delivered = 0;
 140 }
 141
 142 int apic_get_irq_delivered(void)
 143 {
 144     trace_apic_get_irq_delivered(apic_irq_delivered);
 145
 146     return apic_irq_delivered;
 147 }
 148
 149 void apic_deliver_nmi(DeviceState *dev)
 150 {
 151     APICCommonState *s = APIC_COMMON(dev);
 152     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 153
 154     info->external_nmi(s);
 155 }
 156
 157 bool apic_next_timer(APICCommonState *s, int64_t current_time)
 158 {
 159     int64_t d;
 160
 161     /* We need to store the timer state separately to support APIC
 162      * implementations that maintain a non-QEMU timer, e.g. inside the
 163      * host kernel. This open-coded state allows us to migrate between
 164      * both models. */
 165     s->timer_expiry = -1;
 166
 167     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED) {
 168         return false;
 169     }
 170
 171     d = (current_time - s->initial_count_load_time) >> s->count_shift;
 172
 173     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 174         if (!s->initial_count) {
 175             return false;
 176         }
 177         d = ((d / ((uint64_t)s->initial_count + 1)) + 1) *
 178             ((uint64_t)s->initial_count + 1);
 179     } else {
 180         if (d >= s->initial_count) {
 181             return false;
 182         }
 183         d = (uint64_t)s->initial_count + 1;
 184     }
 185     s->next_time = s->initial_count_load_time + (d << s->count_shift);
 186     s->timer_expiry = s->next_time;
 187     return true;
 188 }
 189
 190 void apic_init_reset(DeviceState *dev)
 191 {
 192     APICCommonState *s;
 193     APICCommonClass *info;
 194     int i;
 195
 196     if (!dev) {
 197         return;
 198     }
 199     s = APIC_COMMON(dev);
 200     s->tpr = 0;
 201     s->spurious_vec = 0xff;
 202     s->log_dest = 0;
 203     s->dest_mode = 0xf;
 204     memset(s->isr, 0, sizeof(s->isr));
 205     memset(s->tmr, 0, sizeof(s->tmr));
 206     memset(s->irr, 0, sizeof(s->irr));
 207     for (i = 0; i < APIC_LVT_NB; i++) {
 208         s->lvt[i] = APIC_LVT_MASKED;
 209     }
 210     s->esr = 0;
 211     memset(s->icr, 0, sizeof(s->icr));
 212     s->divide_conf = 0;
 213     s->count_shift = 0;
 214     s->initial_count = 0;
 215     s->initial_count_load_time = 0;
 216     s->next_time = 0;
 217     s->wait_for_sipi = !cpu_is_bsp(s->cpu);
 218
 219     if (s->timer) {
 220         timer_del(s->timer);
 221     }
 222     s->timer_expiry = -1;
 223
 224     info = APIC_COMMON_GET_CLASS(s);
 225     if (info->reset) {
 226         info->reset(s);
 227     }
 228 }
 229
 230 void apic_designate_bsp(DeviceState *dev, bool bsp)
 231 {
 232     if (dev == NULL) {
 233         return;
 234     }
 235
 236     APICCommonState *s = APIC_COMMON(dev);
 237     if (bsp) {
 238         s->apicbase |= MSR_IA32_APICBASE_BSP;
 239     } else {
 240         s->apicbase &= ~MSR_IA32_APICBASE_BSP;
 241     }
 242 }
 243
 244 static void apic_reset_common(DeviceState *dev)
 245 {
 246     APICCommonState *s = APIC_COMMON(dev);
 247     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 248     uint32_t bsp;
 249
 250     bsp = s->apicbase & MSR_IA32_APICBASE_BSP;
 251     s->apicbase = APIC_DEFAULT_ADDRESS | bsp | MSR_IA32_APICBASE_ENABLE;
 252     s->id = s->initial_apic_id;
 253
 254     s->vapic_paddr = 0;
 255     info->vapic_base_update(s);
 256
 257     apic_init_reset(dev);
 258 }
 259
 260 /* This function is only used for old state version 1 and 2 */
 261 static int apic_load_old(QEMUFile *f, void *opaque, int version_id)
 262 {
 263     APICCommonState *s = opaque;
 264     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 265     int i;
 266
 267     if (version_id > 2) {
 268         return -EINVAL;
 269     }
 270
 271     /* XXX: what if the base changes? (registered memory regions) */
 272     qemu_get_be32s(f, &s->apicbase);
 273     qemu_get_8s(f, &s->id);
 274     qemu_get_8s(f, &s->arb_id);
 275     qemu_get_8s(f, &s->tpr);
 276     qemu_get_be32s(f, &s->spurious_vec);
 277     qemu_get_8s(f, &s->log_dest);
 278     qemu_get_8s(f, &s->dest_mode);
 279     for (i = 0; i < 8; i++) {
 280         qemu_get_be32s(f, &s->isr[i]);
 281         qemu_get_be32s(f, &s->tmr[i]);
 282         qemu_get_be32s(f, &s->irr[i]);
 283     }
 284     for (i = 0; i < APIC_LVT_NB; i++) {
 285         qemu_get_be32s(f, &s->lvt[i]);
 286     }
 287     qemu_get_be32s(f, &s->esr);
 288     qemu_get_be32s(f, &s->icr[0]);
 289     qemu_get_be32s(f, &s->icr[1]);
 290     qemu_get_be32s(f, &s->divide_conf);
 291     s->count_shift = qemu_get_be32(f);
 292     qemu_get_be32s(f, &s->initial_count);
 293     s->initial_count_load_time = qemu_get_be64(f);
 294     s->next_time = qemu_get_be64(f);
 295
 296     if (version_id >= 2) {
 297         s->timer_expiry = qemu_get_be64(f);
 298     }
 299
 300     if (info->post_load) {
 301         info->post_load(s);
 302     }
 303     return 0;
 304 }
 305
 306 static const VMStateDescription vmstate_apic_common;
 307
 308 static void apic_common_realize(DeviceState *dev, Error **errp)
 309 {
 310     APICCommonState *s = APIC_COMMON(dev);
 311     APICCommonClass *info;
 312     static DeviceState *vapic;
 313     int instance_id = s->id;
 314
 315     info = APIC_COMMON_GET_CLASS(s);
 316     info->realize(dev, errp);
 317
 318     /* Note: We need at least 1M to map the VAPIC option ROM */
 319     if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK &&
 320         !hax_enabled() && ram_size >= 1024 * 1024) {
 321         vapic = sysbus_create_simple("kvmvapic", -1, NULL);
 322     }
 323     s->vapic = vapic;
 324     if (apic_report_tpr_access && info->enable_tpr_reporting) {
 325         info->enable_tpr_reporting(s, true);
 326     }
 327
 328     if (s->legacy_instance_id) {
 329         instance_id = -1;
 330     }
 331     vmstate_register_with_alias_id(NULL, instance_id, &vmstate_apic_common,
 332                                    s, -1, 0, NULL);
 333 }
 334
 335 static void apic_common_unrealize(DeviceState *dev, Error **errp)
 336 {
 337     APICCommonState *s = APIC_COMMON(dev);
 338     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 339
 340     vmstate_unregister(NULL, &vmstate_apic_common, s);
 341     info->unrealize(dev, errp);
 342
 343     if (apic_report_tpr_access && info->enable_tpr_reporting) {
 344         info->enable_tpr_reporting(s, false);
 345     }
 346 }
 347
 348 static int apic_pre_load(void *opaque)
 349 {
 350     APICCommonState *s = APIC_COMMON(opaque);
 351
 352     /* The default is !cpu_is_bsp(s->cpu), but the common value is 0
 353      * so that's what apic_common_sipi_needed checks for.  Reset to
 354      * the value that is assumed when the apic_sipi subsection is
 355      * absent.
 356      */
 357     s->wait_for_sipi = 0;
 358     return 0;
 359 }
 360
 361 static void apic_dispatch_pre_save(void *opaque)
 362 {
 363     APICCommonState *s = APIC_COMMON(opaque);
 364     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 365
 366     if (info->pre_save) {
 367         info->pre_save(s);
 368     }
 369 }
 370
 371 static int apic_dispatch_post_load(void *opaque, int version_id)
 372 {
 373     APICCommonState *s = APIC_COMMON(opaque);
 374     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 375
 376     if (info->post_load) {
 377         info->post_load(s);
 378     }
 379     return 0;
 380 }
 381
 382 static bool apic_common_sipi_needed(void *opaque)
 383 {
 384     APICCommonState *s = APIC_COMMON(opaque);
 385     return s->wait_for_sipi != 0;
 386 }
 387
 388 static bool apic_irq_delivered_needed(void *opaque)
 389 {
 390     APICCommonState *s = APIC_COMMON(opaque);
 391     return s->cpu == X86_CPU(first_cpu) && apic_irq_delivered != 0;
 392 }
 393
 394 static void apic_irq_delivered_pre_save(void *opaque)
 395 {
 396     APICCommonState *s = APIC_COMMON(opaque);
 397     s->apic_irq_delivered = apic_irq_delivered;
 398 }
 399
 400 static int apic_irq_delivered_post_load(void *opaque, int version_id)
 401 {
 402     APICCommonState *s = APIC_COMMON(opaque);
 403     apic_irq_delivered = s->apic_irq_delivered;
 404     return 0;
 405 }
 406
 407 static const VMStateDescription vmstate_apic_common_sipi = {
 408     .name = "apic_sipi",
 409     .version_id = 1,
 410     .minimum_version_id = 1,
 411     .needed = apic_common_sipi_needed,
 412     .fields = (VMStateField[]) {
 413         VMSTATE_INT32(sipi_vector, APICCommonState),
 414         VMSTATE_INT32(wait_for_sipi, APICCommonState),
 415         VMSTATE_END_OF_LIST()
 416     }
 417 };
 418
 419 static const VMStateDescription vmstate_apic_irq_delivered = {
 420     .name = "apic_irq_delivered",
 421     .version_id = 1,
 422     .minimum_version_id = 1,
 423     .needed = apic_irq_delivered_needed,
 424     .pre_save = apic_irq_delivered_pre_save,
 425     .post_load = apic_irq_delivered_post_load,
 426     .fields = (VMStateField[]) {
 427         VMSTATE_INT32(apic_irq_delivered, APICCommonState),
 428         VMSTATE_END_OF_LIST()
 429     }
 430 };
 431
 432 static const VMStateDescription vmstate_apic_common = {
 433     .name = "apic",
 434     .version_id = 3,
 435     .minimum_version_id = 3,
 436     .minimum_version_id_old = 1,
 437     .load_state_old = apic_load_old,
 438     .pre_load = apic_pre_load,
 439     .pre_save = apic_dispatch_pre_save,
 440     .post_load = apic_dispatch_post_load,
 441     .fields = (VMStateField[]) {
 442         VMSTATE_UINT32(apicbase, APICCommonState),
 443         VMSTATE_UINT8(id, APICCommonState),
 444         VMSTATE_UINT8(arb_id, APICCommonState),
 445         VMSTATE_UINT8(tpr, APICCommonState),
 446         VMSTATE_UINT32(spurious_vec, APICCommonState),
 447         VMSTATE_UINT8(log_dest, APICCommonState),
 448         VMSTATE_UINT8(dest_mode, APICCommonState),
 449         VMSTATE_UINT32_ARRAY(isr, APICCommonState, 8),
 450         VMSTATE_UINT32_ARRAY(tmr, APICCommonState, 8),
 451         VMSTATE_UINT32_ARRAY(irr, APICCommonState, 8),
 452         VMSTATE_UINT32_ARRAY(lvt, APICCommonState, APIC_LVT_NB),
 453         VMSTATE_UINT32(esr, APICCommonState),
 454         VMSTATE_UINT32_ARRAY(icr, APICCommonState, 2),
 455         VMSTATE_UINT32(divide_conf, APICCommonState),
 456         VMSTATE_INT32(count_shift, APICCommonState),
 457         VMSTATE_UINT32(initial_count, APICCommonState),
 458         VMSTATE_INT64(initial_count_load_time, APICCommonState),
 459         VMSTATE_INT64(next_time, APICCommonState),
 460         VMSTATE_INT64(timer_expiry,
 461                       APICCommonState), /* open-coded timer state */
 462         VMSTATE_END_OF_LIST()
 463     },
 464     .subsections = (const VMStateDescription*[]) {
 465         &vmstate_apic_common_sipi,
 466         &vmstate_apic_irq_delivered,
 467         NULL
 468     }
 469 };
 470
 471 static Property apic_properties_common[] = {
 472     DEFINE_PROP_UINT8("version", APICCommonState, version, 0x14),
 473     DEFINE_PROP_BIT("vapic", APICCommonState, vapic_control, VAPIC_ENABLE_BIT,
 474                     true),
 475     DEFINE_PROP_BOOL("legacy-instance-id", APICCommonState, legacy_instance_id,
 476                      false),
 477     DEFINE_PROP_END_OF_LIST(),
 478 };
 479
 480 static void apic_common_get_id(Object *obj, Visitor *v, const char *name,
 481                                void *opaque, Error **errp)
 482 {
 483     APICCommonState *s = APIC_COMMON(obj);
 484     int64_t value;
 485
 486     value = s->apicbase & MSR_IA32_APICBASE_EXTD ? s->initial_apic_id : s->id;
 487     visit_type_int(v, name, &value, errp);
 488 }
 489
 490 static void apic_common_set_id(Object *obj, Visitor *v, const char *name,
 491                                void *opaque, Error **errp)
 492 {
 493     APICCommonState *s = APIC_COMMON(obj);
 494     DeviceState *dev = DEVICE(obj);
 495     Error *local_err = NULL;
 496     int64_t value;
 497
 498     if (dev->realized) {
 499         qdev_prop_set_after_realize(dev, name, errp);
 500         return;
 501     }
 502
 503     visit_type_int(v, name, &value, &local_err);
 504     if (local_err) {
 505         error_propagate(errp, local_err);
 506         return;
 507     }
 508
 509     s->initial_apic_id = value;
 510     s->id = (uint8_t)value;
 511 }
 512
 513 static void apic_common_initfn(Object *obj)
 514 {
 515     APICCommonState *s = APIC_COMMON(obj);
 516
 517     s->id = s->initial_apic_id = -1;
 518     object_property_add(obj, "id", "int",
 519                         apic_common_get_id,
 520                         apic_common_set_id, NULL, NULL, NULL);
 521 }
 522
 523 static void apic_common_class_init(ObjectClass *klass, void *data)
 524 {
 525     DeviceClass *dc = DEVICE_CLASS(klass);
 526
 527     dc->reset = apic_reset_common;
 528     dc->props = apic_properties_common;
 529     dc->realize = apic_common_realize;
 530     dc->unrealize = apic_common_unrealize;
 531     /*
 532      * Reason: APIC and CPU need to be wired up by
 533      * x86_cpu_apic_create()
 534      */
 535     dc->cannot_instantiate_with_device_add_yet = true;
 536 }
 537
 538 static const TypeInfo apic_common_type = {
 539     .name = TYPE_APIC_COMMON,
 540     .parent = TYPE_DEVICE,
 541     .instance_size = sizeof(APICCommonState),
 542     .instance_init = apic_common_initfn,
 543     .class_size = sizeof(APICCommonClass),
 544     .class_init = apic_common_class_init,
 545     .abstract = true,
 546 };
 547
 548 static void apic_common_register_types(void)
 549 {
 550     type_register_static(&apic_common_type);
 551 }
 552
 553 type_init(apic_common_register_types)