target/ppc/mem_helper.c

   1 /*
   2  *  PowerPC memory access emulation helpers for QEMU.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "cpu.h"
  22 #include "exec/exec-all.h"
  23 #include "qemu/host-utils.h"
  24 #include "qemu/main-loop.h"
  25 #include "exec/helper-proto.h"
  26 #include "helper_regs.h"
  27 #include "exec/cpu_ldst.h"
  28 #include "tcg/tcg.h"
  29 #include "internal.h"
  30 #include "qemu/atomic128.h"
  31
  32 /* #define DEBUG_OP */
  33
  34 static inline bool needs_byteswap(const CPUPPCState *env)
  35 {
  36 #if defined(TARGET_WORDS_BIGENDIAN)
  37   return msr_le;
  38 #else
  39   return !msr_le;
  40 #endif
  41 }
  42
  43 /*****************************************************************************/
  44 /* Memory load and stores */
  45
  46 static inline target_ulong addr_add(CPUPPCState *env, target_ulong addr,
  47                                     target_long arg)
  48 {
  49 #if defined(TARGET_PPC64)
  50     if (!msr_is_64bit(env, env->msr)) {
  51         return (uint32_t)(addr + arg);
  52     } else
  53 #endif
  54     {
  55         return addr + arg;
  56     }
  57 }
  58
  59 static void *probe_contiguous(CPUPPCState *env, target_ulong addr, uint32_t nb,
  60                               MMUAccessType access_type, int mmu_idx,
  61                               uintptr_t raddr)
  62 {
  63     void *host1, *host2;
  64     uint32_t nb_pg1, nb_pg2;
  65
  66     nb_pg1 = -(addr | TARGET_PAGE_MASK);
  67     if (likely(nb <= nb_pg1)) {
  68         /* The entire operation is on a single page.  */
  69         return probe_access(env, addr, nb, access_type, mmu_idx, raddr);
  70     }
  71
  72     /* The operation spans two pages.  */
  73     nb_pg2 = nb - nb_pg1;
  74     host1 = probe_access(env, addr, nb_pg1, access_type, mmu_idx, raddr);
  75     addr = addr_add(env, addr, nb_pg1);
  76     host2 = probe_access(env, addr, nb_pg2, access_type, mmu_idx, raddr);
  77
  78     /* If the two host pages are contiguous, optimize.  */
  79     if (host2 == host1 + nb_pg1) {
  80         return host1;
  81     }
  82     return NULL;
  83 }
  84
  85 void helper_lmw(CPUPPCState *env, target_ulong addr, uint32_t reg)
  86 {
  87     for (; reg < 32; reg++) {
  88         if (needs_byteswap(env)) {
  89             env->gpr[reg] = bswap32(cpu_ldl_data_ra(env, addr, GETPC()));
  90         } else {
  91             env->gpr[reg] = cpu_ldl_data_ra(env, addr, GETPC());
  92         }
  93         addr = addr_add(env, addr, 4);
  94     }
  95 }
  96
  97 void helper_stmw(CPUPPCState *env, target_ulong addr, uint32_t reg)
  98 {
  99     for (; reg < 32; reg++) {
 100         if (needs_byteswap(env)) {
 101             cpu_stl_data_ra(env, addr, bswap32((uint32_t)env->gpr[reg]),
 102                                                    GETPC());
 103         } else {
 104             cpu_stl_data_ra(env, addr, (uint32_t)env->gpr[reg], GETPC());
 105         }
 106         addr = addr_add(env, addr, 4);
 107     }
 108 }
 109
 110 static void do_lsw(CPUPPCState *env, target_ulong addr, uint32_t nb,
 111                    uint32_t reg, uintptr_t raddr)
 112 {
 113     int mmu_idx;
 114     void *host;
 115     uint32_t val;
 116
 117     if (unlikely(nb == 0)) {
 118         return;
 119     }
 120
 121     mmu_idx = cpu_mmu_index(env, false);
 122     host = probe_contiguous(env, addr, nb, MMU_DATA_LOAD, mmu_idx, raddr);
 123
 124     if (likely(host)) {
 125         /* Fast path -- the entire operation is in RAM at host.  */
 126         for (; nb > 3; nb -= 4) {
 127             env->gpr[reg] = (uint32_t)ldl_be_p(host);
 128             reg = (reg + 1) % 32;
 129             host += 4;
 130         }
 131         switch (nb) {
 132         default:
 133             return;
 134         case 1:
 135             val = ldub_p(host) << 24;
 136             break;
 137         case 2:
 138             val = lduw_be_p(host) << 16;
 139             break;
 140         case 3:
 141             val = (lduw_be_p(host) << 16) | (ldub_p(host + 2) << 8);
 142             break;
 143         }
 144     } else {
 145         /* Slow path -- at least some of the operation requires i/o.  */
 146         for (; nb > 3; nb -= 4) {
 147             env->gpr[reg] = cpu_ldl_mmuidx_ra(env, addr, mmu_idx, raddr);
 148             reg = (reg + 1) % 32;
 149             addr = addr_add(env, addr, 4);
 150         }
 151         switch (nb) {
 152         default:
 153             return;
 154         case 1:
 155             val = cpu_ldub_mmuidx_ra(env, addr, mmu_idx, raddr) << 24;
 156             break;
 157         case 2:
 158             val = cpu_lduw_mmuidx_ra(env, addr, mmu_idx, raddr) << 16;
 159             break;
 160         case 3:
 161             val = cpu_lduw_mmuidx_ra(env, addr, mmu_idx, raddr) << 16;
 162             addr = addr_add(env, addr, 2);
 163             val |= cpu_ldub_mmuidx_ra(env, addr, mmu_idx, raddr) << 8;
 164             break;
 165         }
 166     }
 167     env->gpr[reg] = val;
 168 }
 169
 170 void helper_lsw(CPUPPCState *env, target_ulong addr,
 171                 uint32_t nb, uint32_t reg)
 172 {
 173     do_lsw(env, addr, nb, reg, GETPC());
 174 }
 175
 176 /*
 177  * PPC32 specification says we must generate an exception if rA is in
 178  * the range of registers to be loaded.  In an other hand, IBM says
 179  * this is valid, but rA won't be loaded.  For now, I'll follow the
 180  * spec...
 181  */
 182 void helper_lswx(CPUPPCState *env, target_ulong addr, uint32_t reg,
 183                  uint32_t ra, uint32_t rb)
 184 {
 185     if (likely(xer_bc != 0)) {
 186         int num_used_regs = DIV_ROUND_UP(xer_bc, 4);
 187         if (unlikely((ra != 0 && lsw_reg_in_range(reg, num_used_regs, ra)) ||
 188                      lsw_reg_in_range(reg, num_used_regs, rb))) {
 189             raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
 190                                    POWERPC_EXCP_INVAL |
 191                                    POWERPC_EXCP_INVAL_LSWX, GETPC());
 192         } else {
 193             do_lsw(env, addr, xer_bc, reg, GETPC());
 194         }
 195     }
 196 }
 197
 198 void helper_stsw(CPUPPCState *env, target_ulong addr, uint32_t nb,
 199                  uint32_t reg)
 200 {
 201     uintptr_t raddr = GETPC();
 202     int mmu_idx;
 203     void *host;
 204     uint32_t val;
 205
 206     if (unlikely(nb == 0)) {
 207         return;
 208     }
 209
 210     mmu_idx = cpu_mmu_index(env, false);
 211     host = probe_contiguous(env, addr, nb, MMU_DATA_STORE, mmu_idx, raddr);
 212
 213     if (likely(host)) {
 214         /* Fast path -- the entire operation is in RAM at host.  */
 215         for (; nb > 3; nb -= 4) {
 216             stl_be_p(host, env->gpr[reg]);
 217             reg = (reg + 1) % 32;
 218             host += 4;
 219         }
 220         val = env->gpr[reg];
 221         switch (nb) {
 222         case 1:
 223             stb_p(host, val >> 24);
 224             break;
 225         case 2:
 226             stw_be_p(host, val >> 16);
 227             break;
 228         case 3:
 229             stw_be_p(host, val >> 16);
 230             stb_p(host + 2, val >> 8);
 231             break;
 232         }
 233     } else {
 234         for (; nb > 3; nb -= 4) {
 235             cpu_stl_mmuidx_ra(env, addr, env->gpr[reg], mmu_idx, raddr);
 236             reg = (reg + 1) % 32;
 237             addr = addr_add(env, addr, 4);
 238         }
 239         val = env->gpr[reg];
 240         switch (nb) {
 241         case 1:
 242             cpu_stb_mmuidx_ra(env, addr, val >> 24, mmu_idx, raddr);
 243             break;
 244         case 2:
 245             cpu_stw_mmuidx_ra(env, addr, val >> 16, mmu_idx, raddr);
 246             break;
 247         case 3:
 248             cpu_stw_mmuidx_ra(env, addr, val >> 16, mmu_idx, raddr);
 249             addr = addr_add(env, addr, 2);
 250             cpu_stb_mmuidx_ra(env, addr, val >> 8, mmu_idx, raddr);
 251             break;
 252         }
 253     }
 254 }
 255
 256 static void dcbz_common(CPUPPCState *env, target_ulong addr,
 257                         uint32_t opcode, bool epid, uintptr_t retaddr)
 258 {
 259     target_ulong mask, dcbz_size = env->dcache_line_size;
 260     uint32_t i;
 261     void *haddr;
 262     int mmu_idx = epid ? PPC_TLB_EPID_STORE : env->dmmu_idx;
 263
 264 #if defined(TARGET_PPC64)
 265     /* Check for dcbz vs dcbzl on 970 */
 266     if (env->excp_model == POWERPC_EXCP_970 &&
 267         !(opcode & 0x00200000) && ((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1) {
 268         dcbz_size = 32;
 269     }
 270 #endif
 271
 272     /* Align address */
 273     mask = ~(dcbz_size - 1);
 274     addr &= mask;
 275
 276     /* Check reservation */
 277     if ((env->reserve_addr & mask) == (addr & mask))  {
 278         env->reserve_addr = (target_ulong)-1ULL;
 279     }
 280
 281     /* Try fast path translate */
 282     haddr = tlb_vaddr_to_host(env, addr, MMU_DATA_STORE, mmu_idx);
 283     if (haddr) {
 284         memset(haddr, 0, dcbz_size);
 285     } else {
 286         /* Slow path */
 287         for (i = 0; i < dcbz_size; i += 8) {
 288             cpu_stq_mmuidx_ra(env, addr + i, 0, mmu_idx, retaddr);
 289         }
 290     }
 291 }
 292
 293 void helper_dcbz(CPUPPCState *env, target_ulong addr, uint32_t opcode)
 294 {
 295     dcbz_common(env, addr, opcode, false, GETPC());
 296 }
 297
 298 void helper_dcbzep(CPUPPCState *env, target_ulong addr, uint32_t opcode)
 299 {
 300     dcbz_common(env, addr, opcode, true, GETPC());
 301 }
 302
 303 void helper_icbi(CPUPPCState *env, target_ulong addr)
 304 {
 305     addr &= ~(env->dcache_line_size - 1);
 306     /*
 307      * Invalidate one cache line :
 308      * PowerPC specification says this is to be treated like a load
 309      * (not a fetch) by the MMU. To be sure it will be so,
 310      * do the load "by hand".
 311      */
 312     cpu_ldl_data_ra(env, addr, GETPC());
 313 }
 314
 315 void helper_icbiep(CPUPPCState *env, target_ulong addr)
 316 {
 317 #if !defined(CONFIG_USER_ONLY)
 318     /* See comments above */
 319     addr &= ~(env->dcache_line_size - 1);
 320     cpu_ldl_mmuidx_ra(env, addr, PPC_TLB_EPID_LOAD, GETPC());
 321 #endif
 322 }
 323
 324 /* XXX: to be tested */
 325 target_ulong helper_lscbx(CPUPPCState *env, target_ulong addr, uint32_t reg,
 326                           uint32_t ra, uint32_t rb)
 327 {
 328     int i, c, d;
 329
 330     d = 24;
 331     for (i = 0; i < xer_bc; i++) {
 332         c = cpu_ldub_data_ra(env, addr, GETPC());
 333         addr = addr_add(env, addr, 1);
 334         /* ra (if not 0) and rb are never modified */
 335         if (likely(reg != rb && (ra == 0 || reg != ra))) {
 336             env->gpr[reg] = (env->gpr[reg] & ~(0xFF << d)) | (c << d);
 337         }
 338         if (unlikely(c == xer_cmp)) {
 339             break;
 340         }
 341         if (likely(d != 0)) {
 342             d -= 8;
 343         } else {
 344             d = 24;
 345             reg++;
 346             reg = reg & 0x1F;
 347         }
 348     }
 349     return i;
 350 }
 351
 352 #ifdef TARGET_PPC64
 353 uint64_t helper_lq_le_parallel(CPUPPCState *env, target_ulong addr,
 354                                uint32_t opidx)
 355 {
 356     Int128 ret;
 357
 358     /* We will have raised EXCP_ATOMIC from the translator.  */
 359     assert(HAVE_ATOMIC128);
 360     ret = helper_atomic_ldo_le_mmu(env, addr, opidx, GETPC());
 361     env->retxh = int128_gethi(ret);
 362     return int128_getlo(ret);
 363 }
 364
 365 uint64_t helper_lq_be_parallel(CPUPPCState *env, target_ulong addr,
 366                                uint32_t opidx)
 367 {
 368     Int128 ret;
 369
 370     /* We will have raised EXCP_ATOMIC from the translator.  */
 371     assert(HAVE_ATOMIC128);
 372     ret = helper_atomic_ldo_be_mmu(env, addr, opidx, GETPC());
 373     env->retxh = int128_gethi(ret);
 374     return int128_getlo(ret);
 375 }
 376
 377 void helper_stq_le_parallel(CPUPPCState *env, target_ulong addr,
 378                             uint64_t lo, uint64_t hi, uint32_t opidx)
 379 {
 380     Int128 val;
 381
 382     /* We will have raised EXCP_ATOMIC from the translator.  */
 383     assert(HAVE_ATOMIC128);
 384     val = int128_make128(lo, hi);
 385     helper_atomic_sto_le_mmu(env, addr, val, opidx, GETPC());
 386 }
 387
 388 void helper_stq_be_parallel(CPUPPCState *env, target_ulong addr,
 389                             uint64_t lo, uint64_t hi, uint32_t opidx)
 390 {
 391     Int128 val;
 392
 393     /* We will have raised EXCP_ATOMIC from the translator.  */
 394     assert(HAVE_ATOMIC128);
 395     val = int128_make128(lo, hi);
 396     helper_atomic_sto_be_mmu(env, addr, val, opidx, GETPC());
 397 }
 398
 399 uint32_t helper_stqcx_le_parallel(CPUPPCState *env, target_ulong addr,
 400                                   uint64_t new_lo, uint64_t new_hi,
 401                                   uint32_t opidx)
 402 {
 403     bool success = false;
 404
 405     /* We will have raised EXCP_ATOMIC from the translator.  */
 406     assert(HAVE_CMPXCHG128);
 407
 408     if (likely(addr == env->reserve_addr)) {
 409         Int128 oldv, cmpv, newv;
 410
 411         cmpv = int128_make128(env->reserve_val2, env->reserve_val);
 412         newv = int128_make128(new_lo, new_hi);
 413         oldv = helper_atomic_cmpxchgo_le_mmu(env, addr, cmpv, newv,
 414                                              opidx, GETPC());
 415         success = int128_eq(oldv, cmpv);
 416     }
 417     env->reserve_addr = -1;
 418     return env->so + success * CRF_EQ_BIT;
 419 }
 420
 421 uint32_t helper_stqcx_be_parallel(CPUPPCState *env, target_ulong addr,
 422                                   uint64_t new_lo, uint64_t new_hi,
 423                                   uint32_t opidx)
 424 {
 425     bool success = false;
 426
 427     /* We will have raised EXCP_ATOMIC from the translator.  */
 428     assert(HAVE_CMPXCHG128);
 429
 430     if (likely(addr == env->reserve_addr)) {
 431         Int128 oldv, cmpv, newv;
 432
 433         cmpv = int128_make128(env->reserve_val2, env->reserve_val);
 434         newv = int128_make128(new_lo, new_hi);
 435         oldv = helper_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv,
 436                                              opidx, GETPC());
 437         success = int128_eq(oldv, cmpv);
 438     }
 439     env->reserve_addr = -1;
 440     return env->so + success * CRF_EQ_BIT;
 441 }
 442 #endif
 443
 444 /*****************************************************************************/
 445 /* Altivec extension helpers */
 446 #if defined(HOST_WORDS_BIGENDIAN)
 447 #define HI_IDX 0
 448 #define LO_IDX 1
 449 #else
 450 #define HI_IDX 1
 451 #define LO_IDX 0
 452 #endif
 453
 454 /*
 455  * We use msr_le to determine index ordering in a vector.  However,
 456  * byteswapping is not simply controlled by msr_le.  We also need to
 457  * take into account endianness of the target.  This is done for the
 458  * little-endian PPC64 user-mode target.
 459  */
 460
 461 #define LVE(name, access, swap, element)                        \
 462     void helper_##name(CPUPPCState *env, ppc_avr_t *r,          \
 463                        target_ulong addr)                       \
 464     {                                                           \
 465         size_t n_elems = ARRAY_SIZE(r->element);                \
 466         int adjust = HI_IDX * (n_elems - 1);                    \
 467         int sh = sizeof(r->element[0]) >> 1;                    \
 468         int index = (addr & 0xf) >> sh;                         \
 469         if (msr_le) {                                           \
 470             index = n_elems - index - 1;                        \
 471         }                                                       \
 472                                                                 \
 473         if (needs_byteswap(env)) {                              \
 474             r->element[LO_IDX ? index : (adjust - index)] =     \
 475                 swap(access(env, addr, GETPC()));               \
 476         } else {                                                \
 477             r->element[LO_IDX ? index : (adjust - index)] =     \
 478                 access(env, addr, GETPC());                     \
 479         }                                                       \
 480     }
 481 #define I(x) (x)
 482 LVE(lvebx, cpu_ldub_data_ra, I, u8)
 483 LVE(lvehx, cpu_lduw_data_ra, bswap16, u16)
 484 LVE(lvewx, cpu_ldl_data_ra, bswap32, u32)
 485 #undef I
 486 #undef LVE
 487
 488 #define STVE(name, access, swap, element)                               \
 489     void helper_##name(CPUPPCState *env, ppc_avr_t *r,                  \
 490                        target_ulong addr)                               \
 491     {                                                                   \
 492         size_t n_elems = ARRAY_SIZE(r->element);                        \
 493         int adjust = HI_IDX * (n_elems - 1);                            \
 494         int sh = sizeof(r->element[0]) >> 1;                            \
 495         int index = (addr & 0xf) >> sh;                                 \
 496         if (msr_le) {                                                   \
 497             index = n_elems - index - 1;                                \
 498         }                                                               \
 499                                                                         \
 500         if (needs_byteswap(env)) {                                      \
 501             access(env, addr, swap(r->element[LO_IDX ? index :          \
 502                                               (adjust - index)]),       \
 503                         GETPC());                                       \
 504         } else {                                                        \
 505             access(env, addr, r->element[LO_IDX ? index :               \
 506                                          (adjust - index)], GETPC());   \
 507         }                                                               \
 508     }
 509 #define I(x) (x)
 510 STVE(stvebx, cpu_stb_data_ra, I, u8)
 511 STVE(stvehx, cpu_stw_data_ra, bswap16, u16)
 512 STVE(stvewx, cpu_stl_data_ra, bswap32, u32)
 513 #undef I
 514 #undef LVE
 515
 516 #ifdef TARGET_PPC64
 517 #define GET_NB(rb) ((rb >> 56) & 0xFF)
 518
 519 #define VSX_LXVL(name, lj)                                              \
 520 void helper_##name(CPUPPCState *env, target_ulong addr,                 \
 521                    ppc_vsr_t *xt, target_ulong rb)                      \
 522 {                                                                       \
 523     ppc_vsr_t t;                                                        \
 524     uint64_t nb = GET_NB(rb);                                           \
 525     int i;                                                              \
 526                                                                         \
 527     t.s128 = int128_zero();                                             \
 528     if (nb) {                                                           \
 529         nb = (nb >= 16) ? 16 : nb;                                      \
 530         if (msr_le && !lj) {                                            \
 531             for (i = 16; i > 16 - nb; i--) {                            \
 532                 t.VsrB(i - 1) = cpu_ldub_data_ra(env, addr, GETPC());   \
 533                 addr = addr_add(env, addr, 1);                          \
 534             }                                                           \
 535         } else {                                                        \
 536             for (i = 0; i < nb; i++) {                                  \
 537                 t.VsrB(i) = cpu_ldub_data_ra(env, addr, GETPC());       \
 538                 addr = addr_add(env, addr, 1);                          \
 539             }                                                           \
 540         }                                                               \
 541     }                                                                   \
 542     *xt = t;                                                            \
 543 }
 544
 545 VSX_LXVL(lxvl, 0)
 546 VSX_LXVL(lxvll, 1)
 547 #undef VSX_LXVL
 548
 549 #define VSX_STXVL(name, lj)                                       \
 550 void helper_##name(CPUPPCState *env, target_ulong addr,           \
 551                    ppc_vsr_t *xt, target_ulong rb)                \
 552 {                                                                 \
 553     target_ulong nb = GET_NB(rb);                                 \
 554     int i;                                                        \
 555                                                                   \
 556     if (!nb) {                                                    \
 557         return;                                                   \
 558     }                                                             \
 559                                                                   \
 560     nb = (nb >= 16) ? 16 : nb;                                    \
 561     if (msr_le && !lj) {                                          \
 562         for (i = 16; i > 16 - nb; i--) {                          \
 563             cpu_stb_data_ra(env, addr, xt->VsrB(i - 1), GETPC()); \
 564             addr = addr_add(env, addr, 1);                        \
 565         }                                                         \
 566     } else {                                                      \
 567         for (i = 0; i < nb; i++) {                                \
 568             cpu_stb_data_ra(env, addr, xt->VsrB(i), GETPC());     \
 569             addr = addr_add(env, addr, 1);                        \
 570         }                                                         \
 571     }                                                             \
 572 }
 573
 574 VSX_STXVL(stxvl, 0)
 575 VSX_STXVL(stxvll, 1)
 576 #undef VSX_STXVL
 577 #undef GET_NB
 578 #endif /* TARGET_PPC64 */
 579
 580 #undef HI_IDX
 581 #undef LO_IDX
 582
 583 void helper_tbegin(CPUPPCState *env)
 584 {
 585     /*
 586      * As a degenerate implementation, always fail tbegin.  The reason
 587      * given is "Nesting overflow".  The "persistent" bit is set,
 588      * providing a hint to the error handler to not retry.  The TFIAR
 589      * captures the address of the failure, which is this tbegin
 590      * instruction.  Instruction execution will continue with the next
 591      * instruction in memory, which is precisely what we want.
 592      */
 593
 594     env->spr[SPR_TEXASR] =
 595         (1ULL << TEXASR_FAILURE_PERSISTENT) |
 596         (1ULL << TEXASR_NESTING_OVERFLOW) |
 597         (msr_hv << TEXASR_PRIVILEGE_HV) |
 598         (msr_pr << TEXASR_PRIVILEGE_PR) |
 599         (1ULL << TEXASR_FAILURE_SUMMARY) |
 600         (1ULL << TEXASR_TFIAR_EXACT);
 601     env->spr[SPR_TFIAR] = env->nip | (msr_hv << 1) | msr_pr;
 602     env->spr[SPR_TFHAR] = env->nip + 4;
 603     env->crf[0] = 0xB; /* 0b1010 = transaction failure */
 604 }