2 * Copyright (C) 2014-2016 Broadcom Corporation
3 * Copyright (c) 2017 Red Hat, Inc.
4 * Written by Prem Mallappa, Eric Auger
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * Author: Prem Mallappa <pmallapp@broadcom.com>
19 #include "qemu/osdep.h"
21 #include "exec/target_page.h"
22 #include "hw/core/cpu.h"
23 #include "hw/qdev-properties.h"
24 #include "qapi/error.h"
25 #include "qemu/jhash.h"
26 #include "qemu/module.h"
28 #include "qemu/error-report.h"
29 #include "hw/arm/smmu-common.h"
30 #include "smmu-internal.h"
32 /* IOTLB Management */
34 static guint
smmu_iotlb_key_hash(gconstpointer v
)
36 SMMUIOTLBKey
*key
= (SMMUIOTLBKey
*)v
;
40 a
= b
= c
= JHASH_INITVAL
+ sizeof(*key
);
41 a
+= key
->asid
+ key
->vmid
+ key
->level
+ key
->tg
;
42 b
+= extract64(key
->iova
, 0, 32);
43 c
+= extract64(key
->iova
, 32, 32);
46 __jhash_final(a
, b
, c
);
51 static gboolean
smmu_iotlb_key_equal(gconstpointer v1
, gconstpointer v2
)
53 SMMUIOTLBKey
*k1
= (SMMUIOTLBKey
*)v1
, *k2
= (SMMUIOTLBKey
*)v2
;
55 return (k1
->asid
== k2
->asid
) && (k1
->iova
== k2
->iova
) &&
56 (k1
->level
== k2
->level
) && (k1
->tg
== k2
->tg
) &&
57 (k1
->vmid
== k2
->vmid
);
60 SMMUIOTLBKey
smmu_get_iotlb_key(int asid
, int vmid
, uint64_t iova
,
61 uint8_t tg
, uint8_t level
)
63 SMMUIOTLBKey key
= {.asid
= asid
, .vmid
= vmid
, .iova
= iova
,
64 .tg
= tg
, .level
= level
};
69 static SMMUTLBEntry
*smmu_iotlb_lookup_all_levels(SMMUState
*bs
,
71 SMMUTransTableInfo
*tt
,
74 uint8_t tg
= (tt
->granule_sz
- 10) / 2;
75 uint8_t inputsize
= 64 - tt
->tsz
;
76 uint8_t stride
= tt
->granule_sz
- 3;
77 uint8_t level
= 4 - (inputsize
- 4) / stride
;
78 SMMUTLBEntry
*entry
= NULL
;
81 uint64_t subpage_size
= 1ULL << level_shift(level
, tt
->granule_sz
);
82 uint64_t mask
= subpage_size
- 1;
85 key
= smmu_get_iotlb_key(cfg
->asid
, cfg
->s2cfg
.vmid
,
86 iova
& ~mask
, tg
, level
);
87 entry
= g_hash_table_lookup(bs
->iotlb
, &key
);
97 * smmu_iotlb_lookup - Look up for a TLB entry.
98 * @bs: SMMU state which includes the TLB instance
99 * @cfg: Configuration of the translation
100 * @tt: Translation table info (granule and tsz)
101 * @iova: IOVA address to lookup
103 * returns a valid entry on success, otherwise NULL.
104 * In case of nested translation, tt can be updated to include
105 * the granule of the found entry as it might different from
108 SMMUTLBEntry
*smmu_iotlb_lookup(SMMUState
*bs
, SMMUTransCfg
*cfg
,
109 SMMUTransTableInfo
*tt
, hwaddr iova
)
111 SMMUTLBEntry
*entry
= NULL
;
113 entry
= smmu_iotlb_lookup_all_levels(bs
, cfg
, tt
, iova
);
115 * For nested translation also try the s2 granule, as the TLB will insert
116 * it if the size of s2 tlb entry was smaller.
118 if (!entry
&& (cfg
->stage
== SMMU_NESTED
) &&
119 (cfg
->s2cfg
.granule_sz
!= tt
->granule_sz
)) {
120 tt
->granule_sz
= cfg
->s2cfg
.granule_sz
;
121 entry
= smmu_iotlb_lookup_all_levels(bs
, cfg
, tt
, iova
);
126 trace_smmu_iotlb_lookup_hit(cfg
->asid
, cfg
->s2cfg
.vmid
, iova
,
127 cfg
->iotlb_hits
, cfg
->iotlb_misses
,
128 100 * cfg
->iotlb_hits
/
129 (cfg
->iotlb_hits
+ cfg
->iotlb_misses
));
132 trace_smmu_iotlb_lookup_miss(cfg
->asid
, cfg
->s2cfg
.vmid
, iova
,
133 cfg
->iotlb_hits
, cfg
->iotlb_misses
,
134 100 * cfg
->iotlb_hits
/
135 (cfg
->iotlb_hits
+ cfg
->iotlb_misses
));
140 void smmu_iotlb_insert(SMMUState
*bs
, SMMUTransCfg
*cfg
, SMMUTLBEntry
*new)
142 SMMUIOTLBKey
*key
= g_new0(SMMUIOTLBKey
, 1);
143 uint8_t tg
= (new->granule
- 10) / 2;
145 if (g_hash_table_size(bs
->iotlb
) >= SMMU_IOTLB_MAX_SIZE
) {
146 smmu_iotlb_inv_all(bs
);
149 *key
= smmu_get_iotlb_key(cfg
->asid
, cfg
->s2cfg
.vmid
, new->entry
.iova
,
151 trace_smmu_iotlb_insert(cfg
->asid
, cfg
->s2cfg
.vmid
, new->entry
.iova
,
153 g_hash_table_insert(bs
->iotlb
, key
, new);
156 void smmu_iotlb_inv_all(SMMUState
*s
)
158 trace_smmu_iotlb_inv_all();
159 g_hash_table_remove_all(s
->iotlb
);
162 static gboolean
smmu_hash_remove_by_asid_vmid(gpointer key
, gpointer value
,
165 SMMUIOTLBPageInvInfo
*info
= (SMMUIOTLBPageInvInfo
*)user_data
;
166 SMMUIOTLBKey
*iotlb_key
= (SMMUIOTLBKey
*)key
;
168 return (SMMU_IOTLB_ASID(*iotlb_key
) == info
->asid
) &&
169 (SMMU_IOTLB_VMID(*iotlb_key
) == info
->vmid
);
172 static gboolean
smmu_hash_remove_by_vmid(gpointer key
, gpointer value
,
175 int vmid
= *(int *)user_data
;
176 SMMUIOTLBKey
*iotlb_key
= (SMMUIOTLBKey
*)key
;
178 return SMMU_IOTLB_VMID(*iotlb_key
) == vmid
;
181 static gboolean
smmu_hash_remove_by_vmid_s1(gpointer key
, gpointer value
,
184 int vmid
= *(int *)user_data
;
185 SMMUIOTLBKey
*iotlb_key
= (SMMUIOTLBKey
*)key
;
187 return (SMMU_IOTLB_VMID(*iotlb_key
) == vmid
) &&
188 (SMMU_IOTLB_ASID(*iotlb_key
) >= 0);
191 static gboolean
smmu_hash_remove_by_asid_vmid_iova(gpointer key
, gpointer value
,
194 SMMUTLBEntry
*iter
= (SMMUTLBEntry
*)value
;
195 IOMMUTLBEntry
*entry
= &iter
->entry
;
196 SMMUIOTLBPageInvInfo
*info
= (SMMUIOTLBPageInvInfo
*)user_data
;
197 SMMUIOTLBKey iotlb_key
= *(SMMUIOTLBKey
*)key
;
199 if (info
->asid
>= 0 && info
->asid
!= SMMU_IOTLB_ASID(iotlb_key
)) {
202 if (info
->vmid
>= 0 && info
->vmid
!= SMMU_IOTLB_VMID(iotlb_key
)) {
205 return ((info
->iova
& ~entry
->addr_mask
) == entry
->iova
) ||
206 ((entry
->iova
& ~info
->mask
) == info
->iova
);
209 static gboolean
smmu_hash_remove_by_vmid_ipa(gpointer key
, gpointer value
,
212 SMMUTLBEntry
*iter
= (SMMUTLBEntry
*)value
;
213 IOMMUTLBEntry
*entry
= &iter
->entry
;
214 SMMUIOTLBPageInvInfo
*info
= (SMMUIOTLBPageInvInfo
*)user_data
;
215 SMMUIOTLBKey iotlb_key
= *(SMMUIOTLBKey
*)key
;
217 if (SMMU_IOTLB_ASID(iotlb_key
) >= 0) {
218 /* This is a stage-1 address. */
221 if (info
->vmid
!= SMMU_IOTLB_VMID(iotlb_key
)) {
224 return ((info
->iova
& ~entry
->addr_mask
) == entry
->iova
) ||
225 ((entry
->iova
& ~info
->mask
) == info
->iova
);
228 void smmu_iotlb_inv_iova(SMMUState
*s
, int asid
, int vmid
, dma_addr_t iova
,
229 uint8_t tg
, uint64_t num_pages
, uint8_t ttl
)
231 /* if tg is not set we use 4KB range invalidation */
232 uint8_t granule
= tg
? tg
* 2 + 10 : 12;
234 if (ttl
&& (num_pages
== 1) && (asid
>= 0)) {
235 SMMUIOTLBKey key
= smmu_get_iotlb_key(asid
, vmid
, iova
, tg
, ttl
);
237 if (g_hash_table_remove(s
->iotlb
, &key
)) {
241 * if the entry is not found, let's see if it does not
242 * belong to a larger IOTLB entry
246 SMMUIOTLBPageInvInfo info
= {
247 .asid
= asid
, .iova
= iova
,
249 .mask
= (num_pages
* 1 << granule
) - 1};
251 g_hash_table_foreach_remove(s
->iotlb
,
252 smmu_hash_remove_by_asid_vmid_iova
,
257 * Similar to smmu_iotlb_inv_iova(), but for Stage-2, ASID is always -1,
258 * in Stage-1 invalidation ASID = -1, means don't care.
260 void smmu_iotlb_inv_ipa(SMMUState
*s
, int vmid
, dma_addr_t ipa
, uint8_t tg
,
261 uint64_t num_pages
, uint8_t ttl
)
263 uint8_t granule
= tg
? tg
* 2 + 10 : 12;
266 if (ttl
&& (num_pages
== 1)) {
267 SMMUIOTLBKey key
= smmu_get_iotlb_key(asid
, vmid
, ipa
, tg
, ttl
);
269 if (g_hash_table_remove(s
->iotlb
, &key
)) {
274 SMMUIOTLBPageInvInfo info
= {
277 .mask
= (num_pages
<< granule
) - 1};
279 g_hash_table_foreach_remove(s
->iotlb
,
280 smmu_hash_remove_by_vmid_ipa
,
284 void smmu_iotlb_inv_asid_vmid(SMMUState
*s
, int asid
, int vmid
)
286 SMMUIOTLBPageInvInfo info
= {
291 trace_smmu_iotlb_inv_asid_vmid(asid
, vmid
);
292 g_hash_table_foreach_remove(s
->iotlb
, smmu_hash_remove_by_asid_vmid
, &info
);
295 void smmu_iotlb_inv_vmid(SMMUState
*s
, int vmid
)
297 trace_smmu_iotlb_inv_vmid(vmid
);
298 g_hash_table_foreach_remove(s
->iotlb
, smmu_hash_remove_by_vmid
, &vmid
);
301 inline void smmu_iotlb_inv_vmid_s1(SMMUState
*s
, int vmid
)
303 trace_smmu_iotlb_inv_vmid_s1(vmid
);
304 g_hash_table_foreach_remove(s
->iotlb
, smmu_hash_remove_by_vmid_s1
, &vmid
);
307 /* VMSAv8-64 Translation */
310 * get_pte - Get the content of a page table entry located at
313 static int get_pte(dma_addr_t baseaddr
, uint32_t index
, uint64_t *pte
,
314 SMMUPTWEventInfo
*info
)
317 dma_addr_t addr
= baseaddr
+ index
* sizeof(*pte
);
319 /* TODO: guarantee 64-bit single-copy atomicity */
320 ret
= ldq_le_dma(&address_space_memory
, addr
, pte
, MEMTXATTRS_UNSPECIFIED
);
322 if (ret
!= MEMTX_OK
) {
323 info
->type
= SMMU_PTW_ERR_WALK_EABT
;
327 trace_smmu_get_pte(baseaddr
, index
, addr
, *pte
);
331 /* VMSAv8-64 Translation Table Format Descriptor Decoding */
334 * get_page_pte_address - returns the L3 descriptor output address,
336 * ARM ARM spec: Figure D4-17 VMSAv8-64 level 3 descriptor format
338 static inline hwaddr
get_page_pte_address(uint64_t pte
, int granule_sz
)
340 return PTE_ADDRESS(pte
, granule_sz
);
344 * get_table_pte_address - return table descriptor output address,
345 * ie. address of next level table
346 * ARM ARM Figure D4-16 VMSAv8-64 level0, level1, and level 2 descriptor formats
348 static inline hwaddr
get_table_pte_address(uint64_t pte
, int granule_sz
)
350 return PTE_ADDRESS(pte
, granule_sz
);
354 * get_block_pte_address - return block descriptor output address and block size
355 * ARM ARM Figure D4-16 VMSAv8-64 level0, level1, and level 2 descriptor formats
357 static inline hwaddr
get_block_pte_address(uint64_t pte
, int level
,
358 int granule_sz
, uint64_t *bsz
)
360 int n
= level_shift(level
, granule_sz
);
363 return PTE_ADDRESS(pte
, n
);
366 SMMUTransTableInfo
*select_tt(SMMUTransCfg
*cfg
, dma_addr_t iova
)
368 bool tbi
= extract64(iova
, 55, 1) ? TBI1(cfg
->tbi
) : TBI0(cfg
->tbi
);
369 uint8_t tbi_byte
= tbi
* 8;
371 if (cfg
->tt
[0].tsz
&&
372 !extract64(iova
, 64 - cfg
->tt
[0].tsz
, cfg
->tt
[0].tsz
- tbi_byte
)) {
373 /* there is a ttbr0 region and we are in it (high bits all zero) */
375 } else if (cfg
->tt
[1].tsz
&&
376 sextract64(iova
, 64 - cfg
->tt
[1].tsz
, cfg
->tt
[1].tsz
- tbi_byte
) == -1) {
377 /* there is a ttbr1 region and we are in it (high bits all one) */
379 } else if (!cfg
->tt
[0].tsz
) {
380 /* ttbr0 region is "everything not in the ttbr1 region" */
382 } else if (!cfg
->tt
[1].tsz
) {
383 /* ttbr1 region is "everything not in the ttbr0 region" */
386 /* in the gap between the two regions, this is a Translation fault */
390 /* Translate stage-1 table address using stage-2 page table. */
391 static inline int translate_table_addr_ipa(SMMUState
*bs
,
392 dma_addr_t
*table_addr
,
394 SMMUPTWEventInfo
*info
)
396 dma_addr_t addr
= *table_addr
;
397 SMMUTLBEntry
*cached_entry
;
401 * The translation table walks performed from TTB0 or TTB1 are always
402 * performed in IPA space if stage 2 translations are enabled.
405 cfg
->stage
= SMMU_STAGE_2
;
407 cached_entry
= smmu_translate(bs
, cfg
, addr
, IOMMU_RO
, info
);
409 cfg
->stage
= SMMU_NESTED
;
412 *table_addr
= CACHED_ENTRY_TO_ADDR(cached_entry
, addr
);
416 info
->stage
= SMMU_STAGE_2
;
418 info
->is_ipa_descriptor
= true;
423 * smmu_ptw_64_s1 - VMSAv8-64 Walk of the page tables for a given IOVA
424 * @bs: smmu state which includes TLB instance
425 * @cfg: translation config
426 * @iova: iova to translate
428 * @tlbe: SMMUTLBEntry (out)
429 * @info: handle to an error info
431 * Return 0 on success, < 0 on error. In case of error, @info is filled
432 * and tlbe->perm is set to IOMMU_NONE.
433 * Upon success, @tlbe is filled with translated_addr and entry
436 static int smmu_ptw_64_s1(SMMUState
*bs
, SMMUTransCfg
*cfg
,
437 dma_addr_t iova
, IOMMUAccessFlags perm
,
438 SMMUTLBEntry
*tlbe
, SMMUPTWEventInfo
*info
)
440 dma_addr_t baseaddr
, indexmask
;
441 SMMUStage stage
= cfg
->stage
;
442 SMMUTransTableInfo
*tt
= select_tt(cfg
, iova
);
443 uint8_t level
, granule_sz
, inputsize
, stride
;
445 if (!tt
|| tt
->disabled
) {
446 info
->type
= SMMU_PTW_ERR_TRANSLATION
;
450 granule_sz
= tt
->granule_sz
;
451 stride
= VMSA_STRIDE(granule_sz
);
452 inputsize
= 64 - tt
->tsz
;
453 level
= 4 - (inputsize
- 4) / stride
;
454 indexmask
= VMSA_IDXMSK(inputsize
, stride
, level
);
455 baseaddr
= extract64(tt
->ttb
, 0, 48);
456 baseaddr
&= ~indexmask
;
458 while (level
< VMSA_LEVELS
) {
459 uint64_t subpage_size
= 1ULL << level_shift(level
, granule_sz
);
460 uint64_t mask
= subpage_size
- 1;
461 uint32_t offset
= iova_level_offset(iova
, inputsize
, level
, granule_sz
);
463 dma_addr_t pte_addr
= baseaddr
+ offset
* sizeof(pte
);
466 if (get_pte(baseaddr
, offset
, &pte
, info
)) {
469 trace_smmu_ptw_level(stage
, level
, iova
, subpage_size
,
470 baseaddr
, offset
, pte
);
472 if (is_invalid_pte(pte
) || is_reserved_pte(pte
, level
)) {
473 trace_smmu_ptw_invalid_pte(stage
, level
, baseaddr
,
474 pte_addr
, offset
, pte
);
478 if (is_table_pte(pte
, level
)) {
479 ap
= PTE_APTABLE(pte
);
481 if (is_permission_fault(ap
, perm
) && !tt
->had
) {
482 info
->type
= SMMU_PTW_ERR_PERMISSION
;
485 baseaddr
= get_table_pte_address(pte
, granule_sz
);
486 if (cfg
->stage
== SMMU_NESTED
) {
487 if (translate_table_addr_ipa(bs
, &baseaddr
, cfg
, info
)) {
493 } else if (is_page_pte(pte
, level
)) {
494 gpa
= get_page_pte_address(pte
, granule_sz
);
495 trace_smmu_ptw_page_pte(stage
, level
, iova
,
496 baseaddr
, pte_addr
, pte
, gpa
);
500 gpa
= get_block_pte_address(pte
, level
, granule_sz
,
502 trace_smmu_ptw_block_pte(stage
, level
, baseaddr
,
503 pte_addr
, pte
, iova
, gpa
,
508 * QEMU does not currently implement HTTU, so if AFFD and PTE.AF
509 * are 0 we take an Access flag fault. (5.4. Context Descriptor)
510 * An Access flag fault takes priority over a Permission fault.
512 if (!PTE_AF(pte
) && !cfg
->affd
) {
513 info
->type
= SMMU_PTW_ERR_ACCESS
;
518 if (is_permission_fault(ap
, perm
)) {
519 info
->type
= SMMU_PTW_ERR_PERMISSION
;
524 * The address output from the translation causes a stage 1 Address
525 * Size fault if it exceeds the range of the effective IPA size for
528 if (gpa
>= (1ULL << cfg
->oas
)) {
529 info
->type
= SMMU_PTW_ERR_ADDR_SIZE
;
533 tlbe
->entry
.translated_addr
= gpa
;
534 tlbe
->entry
.iova
= iova
& ~mask
;
535 tlbe
->entry
.addr_mask
= mask
;
536 tlbe
->parent_perm
= PTE_AP_TO_PERM(ap
);
537 tlbe
->entry
.perm
= tlbe
->parent_perm
;
539 tlbe
->granule
= granule_sz
;
542 info
->type
= SMMU_PTW_ERR_TRANSLATION
;
545 info
->stage
= SMMU_STAGE_1
;
546 tlbe
->entry
.perm
= IOMMU_NONE
;
551 * smmu_ptw_64_s2 - VMSAv8-64 Walk of the page tables for a given ipa
553 * @cfg: translation config
554 * @ipa: ipa to translate
556 * @tlbe: SMMUTLBEntry (out)
557 * @info: handle to an error info
559 * Return 0 on success, < 0 on error. In case of error, @info is filled
560 * and tlbe->perm is set to IOMMU_NONE.
561 * Upon success, @tlbe is filled with translated_addr and entry
564 static int smmu_ptw_64_s2(SMMUTransCfg
*cfg
,
565 dma_addr_t ipa
, IOMMUAccessFlags perm
,
566 SMMUTLBEntry
*tlbe
, SMMUPTWEventInfo
*info
)
568 const SMMUStage stage
= SMMU_STAGE_2
;
569 int granule_sz
= cfg
->s2cfg
.granule_sz
;
570 /* ARM DDI0487I.a: Table D8-7. */
571 int inputsize
= 64 - cfg
->s2cfg
.tsz
;
572 int level
= get_start_level(cfg
->s2cfg
.sl0
, granule_sz
);
573 int stride
= VMSA_STRIDE(granule_sz
);
574 int idx
= pgd_concat_idx(level
, granule_sz
, ipa
);
576 * Get the ttb from concatenated structure.
577 * The offset is the idx * size of each ttb(number of ptes * (sizeof(pte))
579 uint64_t baseaddr
= extract64(cfg
->s2cfg
.vttb
, 0, 48) + (1 << stride
) *
580 idx
* sizeof(uint64_t);
581 dma_addr_t indexmask
= VMSA_IDXMSK(inputsize
, stride
, level
);
583 baseaddr
&= ~indexmask
;
586 * On input, a stage 2 Translation fault occurs if the IPA is outside the
587 * range configured by the relevant S2T0SZ field of the STE.
589 if (ipa
>= (1ULL << inputsize
)) {
590 info
->type
= SMMU_PTW_ERR_TRANSLATION
;
594 while (level
< VMSA_LEVELS
) {
595 uint64_t subpage_size
= 1ULL << level_shift(level
, granule_sz
);
596 uint64_t mask
= subpage_size
- 1;
597 uint32_t offset
= iova_level_offset(ipa
, inputsize
, level
, granule_sz
);
599 dma_addr_t pte_addr
= baseaddr
+ offset
* sizeof(pte
);
602 if (get_pte(baseaddr
, offset
, &pte
, info
)) {
605 trace_smmu_ptw_level(stage
, level
, ipa
, subpage_size
,
606 baseaddr
, offset
, pte
);
607 if (is_invalid_pte(pte
) || is_reserved_pte(pte
, level
)) {
608 trace_smmu_ptw_invalid_pte(stage
, level
, baseaddr
,
609 pte_addr
, offset
, pte
);
613 if (is_table_pte(pte
, level
)) {
614 baseaddr
= get_table_pte_address(pte
, granule_sz
);
617 } else if (is_page_pte(pte
, level
)) {
618 gpa
= get_page_pte_address(pte
, granule_sz
);
619 trace_smmu_ptw_page_pte(stage
, level
, ipa
,
620 baseaddr
, pte_addr
, pte
, gpa
);
624 gpa
= get_block_pte_address(pte
, level
, granule_sz
,
626 trace_smmu_ptw_block_pte(stage
, level
, baseaddr
,
627 pte_addr
, pte
, ipa
, gpa
,
632 * If S2AFFD and PTE.AF are 0 => fault. (5.2. Stream Table Entry)
633 * An Access fault takes priority over a Permission fault.
635 if (!PTE_AF(pte
) && !cfg
->s2cfg
.affd
) {
636 info
->type
= SMMU_PTW_ERR_ACCESS
;
641 if (is_permission_fault_s2(s2ap
, perm
)) {
642 info
->type
= SMMU_PTW_ERR_PERMISSION
;
647 * The address output from the translation causes a stage 2 Address
648 * Size fault if it exceeds the effective PA output range.
650 if (gpa
>= (1ULL << cfg
->s2cfg
.eff_ps
)) {
651 info
->type
= SMMU_PTW_ERR_ADDR_SIZE
;
655 tlbe
->entry
.translated_addr
= gpa
;
656 tlbe
->entry
.iova
= ipa
& ~mask
;
657 tlbe
->entry
.addr_mask
= mask
;
658 tlbe
->parent_perm
= s2ap
;
659 tlbe
->entry
.perm
= tlbe
->parent_perm
;
661 tlbe
->granule
= granule_sz
;
664 info
->type
= SMMU_PTW_ERR_TRANSLATION
;
669 info
->stage
= SMMU_STAGE_2
;
670 tlbe
->entry
.perm
= IOMMU_NONE
;
675 * combine S1 and S2 TLB entries into a single entry.
676 * As a result the S1 entry is overriden with combined data.
678 static void combine_tlb(SMMUTLBEntry
*tlbe
, SMMUTLBEntry
*tlbe_s2
,
679 dma_addr_t iova
, SMMUTransCfg
*cfg
)
681 if (tlbe_s2
->entry
.addr_mask
< tlbe
->entry
.addr_mask
) {
682 tlbe
->entry
.addr_mask
= tlbe_s2
->entry
.addr_mask
;
683 tlbe
->granule
= tlbe_s2
->granule
;
684 tlbe
->level
= tlbe_s2
->level
;
687 tlbe
->entry
.translated_addr
= CACHED_ENTRY_TO_ADDR(tlbe_s2
,
688 tlbe
->entry
.translated_addr
);
690 tlbe
->entry
.iova
= iova
& ~tlbe
->entry
.addr_mask
;
691 /* parent_perm has s2 perm while perm keeps s1 perm. */
692 tlbe
->parent_perm
= tlbe_s2
->entry
.perm
;
697 * smmu_ptw - Walk the page tables for an IOVA, according to @cfg
699 * @bs: smmu state which includes TLB instance
700 * @cfg: translation configuration
701 * @iova: iova to translate
702 * @perm: tentative access type
703 * @tlbe: returned entry
704 * @info: ptw event handle
706 * return 0 on success
708 int smmu_ptw(SMMUState
*bs
, SMMUTransCfg
*cfg
, dma_addr_t iova
,
709 IOMMUAccessFlags perm
, SMMUTLBEntry
*tlbe
, SMMUPTWEventInfo
*info
)
712 SMMUTLBEntry tlbe_s2
;
715 if (cfg
->stage
== SMMU_STAGE_1
) {
716 return smmu_ptw_64_s1(bs
, cfg
, iova
, perm
, tlbe
, info
);
717 } else if (cfg
->stage
== SMMU_STAGE_2
) {
719 * If bypassing stage 1(or unimplemented), the input address is passed
720 * directly to stage 2 as IPA. If the input address of a transaction
721 * exceeds the size of the IAS, a stage 1 Address Size fault occurs.
722 * For AA64, IAS = OAS according to (IHI 0070.E.a) "3.4 Address sizes"
724 if (iova
>= (1ULL << cfg
->oas
)) {
725 info
->type
= SMMU_PTW_ERR_ADDR_SIZE
;
726 info
->stage
= SMMU_STAGE_1
;
727 tlbe
->entry
.perm
= IOMMU_NONE
;
731 return smmu_ptw_64_s2(cfg
, iova
, perm
, tlbe
, info
);
735 ret
= smmu_ptw_64_s1(bs
, cfg
, iova
, perm
, tlbe
, info
);
740 ipa
= CACHED_ENTRY_TO_ADDR(tlbe
, iova
);
741 ret
= smmu_ptw_64_s2(cfg
, ipa
, perm
, &tlbe_s2
, info
);
746 combine_tlb(tlbe
, &tlbe_s2
, iova
, cfg
);
750 SMMUTLBEntry
*smmu_translate(SMMUState
*bs
, SMMUTransCfg
*cfg
, dma_addr_t addr
,
751 IOMMUAccessFlags flag
, SMMUPTWEventInfo
*info
)
753 SMMUTLBEntry
*cached_entry
= NULL
;
754 SMMUTransTableInfo
*tt
;
758 * Combined attributes used for TLB lookup, holds the attributes for
761 SMMUTransTableInfo tt_combined
;
763 if (cfg
->stage
== SMMU_STAGE_2
) {
765 tt_combined
.granule_sz
= cfg
->s2cfg
.granule_sz
;
766 tt_combined
.tsz
= cfg
->s2cfg
.tsz
;
768 /* Select stage1 translation table. */
769 tt
= select_tt(cfg
, addr
);
771 info
->type
= SMMU_PTW_ERR_TRANSLATION
;
772 info
->stage
= SMMU_STAGE_1
;
775 tt_combined
.granule_sz
= tt
->granule_sz
;
776 tt_combined
.tsz
= tt
->tsz
;
779 cached_entry
= smmu_iotlb_lookup(bs
, cfg
, &tt_combined
, addr
);
781 if ((flag
& IOMMU_WO
) && !(cached_entry
->entry
.perm
&
782 cached_entry
->parent_perm
& IOMMU_WO
)) {
783 info
->type
= SMMU_PTW_ERR_PERMISSION
;
784 info
->stage
= !(cached_entry
->entry
.perm
& IOMMU_WO
) ?
792 cached_entry
= g_new0(SMMUTLBEntry
, 1);
793 status
= smmu_ptw(bs
, cfg
, addr
, flag
, cached_entry
, info
);
795 g_free(cached_entry
);
798 smmu_iotlb_insert(bs
, cfg
, cached_entry
);
803 * The bus number is used for lookup when SID based invalidation occurs.
804 * In that case we lazily populate the SMMUPciBus array from the bus hash
805 * table. At the time the SMMUPciBus is created (smmu_find_add_as), the bus
806 * numbers may not be always initialized yet.
808 SMMUPciBus
*smmu_find_smmu_pcibus(SMMUState
*s
, uint8_t bus_num
)
810 SMMUPciBus
*smmu_pci_bus
= s
->smmu_pcibus_by_bus_num
[bus_num
];
817 g_hash_table_iter_init(&iter
, s
->smmu_pcibus_by_busptr
);
818 while (g_hash_table_iter_next(&iter
, NULL
, (void **)&smmu_pci_bus
)) {
819 if (pci_bus_num(smmu_pci_bus
->bus
) == bus_num
) {
820 s
->smmu_pcibus_by_bus_num
[bus_num
] = smmu_pci_bus
;
828 static AddressSpace
*smmu_find_add_as(PCIBus
*bus
, void *opaque
, int devfn
)
830 SMMUState
*s
= opaque
;
831 SMMUPciBus
*sbus
= g_hash_table_lookup(s
->smmu_pcibus_by_busptr
, bus
);
833 static unsigned int index
;
836 sbus
= g_malloc0(sizeof(SMMUPciBus
) +
837 sizeof(SMMUDevice
*) * SMMU_PCI_DEVFN_MAX
);
839 g_hash_table_insert(s
->smmu_pcibus_by_busptr
, bus
, sbus
);
842 sdev
= sbus
->pbdev
[devfn
];
844 char *name
= g_strdup_printf("%s-%d-%d", s
->mrtypename
, devfn
, index
++);
846 sdev
= sbus
->pbdev
[devfn
] = g_new0(SMMUDevice
, 1);
852 memory_region_init_iommu(&sdev
->iommu
, sizeof(sdev
->iommu
),
854 OBJECT(s
), name
, UINT64_MAX
);
855 address_space_init(&sdev
->as
,
856 MEMORY_REGION(&sdev
->iommu
), name
);
857 trace_smmu_add_mr(name
);
864 static const PCIIOMMUOps smmu_ops
= {
865 .get_address_space
= smmu_find_add_as
,
868 SMMUDevice
*smmu_find_sdev(SMMUState
*s
, uint32_t sid
)
870 uint8_t bus_n
, devfn
;
871 SMMUPciBus
*smmu_bus
;
873 bus_n
= PCI_BUS_NUM(sid
);
874 smmu_bus
= smmu_find_smmu_pcibus(s
, bus_n
);
876 devfn
= SMMU_PCI_DEVFN(sid
);
877 return smmu_bus
->pbdev
[devfn
];
882 /* Unmap all notifiers attached to @mr */
883 static void smmu_inv_notifiers_mr(IOMMUMemoryRegion
*mr
)
887 trace_smmu_inv_notifiers_mr(mr
->parent_obj
.name
);
888 IOMMU_NOTIFIER_FOREACH(n
, mr
) {
889 memory_region_unmap_iommu_notifier_range(n
);
893 /* Unmap all notifiers of all mr's */
894 void smmu_inv_notifiers_all(SMMUState
*s
)
898 QLIST_FOREACH(sdev
, &s
->devices_with_notifiers
, next
) {
899 smmu_inv_notifiers_mr(&sdev
->iommu
);
903 static void smmu_base_realize(DeviceState
*dev
, Error
**errp
)
905 SMMUState
*s
= ARM_SMMU(dev
);
906 SMMUBaseClass
*sbc
= ARM_SMMU_GET_CLASS(dev
);
907 Error
*local_err
= NULL
;
909 sbc
->parent_realize(dev
, &local_err
);
911 error_propagate(errp
, local_err
);
914 s
->configs
= g_hash_table_new_full(NULL
, NULL
, NULL
, g_free
);
915 s
->iotlb
= g_hash_table_new_full(smmu_iotlb_key_hash
, smmu_iotlb_key_equal
,
917 s
->smmu_pcibus_by_busptr
= g_hash_table_new(NULL
, NULL
);
919 if (s
->primary_bus
) {
920 pci_setup_iommu(s
->primary_bus
, &smmu_ops
, s
);
922 error_setg(errp
, "SMMU is not attached to any PCI bus!");
926 static void smmu_base_reset_hold(Object
*obj
, ResetType type
)
928 SMMUState
*s
= ARM_SMMU(obj
);
930 memset(s
->smmu_pcibus_by_bus_num
, 0, sizeof(s
->smmu_pcibus_by_bus_num
));
932 g_hash_table_remove_all(s
->configs
);
933 g_hash_table_remove_all(s
->iotlb
);
936 static Property smmu_dev_properties
[] = {
937 DEFINE_PROP_UINT8("bus_num", SMMUState
, bus_num
, 0),
938 DEFINE_PROP_LINK("primary-bus", SMMUState
, primary_bus
,
939 TYPE_PCI_BUS
, PCIBus
*),
940 DEFINE_PROP_END_OF_LIST(),
943 static void smmu_base_class_init(ObjectClass
*klass
, void *data
)
945 DeviceClass
*dc
= DEVICE_CLASS(klass
);
946 ResettableClass
*rc
= RESETTABLE_CLASS(klass
);
947 SMMUBaseClass
*sbc
= ARM_SMMU_CLASS(klass
);
949 device_class_set_props(dc
, smmu_dev_properties
);
950 device_class_set_parent_realize(dc
, smmu_base_realize
,
951 &sbc
->parent_realize
);
952 rc
->phases
.hold
= smmu_base_reset_hold
;
955 static const TypeInfo smmu_base_info
= {
956 .name
= TYPE_ARM_SMMU
,
957 .parent
= TYPE_SYS_BUS_DEVICE
,
958 .instance_size
= sizeof(SMMUState
),
960 .class_size
= sizeof(SMMUBaseClass
),
961 .class_init
= smmu_base_class_init
,
965 static void smmu_base_register_types(void)
967 type_register_static(&smmu_base_info
);
970 type_init(smmu_base_register_types
)