include/hw/arm/aspeed_soc.h

   1 /*
   2  * ASPEED SoC family
   3  *
   4  * Andrew Jeffery <andrew@aj.id.au>
   5  *
   6  * Copyright 2016 IBM Corp.
   7  *
   8  * This code is licensed under the GPL version 2 or later.  See
   9  * the COPYING file in the top-level directory.
  10  */
  11
  12 #ifndef ASPEED_SOC_H
  13 #define ASPEED_SOC_H
  14
  15 #include "hw/cpu/a15mpcore.h"
  16 #include "hw/intc/aspeed_vic.h"
  17 #include "hw/misc/aspeed_scu.h"
  18 #include "hw/misc/aspeed_sdmc.h"
  19 #include "hw/misc/aspeed_xdma.h"
  20 #include "hw/timer/aspeed_timer.h"
  21 #include "hw/rtc/aspeed_rtc.h"
  22 #include "hw/i2c/aspeed_i2c.h"
  23 #include "hw/ssi/aspeed_smc.h"
  24 #include "hw/watchdog/wdt_aspeed.h"
  25 #include "hw/net/ftgmac100.h"
  26 #include "target/arm/cpu.h"
  27 #include "hw/gpio/aspeed_gpio.h"
  28 #include "hw/sd/aspeed_sdhci.h"
  29
  30 #define ASPEED_SPIS_NUM  2
  31 #define ASPEED_WDTS_NUM  4
  32 #define ASPEED_CPUS_NUM  2
  33 #define ASPEED_MACS_NUM  4
  34
  35 typedef struct AspeedSoCState {
  36     /*< private >*/
  37     DeviceState parent;
  38
  39     /*< public >*/
  40     ARMCPU cpu[ASPEED_CPUS_NUM];
  41     uint32_t num_cpus;
  42     A15MPPrivState     a7mpcore;
  43     MemoryRegion *dram_mr;
  44     MemoryRegion sram;
  45     AspeedVICState vic;
  46     AspeedRtcState rtc;
  47     AspeedTimerCtrlState timerctrl;
  48     AspeedI2CState i2c;
  49     AspeedSCUState scu;
  50     AspeedXDMAState xdma;
  51     AspeedSMCState fmc;
  52     AspeedSMCState spi[ASPEED_SPIS_NUM];
  53     AspeedSDMCState sdmc;
  54     AspeedWDTState wdt[ASPEED_WDTS_NUM];
  55     FTGMAC100State ftgmac100[ASPEED_MACS_NUM];
  56     AspeedMiiState mii[ASPEED_MACS_NUM];
  57     AspeedGPIOState gpio;
  58     AspeedGPIOState gpio_1_8v;
  59     AspeedSDHCIState sdhci;
  60 } AspeedSoCState;
  61
  62 #define TYPE_ASPEED_SOC "aspeed-soc"
  63 #define ASPEED_SOC(obj) OBJECT_CHECK(AspeedSoCState, (obj), TYPE_ASPEED_SOC)
  64
  65 typedef struct AspeedSoCClass {
  66     DeviceClass parent_class;
  67
  68     const char *name;
  69     const char *cpu_type;
  70     uint32_t silicon_rev;
  71     uint64_t sram_size;
  72     int spis_num;
  73     int wdts_num;
  74     int macs_num;
  75     const int *irqmap;
  76     const hwaddr *memmap;
  77     uint32_t num_cpus;
  78 } AspeedSoCClass;
  79
  80 #define ASPEED_SOC_CLASS(klass)                                         \
  81     OBJECT_CLASS_CHECK(AspeedSoCClass, (klass), TYPE_ASPEED_SOC)
  82 #define ASPEED_SOC_GET_CLASS(obj)                               \
  83     OBJECT_GET_CLASS(AspeedSoCClass, (obj), TYPE_ASPEED_SOC)
  84
  85 enum {
  86     ASPEED_IOMEM,
  87     ASPEED_UART1,
  88     ASPEED_UART2,
  89     ASPEED_UART3,
  90     ASPEED_UART4,
  91     ASPEED_UART5,
  92     ASPEED_VUART,
  93     ASPEED_FMC,
  94     ASPEED_SPI1,
  95     ASPEED_SPI2,
  96     ASPEED_VIC,
  97     ASPEED_SDMC,
  98     ASPEED_SCU,
  99     ASPEED_ADC,
 100     ASPEED_VIDEO,
 101     ASPEED_SRAM,
 102     ASPEED_SDHCI,
 103     ASPEED_GPIO,
 104     ASPEED_GPIO_1_8V,
 105     ASPEED_RTC,
 106     ASPEED_TIMER1,
 107     ASPEED_TIMER2,
 108     ASPEED_TIMER3,
 109     ASPEED_TIMER4,
 110     ASPEED_TIMER5,
 111     ASPEED_TIMER6,
 112     ASPEED_TIMER7,
 113     ASPEED_TIMER8,
 114     ASPEED_WDT,
 115     ASPEED_PWM,
 116     ASPEED_LPC,
 117     ASPEED_IBT,
 118     ASPEED_I2C,
 119     ASPEED_ETH1,
 120     ASPEED_ETH2,
 121     ASPEED_ETH3,
 122     ASPEED_ETH4,
 123     ASPEED_MII1,
 124     ASPEED_MII2,
 125     ASPEED_MII3,
 126     ASPEED_MII4,
 127     ASPEED_SDRAM,
 128     ASPEED_XDMA,
 129 };
 130
 131 #endif /* ASPEED_SOC_H */