include/hw/arm/aspeed_soc.h

   1 /*
   2  * ASPEED SoC family
   3  *
   4  * Andrew Jeffery <andrew@aj.id.au>
   5  *
   6  * Copyright 2016 IBM Corp.
   7  *
   8  * This code is licensed under the GPL version 2 or later.  See
   9  * the COPYING file in the top-level directory.
  10  */
  11
  12 #ifndef ASPEED_SOC_H
  13 #define ASPEED_SOC_H
  14
  15 #include "hw/cpu/a15mpcore.h"
  16 #include "hw/arm/armv7m.h"
  17 #include "hw/intc/aspeed_vic.h"
  18 #include "hw/intc/aspeed_intc.h"
  19 #include "hw/misc/aspeed_scu.h"
  20 #include "hw/adc/aspeed_adc.h"
  21 #include "hw/misc/aspeed_sdmc.h"
  22 #include "hw/misc/aspeed_xdma.h"
  23 #include "hw/timer/aspeed_timer.h"
  24 #include "hw/rtc/aspeed_rtc.h"
  25 #include "hw/i2c/aspeed_i2c.h"
  26 #include "hw/misc/aspeed_i3c.h"
  27 #include "hw/ssi/aspeed_smc.h"
  28 #include "hw/misc/aspeed_hace.h"
  29 #include "hw/misc/aspeed_sbc.h"
  30 #include "hw/misc/aspeed_sli.h"
  31 #include "hw/watchdog/wdt_aspeed.h"
  32 #include "hw/net/ftgmac100.h"
  33 #include "target/arm/cpu.h"
  34 #include "hw/gpio/aspeed_gpio.h"
  35 #include "hw/sd/aspeed_sdhci.h"
  36 #include "hw/usb/hcd-ehci.h"
  37 #include "qom/object.h"
  38 #include "hw/misc/aspeed_lpc.h"
  39 #include "hw/misc/unimp.h"
  40 #include "hw/misc/aspeed_peci.h"
  41 #include "hw/fsi/aspeed_apb2opb.h"
  42 #include "hw/char/serial.h"
  43 #include "hw/intc/arm_gicv3.h"
  44
  45 #define ASPEED_SPIS_NUM  2
  46 #define ASPEED_EHCIS_NUM 2
  47 #define ASPEED_WDTS_NUM  8
  48 #define ASPEED_CPUS_NUM  4
  49 #define ASPEED_MACS_NUM  4
  50 #define ASPEED_UARTS_NUM 13
  51 #define ASPEED_JTAG_NUM  2
  52
  53 struct AspeedSoCState {
  54     DeviceState parent;
  55
  56     MemoryRegion *memory;
  57     MemoryRegion *dram_mr;
  58     MemoryRegion dram_container;
  59     MemoryRegion sram;
  60     MemoryRegion spi_boot_container;
  61     MemoryRegion spi_boot;
  62     AddressSpace dram_as;
  63     AspeedRtcState rtc;
  64     AspeedTimerCtrlState timerctrl;
  65     AspeedI2CState i2c;
  66     AspeedI3CState i3c;
  67     AspeedSCUState scu;
  68     AspeedSCUState scuio;
  69     AspeedHACEState hace;
  70     AspeedXDMAState xdma;
  71     AspeedADCState adc;
  72     AspeedSMCState fmc;
  73     AspeedSMCState spi[ASPEED_SPIS_NUM];
  74     EHCISysBusState ehci[ASPEED_EHCIS_NUM];
  75     AspeedSBCState sbc;
  76     AspeedSLIState sli;
  77     AspeedSLIState sliio;
  78     MemoryRegion secsram;
  79     UnimplementedDeviceState sbc_unimplemented;
  80     AspeedSDMCState sdmc;
  81     AspeedWDTState wdt[ASPEED_WDTS_NUM];
  82     FTGMAC100State ftgmac100[ASPEED_MACS_NUM];
  83     AspeedMiiState mii[ASPEED_MACS_NUM];
  84     AspeedGPIOState gpio;
  85     AspeedGPIOState gpio_1_8v;
  86     AspeedSDHCIState sdhci;
  87     AspeedSDHCIState emmc;
  88     AspeedLPCState lpc;
  89     AspeedPECIState peci;
  90     SerialMM uart[ASPEED_UARTS_NUM];
  91     Clock *sysclk;
  92     UnimplementedDeviceState iomem;
  93     UnimplementedDeviceState video;
  94     UnimplementedDeviceState emmc_boot_controller;
  95     UnimplementedDeviceState dpmcu;
  96     UnimplementedDeviceState pwm;
  97     UnimplementedDeviceState espi;
  98     UnimplementedDeviceState udc;
  99     UnimplementedDeviceState sgpiom;
 100     UnimplementedDeviceState jtag[ASPEED_JTAG_NUM];
 101     AspeedAPB2OPBState fsi[2];
 102 };
 103
 104 #define TYPE_ASPEED_SOC "aspeed-soc"
 105 OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
 106
 107 struct Aspeed2400SoCState {
 108     AspeedSoCState parent;
 109
 110     ARMCPU cpu[ASPEED_CPUS_NUM];
 111     AspeedVICState vic;
 112 };
 113
 114 #define TYPE_ASPEED2400_SOC "aspeed2400-soc"
 115 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2400SoCState, ASPEED2400_SOC)
 116
 117 struct Aspeed2600SoCState {
 118     AspeedSoCState parent;
 119
 120     A15MPPrivState a7mpcore;
 121     ARMCPU cpu[ASPEED_CPUS_NUM]; /* XXX belong to a7mpcore */
 122 };
 123
 124 #define TYPE_ASPEED2600_SOC "aspeed2600-soc"
 125 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC)
 126
 127 struct Aspeed27x0SoCState {
 128     AspeedSoCState parent;
 129
 130     ARMCPU cpu[ASPEED_CPUS_NUM];
 131     AspeedINTCState intc;
 132     GICv3State gic;
 133     MemoryRegion dram_empty;
 134 };
 135
 136 #define TYPE_ASPEED27X0_SOC "aspeed27x0-soc"
 137 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SoCState, ASPEED27X0_SOC)
 138
 139 struct Aspeed10x0SoCState {
 140     AspeedSoCState parent;
 141
 142     ARMv7MState armv7m;
 143 };
 144
 145 #define TYPE_ASPEED10X0_SOC "aspeed10x0-soc"
 146 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed10x0SoCState, ASPEED10X0_SOC)
 147
 148 struct AspeedSoCClass {
 149     DeviceClass parent_class;
 150
 151     const char *name;
 152     /** valid_cpu_types: NULL terminated array of a single CPU type. */
 153     const char * const *valid_cpu_types;
 154     uint32_t silicon_rev;
 155     uint64_t sram_size;
 156     uint64_t secsram_size;
 157     int spis_num;
 158     int ehcis_num;
 159     int wdts_num;
 160     int macs_num;
 161     int uarts_num;
 162     int uarts_base;
 163     const int *irqmap;
 164     const hwaddr *memmap;
 165     uint32_t num_cpus;
 166     qemu_irq (*get_irq)(AspeedSoCState *s, int dev);
 167     bool (*boot_from_emmc)(AspeedSoCState *s);
 168 };
 169
 170 const char *aspeed_soc_cpu_type(AspeedSoCClass *sc);
 171
 172 enum {
 173     ASPEED_DEV_SPI_BOOT,
 174     ASPEED_DEV_IOMEM,
 175     ASPEED_DEV_UART0,
 176     ASPEED_DEV_UART1,
 177     ASPEED_DEV_UART2,
 178     ASPEED_DEV_UART3,
 179     ASPEED_DEV_UART4,
 180     ASPEED_DEV_UART5,
 181     ASPEED_DEV_UART6,
 182     ASPEED_DEV_UART7,
 183     ASPEED_DEV_UART8,
 184     ASPEED_DEV_UART9,
 185     ASPEED_DEV_UART10,
 186     ASPEED_DEV_UART11,
 187     ASPEED_DEV_UART12,
 188     ASPEED_DEV_UART13,
 189     ASPEED_DEV_VUART,
 190     ASPEED_DEV_FMC,
 191     ASPEED_DEV_SPI0,
 192     ASPEED_DEV_SPI1,
 193     ASPEED_DEV_SPI2,
 194     ASPEED_DEV_EHCI1,
 195     ASPEED_DEV_EHCI2,
 196     ASPEED_DEV_VIC,
 197     ASPEED_DEV_INTC,
 198     ASPEED_DEV_SDMC,
 199     ASPEED_DEV_SCU,
 200     ASPEED_DEV_ADC,
 201     ASPEED_DEV_SBC,
 202     ASPEED_DEV_SECSRAM,
 203     ASPEED_DEV_EMMC_BC,
 204     ASPEED_DEV_VIDEO,
 205     ASPEED_DEV_SRAM,
 206     ASPEED_DEV_SDHCI,
 207     ASPEED_DEV_GPIO,
 208     ASPEED_DEV_GPIO_1_8V,
 209     ASPEED_DEV_RTC,
 210     ASPEED_DEV_TIMER1,
 211     ASPEED_DEV_TIMER2,
 212     ASPEED_DEV_TIMER3,
 213     ASPEED_DEV_TIMER4,
 214     ASPEED_DEV_TIMER5,
 215     ASPEED_DEV_TIMER6,
 216     ASPEED_DEV_TIMER7,
 217     ASPEED_DEV_TIMER8,
 218     ASPEED_DEV_WDT,
 219     ASPEED_DEV_PWM,
 220     ASPEED_DEV_LPC,
 221     ASPEED_DEV_IBT,
 222     ASPEED_DEV_I2C,
 223     ASPEED_DEV_PECI,
 224     ASPEED_DEV_ETH1,
 225     ASPEED_DEV_ETH2,
 226     ASPEED_DEV_ETH3,
 227     ASPEED_DEV_ETH4,
 228     ASPEED_DEV_MII1,
 229     ASPEED_DEV_MII2,
 230     ASPEED_DEV_MII3,
 231     ASPEED_DEV_MII4,
 232     ASPEED_DEV_SDRAM,
 233     ASPEED_DEV_XDMA,
 234     ASPEED_DEV_EMMC,
 235     ASPEED_DEV_KCS,
 236     ASPEED_DEV_HACE,
 237     ASPEED_DEV_DPMCU,
 238     ASPEED_DEV_DP,
 239     ASPEED_DEV_I3C,
 240     ASPEED_DEV_ESPI,
 241     ASPEED_DEV_UDC,
 242     ASPEED_DEV_SGPIOM,
 243     ASPEED_DEV_JTAG0,
 244     ASPEED_DEV_JTAG1,
 245     ASPEED_DEV_FSI1,
 246     ASPEED_DEV_FSI2,
 247     ASPEED_DEV_SCUIO,
 248     ASPEED_DEV_SLI,
 249     ASPEED_DEV_SLIIO,
 250     ASPEED_GIC_DIST,
 251     ASPEED_GIC_REDIST,
 252 };
 253
 254 qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev);
 255 bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp);
 256 void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr);
 257 bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp);
 258 void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr);
 259 void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
 260                                    const char *name, hwaddr addr,
 261                                    uint64_t size);
 262 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
 263                                unsigned int count, int unit0);
 264
 265 static inline int aspeed_uart_index(int uart_dev)
 266 {
 267     return uart_dev - ASPEED_DEV_UART0;
 268 }
 269
 270 static inline int aspeed_uart_first(AspeedSoCClass *sc)
 271 {
 272     return aspeed_uart_index(sc->uarts_base);
 273 }
 274
 275 static inline int aspeed_uart_last(AspeedSoCClass *sc)
 276 {
 277     return aspeed_uart_first(sc) + sc->uarts_num - 1;
 278 }
 279
 280 #endif /* ASPEED_SOC_H */