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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210330' into...
[qemu/ar7.git] / hw / block / m25p80.c
blob183d3f44c25946e63a79c53864c3bce924fb57f0
1 /*
2 * ST M25P80 emulator. Emulate all SPI flash devices based on the m25p80 command
3 * set. Known devices table current as of Jun/2012 and taken from linux.
4 * See drivers/mtd/devices/m25p80.c.
5 *
6 * Copyright (C) 2011 Edgar E. Iglesias <edgar.iglesias@gmail.com>
7 * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
8 * Copyright (C) 2012 PetaLogix
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 or
13 * (at your option) a later version of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 */
23
24 #include "qemu/osdep.h"
25 #include "qemu/units.h"
26 #include "sysemu/block-backend.h"
27 #include "hw/qdev-properties.h"
28 #include "hw/qdev-properties-system.h"
29 #include "hw/ssi/ssi.h"
30 #include "migration/vmstate.h"
31 #include "qemu/bitops.h"
32 #include "qemu/log.h"
33 #include "qemu/module.h"
34 #include "qemu/error-report.h"
35 #include "qapi/error.h"
36 #include "trace.h"
37 #include "qom/object.h"
38
39 /* Fields for FlashPartInfo->flags */
40
41 /* erase capabilities */
42 #define ER_4K 1
43 #define ER_32K 2
44 /* set to allow the page program command to write 0s back to 1. Useful for
45 * modelling EEPROM with SPI flash command set
46 */
47 #define EEPROM 0x100
48
49 /* 16 MiB max in 3 byte address mode */
50 #define MAX_3BYTES_SIZE 0x1000000
51
52 #define SPI_NOR_MAX_ID_LEN 6
53
54 typedef struct FlashPartInfo {
55 const char *part_name;
56 /*
57 * This array stores the ID bytes.
58 * The first three bytes are the JEDIC ID.
59 * JEDEC ID zero means "no ID" (mostly older chips).
60 */
61 uint8_t id[SPI_NOR_MAX_ID_LEN];
62 uint8_t id_len;
63 /* there is confusion between manufacturers as to what a sector is. In this
64 * device model, a "sector" is the size that is erased by the ERASE_SECTOR
65 * command (opcode 0xd8).
66 */
67 uint32_t sector_size;
68 uint32_t n_sectors;
69 uint32_t page_size;
70 uint16_t flags;
71 /*
72 * Big sized spi nor are often stacked devices, thus sometime
73 * replace chip erase with die erase.
74 * This field inform how many die is in the chip.
75 */
76 uint8_t die_cnt;
77 } FlashPartInfo;
78
79 /* adapted from linux */
80 /* Used when the "_ext_id" is two bytes at most */
81 #define INFO(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\
82 .part_name = _part_name,\
83 .id = {\
84 ((_jedec_id) >> 16) & 0xff,\
85 ((_jedec_id) >> 8) & 0xff,\
86 (_jedec_id) & 0xff,\
87 ((_ext_id) >> 8) & 0xff,\
88 (_ext_id) & 0xff,\
89 },\
90 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\
91 .sector_size = (_sector_size),\
92 .n_sectors = (_n_sectors),\
93 .page_size = 256,\
94 .flags = (_flags),\
95 .die_cnt = 0
96
97 #define INFO6(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\
98 .part_name = _part_name,\
99 .id = {\
100 ((_jedec_id) >> 16) & 0xff,\
101 ((_jedec_id) >> 8) & 0xff,\
102 (_jedec_id) & 0xff,\
103 ((_ext_id) >> 16) & 0xff,\
104 ((_ext_id) >> 8) & 0xff,\
105 (_ext_id) & 0xff,\
106 },\
107 .id_len = 6,\
108 .sector_size = (_sector_size),\
109 .n_sectors = (_n_sectors),\
110 .page_size = 256,\
111 .flags = (_flags),\
112 .die_cnt = 0
113
114 #define INFO_STACKED(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors,\
115 _flags, _die_cnt)\
116 .part_name = _part_name,\
117 .id = {\
118 ((_jedec_id) >> 16) & 0xff,\
119 ((_jedec_id) >> 8) & 0xff,\
120 (_jedec_id) & 0xff,\
121 ((_ext_id) >> 8) & 0xff,\
122 (_ext_id) & 0xff,\
123 },\
124 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\
125 .sector_size = (_sector_size),\
126 .n_sectors = (_n_sectors),\
127 .page_size = 256,\
128 .flags = (_flags),\
129 .die_cnt = _die_cnt
130
131 #define JEDEC_NUMONYX 0x20
132 #define JEDEC_WINBOND 0xEF
133 #define JEDEC_SPANSION 0x01
134
135 /* Numonyx (Micron) Configuration register macros */
136 #define VCFG_DUMMY 0x1
137 #define VCFG_WRAP_SEQUENTIAL 0x2
138 #define NVCFG_XIP_MODE_DISABLED (7 << 9)
139 #define NVCFG_XIP_MODE_MASK (7 << 9)
140 #define VCFG_XIP_MODE_DISABLED (1 << 3)
141 #define CFG_DUMMY_CLK_LEN 4
142 #define NVCFG_DUMMY_CLK_POS 12
143 #define VCFG_DUMMY_CLK_POS 4
144 #define EVCFG_OUT_DRIVER_STRENGTH_DEF 7
145 #define EVCFG_VPP_ACCELERATOR (1 << 3)
146 #define EVCFG_RESET_HOLD_ENABLED (1 << 4)
147 #define NVCFG_DUAL_IO_MASK (1 << 2)
148 #define EVCFG_DUAL_IO_DISABLED (1 << 6)
149 #define NVCFG_QUAD_IO_MASK (1 << 3)
150 #define EVCFG_QUAD_IO_DISABLED (1 << 7)
151 #define NVCFG_4BYTE_ADDR_MASK (1 << 0)
152 #define NVCFG_LOWER_SEGMENT_MASK (1 << 1)
153
154 /* Numonyx (Micron) Flag Status Register macros */
155 #define FSR_4BYTE_ADDR_MODE_ENABLED 0x1
156 #define FSR_FLASH_READY (1 << 7)
157
158 /* Spansion configuration registers macros. */
159 #define SPANSION_QUAD_CFG_POS 0
160 #define SPANSION_QUAD_CFG_LEN 1
161 #define SPANSION_DUMMY_CLK_POS 0
162 #define SPANSION_DUMMY_CLK_LEN 4
163 #define SPANSION_ADDR_LEN_POS 7
164 #define SPANSION_ADDR_LEN_LEN 1
165
166 /*
167 * Spansion read mode command length in bytes,
168 * the mode is currently not supported.
169 */
170
171 #define SPANSION_CONTINUOUS_READ_MODE_CMD_LEN 1
172 #define WINBOND_CONTINUOUS_READ_MODE_CMD_LEN 1
173
174 static const FlashPartInfo known_devices[] = {
175 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
176 { INFO("at25fs010", 0x1f6601, 0, 32 << 10, 4, ER_4K) },
177 { INFO("at25fs040", 0x1f6604, 0, 64 << 10, 8, ER_4K) },
178
179 { INFO("at25df041a", 0x1f4401, 0, 64 << 10, 8, ER_4K) },
180 { INFO("at25df321a", 0x1f4701, 0, 64 << 10, 64, ER_4K) },
181 { INFO("at25df641", 0x1f4800, 0, 64 << 10, 128, ER_4K) },
182
183 { INFO("at26f004", 0x1f0400, 0, 64 << 10, 8, ER_4K) },
184 { INFO("at26df081a", 0x1f4501, 0, 64 << 10, 16, ER_4K) },
185 { INFO("at26df161a", 0x1f4601, 0, 64 << 10, 32, ER_4K) },
186 { INFO("at26df321", 0x1f4700, 0, 64 << 10, 64, ER_4K) },
187
188 { INFO("at45db081d", 0x1f2500, 0, 64 << 10, 16, ER_4K) },
189
190 /* Atmel EEPROMS - it is assumed, that don't care bit in command
191 * is set to 0. Block protection is not supported.
192 */
193 { INFO("at25128a-nonjedec", 0x0, 0, 1, 131072, EEPROM) },
194 { INFO("at25256a-nonjedec", 0x0, 0, 1, 262144, EEPROM) },
195
196 /* EON -- en25xxx */
197 { INFO("en25f32", 0x1c3116, 0, 64 << 10, 64, ER_4K) },
198 { INFO("en25p32", 0x1c2016, 0, 64 << 10, 64, 0) },
199 { INFO("en25q32b", 0x1c3016, 0, 64 << 10, 64, 0) },
200 { INFO("en25p64", 0x1c2017, 0, 64 << 10, 128, 0) },
201 { INFO("en25q64", 0x1c3017, 0, 64 << 10, 128, ER_4K) },
202
203 /* GigaDevice */
204 { INFO("gd25q32", 0xc84016, 0, 64 << 10, 64, ER_4K) },
205 { INFO("gd25q64", 0xc84017, 0, 64 << 10, 128, ER_4K) },
206
207 /* Intel/Numonyx -- xxxs33b */
208 { INFO("160s33b", 0x898911, 0, 64 << 10, 32, 0) },
209 { INFO("320s33b", 0x898912, 0, 64 << 10, 64, 0) },
210 { INFO("640s33b", 0x898913, 0, 64 << 10, 128, 0) },
211 { INFO("n25q064", 0x20ba17, 0, 64 << 10, 128, 0) },
212
213 /* ISSI */
214 { INFO("is25lq040b", 0x9d4013, 0, 64 << 10, 8, ER_4K) },
215 { INFO("is25lp080d", 0x9d6014, 0, 64 << 10, 16, ER_4K) },
216 { INFO("is25lp016d", 0x9d6015, 0, 64 << 10, 32, ER_4K) },
217 { INFO("is25lp032", 0x9d6016, 0, 64 << 10, 64, ER_4K) },
218 { INFO("is25lp064", 0x9d6017, 0, 64 << 10, 128, ER_4K) },
219 { INFO("is25lp128", 0x9d6018, 0, 64 << 10, 256, ER_4K) },
220 { INFO("is25lp256", 0x9d6019, 0, 64 << 10, 512, ER_4K) },
221 { INFO("is25wp032", 0x9d7016, 0, 64 << 10, 64, ER_4K) },
222 { INFO("is25wp064", 0x9d7017, 0, 64 << 10, 128, ER_4K) },
223 { INFO("is25wp128", 0x9d7018, 0, 64 << 10, 256, ER_4K) },
224 { INFO("is25wp256", 0x9d7019, 0, 64 << 10, 512, ER_4K) },
225
226 /* Macronix */
227 { INFO("mx25l2005a", 0xc22012, 0, 64 << 10, 4, ER_4K) },
228 { INFO("mx25l4005a", 0xc22013, 0, 64 << 10, 8, ER_4K) },
229 { INFO("mx25l8005", 0xc22014, 0, 64 << 10, 16, 0) },
230 { INFO("mx25l1606e", 0xc22015, 0, 64 << 10, 32, ER_4K) },
231 { INFO("mx25l3205d", 0xc22016, 0, 64 << 10, 64, 0) },
232 { INFO("mx25l6405d", 0xc22017, 0, 64 << 10, 128, 0) },
233 { INFO("mx25l12805d", 0xc22018, 0, 64 << 10, 256, 0) },
234 { INFO("mx25l12855e", 0xc22618, 0, 64 << 10, 256, 0) },
235 { INFO6("mx25l25635e", 0xc22019, 0xc22019, 64 << 10, 512, 0) },
236 { INFO("mx25l25655e", 0xc22619, 0, 64 << 10, 512, 0) },
237 { INFO("mx66l51235f", 0xc2201a, 0, 64 << 10, 1024, ER_4K | ER_32K) },
238 { INFO("mx66u51235f", 0xc2253a, 0, 64 << 10, 1024, ER_4K | ER_32K) },
239 { INFO("mx66u1g45g", 0xc2253b, 0, 64 << 10, 2048, ER_4K | ER_32K) },
240 { INFO("mx66l1g45g", 0xc2201b, 0, 64 << 10, 2048, ER_4K | ER_32K) },
241
242 /* Micron */
243 { INFO("n25q032a11", 0x20bb16, 0, 64 << 10, 64, ER_4K) },
244 { INFO("n25q032a13", 0x20ba16, 0, 64 << 10, 64, ER_4K) },
245 { INFO("n25q064a11", 0x20bb17, 0, 64 << 10, 128, ER_4K) },
246 { INFO("n25q064a13", 0x20ba17, 0, 64 << 10, 128, ER_4K) },
247 { INFO("n25q128a11", 0x20bb18, 0, 64 << 10, 256, ER_4K) },
248 { INFO("n25q128a13", 0x20ba18, 0, 64 << 10, 256, ER_4K) },
249 { INFO("n25q256a11", 0x20bb19, 0, 64 << 10, 512, ER_4K) },
250 { INFO("n25q256a13", 0x20ba19, 0, 64 << 10, 512, ER_4K) },
251 { INFO("n25q512a11", 0x20bb20, 0, 64 << 10, 1024, ER_4K) },
252 { INFO("n25q512a13", 0x20ba20, 0, 64 << 10, 1024, ER_4K) },
253 { INFO("n25q128", 0x20ba18, 0, 64 << 10, 256, 0) },
254 { INFO("n25q256a", 0x20ba19, 0, 64 << 10, 512, ER_4K) },
255 { INFO("n25q512a", 0x20ba20, 0, 64 << 10, 1024, ER_4K) },
256 { INFO("n25q512ax3", 0x20ba20, 0x1000, 64 << 10, 1024, ER_4K) },
257 { INFO("mt25ql512ab", 0x20ba20, 0x1044, 64 << 10, 1024, ER_4K | ER_32K) },
258 { INFO_STACKED("n25q00", 0x20ba21, 0x1000, 64 << 10, 2048, ER_4K, 4) },
259 { INFO_STACKED("n25q00a", 0x20bb21, 0x1000, 64 << 10, 2048, ER_4K, 4) },
260 { INFO_STACKED("mt25ql01g", 0x20ba21, 0x1040, 64 << 10, 2048, ER_4K, 2) },
261 { INFO_STACKED("mt25qu01g", 0x20bb21, 0x1040, 64 << 10, 2048, ER_4K, 2) },
262
263 /* Spansion -- single (large) sector size only, at least
264 * for the chips listed here (without boot sectors).
265 */
266 { INFO("s25sl032p", 0x010215, 0x4d00, 64 << 10, 64, ER_4K) },
267 { INFO("s25sl064p", 0x010216, 0x4d00, 64 << 10, 128, ER_4K) },
268 { INFO("s25fl256s0", 0x010219, 0x4d00, 256 << 10, 128, 0) },
269 { INFO("s25fl256s1", 0x010219, 0x4d01, 64 << 10, 512, 0) },
270 { INFO6("s25fl512s", 0x010220, 0x4d0080, 256 << 10, 256, 0) },
271 { INFO6("s70fl01gs", 0x010221, 0x4d0080, 256 << 10, 512, 0) },
272 { INFO("s25sl12800", 0x012018, 0x0300, 256 << 10, 64, 0) },
273 { INFO("s25sl12801", 0x012018, 0x0301, 64 << 10, 256, 0) },
274 { INFO("s25fl129p0", 0x012018, 0x4d00, 256 << 10, 64, 0) },
275 { INFO("s25fl129p1", 0x012018, 0x4d01, 64 << 10, 256, 0) },
276 { INFO("s25sl004a", 0x010212, 0, 64 << 10, 8, 0) },
277 { INFO("s25sl008a", 0x010213, 0, 64 << 10, 16, 0) },
278 { INFO("s25sl016a", 0x010214, 0, 64 << 10, 32, 0) },
279 { INFO("s25sl032a", 0x010215, 0, 64 << 10, 64, 0) },
280 { INFO("s25sl064a", 0x010216, 0, 64 << 10, 128, 0) },
281 { INFO("s25fl016k", 0xef4015, 0, 64 << 10, 32, ER_4K | ER_32K) },
282 { INFO("s25fl064k", 0xef4017, 0, 64 << 10, 128, ER_4K | ER_32K) },
283
284 /* Spansion -- boot sectors support */
285 { INFO6("s25fs512s", 0x010220, 0x4d0081, 256 << 10, 256, 0) },
286 { INFO6("s70fs01gs", 0x010221, 0x4d0081, 256 << 10, 512, 0) },
287
288 /* SST -- large erase sizes are "overlays", "sectors" are 4<< 10 */
289 { INFO("sst25vf040b", 0xbf258d, 0, 64 << 10, 8, ER_4K) },
290 { INFO("sst25vf080b", 0xbf258e, 0, 64 << 10, 16, ER_4K) },
291 { INFO("sst25vf016b", 0xbf2541, 0, 64 << 10, 32, ER_4K) },
292 { INFO("sst25vf032b", 0xbf254a, 0, 64 << 10, 64, ER_4K) },
293 { INFO("sst25wf512", 0xbf2501, 0, 64 << 10, 1, ER_4K) },
294 { INFO("sst25wf010", 0xbf2502, 0, 64 << 10, 2, ER_4K) },
295 { INFO("sst25wf020", 0xbf2503, 0, 64 << 10, 4, ER_4K) },
296 { INFO("sst25wf040", 0xbf2504, 0, 64 << 10, 8, ER_4K) },
297 { INFO("sst25wf080", 0xbf2505, 0, 64 << 10, 16, ER_4K) },
298
299 /* ST Microelectronics -- newer production may have feature updates */
300 { INFO("m25p05", 0x202010, 0, 32 << 10, 2, 0) },
301 { INFO("m25p10", 0x202011, 0, 32 << 10, 4, 0) },
302 { INFO("m25p20", 0x202012, 0, 64 << 10, 4, 0) },
303 { INFO("m25p40", 0x202013, 0, 64 << 10, 8, 0) },
304 { INFO("m25p80", 0x202014, 0, 64 << 10, 16, 0) },
305 { INFO("m25p16", 0x202015, 0, 64 << 10, 32, 0) },
306 { INFO("m25p32", 0x202016, 0, 64 << 10, 64, 0) },
307 { INFO("m25p64", 0x202017, 0, 64 << 10, 128, 0) },
308 { INFO("m25p128", 0x202018, 0, 256 << 10, 64, 0) },
309 { INFO("n25q032", 0x20ba16, 0, 64 << 10, 64, 0) },
310
311 { INFO("m45pe10", 0x204011, 0, 64 << 10, 2, 0) },
312 { INFO("m45pe80", 0x204014, 0, 64 << 10, 16, 0) },
313 { INFO("m45pe16", 0x204015, 0, 64 << 10, 32, 0) },
314
315 { INFO("m25pe20", 0x208012, 0, 64 << 10, 4, 0) },
316 { INFO("m25pe80", 0x208014, 0, 64 << 10, 16, 0) },
317 { INFO("m25pe16", 0x208015, 0, 64 << 10, 32, ER_4K) },
318
319 { INFO("m25px32", 0x207116, 0, 64 << 10, 64, ER_4K) },
320 { INFO("m25px32-s0", 0x207316, 0, 64 << 10, 64, ER_4K) },
321 { INFO("m25px32-s1", 0x206316, 0, 64 << 10, 64, ER_4K) },
322 { INFO("m25px64", 0x207117, 0, 64 << 10, 128, 0) },
323
324 /* Winbond -- w25x "blocks" are 64k, "sectors" are 4KiB */
325 { INFO("w25x10", 0xef3011, 0, 64 << 10, 2, ER_4K) },
326 { INFO("w25x20", 0xef3012, 0, 64 << 10, 4, ER_4K) },
327 { INFO("w25x40", 0xef3013, 0, 64 << 10, 8, ER_4K) },
328 { INFO("w25x80", 0xef3014, 0, 64 << 10, 16, ER_4K) },
329 { INFO("w25x16", 0xef3015, 0, 64 << 10, 32, ER_4K) },
330 { INFO("w25x32", 0xef3016, 0, 64 << 10, 64, ER_4K) },
331 { INFO("w25q32", 0xef4016, 0, 64 << 10, 64, ER_4K) },
332 { INFO("w25q32dw", 0xef6016, 0, 64 << 10, 64, ER_4K) },
333 { INFO("w25x64", 0xef3017, 0, 64 << 10, 128, ER_4K) },
334 { INFO("w25q64", 0xef4017, 0, 64 << 10, 128, ER_4K) },
335 { INFO("w25q80", 0xef5014, 0, 64 << 10, 16, ER_4K) },
336 { INFO("w25q80bl", 0xef4014, 0, 64 << 10, 16, ER_4K) },
337 { INFO("w25q256", 0xef4019, 0, 64 << 10, 512, ER_4K) },
338 { INFO("w25q512jv", 0xef4020, 0, 64 << 10, 1024, ER_4K) },
339 };
340
341 typedef enum {
342 NOP = 0,
343 WRSR = 0x1,
344 WRDI = 0x4,
345 RDSR = 0x5,
346 WREN = 0x6,
347 BRRD = 0x16,
348 BRWR = 0x17,
349 JEDEC_READ = 0x9f,
350 BULK_ERASE_60 = 0x60,
351 BULK_ERASE = 0xc7,
352 READ_FSR = 0x70,
353 RDCR = 0x15,
354
355 READ = 0x03,
356 READ4 = 0x13,
357 FAST_READ = 0x0b,
358 FAST_READ4 = 0x0c,
359 DOR = 0x3b,
360 DOR4 = 0x3c,
361 QOR = 0x6b,
362 QOR4 = 0x6c,
363 DIOR = 0xbb,
364 DIOR4 = 0xbc,
365 QIOR = 0xeb,
366 QIOR4 = 0xec,
367
368 PP = 0x02,
369 PP4 = 0x12,
370 PP4_4 = 0x3e,
371 DPP = 0xa2,
372 QPP = 0x32,
373 QPP_4 = 0x34,
374 RDID_90 = 0x90,
375 RDID_AB = 0xab,
376 AAI_WP = 0xad,
377
378 ERASE_4K = 0x20,
379 ERASE4_4K = 0x21,
380 ERASE_32K = 0x52,
381 ERASE4_32K = 0x5c,
382 ERASE_SECTOR = 0xd8,
383 ERASE4_SECTOR = 0xdc,
384
385 EN_4BYTE_ADDR = 0xB7,
386 EX_4BYTE_ADDR = 0xE9,
387
388 EXTEND_ADDR_READ = 0xC8,
389 EXTEND_ADDR_WRITE = 0xC5,
390
391 RESET_ENABLE = 0x66,
392 RESET_MEMORY = 0x99,
393
394 /*
395 * Micron: 0x35 - enable QPI
396 * Spansion: 0x35 - read control register
397 */
398 RDCR_EQIO = 0x35,
399 RSTQIO = 0xf5,
400
401 RNVCR = 0xB5,
402 WNVCR = 0xB1,
403
404 RVCR = 0x85,
405 WVCR = 0x81,
406
407 REVCR = 0x65,
408 WEVCR = 0x61,
409
410 DIE_ERASE = 0xC4,
411 } FlashCMD;
412
413 typedef enum {
414 STATE_IDLE,
415 STATE_PAGE_PROGRAM,
416 STATE_READ,
417 STATE_COLLECTING_DATA,
418 STATE_COLLECTING_VAR_LEN_DATA,
419 STATE_READING_DATA,
420 } CMDState;
421
422 typedef enum {
423 MAN_SPANSION,
424 MAN_MACRONIX,
425 MAN_NUMONYX,
426 MAN_WINBOND,
427 MAN_SST,
428 MAN_ISSI,
429 MAN_GENERIC,
430 } Manufacturer;
431
432 typedef enum {
433 MODE_STD = 0,
434 MODE_DIO = 1,
435 MODE_QIO = 2
436 } SPIMode;
437
438 #define M25P80_INTERNAL_DATA_BUFFER_SZ 16
439
440 struct Flash {
441 SSIPeripheral parent_obj;
442
443 BlockBackend *blk;
444
445 uint8_t *storage;
446 uint32_t size;
447 int page_size;
448
449 uint8_t state;
450 uint8_t data[M25P80_INTERNAL_DATA_BUFFER_SZ];
451 uint32_t len;
452 uint32_t pos;
453 bool data_read_loop;
454 uint8_t needed_bytes;
455 uint8_t cmd_in_progress;
456 uint32_t cur_addr;
457 uint32_t nonvolatile_cfg;
458 /* Configuration register for Macronix */
459 uint32_t volatile_cfg;
460 uint32_t enh_volatile_cfg;
461 /* Spansion cfg registers. */
462 uint8_t spansion_cr1nv;
463 uint8_t spansion_cr2nv;
464 uint8_t spansion_cr3nv;
465 uint8_t spansion_cr4nv;
466 uint8_t spansion_cr1v;
467 uint8_t spansion_cr2v;
468 uint8_t spansion_cr3v;
469 uint8_t spansion_cr4v;
470 bool write_enable;
471 bool four_bytes_address_mode;
472 bool reset_enable;
473 bool quad_enable;
474 bool aai_enable;
475 uint8_t ear;
476
477 int64_t dirty_page;
478
479 const FlashPartInfo *pi;
480
481 };
482
483 struct M25P80Class {
484 SSIPeripheralClass parent_class;
485 FlashPartInfo *pi;
486 };
487
488 #define TYPE_M25P80 "m25p80-generic"
489 OBJECT_DECLARE_TYPE(Flash, M25P80Class, M25P80)
490
491 static inline Manufacturer get_man(Flash *s)
492 {
493 switch (s->pi->id[0]) {
494 case 0x20:
495 return MAN_NUMONYX;
496 case 0xEF:
497 return MAN_WINBOND;
498 case 0x01:
499 return MAN_SPANSION;
500 case 0xC2:
501 return MAN_MACRONIX;
502 case 0xBF:
503 return MAN_SST;
504 case 0x9D:
505 return MAN_ISSI;
506 default:
507 return MAN_GENERIC;
508 }
509 }
510
511 static void blk_sync_complete(void *opaque, int ret)
512 {
513 QEMUIOVector *iov = opaque;
514
515 qemu_iovec_destroy(iov);
516 g_free(iov);
517
518 /* do nothing. Masters do not directly interact with the backing store,
519 * only the working copy so no mutexing required.
520 */
521 }
522
523 static void flash_sync_page(Flash *s, int page)
524 {
525 QEMUIOVector *iov;
526
527 if (!s->blk || !blk_is_writable(s->blk)) {
528 return;
529 }
530
531 iov = g_new(QEMUIOVector, 1);
532 qemu_iovec_init(iov, 1);
533 qemu_iovec_add(iov, s->storage + page * s->pi->page_size,
534 s->pi->page_size);
535 blk_aio_pwritev(s->blk, page * s->pi->page_size, iov, 0,
536 blk_sync_complete, iov);
537 }
538
539 static inline void flash_sync_area(Flash *s, int64_t off, int64_t len)
540 {
541 QEMUIOVector *iov;
542
543 if (!s->blk || !blk_is_writable(s->blk)) {
544 return;
545 }
546
547 assert(!(len % BDRV_SECTOR_SIZE));
548 iov = g_new(QEMUIOVector, 1);
549 qemu_iovec_init(iov, 1);
550 qemu_iovec_add(iov, s->storage + off, len);
551 blk_aio_pwritev(s->blk, off, iov, 0, blk_sync_complete, iov);
552 }
553
554 static void flash_erase(Flash *s, int offset, FlashCMD cmd)
555 {
556 uint32_t len;
557 uint8_t capa_to_assert = 0;
558
559 switch (cmd) {
560 case ERASE_4K:
561 case ERASE4_4K:
562 len = 4 * KiB;
563 capa_to_assert = ER_4K;
564 break;
565 case ERASE_32K:
566 case ERASE4_32K:
567 len = 32 * KiB;
568 capa_to_assert = ER_32K;
569 break;
570 case ERASE_SECTOR:
571 case ERASE4_SECTOR:
572 len = s->pi->sector_size;
573 break;
574 case BULK_ERASE:
575 len = s->size;
576 break;
577 case DIE_ERASE:
578 if (s->pi->die_cnt) {
579 len = s->size / s->pi->die_cnt;
580 offset = offset & (~(len - 1));
581 } else {
582 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: die erase is not supported"
583 " by device\n");
584 return;
585 }
586 break;
587 default:
588 abort();
589 }
590
591 trace_m25p80_flash_erase(s, offset, len);
592
593 if ((s->pi->flags & capa_to_assert) != capa_to_assert) {
594 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %d erase size not supported by"
595 " device\n", len);
596 }
597
598 if (!s->write_enable) {
599 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: erase with write protect!\n");
600 return;
601 }
602 memset(s->storage + offset, 0xff, len);
603 flash_sync_area(s, offset, len);
604 }
605
606 static inline void flash_sync_dirty(Flash *s, int64_t newpage)
607 {
608 if (s->dirty_page >= 0 && s->dirty_page != newpage) {
609 flash_sync_page(s, s->dirty_page);
610 s->dirty_page = newpage;
611 }
612 }
613
614 static inline
615 void flash_write8(Flash *s, uint32_t addr, uint8_t data)
616 {
617 uint32_t page = addr / s->pi->page_size;
618 uint8_t prev = s->storage[s->cur_addr];
619
620 if (!s->write_enable) {
621 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write protect!\n");
622 return;
623 }
624
625 if ((prev ^ data) & data) {
626 trace_m25p80_programming_zero_to_one(s, addr, prev, data);
627 }
628
629 if (s->pi->flags & EEPROM) {
630 s->storage[s->cur_addr] = data;
631 } else {
632 s->storage[s->cur_addr] &= data;
633 }
634
635 flash_sync_dirty(s, page);
636 s->dirty_page = page;
637 }
638
639 static inline int get_addr_length(Flash *s)
640 {
641 /* check if eeprom is in use */
642 if (s->pi->flags == EEPROM) {
643 return 2;
644 }
645
646 switch (s->cmd_in_progress) {
647 case PP4:
648 case PP4_4:
649 case QPP_4:
650 case READ4:
651 case QIOR4:
652 case ERASE4_4K:
653 case ERASE4_32K:
654 case ERASE4_SECTOR:
655 case FAST_READ4:
656 case DOR4:
657 case QOR4:
658 case DIOR4:
659 return 4;
660 default:
661 return s->four_bytes_address_mode ? 4 : 3;
662 }
663 }
664
665 static void complete_collecting_data(Flash *s)
666 {
667 int i, n;
668
669 n = get_addr_length(s);
670 s->cur_addr = (n == 3 ? s->ear : 0);
671 for (i = 0; i < n; ++i) {
672 s->cur_addr <<= 8;
673 s->cur_addr |= s->data[i];
674 }
675
676 s->cur_addr &= s->size - 1;
677
678 s->state = STATE_IDLE;
679
680 trace_m25p80_complete_collecting(s, s->cmd_in_progress, n, s->ear,
681 s->cur_addr);
682
683 switch (s->cmd_in_progress) {
684 case DPP:
685 case QPP:
686 case QPP_4:
687 case PP:
688 case PP4:
689 case PP4_4:
690 s->state = STATE_PAGE_PROGRAM;
691 break;
692 case AAI_WP:
693 /* AAI programming starts from the even address */
694 s->cur_addr &= ~BIT(0);
695 s->state = STATE_PAGE_PROGRAM;
696 break;
697 case READ:
698 case READ4:
699 case FAST_READ:
700 case FAST_READ4:
701 case DOR:
702 case DOR4:
703 case QOR:
704 case QOR4:
705 case DIOR:
706 case DIOR4:
707 case QIOR:
708 case QIOR4:
709 s->state = STATE_READ;
710 break;
711 case ERASE_4K:
712 case ERASE4_4K:
713 case ERASE_32K:
714 case ERASE4_32K:
715 case ERASE_SECTOR:
716 case ERASE4_SECTOR:
717 case DIE_ERASE:
718 flash_erase(s, s->cur_addr, s->cmd_in_progress);
719 break;
720 case WRSR:
721 switch (get_man(s)) {
722 case MAN_SPANSION:
723 s->quad_enable = !!(s->data[1] & 0x02);
724 break;
725 case MAN_ISSI:
726 s->quad_enable = extract32(s->data[0], 6, 1);
727 break;
728 case MAN_MACRONIX:
729 s->quad_enable = extract32(s->data[0], 6, 1);
730 if (s->len > 1) {
731 s->volatile_cfg = s->data[1];
732 s->four_bytes_address_mode = extract32(s->data[1], 5, 1);
733 }
734 break;
735 default:
736 break;
737 }
738 if (s->write_enable) {
739 s->write_enable = false;
740 }
741 break;
742 case BRWR:
743 case EXTEND_ADDR_WRITE:
744 s->ear = s->data[0];
745 break;
746 case WNVCR:
747 s->nonvolatile_cfg = s->data[0] | (s->data[1] << 8);
748 break;
749 case WVCR:
750 s->volatile_cfg = s->data[0];
751 break;
752 case WEVCR:
753 s->enh_volatile_cfg = s->data[0];
754 break;
755 case RDID_90:
756 case RDID_AB:
757 if (get_man(s) == MAN_SST) {
758 if (s->cur_addr <= 1) {
759 if (s->cur_addr) {
760 s->data[0] = s->pi->id[2];
761 s->data[1] = s->pi->id[0];
762 } else {
763 s->data[0] = s->pi->id[0];
764 s->data[1] = s->pi->id[2];
765 }
766 s->pos = 0;
767 s->len = 2;
768 s->data_read_loop = true;
769 s->state = STATE_READING_DATA;
770 } else {
771 qemu_log_mask(LOG_GUEST_ERROR,
772 "M25P80: Invalid read id address\n");
773 }
774 } else {
775 qemu_log_mask(LOG_GUEST_ERROR,
776 "M25P80: Read id (command 0x90/0xAB) is not supported"
777 " by device\n");
778 }
779 break;
780 default:
781 break;
782 }
783 }
784
785 static void reset_memory(Flash *s)
786 {
787 s->cmd_in_progress = NOP;
788 s->cur_addr = 0;
789 s->ear = 0;
790 s->four_bytes_address_mode = false;
791 s->len = 0;
792 s->needed_bytes = 0;
793 s->pos = 0;
794 s->state = STATE_IDLE;
795 s->write_enable = false;
796 s->reset_enable = false;
797 s->quad_enable = false;
798 s->aai_enable = false;
799
800 switch (get_man(s)) {
801 case MAN_NUMONYX:
802 s->volatile_cfg = 0;
803 s->volatile_cfg |= VCFG_DUMMY;
804 s->volatile_cfg |= VCFG_WRAP_SEQUENTIAL;
805 if ((s->nonvolatile_cfg & NVCFG_XIP_MODE_MASK)
806 == NVCFG_XIP_MODE_DISABLED) {
807 s->volatile_cfg |= VCFG_XIP_MODE_DISABLED;
808 }
809 s->volatile_cfg |= deposit32(s->volatile_cfg,
810 VCFG_DUMMY_CLK_POS,
811 CFG_DUMMY_CLK_LEN,
812 extract32(s->nonvolatile_cfg,
813 NVCFG_DUMMY_CLK_POS,
814 CFG_DUMMY_CLK_LEN)
815 );
816
817 s->enh_volatile_cfg = 0;
818 s->enh_volatile_cfg |= EVCFG_OUT_DRIVER_STRENGTH_DEF;
819 s->enh_volatile_cfg |= EVCFG_VPP_ACCELERATOR;
820 s->enh_volatile_cfg |= EVCFG_RESET_HOLD_ENABLED;
821 if (s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK) {
822 s->enh_volatile_cfg |= EVCFG_DUAL_IO_DISABLED;
823 }
824 if (s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK) {
825 s->enh_volatile_cfg |= EVCFG_QUAD_IO_DISABLED;
826 }
827 if (!(s->nonvolatile_cfg & NVCFG_4BYTE_ADDR_MASK)) {
828 s->four_bytes_address_mode = true;
829 }
830 if (!(s->nonvolatile_cfg & NVCFG_LOWER_SEGMENT_MASK)) {
831 s->ear = s->size / MAX_3BYTES_SIZE - 1;
832 }
833 break;
834 case MAN_MACRONIX:
835 s->volatile_cfg = 0x7;
836 break;
837 case MAN_SPANSION:
838 s->spansion_cr1v = s->spansion_cr1nv;
839 s->spansion_cr2v = s->spansion_cr2nv;
840 s->spansion_cr3v = s->spansion_cr3nv;
841 s->spansion_cr4v = s->spansion_cr4nv;
842 s->quad_enable = extract32(s->spansion_cr1v,
843 SPANSION_QUAD_CFG_POS,
844 SPANSION_QUAD_CFG_LEN
845 );
846 s->four_bytes_address_mode = extract32(s->spansion_cr2v,
847 SPANSION_ADDR_LEN_POS,
848 SPANSION_ADDR_LEN_LEN
849 );
850 break;
851 default:
852 break;
853 }
854
855 trace_m25p80_reset_done(s);
856 }
857
858 static uint8_t numonyx_mode(Flash *s)
859 {
860 if (!(s->enh_volatile_cfg & EVCFG_QUAD_IO_DISABLED)) {
861 return MODE_QIO;
862 } else if (!(s->enh_volatile_cfg & EVCFG_DUAL_IO_DISABLED)) {
863 return MODE_DIO;
864 } else {
865 return MODE_STD;
866 }
867 }
868
869 static uint8_t numonyx_extract_cfg_num_dummies(Flash *s)
870 {
871 uint8_t num_dummies;
872 uint8_t mode;
873 assert(get_man(s) == MAN_NUMONYX);
874
875 mode = numonyx_mode(s);
876 num_dummies = extract32(s->volatile_cfg, 4, 4);
877
878 if (num_dummies == 0x0 || num_dummies == 0xf) {
879 switch (s->cmd_in_progress) {
880 case QIOR:
881 case QIOR4:
882 num_dummies = 10;
883 break;
884 default:
885 num_dummies = (mode == MODE_QIO) ? 10 : 8;
886 break;
887 }
888 }
889
890 return num_dummies;
891 }
892
893 static void decode_fast_read_cmd(Flash *s)
894 {
895 s->needed_bytes = get_addr_length(s);
896 switch (get_man(s)) {
897 /* Dummy cycles - modeled with bytes writes instead of bits */
898 case MAN_SST:
899 s->needed_bytes += 1;
900 break;
901 case MAN_WINBOND:
902 s->needed_bytes += 8;
903 break;
904 case MAN_NUMONYX:
905 s->needed_bytes += numonyx_extract_cfg_num_dummies(s);
906 break;
907 case MAN_MACRONIX:
908 if (extract32(s->volatile_cfg, 6, 2) == 1) {
909 s->needed_bytes += 6;
910 } else {
911 s->needed_bytes += 8;
912 }
913 break;
914 case MAN_SPANSION:
915 s->needed_bytes += extract32(s->spansion_cr2v,
916 SPANSION_DUMMY_CLK_POS,
917 SPANSION_DUMMY_CLK_LEN
918 );
919 break;
920 case MAN_ISSI:
921 /*
922 * The Fast Read instruction code is followed by address bytes and
923 * dummy cycles, transmitted via the SI line.
924 *
925 * The number of dummy cycles is configurable but this is currently
926 * unmodeled, hence the default value 8 is used.
927 *
928 * QPI (Quad Peripheral Interface) mode has different default value
929 * of dummy cycles, but this is unsupported at the time being.
930 */
931 s->needed_bytes += 1;
932 break;
933 default:
934 break;
935 }
936 s->pos = 0;
937 s->len = 0;
938 s->state = STATE_COLLECTING_DATA;
939 }
940
941 static void decode_dio_read_cmd(Flash *s)
942 {
943 s->needed_bytes = get_addr_length(s);
944 /* Dummy cycles modeled with bytes writes instead of bits */
945 switch (get_man(s)) {
946 case MAN_WINBOND:
947 s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN;
948 break;
949 case MAN_SPANSION:
950 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN;
951 s->needed_bytes += extract32(s->spansion_cr2v,
952 SPANSION_DUMMY_CLK_POS,
953 SPANSION_DUMMY_CLK_LEN
954 );
955 break;
956 case MAN_NUMONYX:
957 s->needed_bytes += numonyx_extract_cfg_num_dummies(s);
958 break;
959 case MAN_MACRONIX:
960 switch (extract32(s->volatile_cfg, 6, 2)) {
961 case 1:
962 s->needed_bytes += 6;
963 break;
964 case 2:
965 s->needed_bytes += 8;
966 break;
967 default:
968 s->needed_bytes += 4;
969 break;
970 }
971 break;
972 case MAN_ISSI:
973 /*
974 * The Fast Read Dual I/O instruction code is followed by address bytes
975 * and dummy cycles, transmitted via the IO1 and IO0 line.
976 *
977 * The number of dummy cycles is configurable but this is currently
978 * unmodeled, hence the default value 4 is used.
979 */
980 s->needed_bytes += 1;
981 break;
982 default:
983 break;
984 }
985 s->pos = 0;
986 s->len = 0;
987 s->state = STATE_COLLECTING_DATA;
988 }
989
990 static void decode_qio_read_cmd(Flash *s)
991 {
992 s->needed_bytes = get_addr_length(s);
993 /* Dummy cycles modeled with bytes writes instead of bits */
994 switch (get_man(s)) {
995 case MAN_WINBOND:
996 s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN;
997 s->needed_bytes += 4;
998 break;
999 case MAN_SPANSION:
1000 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN;
1001 s->needed_bytes += extract32(s->spansion_cr2v,
1002 SPANSION_DUMMY_CLK_POS,
1003 SPANSION_DUMMY_CLK_LEN
1004 );
1005 break;
1006 case MAN_NUMONYX:
1007 s->needed_bytes += numonyx_extract_cfg_num_dummies(s);
1008 break;
1009 case MAN_MACRONIX:
1010 switch (extract32(s->volatile_cfg, 6, 2)) {
1011 case 1:
1012 s->needed_bytes += 4;
1013 break;
1014 case 2:
1015 s->needed_bytes += 8;
1016 break;
1017 default:
1018 s->needed_bytes += 6;
1019 break;
1020 }
1021 break;
1022 case MAN_ISSI:
1023 /*
1024 * The Fast Read Quad I/O instruction code is followed by address bytes
1025 * and dummy cycles, transmitted via the IO3, IO2, IO1 and IO0 line.
1026 *
1027 * The number of dummy cycles is configurable but this is currently
1028 * unmodeled, hence the default value 6 is used.
1029 *
1030 * QPI (Quad Peripheral Interface) mode has different default value
1031 * of dummy cycles, but this is unsupported at the time being.
1032 */
1033 s->needed_bytes += 3;
1034 break;
1035 default:
1036 break;
1037 }
1038 s->pos = 0;
1039 s->len = 0;
1040 s->state = STATE_COLLECTING_DATA;
1041 }
1042
1043 static bool is_valid_aai_cmd(uint32_t cmd)
1044 {
1045 return cmd == AAI_WP || cmd == WRDI || cmd == RDSR;
1046 }
1047
1048 static void decode_new_cmd(Flash *s, uint32_t value)
1049 {
1050 int i;
1051
1052 s->cmd_in_progress = value;
1053 trace_m25p80_command_decoded(s, value);
1054
1055 if (value != RESET_MEMORY) {
1056 s->reset_enable = false;
1057 }
1058
1059 if (get_man(s) == MAN_SST && s->aai_enable && !is_valid_aai_cmd(value)) {
1060 qemu_log_mask(LOG_GUEST_ERROR,
1061 "M25P80: Invalid cmd within AAI programming sequence");
1062 }
1063
1064 switch (value) {
1065
1066 case ERASE_4K:
1067 case ERASE4_4K:
1068 case ERASE_32K:
1069 case ERASE4_32K:
1070 case ERASE_SECTOR:
1071 case ERASE4_SECTOR:
1072 case PP:
1073 case PP4:
1074 case DIE_ERASE:
1075 case RDID_90:
1076 case RDID_AB:
1077 s->needed_bytes = get_addr_length(s);
1078 s->pos = 0;
1079 s->len = 0;
1080 s->state = STATE_COLLECTING_DATA;
1081 break;
1082 case READ:
1083 case READ4:
1084 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) == MODE_STD) {
1085 s->needed_bytes = get_addr_length(s);
1086 s->pos = 0;
1087 s->len = 0;
1088 s->state = STATE_COLLECTING_DATA;
1089 } else {
1090 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
1091 "DIO or QIO mode\n", s->cmd_in_progress);
1092 }
1093 break;
1094 case DPP:
1095 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) {
1096 s->needed_bytes = get_addr_length(s);
1097 s->pos = 0;
1098 s->len = 0;
1099 s->state = STATE_COLLECTING_DATA;
1100 } else {
1101 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
1102 "QIO mode\n", s->cmd_in_progress);
1103 }
1104 break;
1105 case QPP:
1106 case QPP_4:
1107 case PP4_4:
1108 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) {
1109 s->needed_bytes = get_addr_length(s);
1110 s->pos = 0;
1111 s->len = 0;
1112 s->state = STATE_COLLECTING_DATA;
1113 } else {
1114 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
1115 "DIO mode\n", s->cmd_in_progress);
1116 }
1117 break;
1118
1119 case FAST_READ:
1120 case FAST_READ4:
1121 decode_fast_read_cmd(s);
1122 break;
1123 case DOR:
1124 case DOR4:
1125 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) {
1126 decode_fast_read_cmd(s);
1127 } else {
1128 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
1129 "QIO mode\n", s->cmd_in_progress);
1130 }
1131 break;
1132 case QOR:
1133 case QOR4:
1134 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) {
1135 decode_fast_read_cmd(s);
1136 } else {
1137 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
1138 "DIO mode\n", s->cmd_in_progress);
1139 }
1140 break;
1141
1142 case DIOR:
1143 case DIOR4:
1144 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) {
1145 decode_dio_read_cmd(s);
1146 } else {
1147 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
1148 "QIO mode\n", s->cmd_in_progress);
1149 }
1150 break;
1151
1152 case QIOR:
1153 case QIOR4:
1154 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) {
1155 decode_qio_read_cmd(s);
1156 } else {
1157 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
1158 "DIO mode\n", s->cmd_in_progress);
1159 }
1160 break;
1161
1162 case WRSR:
1163 if (s->write_enable) {
1164 switch (get_man(s)) {
1165 case MAN_SPANSION:
1166 s->needed_bytes = 2;
1167 s->state = STATE_COLLECTING_DATA;
1168 break;
1169 case MAN_MACRONIX:
1170 s->needed_bytes = 2;
1171 s->state = STATE_COLLECTING_VAR_LEN_DATA;
1172 break;
1173 default:
1174 s->needed_bytes = 1;
1175 s->state = STATE_COLLECTING_DATA;
1176 }
1177 s->pos = 0;
1178 }
1179 break;
1180
1181 case WRDI:
1182 s->write_enable = false;
1183 if (get_man(s) == MAN_SST) {
1184 s->aai_enable = false;
1185 }
1186 break;
1187 case WREN:
1188 s->write_enable = true;
1189 break;
1190
1191 case RDSR:
1192 s->data[0] = (!!s->write_enable) << 1;
1193 if (get_man(s) == MAN_MACRONIX || get_man(s) == MAN_ISSI) {
1194 s->data[0] |= (!!s->quad_enable) << 6;
1195 }
1196 if (get_man(s) == MAN_SST) {
1197 s->data[0] |= (!!s->aai_enable) << 6;
1198 }
1199
1200 s->pos = 0;
1201 s->len = 1;
1202 s->data_read_loop = true;
1203 s->state = STATE_READING_DATA;
1204 break;
1205
1206 case READ_FSR:
1207 s->data[0] = FSR_FLASH_READY;
1208 if (s->four_bytes_address_mode) {
1209 s->data[0] |= FSR_4BYTE_ADDR_MODE_ENABLED;
1210 }
1211 s->pos = 0;
1212 s->len = 1;
1213 s->data_read_loop = true;
1214 s->state = STATE_READING_DATA;
1215 break;
1216
1217 case JEDEC_READ:
1218 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) == MODE_STD) {
1219 trace_m25p80_populated_jedec(s);
1220 for (i = 0; i < s->pi->id_len; i++) {
1221 s->data[i] = s->pi->id[i];
1222 }
1223 for (; i < SPI_NOR_MAX_ID_LEN; i++) {
1224 s->data[i] = 0;
1225 }
1226
1227 s->len = SPI_NOR_MAX_ID_LEN;
1228 s->pos = 0;
1229 s->state = STATE_READING_DATA;
1230 } else {
1231 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute JEDEC read "
1232 "in DIO or QIO mode\n");
1233 }
1234 break;
1235
1236 case RDCR:
1237 s->data[0] = s->volatile_cfg & 0xFF;
1238 s->data[0] |= (!!s->four_bytes_address_mode) << 5;
1239 s->pos = 0;
1240 s->len = 1;
1241 s->state = STATE_READING_DATA;
1242 break;
1243
1244 case BULK_ERASE_60:
1245 case BULK_ERASE:
1246 if (s->write_enable) {
1247 trace_m25p80_chip_erase(s);
1248 flash_erase(s, 0, BULK_ERASE);
1249 } else {
1250 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: chip erase with write "
1251 "protect!\n");
1252 }
1253 break;
1254 case NOP:
1255 break;
1256 case EN_4BYTE_ADDR:
1257 s->four_bytes_address_mode = true;
1258 break;
1259 case EX_4BYTE_ADDR:
1260 s->four_bytes_address_mode = false;
1261 break;
1262 case BRRD:
1263 case EXTEND_ADDR_READ:
1264 s->data[0] = s->ear;
1265 s->pos = 0;
1266 s->len = 1;
1267 s->state = STATE_READING_DATA;
1268 break;
1269 case BRWR:
1270 case EXTEND_ADDR_WRITE:
1271 if (s->write_enable) {
1272 s->needed_bytes = 1;
1273 s->pos = 0;
1274 s->len = 0;
1275 s->state = STATE_COLLECTING_DATA;
1276 }
1277 break;
1278 case RNVCR:
1279 s->data[0] = s->nonvolatile_cfg & 0xFF;
1280 s->data[1] = (s->nonvolatile_cfg >> 8) & 0xFF;
1281 s->pos = 0;
1282 s->len = 2;
1283 s->state = STATE_READING_DATA;
1284 break;
1285 case WNVCR:
1286 if (s->write_enable && get_man(s) == MAN_NUMONYX) {
1287 s->needed_bytes = 2;
1288 s->pos = 0;
1289 s->len = 0;
1290 s->state = STATE_COLLECTING_DATA;
1291 }
1292 break;
1293 case RVCR:
1294 s->data[0] = s->volatile_cfg & 0xFF;
1295 s->pos = 0;
1296 s->len = 1;
1297 s->state = STATE_READING_DATA;
1298 break;
1299 case WVCR:
1300 if (s->write_enable) {
1301 s->needed_bytes = 1;
1302 s->pos = 0;
1303 s->len = 0;
1304 s->state = STATE_COLLECTING_DATA;
1305 }
1306 break;
1307 case REVCR:
1308 s->data[0] = s->enh_volatile_cfg & 0xFF;
1309 s->pos = 0;
1310 s->len = 1;
1311 s->state = STATE_READING_DATA;
1312 break;
1313 case WEVCR:
1314 if (s->write_enable) {
1315 s->needed_bytes = 1;
1316 s->pos = 0;
1317 s->len = 0;
1318 s->state = STATE_COLLECTING_DATA;
1319 }
1320 break;
1321 case RESET_ENABLE:
1322 s->reset_enable = true;
1323 break;
1324 case RESET_MEMORY:
1325 if (s->reset_enable) {
1326 reset_memory(s);
1327 }
1328 break;
1329 case RDCR_EQIO:
1330 switch (get_man(s)) {
1331 case MAN_SPANSION:
1332 s->data[0] = (!!s->quad_enable) << 1;
1333 s->pos = 0;
1334 s->len = 1;
1335 s->state = STATE_READING_DATA;
1336 break;
1337 case MAN_MACRONIX:
1338 s->quad_enable = true;
1339 break;
1340 default:
1341 break;
1342 }
1343 break;
1344 case RSTQIO:
1345 s->quad_enable = false;
1346 break;
1347 case AAI_WP:
1348 if (get_man(s) == MAN_SST) {
1349 if (s->write_enable) {
1350 if (s->aai_enable) {
1351 s->state = STATE_PAGE_PROGRAM;
1352 } else {
1353 s->aai_enable = true;
1354 s->needed_bytes = get_addr_length(s);
1355 s->state = STATE_COLLECTING_DATA;
1356 }
1357 } else {
1358 qemu_log_mask(LOG_GUEST_ERROR,
1359 "M25P80: AAI_WP with write protect\n");
1360 }
1361 } else {
1362 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value);
1363 }
1364 break;
1365 default:
1366 s->pos = 0;
1367 s->len = 1;
1368 s->state = STATE_READING_DATA;
1369 s->data_read_loop = true;
1370 s->data[0] = 0;
1371 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value);
1372 break;
1373 }
1374 }
1375
1376 static int m25p80_cs(SSIPeripheral *ss, bool select)
1377 {
1378 Flash *s = M25P80(ss);
1379
1380 if (select) {
1381 if (s->state == STATE_COLLECTING_VAR_LEN_DATA) {
1382 complete_collecting_data(s);
1383 }
1384 s->len = 0;
1385 s->pos = 0;
1386 s->state = STATE_IDLE;
1387 flash_sync_dirty(s, -1);
1388 s->data_read_loop = false;
1389 }
1390
1391 trace_m25p80_select(s, select ? "de" : "");
1392
1393 return 0;
1394 }
1395
1396 static uint32_t m25p80_transfer8(SSIPeripheral *ss, uint32_t tx)
1397 {
1398 Flash *s = M25P80(ss);
1399 uint32_t r = 0;
1400
1401 trace_m25p80_transfer(s, s->state, s->len, s->needed_bytes, s->pos,
1402 s->cur_addr, (uint8_t)tx);
1403
1404 switch (s->state) {
1405
1406 case STATE_PAGE_PROGRAM:
1407 trace_m25p80_page_program(s, s->cur_addr, (uint8_t)tx);
1408 flash_write8(s, s->cur_addr, (uint8_t)tx);
1409 s->cur_addr = (s->cur_addr + 1) & (s->size - 1);
1410
1411 if (get_man(s) == MAN_SST && s->aai_enable && s->cur_addr == 0) {
1412 /*
1413 * There is no wrap mode during AAI programming once the highest
1414 * unprotected memory address is reached. The Write-Enable-Latch
1415 * bit is automatically reset, and AAI programming mode aborts.
1416 */
1417 s->write_enable = false;
1418 s->aai_enable = false;
1419 }
1420
1421 break;
1422
1423 case STATE_READ:
1424 r = s->storage[s->cur_addr];
1425 trace_m25p80_read_byte(s, s->cur_addr, (uint8_t)r);
1426 s->cur_addr = (s->cur_addr + 1) & (s->size - 1);
1427 break;
1428
1429 case STATE_COLLECTING_DATA:
1430 case STATE_COLLECTING_VAR_LEN_DATA:
1431
1432 if (s->len >= M25P80_INTERNAL_DATA_BUFFER_SZ) {
1433 qemu_log_mask(LOG_GUEST_ERROR,
1434 "M25P80: Write overrun internal data buffer. "
1435 "SPI controller (QEMU emulator or guest driver) "
1436 "is misbehaving\n");
1437 s->len = s->pos = 0;
1438 s->state = STATE_IDLE;
1439 break;
1440 }
1441
1442 s->data[s->len] = (uint8_t)tx;
1443 s->len++;
1444
1445 if (s->len == s->needed_bytes) {
1446 complete_collecting_data(s);
1447 }
1448 break;
1449
1450 case STATE_READING_DATA:
1451
1452 if (s->pos >= M25P80_INTERNAL_DATA_BUFFER_SZ) {
1453 qemu_log_mask(LOG_GUEST_ERROR,
1454 "M25P80: Read overrun internal data buffer. "
1455 "SPI controller (QEMU emulator or guest driver) "
1456 "is misbehaving\n");
1457 s->len = s->pos = 0;
1458 s->state = STATE_IDLE;
1459 break;
1460 }
1461
1462 r = s->data[s->pos];
1463 trace_m25p80_read_data(s, s->pos, (uint8_t)r);
1464 s->pos++;
1465 if (s->pos == s->len) {
1466 s->pos = 0;
1467 if (!s->data_read_loop) {
1468 s->state = STATE_IDLE;
1469 }
1470 }
1471 break;
1472
1473 default:
1474 case STATE_IDLE:
1475 decode_new_cmd(s, (uint8_t)tx);
1476 break;
1477 }
1478
1479 return r;
1480 }
1481
1482 static void m25p80_realize(SSIPeripheral *ss, Error **errp)
1483 {
1484 Flash *s = M25P80(ss);
1485 M25P80Class *mc = M25P80_GET_CLASS(s);
1486 int ret;
1487
1488 s->pi = mc->pi;
1489
1490 s->size = s->pi->sector_size * s->pi->n_sectors;
1491 s->dirty_page = -1;
1492
1493 if (s->blk) {
1494 uint64_t perm = BLK_PERM_CONSISTENT_READ |
1495 (blk_supports_write_perm(s->blk) ? BLK_PERM_WRITE : 0);
1496 ret = blk_set_perm(s->blk, perm, BLK_PERM_ALL, errp);
1497 if (ret < 0) {
1498 return;
1499 }
1500
1501 trace_m25p80_binding(s);
1502 s->storage = blk_blockalign(s->blk, s->size);
1503
1504 if (blk_pread(s->blk, 0, s->storage, s->size) != s->size) {
1505 error_setg(errp, "failed to read the initial flash content");
1506 return;
1507 }
1508 } else {
1509 trace_m25p80_binding_no_bdrv(s);
1510 s->storage = blk_blockalign(NULL, s->size);
1511 memset(s->storage, 0xFF, s->size);
1512 }
1513 }
1514
1515 static void m25p80_reset(DeviceState *d)
1516 {
1517 Flash *s = M25P80(d);
1518
1519 reset_memory(s);
1520 }
1521
1522 static int m25p80_pre_save(void *opaque)
1523 {
1524 flash_sync_dirty((Flash *)opaque, -1);
1525
1526 return 0;
1527 }
1528
1529 static Property m25p80_properties[] = {
1530 /* This is default value for Micron flash */
1531 DEFINE_PROP_UINT32("nonvolatile-cfg", Flash, nonvolatile_cfg, 0x8FFF),
1532 DEFINE_PROP_UINT8("spansion-cr1nv", Flash, spansion_cr1nv, 0x0),
1533 DEFINE_PROP_UINT8("spansion-cr2nv", Flash, spansion_cr2nv, 0x8),
1534 DEFINE_PROP_UINT8("spansion-cr3nv", Flash, spansion_cr3nv, 0x2),
1535 DEFINE_PROP_UINT8("spansion-cr4nv", Flash, spansion_cr4nv, 0x10),
1536 DEFINE_PROP_DRIVE("drive", Flash, blk),
1537 DEFINE_PROP_END_OF_LIST(),
1538 };
1539
1540 static int m25p80_pre_load(void *opaque)
1541 {
1542 Flash *s = (Flash *)opaque;
1543
1544 s->data_read_loop = false;
1545 return 0;
1546 }
1547
1548 static bool m25p80_data_read_loop_needed(void *opaque)
1549 {
1550 Flash *s = (Flash *)opaque;
1551
1552 return s->data_read_loop;
1553 }
1554
1555 static const VMStateDescription vmstate_m25p80_data_read_loop = {
1556 .name = "m25p80/data_read_loop",
1557 .version_id = 1,
1558 .minimum_version_id = 1,
1559 .needed = m25p80_data_read_loop_needed,
1560 .fields = (VMStateField[]) {
1561 VMSTATE_BOOL(data_read_loop, Flash),
1562 VMSTATE_END_OF_LIST()
1563 }
1564 };
1565
1566 static bool m25p80_aai_enable_needed(void *opaque)
1567 {
1568 Flash *s = (Flash *)opaque;
1569
1570 return s->aai_enable;
1571 }
1572
1573 static const VMStateDescription vmstate_m25p80_aai_enable = {
1574 .name = "m25p80/aai_enable",
1575 .version_id = 1,
1576 .minimum_version_id = 1,
1577 .needed = m25p80_aai_enable_needed,
1578 .fields = (VMStateField[]) {
1579 VMSTATE_BOOL(aai_enable, Flash),
1580 VMSTATE_END_OF_LIST()
1581 }
1582 };
1583
1584 static const VMStateDescription vmstate_m25p80 = {
1585 .name = "m25p80",
1586 .version_id = 0,
1587 .minimum_version_id = 0,
1588 .pre_save = m25p80_pre_save,
1589 .pre_load = m25p80_pre_load,
1590 .fields = (VMStateField[]) {
1591 VMSTATE_UINT8(state, Flash),
1592 VMSTATE_UINT8_ARRAY(data, Flash, M25P80_INTERNAL_DATA_BUFFER_SZ),
1593 VMSTATE_UINT32(len, Flash),
1594 VMSTATE_UINT32(pos, Flash),
1595 VMSTATE_UINT8(needed_bytes, Flash),
1596 VMSTATE_UINT8(cmd_in_progress, Flash),
1597 VMSTATE_UINT32(cur_addr, Flash),
1598 VMSTATE_BOOL(write_enable, Flash),
1599 VMSTATE_BOOL(reset_enable, Flash),
1600 VMSTATE_UINT8(ear, Flash),
1601 VMSTATE_BOOL(four_bytes_address_mode, Flash),
1602 VMSTATE_UINT32(nonvolatile_cfg, Flash),
1603 VMSTATE_UINT32(volatile_cfg, Flash),
1604 VMSTATE_UINT32(enh_volatile_cfg, Flash),
1605 VMSTATE_BOOL(quad_enable, Flash),
1606 VMSTATE_UINT8(spansion_cr1nv, Flash),
1607 VMSTATE_UINT8(spansion_cr2nv, Flash),
1608 VMSTATE_UINT8(spansion_cr3nv, Flash),
1609 VMSTATE_UINT8(spansion_cr4nv, Flash),
1610 VMSTATE_END_OF_LIST()
1611 },
1612 .subsections = (const VMStateDescription * []) {
1613 &vmstate_m25p80_data_read_loop,
1614 &vmstate_m25p80_aai_enable,
1615 NULL
1616 }
1617 };
1618
1619 static void m25p80_class_init(ObjectClass *klass, void *data)
1620 {
1621 DeviceClass *dc = DEVICE_CLASS(klass);
1622 SSIPeripheralClass *k = SSI_PERIPHERAL_CLASS(klass);
1623 M25P80Class *mc = M25P80_CLASS(klass);
1624
1625 k->realize = m25p80_realize;
1626 k->transfer = m25p80_transfer8;
1627 k->set_cs = m25p80_cs;
1628 k->cs_polarity = SSI_CS_LOW;
1629 dc->vmsd = &vmstate_m25p80;
1630 device_class_set_props(dc, m25p80_properties);
1631 dc->reset = m25p80_reset;
1632 mc->pi = data;
1633 }
1634
1635 static const TypeInfo m25p80_info = {
1636 .name = TYPE_M25P80,
1637 .parent = TYPE_SSI_PERIPHERAL,
1638 .instance_size = sizeof(Flash),
1639 .class_size = sizeof(M25P80Class),
1640 .abstract = true,
1641 };
1642
1643 static void m25p80_register_types(void)
1644 {
1645 int i;
1646
1647 type_register_static(&m25p80_info);
1648 for (i = 0; i < ARRAY_SIZE(known_devices); ++i) {
1649 TypeInfo ti = {
1650 .name = known_devices[i].part_name,
1651 .parent = TYPE_M25P80,
1652 .class_init = m25p80_class_init,
1653 .class_data = (void *)&known_devices[i],
1654 };
1655 type_register(&ti);
1656 }
1657 }
1658
1659 type_init(m25p80_register_types)
AR7 emulation for QEMU