hw/ppc/spapr_caps.c

   1 /*
   2  * QEMU PowerPC pSeries Logical Partition capabilities handling
   3  *
   4  * Copyright (c) 2017 David Gibson, Red Hat Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qemu/error-report.h"
  27 #include "qapi/error.h"
  28 #include "qapi/visitor.h"
  29 #include "sysemu/hw_accel.h"
  30 #include "exec/ram_addr.h"
  31 #include "target/ppc/cpu.h"
  32 #include "target/ppc/mmu-hash64.h"
  33 #include "cpu-models.h"
  34 #include "kvm_ppc.h"
  35 #include "migration/vmstate.h"
  36 #include "sysemu/tcg.h"
  37
  38 #include "hw/ppc/spapr.h"
  39
  40 typedef struct SpaprCapPossible {
  41     int num;            /* size of vals array below */
  42     const char *help;   /* help text for vals */
  43     /*
  44      * Note:
  45      * - because of the way compatibility is determined vals MUST be ordered
  46      *   such that later options are a superset of all preceding options.
  47      * - the order of vals must be preserved, that is their index is important,
  48      *   however vals may be added to the end of the list so long as the above
  49      *   point is observed
  50      */
  51     const char *vals[];
  52 } SpaprCapPossible;
  53
  54 typedef struct SpaprCapabilityInfo {
  55     const char *name;
  56     const char *description;
  57     int index;
  58
  59     /* Getter and Setter Function Pointers */
  60     ObjectPropertyAccessor *get;
  61     ObjectPropertyAccessor *set;
  62     const char *type;
  63     /* Possible values if this is a custom string type */
  64     SpaprCapPossible *possible;
  65     /* Make sure the virtual hardware can support this capability */
  66     void (*apply)(SpaprMachineState *spapr, uint8_t val, Error **errp);
  67     void (*cpu_apply)(SpaprMachineState *spapr, PowerPCCPU *cpu,
  68                       uint8_t val, Error **errp);
  69     bool (*migrate_needed)(void *opaque);
  70 } SpaprCapabilityInfo;
  71
  72 static void spapr_cap_get_bool(Object *obj, Visitor *v, const char *name,
  73                                void *opaque, Error **errp)
  74 {
  75     SpaprCapabilityInfo *cap = opaque;
  76     SpaprMachineState *spapr = SPAPR_MACHINE(obj);
  77     bool value = spapr_get_cap(spapr, cap->index) == SPAPR_CAP_ON;
  78
  79     visit_type_bool(v, name, &value, errp);
  80 }
  81
  82 static void spapr_cap_set_bool(Object *obj, Visitor *v, const char *name,
  83                                void *opaque, Error **errp)
  84 {
  85     SpaprCapabilityInfo *cap = opaque;
  86     SpaprMachineState *spapr = SPAPR_MACHINE(obj);
  87     bool value;
  88
  89     if (!visit_type_bool(v, name, &value, errp)) {
  90         return;
  91     }
  92
  93     spapr->cmd_line_caps[cap->index] = true;
  94     spapr->eff.caps[cap->index] = value ? SPAPR_CAP_ON : SPAPR_CAP_OFF;
  95 }
  96
  97
  98 static void spapr_cap_get_string(Object *obj, Visitor *v, const char *name,
  99                                  void *opaque, Error **errp)
 100 {
 101     SpaprCapabilityInfo *cap = opaque;
 102     SpaprMachineState *spapr = SPAPR_MACHINE(obj);
 103     g_autofree char *val = NULL;
 104     uint8_t value = spapr_get_cap(spapr, cap->index);
 105
 106     if (value >= cap->possible->num) {
 107         error_setg(errp, "Invalid value (%d) for cap-%s", value, cap->name);
 108         return;
 109     }
 110
 111     val = g_strdup(cap->possible->vals[value]);
 112
 113     visit_type_str(v, name, &val, errp);
 114 }
 115
 116 static void spapr_cap_set_string(Object *obj, Visitor *v, const char *name,
 117                                  void *opaque, Error **errp)
 118 {
 119     SpaprCapabilityInfo *cap = opaque;
 120     SpaprMachineState *spapr = SPAPR_MACHINE(obj);
 121     uint8_t i;
 122     g_autofree char *val = NULL;
 123
 124     if (!visit_type_str(v, name, &val, errp)) {
 125         return;
 126     }
 127
 128     if (!strcmp(val, "?")) {
 129         error_setg(errp, "%s", cap->possible->help);
 130         return;
 131     }
 132     for (i = 0; i < cap->possible->num; i++) {
 133         if (!strcasecmp(val, cap->possible->vals[i])) {
 134             spapr->cmd_line_caps[cap->index] = true;
 135             spapr->eff.caps[cap->index] = i;
 136             return;
 137         }
 138     }
 139
 140     error_setg(errp, "Invalid capability mode \"%s\" for cap-%s", val,
 141                cap->name);
 142 }
 143
 144 static void spapr_cap_get_pagesize(Object *obj, Visitor *v, const char *name,
 145                                    void *opaque, Error **errp)
 146 {
 147     SpaprCapabilityInfo *cap = opaque;
 148     SpaprMachineState *spapr = SPAPR_MACHINE(obj);
 149     uint8_t val = spapr_get_cap(spapr, cap->index);
 150     uint64_t pagesize = (1ULL << val);
 151
 152     visit_type_size(v, name, &pagesize, errp);
 153 }
 154
 155 static void spapr_cap_set_pagesize(Object *obj, Visitor *v, const char *name,
 156                                    void *opaque, Error **errp)
 157 {
 158     SpaprCapabilityInfo *cap = opaque;
 159     SpaprMachineState *spapr = SPAPR_MACHINE(obj);
 160     uint64_t pagesize;
 161     uint8_t val;
 162
 163     if (!visit_type_size(v, name, &pagesize, errp)) {
 164         return;
 165     }
 166
 167     if (!is_power_of_2(pagesize)) {
 168         error_setg(errp, "cap-%s must be a power of 2", cap->name);
 169         return;
 170     }
 171
 172     val = ctz64(pagesize);
 173     spapr->cmd_line_caps[cap->index] = true;
 174     spapr->eff.caps[cap->index] = val;
 175 }
 176
 177 static void cap_htm_apply(SpaprMachineState *spapr, uint8_t val, Error **errp)
 178 {
 179     ERRP_GUARD();
 180     if (!val) {
 181         /* TODO: We don't support disabling htm yet */
 182         return;
 183     }
 184     if (tcg_enabled()) {
 185         error_setg(errp, "No Transactional Memory support in TCG");
 186         error_append_hint(errp, "Try appending -machine cap-htm=off\n");
 187     } else if (kvm_enabled() && !kvmppc_has_cap_htm()) {
 188         error_setg(errp,
 189                    "KVM implementation does not support Transactional Memory");
 190         error_append_hint(errp, "Try appending -machine cap-htm=off\n");
 191     }
 192 }
 193
 194 static void cap_vsx_apply(SpaprMachineState *spapr, uint8_t val, Error **errp)
 195 {
 196     ERRP_GUARD();
 197     PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
 198     CPUPPCState *env = &cpu->env;
 199
 200     if (!val) {
 201         /* TODO: We don't support disabling vsx yet */
 202         return;
 203     }
 204     /* Allowable CPUs in spapr_cpu_core.c should already have gotten
 205      * rid of anything that doesn't do VMX */
 206     g_assert(env->insns_flags & PPC_ALTIVEC);
 207     if (!(env->insns_flags2 & PPC2_VSX)) {
 208         error_setg(errp, "VSX support not available");
 209         error_append_hint(errp, "Try appending -machine cap-vsx=off\n");
 210     }
 211 }
 212
 213 static void cap_dfp_apply(SpaprMachineState *spapr, uint8_t val, Error **errp)
 214 {
 215     ERRP_GUARD();
 216     PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
 217     CPUPPCState *env = &cpu->env;
 218
 219     if (!val) {
 220         /* TODO: We don't support disabling dfp yet */
 221         return;
 222     }
 223     if (!(env->insns_flags2 & PPC2_DFP)) {
 224         error_setg(errp, "DFP support not available");
 225         error_append_hint(errp, "Try appending -machine cap-dfp=off\n");
 226     }
 227 }
 228
 229 SpaprCapPossible cap_cfpc_possible = {
 230     .num = 3,
 231     .vals = {"broken", "workaround", "fixed"},
 232     .help = "broken - no protection, workaround - workaround available,"
 233             " fixed - fixed in hardware",
 234 };
 235
 236 static void cap_safe_cache_apply(SpaprMachineState *spapr, uint8_t val,
 237                                  Error **errp)
 238 {
 239     ERRP_GUARD();
 240     uint8_t kvm_val =  kvmppc_get_cap_safe_cache();
 241
 242     if (tcg_enabled() && val) {
 243         /* TCG only supports broken, allow other values and print a warning */
 244         warn_report("TCG doesn't support requested feature, cap-cfpc=%s",
 245                     cap_cfpc_possible.vals[val]);
 246     } else if (kvm_enabled() && (val > kvm_val)) {
 247         error_setg(errp,
 248                    "Requested safe cache capability level not supported by KVM");
 249         error_append_hint(errp, "Try appending -machine cap-cfpc=%s\n",
 250                           cap_cfpc_possible.vals[kvm_val]);
 251     }
 252 }
 253
 254 SpaprCapPossible cap_sbbc_possible = {
 255     .num = 3,
 256     .vals = {"broken", "workaround", "fixed"},
 257     .help = "broken - no protection, workaround - workaround available,"
 258             " fixed - fixed in hardware",
 259 };
 260
 261 static void cap_safe_bounds_check_apply(SpaprMachineState *spapr, uint8_t val,
 262                                         Error **errp)
 263 {
 264     ERRP_GUARD();
 265     uint8_t kvm_val =  kvmppc_get_cap_safe_bounds_check();
 266
 267     if (tcg_enabled() && val) {
 268         /* TCG only supports broken, allow other values and print a warning */
 269         warn_report("TCG doesn't support requested feature, cap-sbbc=%s",
 270                     cap_sbbc_possible.vals[val]);
 271     } else if (kvm_enabled() && (val > kvm_val)) {
 272         error_setg(errp,
 273 "Requested safe bounds check capability level not supported by KVM");
 274         error_append_hint(errp, "Try appending -machine cap-sbbc=%s\n",
 275                           cap_sbbc_possible.vals[kvm_val]);
 276     }
 277 }
 278
 279 SpaprCapPossible cap_ibs_possible = {
 280     .num = 5,
 281     /* Note workaround only maintained for compatibility */
 282     .vals = {"broken", "workaround", "fixed-ibs", "fixed-ccd", "fixed-na"},
 283     .help = "broken - no protection, workaround - count cache flush"
 284             ", fixed-ibs - indirect branch serialisation,"
 285             " fixed-ccd - cache count disabled,"
 286             " fixed-na - fixed in hardware (no longer applicable)",
 287 };
 288
 289 static void cap_safe_indirect_branch_apply(SpaprMachineState *spapr,
 290                                            uint8_t val, Error **errp)
 291 {
 292     ERRP_GUARD();
 293     uint8_t kvm_val = kvmppc_get_cap_safe_indirect_branch();
 294
 295     if (tcg_enabled() && val) {
 296         /* TCG only supports broken, allow other values and print a warning */
 297         warn_report("TCG doesn't support requested feature, cap-ibs=%s",
 298                     cap_ibs_possible.vals[val]);
 299     } else if (kvm_enabled() && (val > kvm_val)) {
 300         error_setg(errp,
 301 "Requested safe indirect branch capability level not supported by KVM");
 302         error_append_hint(errp, "Try appending -machine cap-ibs=%s\n",
 303                           cap_ibs_possible.vals[kvm_val]);
 304     }
 305 }
 306
 307 #define VALUE_DESC_TRISTATE     " (broken, workaround, fixed)"
 308
 309 bool spapr_check_pagesize(SpaprMachineState *spapr, hwaddr pagesize,
 310                           Error **errp)
 311 {
 312     hwaddr maxpagesize = (1ULL << spapr->eff.caps[SPAPR_CAP_HPT_MAXPAGESIZE]);
 313
 314     if (!kvmppc_hpt_needs_host_contiguous_pages()) {
 315         return true;
 316     }
 317
 318     if (maxpagesize > pagesize) {
 319         error_setg(errp,
 320                    "Can't support %"HWADDR_PRIu" kiB guest pages with %"
 321                    HWADDR_PRIu" kiB host pages with this KVM implementation",
 322                    maxpagesize >> 10, pagesize >> 10);
 323         return false;
 324     }
 325
 326     return true;
 327 }
 328
 329 static void cap_hpt_maxpagesize_apply(SpaprMachineState *spapr,
 330                                       uint8_t val, Error **errp)
 331 {
 332     if (val < 12) {
 333         error_setg(errp, "Require at least 4kiB hpt-max-page-size");
 334         return;
 335     } else if (val < 16) {
 336         warn_report("Many guests require at least 64kiB hpt-max-page-size");
 337     }
 338
 339     spapr_check_pagesize(spapr, qemu_minrampagesize(), errp);
 340 }
 341
 342 static bool cap_hpt_maxpagesize_migrate_needed(void *opaque)
 343 {
 344     return !SPAPR_MACHINE_GET_CLASS(opaque)->pre_4_1_migration;
 345 }
 346
 347 static bool spapr_pagesize_cb(void *opaque, uint32_t seg_pshift,
 348                               uint32_t pshift)
 349 {
 350     unsigned maxshift = *((unsigned *)opaque);
 351
 352     assert(pshift >= seg_pshift);
 353
 354     /* Don't allow the guest to use pages bigger than the configured
 355      * maximum size */
 356     if (pshift > maxshift) {
 357         return false;
 358     }
 359
 360     /* For whatever reason, KVM doesn't allow multiple pagesizes
 361      * within a segment, *except* for the case of 16M pages in a 4k or
 362      * 64k segment.  Always exclude other cases, so that TCG and KVM
 363      * guests see a consistent environment */
 364     if ((pshift != seg_pshift) && (pshift != 24)) {
 365         return false;
 366     }
 367
 368     return true;
 369 }
 370
 371 static void ppc_hash64_filter_pagesizes(PowerPCCPU *cpu,
 372                                  bool (*cb)(void *, uint32_t, uint32_t),
 373                                  void *opaque)
 374 {
 375     PPCHash64Options *opts = cpu->hash64_opts;
 376     int i;
 377     int n = 0;
 378     bool ci_largepage = false;
 379
 380     assert(opts);
 381
 382     n = 0;
 383     for (i = 0; i < ARRAY_SIZE(opts->sps); i++) {
 384         PPCHash64SegmentPageSizes *sps = &opts->sps[i];
 385         int j;
 386         int m = 0;
 387
 388         assert(n <= i);
 389
 390         if (!sps->page_shift) {
 391             break;
 392         }
 393
 394         for (j = 0; j < ARRAY_SIZE(sps->enc); j++) {
 395             PPCHash64PageSize *ps = &sps->enc[j];
 396
 397             assert(m <= j);
 398             if (!ps->page_shift) {
 399                 break;
 400             }
 401
 402             if (cb(opaque, sps->page_shift, ps->page_shift)) {
 403                 if (ps->page_shift >= 16) {
 404                     ci_largepage = true;
 405                 }
 406                 sps->enc[m++] = *ps;
 407             }
 408         }
 409
 410         /* Clear rest of the row */
 411         for (j = m; j < ARRAY_SIZE(sps->enc); j++) {
 412             memset(&sps->enc[j], 0, sizeof(sps->enc[j]));
 413         }
 414
 415         if (m) {
 416             n++;
 417         }
 418     }
 419
 420     /* Clear the rest of the table */
 421     for (i = n; i < ARRAY_SIZE(opts->sps); i++) {
 422         memset(&opts->sps[i], 0, sizeof(opts->sps[i]));
 423     }
 424
 425     if (!ci_largepage) {
 426         opts->flags &= ~PPC_HASH64_CI_LARGEPAGE;
 427     }
 428 }
 429
 430 static void cap_hpt_maxpagesize_cpu_apply(SpaprMachineState *spapr,
 431                                           PowerPCCPU *cpu,
 432                                           uint8_t val, Error **errp)
 433 {
 434     unsigned maxshift = val;
 435
 436     ppc_hash64_filter_pagesizes(cpu, spapr_pagesize_cb, &maxshift);
 437 }
 438
 439 static void cap_nested_kvm_hv_apply(SpaprMachineState *spapr,
 440                                     uint8_t val, Error **errp)
 441 {
 442     ERRP_GUARD();
 443     PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
 444     CPUPPCState *env = &cpu->env;
 445
 446     if (!val) {
 447         /* capability disabled by default */
 448         return;
 449     }
 450
 451     if (!(env->insns_flags2 & PPC2_ISA300)) {
 452         error_setg(errp, "Nested-HV only supported on POWER9 and later");
 453         error_append_hint(errp, "Try appending -machine cap-nested-hv=off\n");
 454         return;
 455     }
 456
 457     if (kvm_enabled()) {
 458         if (!ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0,
 459                               spapr->max_compat_pvr)) {
 460             error_setg(errp, "Nested-HV only supported on POWER9 and later");
 461             error_append_hint(errp,
 462                               "Try appending -machine max-cpu-compat=power9\n");
 463             return;
 464         }
 465
 466         if (!kvmppc_has_cap_nested_kvm_hv()) {
 467             error_setg(errp,
 468                        "KVM implementation does not support Nested-HV");
 469             error_append_hint(errp,
 470                               "Try appending -machine cap-nested-hv=off\n");
 471         } else if (kvmppc_set_cap_nested_kvm_hv(val) < 0) {
 472                 error_setg(errp, "Error enabling cap-nested-hv with KVM");
 473                 error_append_hint(errp,
 474                                   "Try appending -machine cap-nested-hv=off\n");
 475         }
 476     } else if (tcg_enabled()) {
 477         MachineState *ms = MACHINE(spapr);
 478         unsigned int smp_threads = ms->smp.threads;
 479
 480         /*
 481          * Nested-HV vCPU env state to L2, so SMT-shared SPR updates, for
 482          * example, do not necessarily update the correct SPR value on sibling
 483          * threads that are in a different guest/host context.
 484          */
 485         if (smp_threads > 1) {
 486             error_setg(errp, "TCG does not support nested-HV with SMT");
 487             error_append_hint(errp, "Try appending -machine cap-nested-hv=off "
 488                                     "or use threads=1 with -smp\n");
 489         }
 490     }
 491 }
 492
 493 static void cap_large_decr_apply(SpaprMachineState *spapr,
 494                                  uint8_t val, Error **errp)
 495 {
 496     ERRP_GUARD();
 497     PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
 498     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
 499
 500     if (!val) {
 501         return; /* Disabled by default */
 502     }
 503
 504     if (tcg_enabled()) {
 505         if (!ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0,
 506                               spapr->max_compat_pvr)) {
 507             error_setg(errp, "Large decrementer only supported on POWER9");
 508             error_append_hint(errp, "Try -cpu POWER9\n");
 509             return;
 510         }
 511     } else if (kvm_enabled()) {
 512         int kvm_nr_bits = kvmppc_get_cap_large_decr();
 513
 514         if (!kvm_nr_bits) {
 515             error_setg(errp, "No large decrementer support");
 516             error_append_hint(errp,
 517                               "Try appending -machine cap-large-decr=off\n");
 518         } else if (pcc->lrg_decr_bits != kvm_nr_bits) {
 519             error_setg(errp,
 520                        "KVM large decrementer size (%d) differs to model (%d)",
 521                        kvm_nr_bits, pcc->lrg_decr_bits);
 522             error_append_hint(errp,
 523                               "Try appending -machine cap-large-decr=off\n");
 524         }
 525     }
 526 }
 527
 528 static void cap_large_decr_cpu_apply(SpaprMachineState *spapr,
 529                                      PowerPCCPU *cpu,
 530                                      uint8_t val, Error **errp)
 531 {
 532     ERRP_GUARD();
 533     CPUPPCState *env = &cpu->env;
 534     target_ulong lpcr = env->spr[SPR_LPCR];
 535
 536     if (kvm_enabled()) {
 537         if (kvmppc_enable_cap_large_decr(cpu, val)) {
 538             error_setg(errp, "No large decrementer support");
 539             error_append_hint(errp,
 540                               "Try appending -machine cap-large-decr=off\n");
 541         }
 542     }
 543
 544     if (val) {
 545         lpcr |= LPCR_LD;
 546     } else {
 547         lpcr &= ~LPCR_LD;
 548     }
 549     ppc_store_lpcr(cpu, lpcr);
 550 }
 551
 552 static void cap_ccf_assist_apply(SpaprMachineState *spapr, uint8_t val,
 553                                  Error **errp)
 554 {
 555     ERRP_GUARD();
 556     uint8_t kvm_val = kvmppc_get_cap_count_cache_flush_assist();
 557
 558     if (tcg_enabled() && val) {
 559         /* TCG doesn't implement anything here, but allow with a warning */
 560         warn_report("TCG doesn't support requested feature, cap-ccf-assist=on");
 561     } else if (kvm_enabled() && (val > kvm_val)) {
 562         uint8_t kvm_ibs = kvmppc_get_cap_safe_indirect_branch();
 563
 564         if (kvm_ibs == SPAPR_CAP_FIXED_CCD) {
 565             /*
 566              * If we don't have CCF assist on the host, the assist
 567              * instruction is a harmless no-op.  It won't correctly
 568              * implement the cache count flush *but* if we have
 569              * count-cache-disabled in the host, that flush is
 570              * unnecessary.  So, specifically allow this case.  This
 571              * allows us to have better performance on POWER9 DD2.3,
 572              * while still working on POWER9 DD2.2 and POWER8 host
 573              * cpus.
 574              */
 575             return;
 576         }
 577         error_setg(errp,
 578                    "Requested count cache flush assist capability level not supported by KVM");
 579         error_append_hint(errp, "Try appending -machine cap-ccf-assist=off\n");
 580     }
 581 }
 582
 583 static void cap_fwnmi_apply(SpaprMachineState *spapr, uint8_t val,
 584                                 Error **errp)
 585 {
 586     ERRP_GUARD();
 587     if (!val) {
 588         return; /* Disabled by default */
 589     }
 590
 591     if (kvm_enabled()) {
 592         if (!kvmppc_get_fwnmi()) {
 593             error_setg(errp,
 594 "Firmware Assisted Non-Maskable Interrupts(FWNMI) not supported by KVM.");
 595             error_append_hint(errp, "Try appending -machine cap-fwnmi=off\n");
 596         }
 597     }
 598 }
 599
 600 static void cap_rpt_invalidate_apply(SpaprMachineState *spapr,
 601                                      uint8_t val, Error **errp)
 602 {
 603     ERRP_GUARD();
 604
 605     if (!val) {
 606         /* capability disabled by default */
 607         return;
 608     }
 609
 610     if (tcg_enabled()) {
 611         error_setg(errp, "No H_RPT_INVALIDATE support in TCG");
 612         error_append_hint(errp,
 613                           "Try appending -machine cap-rpt-invalidate=off\n");
 614     } else if (kvm_enabled()) {
 615         if (!kvmppc_has_cap_mmu_radix()) {
 616             error_setg(errp, "H_RPT_INVALIDATE only supported on Radix");
 617             return;
 618         }
 619
 620         if (!kvmppc_has_cap_rpt_invalidate()) {
 621             error_setg(errp,
 622                        "KVM implementation does not support H_RPT_INVALIDATE");
 623             error_append_hint(errp,
 624                               "Try appending -machine cap-rpt-invalidate=off\n");
 625         } else {
 626             kvmppc_enable_h_rpt_invalidate();
 627         }
 628     }
 629 }
 630
 631 static void cap_ail_mode_3_apply(SpaprMachineState *spapr,
 632                                      uint8_t val, Error **errp)
 633 {
 634     ERRP_GUARD();
 635     PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
 636     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
 637
 638     if (!val) {
 639         return;
 640     }
 641
 642     if (tcg_enabled()) {
 643         /* AIL-3 is only supported on POWER8 and above CPUs. */
 644         if (!(pcc->insns_flags2 & PPC2_ISA207S)) {
 645             error_setg(errp, "TCG only supports cap-ail-mode-3 on POWER8 and later CPUs");
 646             error_append_hint(errp, "Try appending -machine cap-ail-mode-3=off\n");
 647             return;
 648         }
 649     } else if (kvm_enabled()) {
 650         if (!kvmppc_supports_ail_3()) {
 651             error_setg(errp, "KVM implementation does not support cap-ail-mode-3");
 652             error_append_hint(errp, "Try appending -machine cap-ail-mode-3=off\n");
 653             return;
 654         }
 655     }
 656 }
 657
 658 SpaprCapabilityInfo capability_table[SPAPR_CAP_NUM] = {
 659     [SPAPR_CAP_HTM] = {
 660         .name = "htm",
 661         .description = "Allow Hardware Transactional Memory (HTM)",
 662         .index = SPAPR_CAP_HTM,
 663         .get = spapr_cap_get_bool,
 664         .set = spapr_cap_set_bool,
 665         .type = "bool",
 666         .apply = cap_htm_apply,
 667     },
 668     [SPAPR_CAP_VSX] = {
 669         .name = "vsx",
 670         .description = "Allow Vector Scalar Extensions (VSX)",
 671         .index = SPAPR_CAP_VSX,
 672         .get = spapr_cap_get_bool,
 673         .set = spapr_cap_set_bool,
 674         .type = "bool",
 675         .apply = cap_vsx_apply,
 676     },
 677     [SPAPR_CAP_DFP] = {
 678         .name = "dfp",
 679         .description = "Allow Decimal Floating Point (DFP)",
 680         .index = SPAPR_CAP_DFP,
 681         .get = spapr_cap_get_bool,
 682         .set = spapr_cap_set_bool,
 683         .type = "bool",
 684         .apply = cap_dfp_apply,
 685     },
 686     [SPAPR_CAP_CFPC] = {
 687         .name = "cfpc",
 688         .description = "Cache Flush on Privilege Change" VALUE_DESC_TRISTATE,
 689         .index = SPAPR_CAP_CFPC,
 690         .get = spapr_cap_get_string,
 691         .set = spapr_cap_set_string,
 692         .type = "string",
 693         .possible = &cap_cfpc_possible,
 694         .apply = cap_safe_cache_apply,
 695     },
 696     [SPAPR_CAP_SBBC] = {
 697         .name = "sbbc",
 698         .description = "Speculation Barrier Bounds Checking" VALUE_DESC_TRISTATE,
 699         .index = SPAPR_CAP_SBBC,
 700         .get = spapr_cap_get_string,
 701         .set = spapr_cap_set_string,
 702         .type = "string",
 703         .possible = &cap_sbbc_possible,
 704         .apply = cap_safe_bounds_check_apply,
 705     },
 706     [SPAPR_CAP_IBS] = {
 707         .name = "ibs",
 708         .description =
 709             "Indirect Branch Speculation (broken, workaround, fixed-ibs,"
 710             "fixed-ccd, fixed-na)",
 711         .index = SPAPR_CAP_IBS,
 712         .get = spapr_cap_get_string,
 713         .set = spapr_cap_set_string,
 714         .type = "string",
 715         .possible = &cap_ibs_possible,
 716         .apply = cap_safe_indirect_branch_apply,
 717     },
 718     [SPAPR_CAP_HPT_MAXPAGESIZE] = {
 719         .name = "hpt-max-page-size",
 720         .description = "Maximum page size for Hash Page Table guests",
 721         .index = SPAPR_CAP_HPT_MAXPAGESIZE,
 722         .get = spapr_cap_get_pagesize,
 723         .set = spapr_cap_set_pagesize,
 724         .type = "int",
 725         .apply = cap_hpt_maxpagesize_apply,
 726         .cpu_apply = cap_hpt_maxpagesize_cpu_apply,
 727         .migrate_needed = cap_hpt_maxpagesize_migrate_needed,
 728     },
 729     [SPAPR_CAP_NESTED_KVM_HV] = {
 730         .name = "nested-hv",
 731         .description = "Allow Nested KVM-HV",
 732         .index = SPAPR_CAP_NESTED_KVM_HV,
 733         .get = spapr_cap_get_bool,
 734         .set = spapr_cap_set_bool,
 735         .type = "bool",
 736         .apply = cap_nested_kvm_hv_apply,
 737     },
 738     [SPAPR_CAP_LARGE_DECREMENTER] = {
 739         .name = "large-decr",
 740         .description = "Allow Large Decrementer",
 741         .index = SPAPR_CAP_LARGE_DECREMENTER,
 742         .get = spapr_cap_get_bool,
 743         .set = spapr_cap_set_bool,
 744         .type = "bool",
 745         .apply = cap_large_decr_apply,
 746         .cpu_apply = cap_large_decr_cpu_apply,
 747     },
 748     [SPAPR_CAP_CCF_ASSIST] = {
 749         .name = "ccf-assist",
 750         .description = "Count Cache Flush Assist via HW Instruction",
 751         .index = SPAPR_CAP_CCF_ASSIST,
 752         .get = spapr_cap_get_bool,
 753         .set = spapr_cap_set_bool,
 754         .type = "bool",
 755         .apply = cap_ccf_assist_apply,
 756     },
 757     [SPAPR_CAP_FWNMI] = {
 758         .name = "fwnmi",
 759         .description = "Implements PAPR FWNMI option",
 760         .index = SPAPR_CAP_FWNMI,
 761         .get = spapr_cap_get_bool,
 762         .set = spapr_cap_set_bool,
 763         .type = "bool",
 764         .apply = cap_fwnmi_apply,
 765     },
 766     [SPAPR_CAP_RPT_INVALIDATE] = {
 767         .name = "rpt-invalidate",
 768         .description = "Allow H_RPT_INVALIDATE",
 769         .index = SPAPR_CAP_RPT_INVALIDATE,
 770         .get = spapr_cap_get_bool,
 771         .set = spapr_cap_set_bool,
 772         .type = "bool",
 773         .apply = cap_rpt_invalidate_apply,
 774     },
 775     [SPAPR_CAP_AIL_MODE_3] = {
 776         .name = "ail-mode-3",
 777         .description = "Alternate Interrupt Location (AIL) mode 3 support",
 778         .index = SPAPR_CAP_AIL_MODE_3,
 779         .get = spapr_cap_get_bool,
 780         .set = spapr_cap_set_bool,
 781         .type = "bool",
 782         .apply = cap_ail_mode_3_apply,
 783     },
 784 };
 785
 786 static SpaprCapabilities default_caps_with_cpu(SpaprMachineState *spapr,
 787                                                const char *cputype)
 788 {
 789     SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
 790     SpaprCapabilities caps;
 791
 792     caps = smc->default_caps;
 793
 794     if (!ppc_type_check_compat(cputype, CPU_POWERPC_LOGICAL_3_00,
 795                                0, spapr->max_compat_pvr)) {
 796         caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF;
 797     }
 798
 799     if (!ppc_type_check_compat(cputype, CPU_POWERPC_LOGICAL_2_07,
 800                                0, spapr->max_compat_pvr)) {
 801         caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF;
 802         caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN;
 803         caps.caps[SPAPR_CAP_AIL_MODE_3] = SPAPR_CAP_OFF;
 804     }
 805
 806     if (!ppc_type_check_compat(cputype, CPU_POWERPC_LOGICAL_2_06_PLUS,
 807                                0, spapr->max_compat_pvr)) {
 808         caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN;
 809     }
 810
 811     if (!ppc_type_check_compat(cputype, CPU_POWERPC_LOGICAL_2_06,
 812                                0, spapr->max_compat_pvr)) {
 813         caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_OFF;
 814         caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_OFF;
 815         caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN;
 816     }
 817
 818     /* This is for pseries-2.12 and older */
 819     if (smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] == 0) {
 820         uint8_t mps;
 821
 822         if (kvmppc_hpt_needs_host_contiguous_pages()) {
 823             mps = ctz64(qemu_minrampagesize());
 824         } else {
 825             mps = 34; /* allow everything up to 16GiB, i.e. everything */
 826         }
 827
 828         caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = mps;
 829     }
 830
 831     return caps;
 832 }
 833
 834 int spapr_caps_pre_load(void *opaque)
 835 {
 836     SpaprMachineState *spapr = opaque;
 837
 838     /* Set to default so we can tell if this came in with the migration */
 839     spapr->mig = spapr->def;
 840     return 0;
 841 }
 842
 843 int spapr_caps_pre_save(void *opaque)
 844 {
 845     SpaprMachineState *spapr = opaque;
 846
 847     spapr->mig = spapr->eff;
 848     return 0;
 849 }
 850
 851 /* This has to be called from the top-level spapr post_load, not the
 852  * caps specific one.  Otherwise it wouldn't be called when the source
 853  * caps are all defaults, which could still conflict with overridden
 854  * caps on the destination */
 855 int spapr_caps_post_migration(SpaprMachineState *spapr)
 856 {
 857     int i;
 858     bool ok = true;
 859     SpaprCapabilities dstcaps = spapr->eff;
 860     SpaprCapabilities srccaps;
 861
 862     srccaps = default_caps_with_cpu(spapr, MACHINE(spapr)->cpu_type);
 863     for (i = 0; i < SPAPR_CAP_NUM; i++) {
 864         /* If not default value then assume came in with the migration */
 865         if (spapr->mig.caps[i] != spapr->def.caps[i]) {
 866             srccaps.caps[i] = spapr->mig.caps[i];
 867         }
 868     }
 869
 870     for (i = 0; i < SPAPR_CAP_NUM; i++) {
 871         SpaprCapabilityInfo *info = &capability_table[i];
 872
 873         if (srccaps.caps[i] > dstcaps.caps[i]) {
 874             error_report("cap-%s higher level (%d) in incoming stream than on destination (%d)",
 875                          info->name, srccaps.caps[i], dstcaps.caps[i]);
 876             ok = false;
 877         }
 878
 879         if (srccaps.caps[i] < dstcaps.caps[i]) {
 880             warn_report("cap-%s lower level (%d) in incoming stream than on destination (%d)",
 881                          info->name, srccaps.caps[i], dstcaps.caps[i]);
 882         }
 883     }
 884
 885     return ok ? 0 : -EINVAL;
 886 }
 887
 888 /* Used to generate the migration field and needed function for a spapr cap */
 889 #define SPAPR_CAP_MIG_STATE(sname, cap)                 \
 890 static bool spapr_cap_##sname##_needed(void *opaque)    \
 891 {                                                       \
 892     SpaprMachineState *spapr = opaque;                  \
 893     bool (*needed)(void *opaque) =                      \
 894         capability_table[cap].migrate_needed;           \
 895                                                         \
 896     return needed ? needed(opaque) : true &&            \
 897            spapr->cmd_line_caps[cap] &&                 \
 898            (spapr->eff.caps[cap] !=                     \
 899             spapr->def.caps[cap]);                      \
 900 }                                                       \
 901                                                         \
 902 const VMStateDescription vmstate_spapr_cap_##sname = {  \
 903     .name = "spapr/cap/" #sname,                        \
 904     .version_id = 1,                                    \
 905     .minimum_version_id = 1,                            \
 906     .needed = spapr_cap_##sname##_needed,               \
 907     .fields = (VMStateField[]) {                        \
 908         VMSTATE_UINT8(mig.caps[cap],                    \
 909                       SpaprMachineState),               \
 910         VMSTATE_END_OF_LIST()                           \
 911     },                                                  \
 912 }
 913
 914 SPAPR_CAP_MIG_STATE(htm, SPAPR_CAP_HTM);
 915 SPAPR_CAP_MIG_STATE(vsx, SPAPR_CAP_VSX);
 916 SPAPR_CAP_MIG_STATE(dfp, SPAPR_CAP_DFP);
 917 SPAPR_CAP_MIG_STATE(cfpc, SPAPR_CAP_CFPC);
 918 SPAPR_CAP_MIG_STATE(sbbc, SPAPR_CAP_SBBC);
 919 SPAPR_CAP_MIG_STATE(ibs, SPAPR_CAP_IBS);
 920 SPAPR_CAP_MIG_STATE(hpt_maxpagesize, SPAPR_CAP_HPT_MAXPAGESIZE);
 921 SPAPR_CAP_MIG_STATE(nested_kvm_hv, SPAPR_CAP_NESTED_KVM_HV);
 922 SPAPR_CAP_MIG_STATE(large_decr, SPAPR_CAP_LARGE_DECREMENTER);
 923 SPAPR_CAP_MIG_STATE(ccf_assist, SPAPR_CAP_CCF_ASSIST);
 924 SPAPR_CAP_MIG_STATE(fwnmi, SPAPR_CAP_FWNMI);
 925 SPAPR_CAP_MIG_STATE(rpt_invalidate, SPAPR_CAP_RPT_INVALIDATE);
 926
 927 void spapr_caps_init(SpaprMachineState *spapr)
 928 {
 929     SpaprCapabilities default_caps;
 930     int i;
 931
 932     /* Compute the actual set of caps we should run with */
 933     default_caps = default_caps_with_cpu(spapr, MACHINE(spapr)->cpu_type);
 934
 935     for (i = 0; i < SPAPR_CAP_NUM; i++) {
 936         /* Store the defaults */
 937         spapr->def.caps[i] = default_caps.caps[i];
 938         /* If not set on the command line then apply the default value */
 939         if (!spapr->cmd_line_caps[i]) {
 940             spapr->eff.caps[i] = default_caps.caps[i];
 941         }
 942     }
 943 }
 944
 945 void spapr_caps_apply(SpaprMachineState *spapr)
 946 {
 947     int i;
 948
 949     for (i = 0; i < SPAPR_CAP_NUM; i++) {
 950         SpaprCapabilityInfo *info = &capability_table[i];
 951
 952         /*
 953          * If the apply function can't set the desired level and thinks it's
 954          * fatal, it should cause that.
 955          */
 956         info->apply(spapr, spapr->eff.caps[i], &error_fatal);
 957     }
 958 }
 959
 960 void spapr_caps_cpu_apply(SpaprMachineState *spapr, PowerPCCPU *cpu)
 961 {
 962     int i;
 963
 964     for (i = 0; i < SPAPR_CAP_NUM; i++) {
 965         SpaprCapabilityInfo *info = &capability_table[i];
 966
 967         /*
 968          * If the apply function can't set the desired level and thinks it's
 969          * fatal, it should cause that.
 970          */
 971         if (info->cpu_apply) {
 972             info->cpu_apply(spapr, cpu, spapr->eff.caps[i], &error_fatal);
 973         }
 974     }
 975 }
 976
 977 void spapr_caps_add_properties(SpaprMachineClass *smc)
 978 {
 979     ObjectClass *klass = OBJECT_CLASS(smc);
 980     int i;
 981
 982     for (i = 0; i < ARRAY_SIZE(capability_table); i++) {
 983         SpaprCapabilityInfo *cap = &capability_table[i];
 984         g_autofree char *name = g_strdup_printf("cap-%s", cap->name);
 985         g_autofree char *desc = g_strdup_printf("%s", cap->description);
 986
 987         object_class_property_add(klass, name, cap->type,
 988                                   cap->get, cap->set,
 989                                   NULL, cap);
 990
 991         object_class_property_set_description(klass, name, desc);
 992     }
 993 }