s390x/tcg: Implement MULTIPLY SINGLE (MSC, MSGC, MSGRKC, MSRKC)
[qemu/ar7.git] / hw / arm / virt.c
blob1231a197c8504f0b9123fcd510d247ed247b21b6
1 /*
2 * ARM mach-virt emulation
4 * Copyright (c) 2013 Linaro Limited
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
18 * Emulate a virtual board which works by passing Linux all the information
19 * it needs about what devices are present via the device tree.
20 * There are some restrictions about what we can do here:
21 * + we can only present devices whose Linux drivers will work based
22 * purely on the device tree with no platform data at all
23 * + we want to present a very stripped-down minimalist platform,
24 * both because this reduces the security attack surface from the guest
25 * and also because it reduces our exposure to being broken when
26 * the kernel updates its device tree bindings and requires further
27 * information in a device binding that we aren't providing.
28 * This is essentially the same approach kvmtool uses.
31 #include "qemu/osdep.h"
32 #include "qemu-common.h"
33 #include "qemu/units.h"
34 #include "qemu/option.h"
35 #include "monitor/qdev.h"
36 #include "qapi/error.h"
37 #include "hw/sysbus.h"
38 #include "hw/boards.h"
39 #include "hw/arm/boot.h"
40 #include "hw/arm/primecell.h"
41 #include "hw/arm/virt.h"
42 #include "hw/block/flash.h"
43 #include "hw/vfio/vfio-calxeda-xgmac.h"
44 #include "hw/vfio/vfio-amd-xgbe.h"
45 #include "hw/display/ramfb.h"
46 #include "net/net.h"
47 #include "sysemu/device_tree.h"
48 #include "sysemu/numa.h"
49 #include "sysemu/runstate.h"
50 #include "sysemu/sysemu.h"
51 #include "sysemu/tpm.h"
52 #include "sysemu/kvm.h"
53 #include "hw/loader.h"
54 #include "exec/address-spaces.h"
55 #include "qemu/bitops.h"
56 #include "qemu/error-report.h"
57 #include "qemu/module.h"
58 #include "hw/pci-host/gpex.h"
59 #include "hw/virtio/virtio-pci.h"
60 #include "hw/arm/sysbus-fdt.h"
61 #include "hw/platform-bus.h"
62 #include "hw/qdev-properties.h"
63 #include "hw/arm/fdt.h"
64 #include "hw/intc/arm_gic.h"
65 #include "hw/intc/arm_gicv3_common.h"
66 #include "hw/irq.h"
67 #include "kvm_arm.h"
68 #include "hw/firmware/smbios.h"
69 #include "qapi/visitor.h"
70 #include "qapi/qapi-visit-common.h"
71 #include "standard-headers/linux/input.h"
72 #include "hw/arm/smmuv3.h"
73 #include "hw/acpi/acpi.h"
74 #include "target/arm/internals.h"
75 #include "hw/mem/pc-dimm.h"
76 #include "hw/mem/nvdimm.h"
77 #include "hw/acpi/generic_event_device.h"
78 #include "hw/virtio/virtio-iommu.h"
79 #include "hw/char/pl011.h"
80 #include "qemu/guest-random.h"
82 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
83 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
84 void *data) \
85 { \
86 MachineClass *mc = MACHINE_CLASS(oc); \
87 virt_machine_##major##_##minor##_options(mc); \
88 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \
89 if (latest) { \
90 mc->alias = "virt"; \
91 } \
92 } \
93 static const TypeInfo machvirt_##major##_##minor##_info = { \
94 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
95 .parent = TYPE_VIRT_MACHINE, \
96 .class_init = virt_##major##_##minor##_class_init, \
97 }; \
98 static void machvirt_machine_##major##_##minor##_init(void) \
99 { \
100 type_register_static(&machvirt_##major##_##minor##_info); \
102 type_init(machvirt_machine_##major##_##minor##_init);
104 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
105 DEFINE_VIRT_MACHINE_LATEST(major, minor, true)
106 #define DEFINE_VIRT_MACHINE(major, minor) \
107 DEFINE_VIRT_MACHINE_LATEST(major, minor, false)
110 /* Number of external interrupt lines to configure the GIC with */
111 #define NUM_IRQS 256
113 #define PLATFORM_BUS_NUM_IRQS 64
115 /* Legacy RAM limit in GB (< version 4.0) */
116 #define LEGACY_RAMLIMIT_GB 255
117 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB)
119 /* Addresses and sizes of our components.
120 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
121 * 128MB..256MB is used for miscellaneous device I/O.
122 * 256MB..1GB is reserved for possible future PCI support (ie where the
123 * PCI memory window will go if we add a PCI host controller).
124 * 1GB and up is RAM (which may happily spill over into the
125 * high memory region beyond 4GB).
126 * This represents a compromise between how much RAM can be given to
127 * a 32 bit VM and leaving space for expansion and in particular for PCI.
128 * Note that devices should generally be placed at multiples of 0x10000,
129 * to accommodate guests using 64K pages.
131 static const MemMapEntry base_memmap[] = {
132 /* Space up to 0x8000000 is reserved for a boot ROM */
133 [VIRT_FLASH] = { 0, 0x08000000 },
134 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 },
135 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
136 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 },
137 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 },
138 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 },
139 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 },
140 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 },
141 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
142 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 },
143 /* This redistributor space allows up to 2*64kB*123 CPUs */
144 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 },
145 [VIRT_UART] = { 0x09000000, 0x00001000 },
146 [VIRT_RTC] = { 0x09010000, 0x00001000 },
147 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 },
148 [VIRT_GPIO] = { 0x09030000, 0x00001000 },
149 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 },
150 [VIRT_SMMU] = { 0x09050000, 0x00020000 },
151 [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN },
152 [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN },
153 [VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN},
154 [VIRT_MMIO] = { 0x0a000000, 0x00000200 },
155 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
156 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 },
157 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 },
158 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 },
159 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 },
160 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 },
161 /* Actual RAM size depends on initial RAM and device memory settings */
162 [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES },
166 * Highmem IO Regions: This memory map is floating, located after the RAM.
167 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the
168 * top of the RAM, so that its base get the same alignment as the size,
169 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is
170 * less than 256GiB of RAM, the floating area starts at the 256GiB mark.
171 * Note the extended_memmap is sized so that it eventually also includes the
172 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
173 * index of base_memmap).
175 static MemMapEntry extended_memmap[] = {
176 /* Additional 64 MB redist region (can contain up to 512 redistributors) */
177 [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB },
178 [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB },
179 /* Second PCIe window */
180 [VIRT_HIGH_PCIE_MMIO] = { 0x0, 512 * GiB },
183 static const int a15irqmap[] = {
184 [VIRT_UART] = 1,
185 [VIRT_RTC] = 2,
186 [VIRT_PCIE] = 3, /* ... to 6 */
187 [VIRT_GPIO] = 7,
188 [VIRT_SECURE_UART] = 8,
189 [VIRT_ACPI_GED] = 9,
190 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
191 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
192 [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */
193 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
196 static const char *valid_cpus[] = {
197 ARM_CPU_TYPE_NAME("cortex-a7"),
198 ARM_CPU_TYPE_NAME("cortex-a15"),
199 ARM_CPU_TYPE_NAME("cortex-a53"),
200 ARM_CPU_TYPE_NAME("cortex-a57"),
201 ARM_CPU_TYPE_NAME("cortex-a72"),
202 ARM_CPU_TYPE_NAME("host"),
203 ARM_CPU_TYPE_NAME("max"),
206 static bool cpu_type_valid(const char *cpu)
208 int i;
210 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) {
211 if (strcmp(cpu, valid_cpus[i]) == 0) {
212 return true;
215 return false;
218 static void create_kaslr_seed(VirtMachineState *vms, const char *node)
220 uint64_t seed;
222 if (qemu_guest_getrandom(&seed, sizeof(seed), NULL)) {
223 return;
225 qemu_fdt_setprop_u64(vms->fdt, node, "kaslr-seed", seed);
228 static void create_fdt(VirtMachineState *vms)
230 MachineState *ms = MACHINE(vms);
231 int nb_numa_nodes = ms->numa_state->num_nodes;
232 void *fdt = create_device_tree(&vms->fdt_size);
234 if (!fdt) {
235 error_report("create_device_tree() failed");
236 exit(1);
239 vms->fdt = fdt;
241 /* Header */
242 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt");
243 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
244 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
246 /* /chosen must exist for load_dtb to fill in necessary properties later */
247 qemu_fdt_add_subnode(fdt, "/chosen");
248 create_kaslr_seed(vms, "/chosen");
250 if (vms->secure) {
251 qemu_fdt_add_subnode(fdt, "/secure-chosen");
252 create_kaslr_seed(vms, "/secure-chosen");
255 /* Clock node, for the benefit of the UART. The kernel device tree
256 * binding documentation claims the PL011 node clock properties are
257 * optional but in practice if you omit them the kernel refuses to
258 * probe for the device.
260 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt);
261 qemu_fdt_add_subnode(fdt, "/apb-pclk");
262 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock");
263 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0);
264 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000);
265 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names",
266 "clk24mhz");
267 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle);
269 if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) {
270 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
271 uint32_t *matrix = g_malloc0(size);
272 int idx, i, j;
274 for (i = 0; i < nb_numa_nodes; i++) {
275 for (j = 0; j < nb_numa_nodes; j++) {
276 idx = (i * nb_numa_nodes + j) * 3;
277 matrix[idx + 0] = cpu_to_be32(i);
278 matrix[idx + 1] = cpu_to_be32(j);
279 matrix[idx + 2] =
280 cpu_to_be32(ms->numa_state->nodes[i].distance[j]);
284 qemu_fdt_add_subnode(fdt, "/distance-map");
285 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible",
286 "numa-distance-map-v1");
287 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix",
288 matrix, size);
289 g_free(matrix);
293 static void fdt_add_timer_nodes(const VirtMachineState *vms)
295 /* On real hardware these interrupts are level-triggered.
296 * On KVM they were edge-triggered before host kernel version 4.4,
297 * and level-triggered afterwards.
298 * On emulated QEMU they are level-triggered.
300 * Getting the DTB info about them wrong is awkward for some
301 * guest kernels:
302 * pre-4.8 ignore the DT and leave the interrupt configured
303 * with whatever the GIC reset value (or the bootloader) left it at
304 * 4.8 before rc6 honour the incorrect data by programming it back
305 * into the GIC, causing problems
306 * 4.8rc6 and later ignore the DT and always write "level triggered"
307 * into the GIC
309 * For backwards-compatibility, virt-2.8 and earlier will continue
310 * to say these are edge-triggered, but later machines will report
311 * the correct information.
313 ARMCPU *armcpu;
314 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
315 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
317 if (vmc->claim_edge_triggered_timers) {
318 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI;
321 if (vms->gic_version == VIRT_GIC_VERSION_2) {
322 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
323 GIC_FDT_IRQ_PPI_CPU_WIDTH,
324 (1 << vms->smp_cpus) - 1);
327 qemu_fdt_add_subnode(vms->fdt, "/timer");
329 armcpu = ARM_CPU(qemu_get_cpu(0));
330 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
331 const char compat[] = "arm,armv8-timer\0arm,armv7-timer";
332 qemu_fdt_setprop(vms->fdt, "/timer", "compatible",
333 compat, sizeof(compat));
334 } else {
335 qemu_fdt_setprop_string(vms->fdt, "/timer", "compatible",
336 "arm,armv7-timer");
338 qemu_fdt_setprop(vms->fdt, "/timer", "always-on", NULL, 0);
339 qemu_fdt_setprop_cells(vms->fdt, "/timer", "interrupts",
340 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags,
341 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags,
342 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags,
343 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags);
346 static void fdt_add_cpu_nodes(const VirtMachineState *vms)
348 int cpu;
349 int addr_cells = 1;
350 const MachineState *ms = MACHINE(vms);
353 * From Documentation/devicetree/bindings/arm/cpus.txt
354 * On ARM v8 64-bit systems value should be set to 2,
355 * that corresponds to the MPIDR_EL1 register size.
356 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
357 * in the system, #address-cells can be set to 1, since
358 * MPIDR_EL1[63:32] bits are not used for CPUs
359 * identification.
361 * Here we actually don't know whether our system is 32- or 64-bit one.
362 * The simplest way to go is to examine affinity IDs of all our CPUs. If
363 * at least one of them has Aff3 populated, we set #address-cells to 2.
365 for (cpu = 0; cpu < vms->smp_cpus; cpu++) {
366 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
368 if (armcpu->mp_affinity & ARM_AFF3_MASK) {
369 addr_cells = 2;
370 break;
374 qemu_fdt_add_subnode(vms->fdt, "/cpus");
375 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#address-cells", addr_cells);
376 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#size-cells", 0x0);
378 for (cpu = vms->smp_cpus - 1; cpu >= 0; cpu--) {
379 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
380 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
381 CPUState *cs = CPU(armcpu);
383 qemu_fdt_add_subnode(vms->fdt, nodename);
384 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "cpu");
385 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
386 armcpu->dtb_compatible);
388 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED
389 && vms->smp_cpus > 1) {
390 qemu_fdt_setprop_string(vms->fdt, nodename,
391 "enable-method", "psci");
394 if (addr_cells == 2) {
395 qemu_fdt_setprop_u64(vms->fdt, nodename, "reg",
396 armcpu->mp_affinity);
397 } else {
398 qemu_fdt_setprop_cell(vms->fdt, nodename, "reg",
399 armcpu->mp_affinity);
402 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
403 qemu_fdt_setprop_cell(vms->fdt, nodename, "numa-node-id",
404 ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
407 g_free(nodename);
411 static void fdt_add_its_gic_node(VirtMachineState *vms)
413 char *nodename;
415 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt);
416 nodename = g_strdup_printf("/intc/its@%" PRIx64,
417 vms->memmap[VIRT_GIC_ITS].base);
418 qemu_fdt_add_subnode(vms->fdt, nodename);
419 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
420 "arm,gic-v3-its");
421 qemu_fdt_setprop(vms->fdt, nodename, "msi-controller", NULL, 0);
422 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
423 2, vms->memmap[VIRT_GIC_ITS].base,
424 2, vms->memmap[VIRT_GIC_ITS].size);
425 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->msi_phandle);
426 g_free(nodename);
429 static void fdt_add_v2m_gic_node(VirtMachineState *vms)
431 char *nodename;
433 nodename = g_strdup_printf("/intc/v2m@%" PRIx64,
434 vms->memmap[VIRT_GIC_V2M].base);
435 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt);
436 qemu_fdt_add_subnode(vms->fdt, nodename);
437 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
438 "arm,gic-v2m-frame");
439 qemu_fdt_setprop(vms->fdt, nodename, "msi-controller", NULL, 0);
440 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
441 2, vms->memmap[VIRT_GIC_V2M].base,
442 2, vms->memmap[VIRT_GIC_V2M].size);
443 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->msi_phandle);
444 g_free(nodename);
447 static void fdt_add_gic_node(VirtMachineState *vms)
449 char *nodename;
451 vms->gic_phandle = qemu_fdt_alloc_phandle(vms->fdt);
452 qemu_fdt_setprop_cell(vms->fdt, "/", "interrupt-parent", vms->gic_phandle);
454 nodename = g_strdup_printf("/intc@%" PRIx64,
455 vms->memmap[VIRT_GIC_DIST].base);
456 qemu_fdt_add_subnode(vms->fdt, nodename);
457 qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 3);
458 qemu_fdt_setprop(vms->fdt, nodename, "interrupt-controller", NULL, 0);
459 qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 0x2);
460 qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 0x2);
461 qemu_fdt_setprop(vms->fdt, nodename, "ranges", NULL, 0);
462 if (vms->gic_version == VIRT_GIC_VERSION_3) {
463 int nb_redist_regions = virt_gicv3_redist_region_count(vms);
465 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
466 "arm,gic-v3");
468 qemu_fdt_setprop_cell(vms->fdt, nodename,
469 "#redistributor-regions", nb_redist_regions);
471 if (nb_redist_regions == 1) {
472 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
473 2, vms->memmap[VIRT_GIC_DIST].base,
474 2, vms->memmap[VIRT_GIC_DIST].size,
475 2, vms->memmap[VIRT_GIC_REDIST].base,
476 2, vms->memmap[VIRT_GIC_REDIST].size);
477 } else {
478 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
479 2, vms->memmap[VIRT_GIC_DIST].base,
480 2, vms->memmap[VIRT_GIC_DIST].size,
481 2, vms->memmap[VIRT_GIC_REDIST].base,
482 2, vms->memmap[VIRT_GIC_REDIST].size,
483 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base,
484 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size);
487 if (vms->virt) {
488 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
489 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ,
490 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
492 } else {
493 /* 'cortex-a15-gic' means 'GIC v2' */
494 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
495 "arm,cortex-a15-gic");
496 if (!vms->virt) {
497 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
498 2, vms->memmap[VIRT_GIC_DIST].base,
499 2, vms->memmap[VIRT_GIC_DIST].size,
500 2, vms->memmap[VIRT_GIC_CPU].base,
501 2, vms->memmap[VIRT_GIC_CPU].size);
502 } else {
503 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
504 2, vms->memmap[VIRT_GIC_DIST].base,
505 2, vms->memmap[VIRT_GIC_DIST].size,
506 2, vms->memmap[VIRT_GIC_CPU].base,
507 2, vms->memmap[VIRT_GIC_CPU].size,
508 2, vms->memmap[VIRT_GIC_HYP].base,
509 2, vms->memmap[VIRT_GIC_HYP].size,
510 2, vms->memmap[VIRT_GIC_VCPU].base,
511 2, vms->memmap[VIRT_GIC_VCPU].size);
512 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
513 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ,
514 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
518 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->gic_phandle);
519 g_free(nodename);
522 static void fdt_add_pmu_nodes(const VirtMachineState *vms)
524 CPUState *cpu;
525 ARMCPU *armcpu;
526 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
528 CPU_FOREACH(cpu) {
529 armcpu = ARM_CPU(cpu);
530 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
531 return;
533 if (kvm_enabled()) {
534 if (kvm_irqchip_in_kernel()) {
535 kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ));
537 kvm_arm_pmu_init(cpu);
541 if (vms->gic_version == VIRT_GIC_VERSION_2) {
542 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
543 GIC_FDT_IRQ_PPI_CPU_WIDTH,
544 (1 << vms->smp_cpus) - 1);
547 armcpu = ARM_CPU(qemu_get_cpu(0));
548 qemu_fdt_add_subnode(vms->fdt, "/pmu");
549 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
550 const char compat[] = "arm,armv8-pmuv3";
551 qemu_fdt_setprop(vms->fdt, "/pmu", "compatible",
552 compat, sizeof(compat));
553 qemu_fdt_setprop_cells(vms->fdt, "/pmu", "interrupts",
554 GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags);
558 static inline DeviceState *create_acpi_ged(VirtMachineState *vms)
560 DeviceState *dev;
561 MachineState *ms = MACHINE(vms);
562 int irq = vms->irqmap[VIRT_ACPI_GED];
563 uint32_t event = ACPI_GED_PWR_DOWN_EVT;
565 if (ms->ram_slots) {
566 event |= ACPI_GED_MEM_HOTPLUG_EVT;
569 if (ms->nvdimms_state->is_enabled) {
570 event |= ACPI_GED_NVDIMM_HOTPLUG_EVT;
573 dev = qdev_new(TYPE_ACPI_GED);
574 qdev_prop_set_uint32(dev, "ged-event", event);
576 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base);
577 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base);
578 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq));
580 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
582 return dev;
585 static void create_its(VirtMachineState *vms)
587 const char *itsclass = its_class_name();
588 DeviceState *dev;
590 if (!itsclass) {
591 /* Do nothing if not supported */
592 return;
595 dev = qdev_new(itsclass);
597 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic),
598 &error_abort);
599 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
600 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base);
602 fdt_add_its_gic_node(vms);
603 vms->msi_controller = VIRT_MSI_CTRL_ITS;
606 static void create_v2m(VirtMachineState *vms)
608 int i;
609 int irq = vms->irqmap[VIRT_GIC_V2M];
610 DeviceState *dev;
612 dev = qdev_new("arm-gicv2m");
613 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base);
614 qdev_prop_set_uint32(dev, "base-spi", irq);
615 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS);
616 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
618 for (i = 0; i < NUM_GICV2M_SPIS; i++) {
619 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
620 qdev_get_gpio_in(vms->gic, irq + i));
623 fdt_add_v2m_gic_node(vms);
624 vms->msi_controller = VIRT_MSI_CTRL_GICV2M;
627 static void create_gic(VirtMachineState *vms)
629 MachineState *ms = MACHINE(vms);
630 /* We create a standalone GIC */
631 SysBusDevice *gicbusdev;
632 const char *gictype;
633 int type = vms->gic_version, i;
634 unsigned int smp_cpus = ms->smp.cpus;
635 uint32_t nb_redist_regions = 0;
637 gictype = (type == 3) ? gicv3_class_name() : gic_class_name();
639 vms->gic = qdev_new(gictype);
640 qdev_prop_set_uint32(vms->gic, "revision", type);
641 qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus);
642 /* Note that the num-irq property counts both internal and external
643 * interrupts; there are always 32 of the former (mandated by GIC spec).
645 qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32);
646 if (!kvm_irqchip_in_kernel()) {
647 qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure);
650 if (type == 3) {
651 uint32_t redist0_capacity =
652 vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
653 uint32_t redist0_count = MIN(smp_cpus, redist0_capacity);
655 nb_redist_regions = virt_gicv3_redist_region_count(vms);
657 qdev_prop_set_uint32(vms->gic, "len-redist-region-count",
658 nb_redist_regions);
659 qdev_prop_set_uint32(vms->gic, "redist-region-count[0]", redist0_count);
661 if (nb_redist_regions == 2) {
662 uint32_t redist1_capacity =
663 vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE;
665 qdev_prop_set_uint32(vms->gic, "redist-region-count[1]",
666 MIN(smp_cpus - redist0_count, redist1_capacity));
668 } else {
669 if (!kvm_irqchip_in_kernel()) {
670 qdev_prop_set_bit(vms->gic, "has-virtualization-extensions",
671 vms->virt);
674 gicbusdev = SYS_BUS_DEVICE(vms->gic);
675 sysbus_realize_and_unref(gicbusdev, &error_fatal);
676 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base);
677 if (type == 3) {
678 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base);
679 if (nb_redist_regions == 2) {
680 sysbus_mmio_map(gicbusdev, 2,
681 vms->memmap[VIRT_HIGH_GIC_REDIST2].base);
683 } else {
684 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base);
685 if (vms->virt) {
686 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base);
687 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base);
691 /* Wire the outputs from each CPU's generic timer and the GICv3
692 * maintenance interrupt signal to the appropriate GIC PPI inputs,
693 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
695 for (i = 0; i < smp_cpus; i++) {
696 DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
697 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
698 int irq;
699 /* Mapping from the output timer irq lines from the CPU to the
700 * GIC PPI inputs we use for the virt board.
702 const int timer_irq[] = {
703 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
704 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
705 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
706 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,
709 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
710 qdev_connect_gpio_out(cpudev, irq,
711 qdev_get_gpio_in(vms->gic,
712 ppibase + timer_irq[irq]));
715 if (type == 3) {
716 qemu_irq irq = qdev_get_gpio_in(vms->gic,
717 ppibase + ARCH_GIC_MAINT_IRQ);
718 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
719 0, irq);
720 } else if (vms->virt) {
721 qemu_irq irq = qdev_get_gpio_in(vms->gic,
722 ppibase + ARCH_GIC_MAINT_IRQ);
723 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq);
726 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
727 qdev_get_gpio_in(vms->gic, ppibase
728 + VIRTUAL_PMU_IRQ));
730 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
731 sysbus_connect_irq(gicbusdev, i + smp_cpus,
732 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
733 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus,
734 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
735 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
736 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
739 fdt_add_gic_node(vms);
741 if (type == 3 && vms->its) {
742 create_its(vms);
743 } else if (type == 2) {
744 create_v2m(vms);
748 static void create_uart(const VirtMachineState *vms, int uart,
749 MemoryRegion *mem, Chardev *chr)
751 char *nodename;
752 hwaddr base = vms->memmap[uart].base;
753 hwaddr size = vms->memmap[uart].size;
754 int irq = vms->irqmap[uart];
755 const char compat[] = "arm,pl011\0arm,primecell";
756 const char clocknames[] = "uartclk\0apb_pclk";
757 DeviceState *dev = qdev_new(TYPE_PL011);
758 SysBusDevice *s = SYS_BUS_DEVICE(dev);
760 qdev_prop_set_chr(dev, "chardev", chr);
761 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
762 memory_region_add_subregion(mem, base,
763 sysbus_mmio_get_region(s, 0));
764 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq));
766 nodename = g_strdup_printf("/pl011@%" PRIx64, base);
767 qemu_fdt_add_subnode(vms->fdt, nodename);
768 /* Note that we can't use setprop_string because of the embedded NUL */
769 qemu_fdt_setprop(vms->fdt, nodename, "compatible",
770 compat, sizeof(compat));
771 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
772 2, base, 2, size);
773 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
774 GIC_FDT_IRQ_TYPE_SPI, irq,
775 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
776 qemu_fdt_setprop_cells(vms->fdt, nodename, "clocks",
777 vms->clock_phandle, vms->clock_phandle);
778 qemu_fdt_setprop(vms->fdt, nodename, "clock-names",
779 clocknames, sizeof(clocknames));
781 if (uart == VIRT_UART) {
782 qemu_fdt_setprop_string(vms->fdt, "/chosen", "stdout-path", nodename);
783 } else {
784 /* Mark as not usable by the normal world */
785 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled");
786 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay");
788 qemu_fdt_setprop_string(vms->fdt, "/secure-chosen", "stdout-path",
789 nodename);
792 g_free(nodename);
795 static void create_rtc(const VirtMachineState *vms)
797 char *nodename;
798 hwaddr base = vms->memmap[VIRT_RTC].base;
799 hwaddr size = vms->memmap[VIRT_RTC].size;
800 int irq = vms->irqmap[VIRT_RTC];
801 const char compat[] = "arm,pl031\0arm,primecell";
803 sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq));
805 nodename = g_strdup_printf("/pl031@%" PRIx64, base);
806 qemu_fdt_add_subnode(vms->fdt, nodename);
807 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat));
808 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
809 2, base, 2, size);
810 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
811 GIC_FDT_IRQ_TYPE_SPI, irq,
812 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
813 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle);
814 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk");
815 g_free(nodename);
818 static DeviceState *gpio_key_dev;
819 static void virt_powerdown_req(Notifier *n, void *opaque)
821 VirtMachineState *s = container_of(n, VirtMachineState, powerdown_notifier);
823 if (s->acpi_dev) {
824 acpi_send_event(s->acpi_dev, ACPI_POWER_DOWN_STATUS);
825 } else {
826 /* use gpio Pin 3 for power button event */
827 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1);
831 static void create_gpio(const VirtMachineState *vms)
833 char *nodename;
834 DeviceState *pl061_dev;
835 hwaddr base = vms->memmap[VIRT_GPIO].base;
836 hwaddr size = vms->memmap[VIRT_GPIO].size;
837 int irq = vms->irqmap[VIRT_GPIO];
838 const char compat[] = "arm,pl061\0arm,primecell";
840 pl061_dev = sysbus_create_simple("pl061", base,
841 qdev_get_gpio_in(vms->gic, irq));
843 uint32_t phandle = qemu_fdt_alloc_phandle(vms->fdt);
844 nodename = g_strdup_printf("/pl061@%" PRIx64, base);
845 qemu_fdt_add_subnode(vms->fdt, nodename);
846 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
847 2, base, 2, size);
848 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat));
849 qemu_fdt_setprop_cell(vms->fdt, nodename, "#gpio-cells", 2);
850 qemu_fdt_setprop(vms->fdt, nodename, "gpio-controller", NULL, 0);
851 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
852 GIC_FDT_IRQ_TYPE_SPI, irq,
853 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
854 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle);
855 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk");
856 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", phandle);
858 gpio_key_dev = sysbus_create_simple("gpio-key", -1,
859 qdev_get_gpio_in(pl061_dev, 3));
860 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys");
861 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-keys");
862 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0);
863 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#address-cells", 1);
865 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys/poweroff");
866 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys/poweroff",
867 "label", "GPIO Key Poweroff");
868 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys/poweroff", "linux,code",
869 KEY_POWER);
870 qemu_fdt_setprop_cells(vms->fdt, "/gpio-keys/poweroff",
871 "gpios", phandle, 3, 0);
872 g_free(nodename);
875 static void create_virtio_devices(const VirtMachineState *vms)
877 int i;
878 hwaddr size = vms->memmap[VIRT_MMIO].size;
880 /* We create the transports in forwards order. Since qbus_realize()
881 * prepends (not appends) new child buses, the incrementing loop below will
882 * create a list of virtio-mmio buses with decreasing base addresses.
884 * When a -device option is processed from the command line,
885 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
886 * order. The upshot is that -device options in increasing command line
887 * order are mapped to virtio-mmio buses with decreasing base addresses.
889 * When this code was originally written, that arrangement ensured that the
890 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
891 * the first -device on the command line. (The end-to-end order is a
892 * function of this loop, qbus_realize(), qbus_find_recursive(), and the
893 * guest kernel's name-to-address assignment strategy.)
895 * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
896 * the message, if not necessarily the code, of commit 70161ff336.
897 * Therefore the loop now establishes the inverse of the original intent.
899 * Unfortunately, we can't counteract the kernel change by reversing the
900 * loop; it would break existing command lines.
902 * In any case, the kernel makes no guarantee about the stability of
903 * enumeration order of virtio devices (as demonstrated by it changing
904 * between kernel versions). For reliable and stable identification
905 * of disks users must use UUIDs or similar mechanisms.
907 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {
908 int irq = vms->irqmap[VIRT_MMIO] + i;
909 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
911 sysbus_create_simple("virtio-mmio", base,
912 qdev_get_gpio_in(vms->gic, irq));
915 /* We add dtb nodes in reverse order so that they appear in the finished
916 * device tree lowest address first.
918 * Note that this mapping is independent of the loop above. The previous
919 * loop influences virtio device to virtio transport assignment, whereas
920 * this loop controls how virtio transports are laid out in the dtb.
922 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
923 char *nodename;
924 int irq = vms->irqmap[VIRT_MMIO] + i;
925 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
927 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base);
928 qemu_fdt_add_subnode(vms->fdt, nodename);
929 qemu_fdt_setprop_string(vms->fdt, nodename,
930 "compatible", "virtio,mmio");
931 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
932 2, base, 2, size);
933 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
934 GIC_FDT_IRQ_TYPE_SPI, irq,
935 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
936 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0);
937 g_free(nodename);
941 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
943 static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms,
944 const char *name,
945 const char *alias_prop_name)
948 * Create a single flash device. We use the same parameters as
949 * the flash devices on the Versatile Express board.
951 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
953 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
954 qdev_prop_set_uint8(dev, "width", 4);
955 qdev_prop_set_uint8(dev, "device-width", 2);
956 qdev_prop_set_bit(dev, "big-endian", false);
957 qdev_prop_set_uint16(dev, "id0", 0x89);
958 qdev_prop_set_uint16(dev, "id1", 0x18);
959 qdev_prop_set_uint16(dev, "id2", 0x00);
960 qdev_prop_set_uint16(dev, "id3", 0x00);
961 qdev_prop_set_string(dev, "name", name);
962 object_property_add_child(OBJECT(vms), name, OBJECT(dev));
963 object_property_add_alias(OBJECT(vms), alias_prop_name,
964 OBJECT(dev), "drive");
965 return PFLASH_CFI01(dev);
968 static void virt_flash_create(VirtMachineState *vms)
970 vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0");
971 vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1");
974 static void virt_flash_map1(PFlashCFI01 *flash,
975 hwaddr base, hwaddr size,
976 MemoryRegion *sysmem)
978 DeviceState *dev = DEVICE(flash);
980 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE));
981 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
982 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
983 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
985 memory_region_add_subregion(sysmem, base,
986 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
987 0));
990 static void virt_flash_map(VirtMachineState *vms,
991 MemoryRegion *sysmem,
992 MemoryRegion *secure_sysmem)
995 * Map two flash devices to fill the VIRT_FLASH space in the memmap.
996 * sysmem is the system memory space. secure_sysmem is the secure view
997 * of the system, and the first flash device should be made visible only
998 * there. The second flash device is visible to both secure and nonsecure.
999 * If sysmem == secure_sysmem this means there is no separate Secure
1000 * address space and both flash devices are generally visible.
1002 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
1003 hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
1005 virt_flash_map1(vms->flash[0], flashbase, flashsize,
1006 secure_sysmem);
1007 virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize,
1008 sysmem);
1011 static void virt_flash_fdt(VirtMachineState *vms,
1012 MemoryRegion *sysmem,
1013 MemoryRegion *secure_sysmem)
1015 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
1016 hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
1017 char *nodename;
1019 if (sysmem == secure_sysmem) {
1020 /* Report both flash devices as a single node in the DT */
1021 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
1022 qemu_fdt_add_subnode(vms->fdt, nodename);
1023 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash");
1024 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
1025 2, flashbase, 2, flashsize,
1026 2, flashbase + flashsize, 2, flashsize);
1027 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4);
1028 g_free(nodename);
1029 } else {
1031 * Report the devices as separate nodes so we can mark one as
1032 * only visible to the secure world.
1034 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase);
1035 qemu_fdt_add_subnode(vms->fdt, nodename);
1036 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash");
1037 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
1038 2, flashbase, 2, flashsize);
1039 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4);
1040 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled");
1041 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay");
1042 g_free(nodename);
1044 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
1045 qemu_fdt_add_subnode(vms->fdt, nodename);
1046 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash");
1047 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
1048 2, flashbase + flashsize, 2, flashsize);
1049 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4);
1050 g_free(nodename);
1054 static bool virt_firmware_init(VirtMachineState *vms,
1055 MemoryRegion *sysmem,
1056 MemoryRegion *secure_sysmem)
1058 int i;
1059 BlockBackend *pflash_blk0;
1061 /* Map legacy -drive if=pflash to machine properties */
1062 for (i = 0; i < ARRAY_SIZE(vms->flash); i++) {
1063 pflash_cfi01_legacy_drive(vms->flash[i],
1064 drive_get(IF_PFLASH, 0, i));
1067 virt_flash_map(vms, sysmem, secure_sysmem);
1069 pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]);
1071 if (bios_name) {
1072 char *fname;
1073 MemoryRegion *mr;
1074 int image_size;
1076 if (pflash_blk0) {
1077 error_report("The contents of the first flash device may be "
1078 "specified with -bios or with -drive if=pflash... "
1079 "but you cannot use both options at once");
1080 exit(1);
1083 /* Fall back to -bios */
1085 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1086 if (!fname) {
1087 error_report("Could not find ROM image '%s'", bios_name);
1088 exit(1);
1090 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0);
1091 image_size = load_image_mr(fname, mr);
1092 g_free(fname);
1093 if (image_size < 0) {
1094 error_report("Could not load ROM image '%s'", bios_name);
1095 exit(1);
1099 return pflash_blk0 || bios_name;
1102 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as)
1104 MachineState *ms = MACHINE(vms);
1105 hwaddr base = vms->memmap[VIRT_FW_CFG].base;
1106 hwaddr size = vms->memmap[VIRT_FW_CFG].size;
1107 FWCfgState *fw_cfg;
1108 char *nodename;
1110 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as);
1111 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus);
1113 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
1114 qemu_fdt_add_subnode(vms->fdt, nodename);
1115 qemu_fdt_setprop_string(vms->fdt, nodename,
1116 "compatible", "qemu,fw-cfg-mmio");
1117 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
1118 2, base, 2, size);
1119 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0);
1120 g_free(nodename);
1121 return fw_cfg;
1124 static void create_pcie_irq_map(const VirtMachineState *vms,
1125 uint32_t gic_phandle,
1126 int first_irq, const char *nodename)
1128 int devfn, pin;
1129 uint32_t full_irq_map[4 * 4 * 10] = { 0 };
1130 uint32_t *irq_map = full_irq_map;
1132 for (devfn = 0; devfn <= 0x18; devfn += 0x8) {
1133 for (pin = 0; pin < 4; pin++) {
1134 int irq_type = GIC_FDT_IRQ_TYPE_SPI;
1135 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS);
1136 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
1137 int i;
1139 uint32_t map[] = {
1140 devfn << 8, 0, 0, /* devfn */
1141 pin + 1, /* PCI pin */
1142 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */
1144 /* Convert map to big endian */
1145 for (i = 0; i < 10; i++) {
1146 irq_map[i] = cpu_to_be32(map[i]);
1148 irq_map += 10;
1152 qemu_fdt_setprop(vms->fdt, nodename, "interrupt-map",
1153 full_irq_map, sizeof(full_irq_map));
1155 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupt-map-mask",
1156 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */
1157 0x7 /* PCI irq */);
1160 static void create_smmu(const VirtMachineState *vms,
1161 PCIBus *bus)
1163 char *node;
1164 const char compat[] = "arm,smmu-v3";
1165 int irq = vms->irqmap[VIRT_SMMU];
1166 int i;
1167 hwaddr base = vms->memmap[VIRT_SMMU].base;
1168 hwaddr size = vms->memmap[VIRT_SMMU].size;
1169 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror";
1170 DeviceState *dev;
1172 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) {
1173 return;
1176 dev = qdev_new("arm-smmuv3");
1178 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus),
1179 &error_abort);
1180 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1181 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
1182 for (i = 0; i < NUM_SMMU_IRQS; i++) {
1183 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
1184 qdev_get_gpio_in(vms->gic, irq + i));
1187 node = g_strdup_printf("/smmuv3@%" PRIx64, base);
1188 qemu_fdt_add_subnode(vms->fdt, node);
1189 qemu_fdt_setprop(vms->fdt, node, "compatible", compat, sizeof(compat));
1190 qemu_fdt_setprop_sized_cells(vms->fdt, node, "reg", 2, base, 2, size);
1192 qemu_fdt_setprop_cells(vms->fdt, node, "interrupts",
1193 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1194 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1195 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1196 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
1198 qemu_fdt_setprop(vms->fdt, node, "interrupt-names", irq_names,
1199 sizeof(irq_names));
1201 qemu_fdt_setprop_cell(vms->fdt, node, "clocks", vms->clock_phandle);
1202 qemu_fdt_setprop_string(vms->fdt, node, "clock-names", "apb_pclk");
1203 qemu_fdt_setprop(vms->fdt, node, "dma-coherent", NULL, 0);
1205 qemu_fdt_setprop_cell(vms->fdt, node, "#iommu-cells", 1);
1207 qemu_fdt_setprop_cell(vms->fdt, node, "phandle", vms->iommu_phandle);
1208 g_free(node);
1211 static void create_virtio_iommu_dt_bindings(VirtMachineState *vms)
1213 const char compat[] = "virtio,pci-iommu";
1214 uint16_t bdf = vms->virtio_iommu_bdf;
1215 char *node;
1217 vms->iommu_phandle = qemu_fdt_alloc_phandle(vms->fdt);
1219 node = g_strdup_printf("%s/virtio_iommu@%d", vms->pciehb_nodename, bdf);
1220 qemu_fdt_add_subnode(vms->fdt, node);
1221 qemu_fdt_setprop(vms->fdt, node, "compatible", compat, sizeof(compat));
1222 qemu_fdt_setprop_sized_cells(vms->fdt, node, "reg",
1223 1, bdf << 8, 1, 0, 1, 0,
1224 1, 0, 1, 0);
1226 qemu_fdt_setprop_cell(vms->fdt, node, "#iommu-cells", 1);
1227 qemu_fdt_setprop_cell(vms->fdt, node, "phandle", vms->iommu_phandle);
1228 g_free(node);
1230 qemu_fdt_setprop_cells(vms->fdt, vms->pciehb_nodename, "iommu-map",
1231 0x0, vms->iommu_phandle, 0x0, bdf,
1232 bdf + 1, vms->iommu_phandle, bdf + 1, 0xffff - bdf);
1235 static void create_pcie(VirtMachineState *vms)
1237 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base;
1238 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size;
1239 hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base;
1240 hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size;
1241 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base;
1242 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size;
1243 hwaddr base_ecam, size_ecam;
1244 hwaddr base = base_mmio;
1245 int nr_pcie_buses;
1246 int irq = vms->irqmap[VIRT_PCIE];
1247 MemoryRegion *mmio_alias;
1248 MemoryRegion *mmio_reg;
1249 MemoryRegion *ecam_alias;
1250 MemoryRegion *ecam_reg;
1251 DeviceState *dev;
1252 char *nodename;
1253 int i, ecam_id;
1254 PCIHostState *pci;
1256 dev = qdev_new(TYPE_GPEX_HOST);
1257 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1259 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam);
1260 base_ecam = vms->memmap[ecam_id].base;
1261 size_ecam = vms->memmap[ecam_id].size;
1262 nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
1263 /* Map only the first size_ecam bytes of ECAM space */
1264 ecam_alias = g_new0(MemoryRegion, 1);
1265 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
1266 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
1267 ecam_reg, 0, size_ecam);
1268 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias);
1270 /* Map the MMIO window into system address space so as to expose
1271 * the section of PCI MMIO space which starts at the same base address
1272 * (ie 1:1 mapping for that part of PCI MMIO space visible through
1273 * the window).
1275 mmio_alias = g_new0(MemoryRegion, 1);
1276 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
1277 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
1278 mmio_reg, base_mmio, size_mmio);
1279 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias);
1281 if (vms->highmem) {
1282 /* Map high MMIO space */
1283 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1);
1285 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high",
1286 mmio_reg, base_mmio_high, size_mmio_high);
1287 memory_region_add_subregion(get_system_memory(), base_mmio_high,
1288 high_mmio_alias);
1291 /* Map IO port space */
1292 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio);
1294 for (i = 0; i < GPEX_NUM_IRQS; i++) {
1295 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
1296 qdev_get_gpio_in(vms->gic, irq + i));
1297 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);
1300 pci = PCI_HOST_BRIDGE(dev);
1301 if (pci->bus) {
1302 for (i = 0; i < nb_nics; i++) {
1303 NICInfo *nd = &nd_table[i];
1305 if (!nd->model) {
1306 nd->model = g_strdup("virtio");
1309 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL);
1313 nodename = vms->pciehb_nodename = g_strdup_printf("/pcie@%" PRIx64, base);
1314 qemu_fdt_add_subnode(vms->fdt, nodename);
1315 qemu_fdt_setprop_string(vms->fdt, nodename,
1316 "compatible", "pci-host-ecam-generic");
1317 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "pci");
1318 qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 3);
1319 qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 2);
1320 qemu_fdt_setprop_cell(vms->fdt, nodename, "linux,pci-domain", 0);
1321 qemu_fdt_setprop_cells(vms->fdt, nodename, "bus-range", 0,
1322 nr_pcie_buses - 1);
1323 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0);
1325 if (vms->msi_phandle) {
1326 qemu_fdt_setprop_cells(vms->fdt, nodename, "msi-parent",
1327 vms->msi_phandle);
1330 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
1331 2, base_ecam, 2, size_ecam);
1333 if (vms->highmem) {
1334 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges",
1335 1, FDT_PCI_RANGE_IOPORT, 2, 0,
1336 2, base_pio, 2, size_pio,
1337 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1338 2, base_mmio, 2, size_mmio,
1339 1, FDT_PCI_RANGE_MMIO_64BIT,
1340 2, base_mmio_high,
1341 2, base_mmio_high, 2, size_mmio_high);
1342 } else {
1343 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges",
1344 1, FDT_PCI_RANGE_IOPORT, 2, 0,
1345 2, base_pio, 2, size_pio,
1346 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1347 2, base_mmio, 2, size_mmio);
1350 qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 1);
1351 create_pcie_irq_map(vms, vms->gic_phandle, irq, nodename);
1353 if (vms->iommu) {
1354 vms->iommu_phandle = qemu_fdt_alloc_phandle(vms->fdt);
1356 switch (vms->iommu) {
1357 case VIRT_IOMMU_SMMUV3:
1358 create_smmu(vms, pci->bus);
1359 qemu_fdt_setprop_cells(vms->fdt, nodename, "iommu-map",
1360 0x0, vms->iommu_phandle, 0x0, 0x10000);
1361 break;
1362 default:
1363 g_assert_not_reached();
1368 static void create_platform_bus(VirtMachineState *vms)
1370 DeviceState *dev;
1371 SysBusDevice *s;
1372 int i;
1373 MemoryRegion *sysmem = get_system_memory();
1375 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE);
1376 dev->id = TYPE_PLATFORM_BUS_DEVICE;
1377 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS);
1378 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size);
1379 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1380 vms->platform_bus_dev = dev;
1382 s = SYS_BUS_DEVICE(dev);
1383 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) {
1384 int irq = vms->irqmap[VIRT_PLATFORM_BUS] + i;
1385 sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq));
1388 memory_region_add_subregion(sysmem,
1389 vms->memmap[VIRT_PLATFORM_BUS].base,
1390 sysbus_mmio_get_region(s, 0));
1393 static void create_tag_ram(MemoryRegion *tag_sysmem,
1394 hwaddr base, hwaddr size,
1395 const char *name)
1397 MemoryRegion *tagram = g_new(MemoryRegion, 1);
1399 memory_region_init_ram(tagram, NULL, name, size / 32, &error_fatal);
1400 memory_region_add_subregion(tag_sysmem, base / 32, tagram);
1403 static void create_secure_ram(VirtMachineState *vms,
1404 MemoryRegion *secure_sysmem,
1405 MemoryRegion *secure_tag_sysmem)
1407 MemoryRegion *secram = g_new(MemoryRegion, 1);
1408 char *nodename;
1409 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base;
1410 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size;
1412 memory_region_init_ram(secram, NULL, "virt.secure-ram", size,
1413 &error_fatal);
1414 memory_region_add_subregion(secure_sysmem, base, secram);
1416 nodename = g_strdup_printf("/secram@%" PRIx64, base);
1417 qemu_fdt_add_subnode(vms->fdt, nodename);
1418 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "memory");
1419 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 2, base, 2, size);
1420 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled");
1421 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay");
1423 if (secure_tag_sysmem) {
1424 create_tag_ram(secure_tag_sysmem, base, size, "mach-virt.secure-tag");
1427 g_free(nodename);
1430 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size)
1432 const VirtMachineState *board = container_of(binfo, VirtMachineState,
1433 bootinfo);
1435 *fdt_size = board->fdt_size;
1436 return board->fdt;
1439 static void virt_build_smbios(VirtMachineState *vms)
1441 MachineClass *mc = MACHINE_GET_CLASS(vms);
1442 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1443 uint8_t *smbios_tables, *smbios_anchor;
1444 size_t smbios_tables_len, smbios_anchor_len;
1445 const char *product = "QEMU Virtual Machine";
1447 if (kvm_enabled()) {
1448 product = "KVM Virtual Machine";
1451 smbios_set_defaults("QEMU", product,
1452 vmc->smbios_old_sys_ver ? "1.0" : mc->name, false,
1453 true, SMBIOS_ENTRY_POINT_30);
1455 smbios_get_tables(MACHINE(vms), NULL, 0, &smbios_tables, &smbios_tables_len,
1456 &smbios_anchor, &smbios_anchor_len);
1458 if (smbios_anchor) {
1459 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables",
1460 smbios_tables, smbios_tables_len);
1461 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor",
1462 smbios_anchor, smbios_anchor_len);
1466 static
1467 void virt_machine_done(Notifier *notifier, void *data)
1469 VirtMachineState *vms = container_of(notifier, VirtMachineState,
1470 machine_done);
1471 MachineState *ms = MACHINE(vms);
1472 ARMCPU *cpu = ARM_CPU(first_cpu);
1473 struct arm_boot_info *info = &vms->bootinfo;
1474 AddressSpace *as = arm_boot_address_space(cpu, info);
1477 * If the user provided a dtb, we assume the dynamic sysbus nodes
1478 * already are integrated there. This corresponds to a use case where
1479 * the dynamic sysbus nodes are complex and their generation is not yet
1480 * supported. In that case the user can take charge of the guest dt
1481 * while qemu takes charge of the qom stuff.
1483 if (info->dtb_filename == NULL) {
1484 platform_bus_add_all_fdt_nodes(vms->fdt, "/intc",
1485 vms->memmap[VIRT_PLATFORM_BUS].base,
1486 vms->memmap[VIRT_PLATFORM_BUS].size,
1487 vms->irqmap[VIRT_PLATFORM_BUS]);
1489 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) {
1490 exit(1);
1493 virt_acpi_setup(vms);
1494 virt_build_smbios(vms);
1497 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
1499 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER;
1500 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1502 if (!vmc->disallow_affinity_adjustment) {
1503 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the
1504 * GIC's target-list limitations. 32-bit KVM hosts currently
1505 * always create clusters of 4 CPUs, but that is expected to
1506 * change when they gain support for gicv3. When KVM is enabled
1507 * it will override the changes we make here, therefore our
1508 * purposes are to make TCG consistent (with 64-bit KVM hosts)
1509 * and to improve SGI efficiency.
1511 if (vms->gic_version == VIRT_GIC_VERSION_3) {
1512 clustersz = GICV3_TARGETLIST_BITS;
1513 } else {
1514 clustersz = GIC_TARGETLIST_BITS;
1517 return arm_cpu_mp_affinity(idx, clustersz);
1520 static void virt_set_memmap(VirtMachineState *vms)
1522 MachineState *ms = MACHINE(vms);
1523 hwaddr base, device_memory_base, device_memory_size;
1524 int i;
1526 vms->memmap = extended_memmap;
1528 for (i = 0; i < ARRAY_SIZE(base_memmap); i++) {
1529 vms->memmap[i] = base_memmap[i];
1532 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) {
1533 error_report("unsupported number of memory slots: %"PRIu64,
1534 ms->ram_slots);
1535 exit(EXIT_FAILURE);
1539 * We compute the base of the high IO region depending on the
1540 * amount of initial and device memory. The device memory start/size
1541 * is aligned on 1GiB. We never put the high IO region below 256GiB
1542 * so that if maxram_size is < 255GiB we keep the legacy memory map.
1543 * The device region size assumes 1GiB page max alignment per slot.
1545 device_memory_base =
1546 ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB);
1547 device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB;
1549 /* Base address of the high IO region */
1550 base = device_memory_base + ROUND_UP(device_memory_size, GiB);
1551 if (base < device_memory_base) {
1552 error_report("maxmem/slots too huge");
1553 exit(EXIT_FAILURE);
1555 if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) {
1556 base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES;
1559 for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
1560 hwaddr size = extended_memmap[i].size;
1562 base = ROUND_UP(base, size);
1563 vms->memmap[i].base = base;
1564 vms->memmap[i].size = size;
1565 base += size;
1567 vms->highest_gpa = base - 1;
1568 if (device_memory_size > 0) {
1569 ms->device_memory = g_malloc0(sizeof(*ms->device_memory));
1570 ms->device_memory->base = device_memory_base;
1571 memory_region_init(&ms->device_memory->mr, OBJECT(vms),
1572 "device-memory", device_memory_size);
1577 * finalize_gic_version - Determines the final gic_version
1578 * according to the gic-version property
1580 * Default GIC type is v2
1582 static void finalize_gic_version(VirtMachineState *vms)
1584 unsigned int max_cpus = MACHINE(vms)->smp.max_cpus;
1586 if (kvm_enabled()) {
1587 int probe_bitmap;
1589 if (!kvm_irqchip_in_kernel()) {
1590 switch (vms->gic_version) {
1591 case VIRT_GIC_VERSION_HOST:
1592 warn_report(
1593 "gic-version=host not relevant with kernel-irqchip=off "
1594 "as only userspace GICv2 is supported. Using v2 ...");
1595 return;
1596 case VIRT_GIC_VERSION_MAX:
1597 case VIRT_GIC_VERSION_NOSEL:
1598 vms->gic_version = VIRT_GIC_VERSION_2;
1599 return;
1600 case VIRT_GIC_VERSION_2:
1601 return;
1602 case VIRT_GIC_VERSION_3:
1603 error_report(
1604 "gic-version=3 is not supported with kernel-irqchip=off");
1605 exit(1);
1609 probe_bitmap = kvm_arm_vgic_probe();
1610 if (!probe_bitmap) {
1611 error_report("Unable to determine GIC version supported by host");
1612 exit(1);
1615 switch (vms->gic_version) {
1616 case VIRT_GIC_VERSION_HOST:
1617 case VIRT_GIC_VERSION_MAX:
1618 if (probe_bitmap & KVM_ARM_VGIC_V3) {
1619 vms->gic_version = VIRT_GIC_VERSION_3;
1620 } else {
1621 vms->gic_version = VIRT_GIC_VERSION_2;
1623 return;
1624 case VIRT_GIC_VERSION_NOSEL:
1625 if ((probe_bitmap & KVM_ARM_VGIC_V2) && max_cpus <= GIC_NCPU) {
1626 vms->gic_version = VIRT_GIC_VERSION_2;
1627 } else if (probe_bitmap & KVM_ARM_VGIC_V3) {
1629 * in case the host does not support v2 in-kernel emulation or
1630 * the end-user requested more than 8 VCPUs we now default
1631 * to v3. In any case defaulting to v2 would be broken.
1633 vms->gic_version = VIRT_GIC_VERSION_3;
1634 } else if (max_cpus > GIC_NCPU) {
1635 error_report("host only supports in-kernel GICv2 emulation "
1636 "but more than 8 vcpus are requested");
1637 exit(1);
1639 break;
1640 case VIRT_GIC_VERSION_2:
1641 case VIRT_GIC_VERSION_3:
1642 break;
1645 /* Check chosen version is effectively supported by the host */
1646 if (vms->gic_version == VIRT_GIC_VERSION_2 &&
1647 !(probe_bitmap & KVM_ARM_VGIC_V2)) {
1648 error_report("host does not support in-kernel GICv2 emulation");
1649 exit(1);
1650 } else if (vms->gic_version == VIRT_GIC_VERSION_3 &&
1651 !(probe_bitmap & KVM_ARM_VGIC_V3)) {
1652 error_report("host does not support in-kernel GICv3 emulation");
1653 exit(1);
1655 return;
1658 /* TCG mode */
1659 switch (vms->gic_version) {
1660 case VIRT_GIC_VERSION_NOSEL:
1661 vms->gic_version = VIRT_GIC_VERSION_2;
1662 break;
1663 case VIRT_GIC_VERSION_MAX:
1664 vms->gic_version = VIRT_GIC_VERSION_3;
1665 break;
1666 case VIRT_GIC_VERSION_HOST:
1667 error_report("gic-version=host requires KVM");
1668 exit(1);
1669 case VIRT_GIC_VERSION_2:
1670 case VIRT_GIC_VERSION_3:
1671 break;
1675 static void machvirt_init(MachineState *machine)
1677 VirtMachineState *vms = VIRT_MACHINE(machine);
1678 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine);
1679 MachineClass *mc = MACHINE_GET_CLASS(machine);
1680 const CPUArchIdList *possible_cpus;
1681 MemoryRegion *sysmem = get_system_memory();
1682 MemoryRegion *secure_sysmem = NULL;
1683 MemoryRegion *tag_sysmem = NULL;
1684 MemoryRegion *secure_tag_sysmem = NULL;
1685 int n, virt_max_cpus;
1686 bool firmware_loaded;
1687 bool aarch64 = true;
1688 bool has_ged = !vmc->no_ged;
1689 unsigned int smp_cpus = machine->smp.cpus;
1690 unsigned int max_cpus = machine->smp.max_cpus;
1693 * In accelerated mode, the memory map is computed earlier in kvm_type()
1694 * to create a VM with the right number of IPA bits.
1696 if (!vms->memmap) {
1697 virt_set_memmap(vms);
1700 /* We can probe only here because during property set
1701 * KVM is not available yet
1703 finalize_gic_version(vms);
1705 if (!cpu_type_valid(machine->cpu_type)) {
1706 error_report("mach-virt: CPU type %s not supported", machine->cpu_type);
1707 exit(1);
1710 if (vms->secure) {
1711 if (kvm_enabled()) {
1712 error_report("mach-virt: KVM does not support Security extensions");
1713 exit(1);
1717 * The Secure view of the world is the same as the NonSecure,
1718 * but with a few extra devices. Create it as a container region
1719 * containing the system memory at low priority; any secure-only
1720 * devices go in at higher priority and take precedence.
1722 secure_sysmem = g_new(MemoryRegion, 1);
1723 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory",
1724 UINT64_MAX);
1725 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1);
1728 firmware_loaded = virt_firmware_init(vms, sysmem,
1729 secure_sysmem ?: sysmem);
1731 /* If we have an EL3 boot ROM then the assumption is that it will
1732 * implement PSCI itself, so disable QEMU's internal implementation
1733 * so it doesn't get in the way. Instead of starting secondary
1734 * CPUs in PSCI powerdown state we will start them all running and
1735 * let the boot ROM sort them out.
1736 * The usual case is that we do use QEMU's PSCI implementation;
1737 * if the guest has EL2 then we will use SMC as the conduit,
1738 * and otherwise we will use HVC (for backwards compatibility and
1739 * because if we're using KVM then we must use HVC).
1741 if (vms->secure && firmware_loaded) {
1742 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
1743 } else if (vms->virt) {
1744 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC;
1745 } else {
1746 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC;
1749 /* The maximum number of CPUs depends on the GIC version, or on how
1750 * many redistributors we can fit into the memory map.
1752 if (vms->gic_version == VIRT_GIC_VERSION_3) {
1753 virt_max_cpus =
1754 vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
1755 virt_max_cpus +=
1756 vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE;
1757 } else {
1758 virt_max_cpus = GIC_NCPU;
1761 if (max_cpus > virt_max_cpus) {
1762 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
1763 "supported by machine 'mach-virt' (%d)",
1764 max_cpus, virt_max_cpus);
1765 exit(1);
1768 vms->smp_cpus = smp_cpus;
1770 if (vms->virt && kvm_enabled()) {
1771 error_report("mach-virt: KVM does not support providing "
1772 "Virtualization extensions to the guest CPU");
1773 exit(1);
1776 if (vms->mte && kvm_enabled()) {
1777 error_report("mach-virt: KVM does not support providing "
1778 "MTE to the guest CPU");
1779 exit(1);
1782 create_fdt(vms);
1784 possible_cpus = mc->possible_cpu_arch_ids(machine);
1785 for (n = 0; n < possible_cpus->len; n++) {
1786 Object *cpuobj;
1787 CPUState *cs;
1789 if (n >= smp_cpus) {
1790 break;
1793 cpuobj = object_new(possible_cpus->cpus[n].type);
1794 object_property_set_int(cpuobj, "mp-affinity",
1795 possible_cpus->cpus[n].arch_id, NULL);
1797 cs = CPU(cpuobj);
1798 cs->cpu_index = n;
1800 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj),
1801 &error_fatal);
1803 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL);
1805 if (!vms->secure) {
1806 object_property_set_bool(cpuobj, "has_el3", false, NULL);
1809 if (!vms->virt && object_property_find(cpuobj, "has_el2")) {
1810 object_property_set_bool(cpuobj, "has_el2", false, NULL);
1813 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) {
1814 object_property_set_int(cpuobj, "psci-conduit", vms->psci_conduit,
1815 NULL);
1817 /* Secondary CPUs start in PSCI powered-down state */
1818 if (n > 0) {
1819 object_property_set_bool(cpuobj, "start-powered-off", true,
1820 NULL);
1824 if (vmc->kvm_no_adjvtime &&
1825 object_property_find(cpuobj, "kvm-no-adjvtime")) {
1826 object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL);
1829 if (vmc->no_pmu && object_property_find(cpuobj, "pmu")) {
1830 object_property_set_bool(cpuobj, "pmu", false, NULL);
1833 if (object_property_find(cpuobj, "reset-cbar")) {
1834 object_property_set_int(cpuobj, "reset-cbar",
1835 vms->memmap[VIRT_CPUPERIPHS].base,
1836 &error_abort);
1839 object_property_set_link(cpuobj, "memory", OBJECT(sysmem),
1840 &error_abort);
1841 if (vms->secure) {
1842 object_property_set_link(cpuobj, "secure-memory",
1843 OBJECT(secure_sysmem), &error_abort);
1846 if (vms->mte) {
1847 /* Create the memory region only once, but link to all cpus. */
1848 if (!tag_sysmem) {
1850 * The property exists only if MemTag is supported.
1851 * If it is, we must allocate the ram to back that up.
1853 if (!object_property_find(cpuobj, "tag-memory")) {
1854 error_report("MTE requested, but not supported "
1855 "by the guest CPU");
1856 exit(1);
1859 tag_sysmem = g_new(MemoryRegion, 1);
1860 memory_region_init(tag_sysmem, OBJECT(machine),
1861 "tag-memory", UINT64_MAX / 32);
1863 if (vms->secure) {
1864 secure_tag_sysmem = g_new(MemoryRegion, 1);
1865 memory_region_init(secure_tag_sysmem, OBJECT(machine),
1866 "secure-tag-memory", UINT64_MAX / 32);
1868 /* As with ram, secure-tag takes precedence over tag. */
1869 memory_region_add_subregion_overlap(secure_tag_sysmem, 0,
1870 tag_sysmem, -1);
1874 object_property_set_link(cpuobj, "tag-memory", OBJECT(tag_sysmem),
1875 &error_abort);
1876 if (vms->secure) {
1877 object_property_set_link(cpuobj, "secure-tag-memory",
1878 OBJECT(secure_tag_sysmem),
1879 &error_abort);
1883 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
1884 object_unref(cpuobj);
1886 fdt_add_timer_nodes(vms);
1887 fdt_add_cpu_nodes(vms);
1889 if (!kvm_enabled()) {
1890 ARMCPU *cpu = ARM_CPU(first_cpu);
1891 bool aarch64 = object_property_get_bool(OBJECT(cpu), "aarch64", NULL);
1893 if (aarch64 && vms->highmem) {
1894 int requested_pa_size, pamax = arm_pamax(cpu);
1896 requested_pa_size = 64 - clz64(vms->highest_gpa);
1897 if (pamax < requested_pa_size) {
1898 error_report("VCPU supports less PA bits (%d) than requested "
1899 "by the memory map (%d)", pamax, requested_pa_size);
1900 exit(1);
1905 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base,
1906 machine->ram);
1907 if (machine->device_memory) {
1908 memory_region_add_subregion(sysmem, machine->device_memory->base,
1909 &machine->device_memory->mr);
1912 virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem);
1914 create_gic(vms);
1916 fdt_add_pmu_nodes(vms);
1918 create_uart(vms, VIRT_UART, sysmem, serial_hd(0));
1920 if (vms->secure) {
1921 create_secure_ram(vms, secure_sysmem, secure_tag_sysmem);
1922 create_uart(vms, VIRT_SECURE_UART, secure_sysmem, serial_hd(1));
1925 if (tag_sysmem) {
1926 create_tag_ram(tag_sysmem, vms->memmap[VIRT_MEM].base,
1927 machine->ram_size, "mach-virt.tag");
1930 vms->highmem_ecam &= vms->highmem && (!firmware_loaded || aarch64);
1932 create_rtc(vms);
1934 create_pcie(vms);
1936 if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) {
1937 vms->acpi_dev = create_acpi_ged(vms);
1938 } else {
1939 create_gpio(vms);
1942 /* connect powerdown request */
1943 vms->powerdown_notifier.notify = virt_powerdown_req;
1944 qemu_register_powerdown_notifier(&vms->powerdown_notifier);
1946 /* Create mmio transports, so the user can create virtio backends
1947 * (which will be automatically plugged in to the transports). If
1948 * no backend is created the transport will just sit harmlessly idle.
1950 create_virtio_devices(vms);
1952 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory);
1953 rom_set_fw(vms->fw_cfg);
1955 create_platform_bus(vms);
1957 if (machine->nvdimms_state->is_enabled) {
1958 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio = {
1959 .space_id = AML_AS_SYSTEM_MEMORY,
1960 .address = vms->memmap[VIRT_NVDIMM_ACPI].base,
1961 .bit_width = NVDIMM_ACPI_IO_LEN << 3
1964 nvdimm_init_acpi_state(machine->nvdimms_state, sysmem,
1965 arm_virt_nvdimm_acpi_dsmio,
1966 vms->fw_cfg, OBJECT(vms));
1969 vms->bootinfo.ram_size = machine->ram_size;
1970 vms->bootinfo.nb_cpus = smp_cpus;
1971 vms->bootinfo.board_id = -1;
1972 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base;
1973 vms->bootinfo.get_dtb = machvirt_dtb;
1974 vms->bootinfo.skip_dtb_autoload = true;
1975 vms->bootinfo.firmware_loaded = firmware_loaded;
1976 arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo);
1978 vms->machine_done.notify = virt_machine_done;
1979 qemu_add_machine_init_done_notifier(&vms->machine_done);
1982 static bool virt_get_secure(Object *obj, Error **errp)
1984 VirtMachineState *vms = VIRT_MACHINE(obj);
1986 return vms->secure;
1989 static void virt_set_secure(Object *obj, bool value, Error **errp)
1991 VirtMachineState *vms = VIRT_MACHINE(obj);
1993 vms->secure = value;
1996 static bool virt_get_virt(Object *obj, Error **errp)
1998 VirtMachineState *vms = VIRT_MACHINE(obj);
2000 return vms->virt;
2003 static void virt_set_virt(Object *obj, bool value, Error **errp)
2005 VirtMachineState *vms = VIRT_MACHINE(obj);
2007 vms->virt = value;
2010 static bool virt_get_highmem(Object *obj, Error **errp)
2012 VirtMachineState *vms = VIRT_MACHINE(obj);
2014 return vms->highmem;
2017 static void virt_set_highmem(Object *obj, bool value, Error **errp)
2019 VirtMachineState *vms = VIRT_MACHINE(obj);
2021 vms->highmem = value;
2024 static bool virt_get_its(Object *obj, Error **errp)
2026 VirtMachineState *vms = VIRT_MACHINE(obj);
2028 return vms->its;
2031 static void virt_set_its(Object *obj, bool value, Error **errp)
2033 VirtMachineState *vms = VIRT_MACHINE(obj);
2035 vms->its = value;
2038 bool virt_is_acpi_enabled(VirtMachineState *vms)
2040 if (vms->acpi == ON_OFF_AUTO_OFF) {
2041 return false;
2043 return true;
2046 static void virt_get_acpi(Object *obj, Visitor *v, const char *name,
2047 void *opaque, Error **errp)
2049 VirtMachineState *vms = VIRT_MACHINE(obj);
2050 OnOffAuto acpi = vms->acpi;
2052 visit_type_OnOffAuto(v, name, &acpi, errp);
2055 static void virt_set_acpi(Object *obj, Visitor *v, const char *name,
2056 void *opaque, Error **errp)
2058 VirtMachineState *vms = VIRT_MACHINE(obj);
2060 visit_type_OnOffAuto(v, name, &vms->acpi, errp);
2063 static bool virt_get_ras(Object *obj, Error **errp)
2065 VirtMachineState *vms = VIRT_MACHINE(obj);
2067 return vms->ras;
2070 static void virt_set_ras(Object *obj, bool value, Error **errp)
2072 VirtMachineState *vms = VIRT_MACHINE(obj);
2074 vms->ras = value;
2077 static bool virt_get_mte(Object *obj, Error **errp)
2079 VirtMachineState *vms = VIRT_MACHINE(obj);
2081 return vms->mte;
2084 static void virt_set_mte(Object *obj, bool value, Error **errp)
2086 VirtMachineState *vms = VIRT_MACHINE(obj);
2088 vms->mte = value;
2091 static char *virt_get_gic_version(Object *obj, Error **errp)
2093 VirtMachineState *vms = VIRT_MACHINE(obj);
2094 const char *val = vms->gic_version == VIRT_GIC_VERSION_3 ? "3" : "2";
2096 return g_strdup(val);
2099 static void virt_set_gic_version(Object *obj, const char *value, Error **errp)
2101 VirtMachineState *vms = VIRT_MACHINE(obj);
2103 if (!strcmp(value, "3")) {
2104 vms->gic_version = VIRT_GIC_VERSION_3;
2105 } else if (!strcmp(value, "2")) {
2106 vms->gic_version = VIRT_GIC_VERSION_2;
2107 } else if (!strcmp(value, "host")) {
2108 vms->gic_version = VIRT_GIC_VERSION_HOST; /* Will probe later */
2109 } else if (!strcmp(value, "max")) {
2110 vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */
2111 } else {
2112 error_setg(errp, "Invalid gic-version value");
2113 error_append_hint(errp, "Valid values are 3, 2, host, max.\n");
2117 static char *virt_get_iommu(Object *obj, Error **errp)
2119 VirtMachineState *vms = VIRT_MACHINE(obj);
2121 switch (vms->iommu) {
2122 case VIRT_IOMMU_NONE:
2123 return g_strdup("none");
2124 case VIRT_IOMMU_SMMUV3:
2125 return g_strdup("smmuv3");
2126 default:
2127 g_assert_not_reached();
2131 static void virt_set_iommu(Object *obj, const char *value, Error **errp)
2133 VirtMachineState *vms = VIRT_MACHINE(obj);
2135 if (!strcmp(value, "smmuv3")) {
2136 vms->iommu = VIRT_IOMMU_SMMUV3;
2137 } else if (!strcmp(value, "none")) {
2138 vms->iommu = VIRT_IOMMU_NONE;
2139 } else {
2140 error_setg(errp, "Invalid iommu value");
2141 error_append_hint(errp, "Valid values are none, smmuv3.\n");
2145 static CpuInstanceProperties
2146 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
2148 MachineClass *mc = MACHINE_GET_CLASS(ms);
2149 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
2151 assert(cpu_index < possible_cpus->len);
2152 return possible_cpus->cpus[cpu_index].props;
2155 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
2157 return idx % ms->numa_state->num_nodes;
2160 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
2162 int n;
2163 unsigned int max_cpus = ms->smp.max_cpus;
2164 VirtMachineState *vms = VIRT_MACHINE(ms);
2166 if (ms->possible_cpus) {
2167 assert(ms->possible_cpus->len == max_cpus);
2168 return ms->possible_cpus;
2171 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
2172 sizeof(CPUArchId) * max_cpus);
2173 ms->possible_cpus->len = max_cpus;
2174 for (n = 0; n < ms->possible_cpus->len; n++) {
2175 ms->possible_cpus->cpus[n].type = ms->cpu_type;
2176 ms->possible_cpus->cpus[n].arch_id =
2177 virt_cpu_mp_affinity(vms, n);
2178 ms->possible_cpus->cpus[n].props.has_thread_id = true;
2179 ms->possible_cpus->cpus[n].props.thread_id = n;
2181 return ms->possible_cpus;
2184 static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2185 Error **errp)
2187 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2188 const MachineState *ms = MACHINE(hotplug_dev);
2189 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
2191 if (!vms->acpi_dev) {
2192 error_setg(errp,
2193 "memory hotplug is not enabled: missing acpi-ged device");
2194 return;
2197 if (vms->mte) {
2198 error_setg(errp, "memory hotplug is not enabled: MTE is enabled");
2199 return;
2202 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
2203 error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'");
2204 return;
2207 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp);
2210 static void virt_memory_plug(HotplugHandler *hotplug_dev,
2211 DeviceState *dev, Error **errp)
2213 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2214 MachineState *ms = MACHINE(hotplug_dev);
2215 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
2216 Error *local_err = NULL;
2218 pc_dimm_plug(PC_DIMM(dev), MACHINE(vms), &local_err);
2219 if (local_err) {
2220 goto out;
2223 if (is_nvdimm) {
2224 nvdimm_plug(ms->nvdimms_state);
2227 hotplug_handler_plug(HOTPLUG_HANDLER(vms->acpi_dev),
2228 dev, &error_abort);
2230 out:
2231 error_propagate(errp, local_err);
2234 static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
2235 DeviceState *dev, Error **errp)
2237 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2239 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2240 virt_memory_pre_plug(hotplug_dev, dev, errp);
2241 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
2242 hwaddr db_start = 0, db_end = 0;
2243 char *resv_prop_str;
2245 switch (vms->msi_controller) {
2246 case VIRT_MSI_CTRL_NONE:
2247 return;
2248 case VIRT_MSI_CTRL_ITS:
2249 /* GITS_TRANSLATER page */
2250 db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000;
2251 db_end = base_memmap[VIRT_GIC_ITS].base +
2252 base_memmap[VIRT_GIC_ITS].size - 1;
2253 break;
2254 case VIRT_MSI_CTRL_GICV2M:
2255 /* MSI_SETSPI_NS page */
2256 db_start = base_memmap[VIRT_GIC_V2M].base;
2257 db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1;
2258 break;
2260 resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u",
2261 db_start, db_end,
2262 VIRTIO_IOMMU_RESV_MEM_T_MSI);
2264 qdev_prop_set_uint32(dev, "len-reserved-regions", 1);
2265 qdev_prop_set_string(dev, "reserved-regions[0]", resv_prop_str);
2266 g_free(resv_prop_str);
2270 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev,
2271 DeviceState *dev, Error **errp)
2273 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2275 if (vms->platform_bus_dev) {
2276 if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE)) {
2277 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev),
2278 SYS_BUS_DEVICE(dev));
2281 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2282 virt_memory_plug(hotplug_dev, dev, errp);
2284 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
2285 PCIDevice *pdev = PCI_DEVICE(dev);
2287 vms->iommu = VIRT_IOMMU_VIRTIO;
2288 vms->virtio_iommu_bdf = pci_get_bdf(pdev);
2289 create_virtio_iommu_dt_bindings(vms);
2293 static void virt_dimm_unplug_request(HotplugHandler *hotplug_dev,
2294 DeviceState *dev, Error **errp)
2296 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2297 Error *local_err = NULL;
2299 if (!vms->acpi_dev) {
2300 error_setg(&local_err,
2301 "memory hotplug is not enabled: missing acpi-ged device");
2302 goto out;
2305 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
2306 error_setg(&local_err,
2307 "nvdimm device hot unplug is not supported yet.");
2308 goto out;
2311 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms->acpi_dev), dev,
2312 &local_err);
2313 out:
2314 error_propagate(errp, local_err);
2317 static void virt_dimm_unplug(HotplugHandler *hotplug_dev,
2318 DeviceState *dev, Error **errp)
2320 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2321 Error *local_err = NULL;
2323 hotplug_handler_unplug(HOTPLUG_HANDLER(vms->acpi_dev), dev, &local_err);
2324 if (local_err) {
2325 goto out;
2328 pc_dimm_unplug(PC_DIMM(dev), MACHINE(vms));
2329 qdev_unrealize(dev);
2331 out:
2332 error_propagate(errp, local_err);
2335 static void virt_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
2336 DeviceState *dev, Error **errp)
2338 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2339 virt_dimm_unplug_request(hotplug_dev, dev, errp);
2340 } else {
2341 error_setg(errp, "device unplug request for unsupported device"
2342 " type: %s", object_get_typename(OBJECT(dev)));
2346 static void virt_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
2347 DeviceState *dev, Error **errp)
2349 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2350 virt_dimm_unplug(hotplug_dev, dev, errp);
2351 } else {
2352 error_setg(errp, "virt: device unplug for unsupported device"
2353 " type: %s", object_get_typename(OBJECT(dev)));
2357 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
2358 DeviceState *dev)
2360 if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE) ||
2361 (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM))) {
2362 return HOTPLUG_HANDLER(machine);
2364 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
2365 VirtMachineState *vms = VIRT_MACHINE(machine);
2367 if (!vms->bootinfo.firmware_loaded || !virt_is_acpi_enabled(vms)) {
2368 return HOTPLUG_HANDLER(machine);
2371 return NULL;
2375 * for arm64 kvm_type [7-0] encodes the requested number of bits
2376 * in the IPA address space
2378 static int virt_kvm_type(MachineState *ms, const char *type_str)
2380 VirtMachineState *vms = VIRT_MACHINE(ms);
2381 int max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms);
2382 int requested_pa_size;
2384 /* we freeze the memory map to compute the highest gpa */
2385 virt_set_memmap(vms);
2387 requested_pa_size = 64 - clz64(vms->highest_gpa);
2389 if (requested_pa_size > max_vm_pa_size) {
2390 error_report("-m and ,maxmem option values "
2391 "require an IPA range (%d bits) larger than "
2392 "the one supported by the host (%d bits)",
2393 requested_pa_size, max_vm_pa_size);
2394 exit(1);
2397 * By default we return 0 which corresponds to an implicit legacy
2398 * 40b IPA setting. Otherwise we return the actual requested PA
2399 * logsize
2401 return requested_pa_size > 40 ? requested_pa_size : 0;
2404 static void virt_machine_class_init(ObjectClass *oc, void *data)
2406 MachineClass *mc = MACHINE_CLASS(oc);
2407 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
2409 mc->init = machvirt_init;
2410 /* Start with max_cpus set to 512, which is the maximum supported by KVM.
2411 * The value may be reduced later when we have more information about the
2412 * configuration of the particular instance.
2414 mc->max_cpus = 512;
2415 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC);
2416 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE);
2417 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
2418 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM);
2419 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS);
2420 mc->block_default_type = IF_VIRTIO;
2421 mc->no_cdrom = 1;
2422 mc->pci_allow_0_address = true;
2423 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */
2424 mc->minimum_page_bits = 12;
2425 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
2426 mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
2427 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
2428 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
2429 mc->kvm_type = virt_kvm_type;
2430 assert(!mc->get_hotplug_handler);
2431 mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
2432 hc->pre_plug = virt_machine_device_pre_plug_cb;
2433 hc->plug = virt_machine_device_plug_cb;
2434 hc->unplug_request = virt_machine_device_unplug_request_cb;
2435 hc->unplug = virt_machine_device_unplug_cb;
2436 mc->nvdimm_supported = true;
2437 mc->auto_enable_numa_with_memhp = true;
2438 mc->auto_enable_numa_with_memdev = true;
2439 mc->default_ram_id = "mach-virt.ram";
2441 object_class_property_add(oc, "acpi", "OnOffAuto",
2442 virt_get_acpi, virt_set_acpi,
2443 NULL, NULL);
2444 object_class_property_set_description(oc, "acpi",
2445 "Enable ACPI");
2448 static void virt_instance_init(Object *obj)
2450 VirtMachineState *vms = VIRT_MACHINE(obj);
2451 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
2453 /* EL3 is disabled by default on virt: this makes us consistent
2454 * between KVM and TCG for this board, and it also allows us to
2455 * boot UEFI blobs which assume no TrustZone support.
2457 vms->secure = false;
2458 object_property_add_bool(obj, "secure", virt_get_secure,
2459 virt_set_secure);
2460 object_property_set_description(obj, "secure",
2461 "Set on/off to enable/disable the ARM "
2462 "Security Extensions (TrustZone)");
2464 /* EL2 is also disabled by default, for similar reasons */
2465 vms->virt = false;
2466 object_property_add_bool(obj, "virtualization", virt_get_virt,
2467 virt_set_virt);
2468 object_property_set_description(obj, "virtualization",
2469 "Set on/off to enable/disable emulating a "
2470 "guest CPU which implements the ARM "
2471 "Virtualization Extensions");
2473 /* High memory is enabled by default */
2474 vms->highmem = true;
2475 object_property_add_bool(obj, "highmem", virt_get_highmem,
2476 virt_set_highmem);
2477 object_property_set_description(obj, "highmem",
2478 "Set on/off to enable/disable using "
2479 "physical address space above 32 bits");
2480 vms->gic_version = VIRT_GIC_VERSION_NOSEL;
2481 object_property_add_str(obj, "gic-version", virt_get_gic_version,
2482 virt_set_gic_version);
2483 object_property_set_description(obj, "gic-version",
2484 "Set GIC version. "
2485 "Valid values are 2, 3, host and max");
2487 vms->highmem_ecam = !vmc->no_highmem_ecam;
2489 if (vmc->no_its) {
2490 vms->its = false;
2491 } else {
2492 /* Default allows ITS instantiation */
2493 vms->its = true;
2494 object_property_add_bool(obj, "its", virt_get_its,
2495 virt_set_its);
2496 object_property_set_description(obj, "its",
2497 "Set on/off to enable/disable "
2498 "ITS instantiation");
2501 /* Default disallows iommu instantiation */
2502 vms->iommu = VIRT_IOMMU_NONE;
2503 object_property_add_str(obj, "iommu", virt_get_iommu, virt_set_iommu);
2504 object_property_set_description(obj, "iommu",
2505 "Set the IOMMU type. "
2506 "Valid values are none and smmuv3");
2508 /* Default disallows RAS instantiation */
2509 vms->ras = false;
2510 object_property_add_bool(obj, "ras", virt_get_ras,
2511 virt_set_ras);
2512 object_property_set_description(obj, "ras",
2513 "Set on/off to enable/disable reporting host memory errors "
2514 "to a KVM guest using ACPI and guest external abort exceptions");
2516 /* MTE is disabled by default. */
2517 vms->mte = false;
2518 object_property_add_bool(obj, "mte", virt_get_mte, virt_set_mte);
2519 object_property_set_description(obj, "mte",
2520 "Set on/off to enable/disable emulating a "
2521 "guest CPU which implements the ARM "
2522 "Memory Tagging Extension");
2524 vms->irqmap = a15irqmap;
2526 virt_flash_create(vms);
2529 static const TypeInfo virt_machine_info = {
2530 .name = TYPE_VIRT_MACHINE,
2531 .parent = TYPE_MACHINE,
2532 .abstract = true,
2533 .instance_size = sizeof(VirtMachineState),
2534 .class_size = sizeof(VirtMachineClass),
2535 .class_init = virt_machine_class_init,
2536 .instance_init = virt_instance_init,
2537 .interfaces = (InterfaceInfo[]) {
2538 { TYPE_HOTPLUG_HANDLER },
2543 static void machvirt_machine_init(void)
2545 type_register_static(&virt_machine_info);
2547 type_init(machvirt_machine_init);
2549 static void virt_machine_5_2_options(MachineClass *mc)
2552 DEFINE_VIRT_MACHINE_AS_LATEST(5, 2)
2554 static void virt_machine_5_1_options(MachineClass *mc)
2556 virt_machine_5_2_options(mc);
2557 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len);
2559 DEFINE_VIRT_MACHINE(5, 1)
2561 static void virt_machine_5_0_options(MachineClass *mc)
2563 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2565 virt_machine_5_1_options(mc);
2566 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len);
2567 mc->numa_mem_supported = true;
2568 vmc->acpi_expose_flash = true;
2569 mc->auto_enable_numa_with_memdev = false;
2571 DEFINE_VIRT_MACHINE(5, 0)
2573 static void virt_machine_4_2_options(MachineClass *mc)
2575 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2577 virt_machine_5_0_options(mc);
2578 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len);
2579 vmc->kvm_no_adjvtime = true;
2581 DEFINE_VIRT_MACHINE(4, 2)
2583 static void virt_machine_4_1_options(MachineClass *mc)
2585 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2587 virt_machine_4_2_options(mc);
2588 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len);
2589 vmc->no_ged = true;
2590 mc->auto_enable_numa_with_memhp = false;
2592 DEFINE_VIRT_MACHINE(4, 1)
2594 static void virt_machine_4_0_options(MachineClass *mc)
2596 virt_machine_4_1_options(mc);
2597 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len);
2599 DEFINE_VIRT_MACHINE(4, 0)
2601 static void virt_machine_3_1_options(MachineClass *mc)
2603 virt_machine_4_0_options(mc);
2604 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len);
2606 DEFINE_VIRT_MACHINE(3, 1)
2608 static void virt_machine_3_0_options(MachineClass *mc)
2610 virt_machine_3_1_options(mc);
2611 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len);
2613 DEFINE_VIRT_MACHINE(3, 0)
2615 static void virt_machine_2_12_options(MachineClass *mc)
2617 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2619 virt_machine_3_0_options(mc);
2620 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len);
2621 vmc->no_highmem_ecam = true;
2622 mc->max_cpus = 255;
2624 DEFINE_VIRT_MACHINE(2, 12)
2626 static void virt_machine_2_11_options(MachineClass *mc)
2628 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2630 virt_machine_2_12_options(mc);
2631 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len);
2632 vmc->smbios_old_sys_ver = true;
2634 DEFINE_VIRT_MACHINE(2, 11)
2636 static void virt_machine_2_10_options(MachineClass *mc)
2638 virt_machine_2_11_options(mc);
2639 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len);
2640 /* before 2.11 we never faulted accesses to bad addresses */
2641 mc->ignore_memory_transaction_failures = true;
2643 DEFINE_VIRT_MACHINE(2, 10)
2645 static void virt_machine_2_9_options(MachineClass *mc)
2647 virt_machine_2_10_options(mc);
2648 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len);
2650 DEFINE_VIRT_MACHINE(2, 9)
2652 static void virt_machine_2_8_options(MachineClass *mc)
2654 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2656 virt_machine_2_9_options(mc);
2657 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len);
2658 /* For 2.8 and earlier we falsely claimed in the DT that
2659 * our timers were edge-triggered, not level-triggered.
2661 vmc->claim_edge_triggered_timers = true;
2663 DEFINE_VIRT_MACHINE(2, 8)
2665 static void virt_machine_2_7_options(MachineClass *mc)
2667 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2669 virt_machine_2_8_options(mc);
2670 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len);
2671 /* ITS was introduced with 2.8 */
2672 vmc->no_its = true;
2673 /* Stick with 1K pages for migration compatibility */
2674 mc->minimum_page_bits = 0;
2676 DEFINE_VIRT_MACHINE(2, 7)
2678 static void virt_machine_2_6_options(MachineClass *mc)
2680 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2682 virt_machine_2_7_options(mc);
2683 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len);
2684 vmc->disallow_affinity_adjustment = true;
2685 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */
2686 vmc->no_pmu = true;
2688 DEFINE_VIRT_MACHINE(2, 6)