2 * ARM mach-virt emulation
4 * Copyright (c) 2013 Linaro Limited
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
18 * Emulate a virtual board which works by passing Linux all the information
19 * it needs about what devices are present via the device tree.
20 * There are some restrictions about what we can do here:
21 * + we can only present devices whose Linux drivers will work based
22 * purely on the device tree with no platform data at all
23 * + we want to present a very stripped-down minimalist platform,
24 * both because this reduces the security attack surface from the guest
25 * and also because it reduces our exposure to being broken when
26 * the kernel updates its device tree bindings and requires further
27 * information in a device binding that we aren't providing.
28 * This is essentially the same approach kvmtool uses.
31 #include "hw/sysbus.h"
32 #include "hw/arm/arm.h"
33 #include "hw/arm/primecell.h"
34 #include "hw/arm/virt.h"
35 #include "hw/devices.h"
37 #include "sysemu/block-backend.h"
38 #include "sysemu/device_tree.h"
39 #include "sysemu/sysemu.h"
40 #include "sysemu/kvm.h"
41 #include "hw/boards.h"
42 #include "hw/loader.h"
43 #include "exec/address-spaces.h"
44 #include "qemu/bitops.h"
45 #include "qemu/error-report.h"
46 #include "hw/pci-host/gpex.h"
48 /* Number of external interrupt lines to configure the GIC with */
51 #define GIC_FDT_IRQ_TYPE_SPI 0
52 #define GIC_FDT_IRQ_TYPE_PPI 1
54 #define GIC_FDT_IRQ_FLAGS_EDGE_LO_HI 1
55 #define GIC_FDT_IRQ_FLAGS_EDGE_HI_LO 2
56 #define GIC_FDT_IRQ_FLAGS_LEVEL_HI 4
57 #define GIC_FDT_IRQ_FLAGS_LEVEL_LO 8
59 #define GIC_FDT_IRQ_PPI_CPU_START 8
60 #define GIC_FDT_IRQ_PPI_CPU_WIDTH 8
62 typedef struct VirtBoardInfo
{
63 struct arm_boot_info bootinfo
;
64 const char *cpu_model
;
65 const MemMapEntry
*memmap
;
70 uint32_t clock_phandle
;
75 VirtBoardInfo
*daughterboard
;
83 #define TYPE_VIRT_MACHINE "virt"
84 #define VIRT_MACHINE(obj) \
85 OBJECT_CHECK(VirtMachineState, (obj), TYPE_VIRT_MACHINE)
86 #define VIRT_MACHINE_GET_CLASS(obj) \
87 OBJECT_GET_CLASS(VirtMachineClass, obj, TYPE_VIRT_MACHINE)
88 #define VIRT_MACHINE_CLASS(klass) \
89 OBJECT_CLASS_CHECK(VirtMachineClass, klass, TYPE_VIRT_MACHINE)
91 /* Addresses and sizes of our components.
92 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
93 * 128MB..256MB is used for miscellaneous device I/O.
94 * 256MB..1GB is reserved for possible future PCI support (ie where the
95 * PCI memory window will go if we add a PCI host controller).
96 * 1GB and up is RAM (which may happily spill over into the
97 * high memory region beyond 4GB).
98 * This represents a compromise between how much RAM can be given to
99 * a 32 bit VM and leaving space for expansion and in particular for PCI.
100 * Note that devices should generally be placed at multiples of 0x10000,
101 * to accommodate guests using 64K pages.
103 static const MemMapEntry a15memmap
[] = {
104 /* Space up to 0x8000000 is reserved for a boot ROM */
105 [VIRT_FLASH
] = { 0, 0x08000000 },
106 [VIRT_CPUPERIPHS
] = { 0x08000000, 0x00020000 },
107 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
108 [VIRT_GIC_DIST
] = { 0x08000000, 0x00010000 },
109 [VIRT_GIC_CPU
] = { 0x08010000, 0x00010000 },
110 [VIRT_UART
] = { 0x09000000, 0x00001000 },
111 [VIRT_RTC
] = { 0x09010000, 0x00001000 },
112 [VIRT_FW_CFG
] = { 0x09020000, 0x0000000a },
113 [VIRT_MMIO
] = { 0x0a000000, 0x00000200 },
114 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
118 * MMIO window { 0x10000000, 0x2eff0000 },
119 * PIO window { 0x3eff0000, 0x00010000 },
120 * ECAM { 0x3f000000, 0x01000000 },
122 [VIRT_PCIE
] = { 0x10000000, 0x30000000 },
123 [VIRT_MEM
] = { 0x40000000, 30ULL * 1024 * 1024 * 1024 },
126 static const int a15irqmap
[] = {
129 [VIRT_PCIE
] = 3, /* ... to 6 */
130 [VIRT_MMIO
] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
133 static VirtBoardInfo machines
[] = {
135 .cpu_model
= "cortex-a15",
140 .cpu_model
= "cortex-a57",
151 static VirtBoardInfo
*find_machine_info(const char *cpu
)
155 for (i
= 0; i
< ARRAY_SIZE(machines
); i
++) {
156 if (strcmp(cpu
, machines
[i
].cpu_model
) == 0) {
163 static void create_fdt(VirtBoardInfo
*vbi
)
165 void *fdt
= create_device_tree(&vbi
->fdt_size
);
168 error_report("create_device_tree() failed");
175 qemu_fdt_setprop_string(fdt
, "/", "compatible", "linux,dummy-virt");
176 qemu_fdt_setprop_cell(fdt
, "/", "#address-cells", 0x2);
177 qemu_fdt_setprop_cell(fdt
, "/", "#size-cells", 0x2);
180 * /chosen and /memory nodes must exist for load_dtb
181 * to fill in necessary properties later
183 qemu_fdt_add_subnode(fdt
, "/chosen");
184 qemu_fdt_add_subnode(fdt
, "/memory");
185 qemu_fdt_setprop_string(fdt
, "/memory", "device_type", "memory");
187 /* Clock node, for the benefit of the UART. The kernel device tree
188 * binding documentation claims the PL011 node clock properties are
189 * optional but in practice if you omit them the kernel refuses to
190 * probe for the device.
192 vbi
->clock_phandle
= qemu_fdt_alloc_phandle(fdt
);
193 qemu_fdt_add_subnode(fdt
, "/apb-pclk");
194 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "compatible", "fixed-clock");
195 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "#clock-cells", 0x0);
196 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "clock-frequency", 24000000);
197 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "clock-output-names",
199 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "phandle", vbi
->clock_phandle
);
203 static void fdt_add_psci_node(const VirtBoardInfo
*vbi
)
205 uint32_t cpu_suspend_fn
;
209 void *fdt
= vbi
->fdt
;
210 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(0));
212 qemu_fdt_add_subnode(fdt
, "/psci");
213 if (armcpu
->psci_version
== 2) {
214 const char comp
[] = "arm,psci-0.2\0arm,psci";
215 qemu_fdt_setprop(fdt
, "/psci", "compatible", comp
, sizeof(comp
));
217 cpu_off_fn
= QEMU_PSCI_0_2_FN_CPU_OFF
;
218 if (arm_feature(&armcpu
->env
, ARM_FEATURE_AARCH64
)) {
219 cpu_suspend_fn
= QEMU_PSCI_0_2_FN64_CPU_SUSPEND
;
220 cpu_on_fn
= QEMU_PSCI_0_2_FN64_CPU_ON
;
221 migrate_fn
= QEMU_PSCI_0_2_FN64_MIGRATE
;
223 cpu_suspend_fn
= QEMU_PSCI_0_2_FN_CPU_SUSPEND
;
224 cpu_on_fn
= QEMU_PSCI_0_2_FN_CPU_ON
;
225 migrate_fn
= QEMU_PSCI_0_2_FN_MIGRATE
;
228 qemu_fdt_setprop_string(fdt
, "/psci", "compatible", "arm,psci");
230 cpu_suspend_fn
= QEMU_PSCI_0_1_FN_CPU_SUSPEND
;
231 cpu_off_fn
= QEMU_PSCI_0_1_FN_CPU_OFF
;
232 cpu_on_fn
= QEMU_PSCI_0_1_FN_CPU_ON
;
233 migrate_fn
= QEMU_PSCI_0_1_FN_MIGRATE
;
236 /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer
237 * to the instruction that should be used to invoke PSCI functions.
238 * However, the device tree binding uses 'method' instead, so that is
239 * what we should use here.
241 qemu_fdt_setprop_string(fdt
, "/psci", "method", "hvc");
243 qemu_fdt_setprop_cell(fdt
, "/psci", "cpu_suspend", cpu_suspend_fn
);
244 qemu_fdt_setprop_cell(fdt
, "/psci", "cpu_off", cpu_off_fn
);
245 qemu_fdt_setprop_cell(fdt
, "/psci", "cpu_on", cpu_on_fn
);
246 qemu_fdt_setprop_cell(fdt
, "/psci", "migrate", migrate_fn
);
249 static void fdt_add_timer_nodes(const VirtBoardInfo
*vbi
)
251 /* Note that on A15 h/w these interrupts are level-triggered,
252 * but for the GIC implementation provided by both QEMU and KVM
253 * they are edge-triggered.
256 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
;
258 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
259 GIC_FDT_IRQ_PPI_CPU_WIDTH
, (1 << vbi
->smp_cpus
) - 1);
261 qemu_fdt_add_subnode(vbi
->fdt
, "/timer");
263 armcpu
= ARM_CPU(qemu_get_cpu(0));
264 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
265 const char compat
[] = "arm,armv8-timer\0arm,armv7-timer";
266 qemu_fdt_setprop(vbi
->fdt
, "/timer", "compatible",
267 compat
, sizeof(compat
));
269 qemu_fdt_setprop_string(vbi
->fdt
, "/timer", "compatible",
272 qemu_fdt_setprop_cells(vbi
->fdt
, "/timer", "interrupts",
273 GIC_FDT_IRQ_TYPE_PPI
, 13, irqflags
,
274 GIC_FDT_IRQ_TYPE_PPI
, 14, irqflags
,
275 GIC_FDT_IRQ_TYPE_PPI
, 11, irqflags
,
276 GIC_FDT_IRQ_TYPE_PPI
, 10, irqflags
);
279 static void fdt_add_cpu_nodes(const VirtBoardInfo
*vbi
)
283 qemu_fdt_add_subnode(vbi
->fdt
, "/cpus");
284 qemu_fdt_setprop_cell(vbi
->fdt
, "/cpus", "#address-cells", 0x1);
285 qemu_fdt_setprop_cell(vbi
->fdt
, "/cpus", "#size-cells", 0x0);
287 for (cpu
= vbi
->smp_cpus
- 1; cpu
>= 0; cpu
--) {
288 char *nodename
= g_strdup_printf("/cpus/cpu@%d", cpu
);
289 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
291 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
292 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "device_type", "cpu");
293 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "compatible",
294 armcpu
->dtb_compatible
);
296 if (vbi
->smp_cpus
> 1) {
297 qemu_fdt_setprop_string(vbi
->fdt
, nodename
,
298 "enable-method", "psci");
301 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "reg", cpu
);
306 static uint32_t fdt_add_gic_node(const VirtBoardInfo
*vbi
)
308 uint32_t gic_phandle
;
310 gic_phandle
= qemu_fdt_alloc_phandle(vbi
->fdt
);
311 qemu_fdt_setprop_cell(vbi
->fdt
, "/", "interrupt-parent", gic_phandle
);
313 qemu_fdt_add_subnode(vbi
->fdt
, "/intc");
314 /* 'cortex-a15-gic' means 'GIC v2' */
315 qemu_fdt_setprop_string(vbi
->fdt
, "/intc", "compatible",
316 "arm,cortex-a15-gic");
317 qemu_fdt_setprop_cell(vbi
->fdt
, "/intc", "#interrupt-cells", 3);
318 qemu_fdt_setprop(vbi
->fdt
, "/intc", "interrupt-controller", NULL
, 0);
319 qemu_fdt_setprop_sized_cells(vbi
->fdt
, "/intc", "reg",
320 2, vbi
->memmap
[VIRT_GIC_DIST
].base
,
321 2, vbi
->memmap
[VIRT_GIC_DIST
].size
,
322 2, vbi
->memmap
[VIRT_GIC_CPU
].base
,
323 2, vbi
->memmap
[VIRT_GIC_CPU
].size
);
324 qemu_fdt_setprop_cell(vbi
->fdt
, "/intc", "phandle", gic_phandle
);
329 static uint32_t create_gic(const VirtBoardInfo
*vbi
, qemu_irq
*pic
)
331 /* We create a standalone GIC v2 */
333 SysBusDevice
*gicbusdev
;
334 const char *gictype
= "arm_gic";
337 if (kvm_irqchip_in_kernel()) {
338 gictype
= "kvm-arm-gic";
341 gicdev
= qdev_create(NULL
, gictype
);
342 qdev_prop_set_uint32(gicdev
, "revision", 2);
343 qdev_prop_set_uint32(gicdev
, "num-cpu", smp_cpus
);
344 /* Note that the num-irq property counts both internal and external
345 * interrupts; there are always 32 of the former (mandated by GIC spec).
347 qdev_prop_set_uint32(gicdev
, "num-irq", NUM_IRQS
+ 32);
348 qdev_init_nofail(gicdev
);
349 gicbusdev
= SYS_BUS_DEVICE(gicdev
);
350 sysbus_mmio_map(gicbusdev
, 0, vbi
->memmap
[VIRT_GIC_DIST
].base
);
351 sysbus_mmio_map(gicbusdev
, 1, vbi
->memmap
[VIRT_GIC_CPU
].base
);
353 /* Wire the outputs from each CPU's generic timer to the
354 * appropriate GIC PPI inputs, and the GIC's IRQ output to
355 * the CPU's IRQ input.
357 for (i
= 0; i
< smp_cpus
; i
++) {
358 DeviceState
*cpudev
= DEVICE(qemu_get_cpu(i
));
359 int ppibase
= NUM_IRQS
+ i
* 32;
360 /* physical timer; we wire it up to the non-secure timer's ID,
361 * since a real A15 always has TrustZone but QEMU doesn't.
363 qdev_connect_gpio_out(cpudev
, 0,
364 qdev_get_gpio_in(gicdev
, ppibase
+ 30));
366 qdev_connect_gpio_out(cpudev
, 1,
367 qdev_get_gpio_in(gicdev
, ppibase
+ 27));
369 sysbus_connect_irq(gicbusdev
, i
, qdev_get_gpio_in(cpudev
, ARM_CPU_IRQ
));
370 sysbus_connect_irq(gicbusdev
, i
+ smp_cpus
,
371 qdev_get_gpio_in(cpudev
, ARM_CPU_FIQ
));
374 for (i
= 0; i
< NUM_IRQS
; i
++) {
375 pic
[i
] = qdev_get_gpio_in(gicdev
, i
);
378 return fdt_add_gic_node(vbi
);
381 static void create_uart(const VirtBoardInfo
*vbi
, qemu_irq
*pic
)
384 hwaddr base
= vbi
->memmap
[VIRT_UART
].base
;
385 hwaddr size
= vbi
->memmap
[VIRT_UART
].size
;
386 int irq
= vbi
->irqmap
[VIRT_UART
];
387 const char compat
[] = "arm,pl011\0arm,primecell";
388 const char clocknames
[] = "uartclk\0apb_pclk";
390 sysbus_create_simple("pl011", base
, pic
[irq
]);
392 nodename
= g_strdup_printf("/pl011@%" PRIx64
, base
);
393 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
394 /* Note that we can't use setprop_string because of the embedded NUL */
395 qemu_fdt_setprop(vbi
->fdt
, nodename
, "compatible",
396 compat
, sizeof(compat
));
397 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
399 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "interrupts",
400 GIC_FDT_IRQ_TYPE_SPI
, irq
,
401 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
402 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "clocks",
403 vbi
->clock_phandle
, vbi
->clock_phandle
);
404 qemu_fdt_setprop(vbi
->fdt
, nodename
, "clock-names",
405 clocknames
, sizeof(clocknames
));
407 qemu_fdt_setprop_string(vbi
->fdt
, "/chosen", "stdout-path", nodename
);
411 static void create_rtc(const VirtBoardInfo
*vbi
, qemu_irq
*pic
)
414 hwaddr base
= vbi
->memmap
[VIRT_RTC
].base
;
415 hwaddr size
= vbi
->memmap
[VIRT_RTC
].size
;
416 int irq
= vbi
->irqmap
[VIRT_RTC
];
417 const char compat
[] = "arm,pl031\0arm,primecell";
419 sysbus_create_simple("pl031", base
, pic
[irq
]);
421 nodename
= g_strdup_printf("/pl031@%" PRIx64
, base
);
422 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
423 qemu_fdt_setprop(vbi
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
424 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
426 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "interrupts",
427 GIC_FDT_IRQ_TYPE_SPI
, irq
,
428 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
429 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "clocks", vbi
->clock_phandle
);
430 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "clock-names", "apb_pclk");
434 static void create_virtio_devices(const VirtBoardInfo
*vbi
, qemu_irq
*pic
)
437 hwaddr size
= vbi
->memmap
[VIRT_MMIO
].size
;
439 /* We create the transports in forwards order. Since qbus_realize()
440 * prepends (not appends) new child buses, the incrementing loop below will
441 * create a list of virtio-mmio buses with decreasing base addresses.
443 * When a -device option is processed from the command line,
444 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
445 * order. The upshot is that -device options in increasing command line
446 * order are mapped to virtio-mmio buses with decreasing base addresses.
448 * When this code was originally written, that arrangement ensured that the
449 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
450 * the first -device on the command line. (The end-to-end order is a
451 * function of this loop, qbus_realize(), qbus_find_recursive(), and the
452 * guest kernel's name-to-address assignment strategy.)
454 * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
455 * the message, if not necessarily the code, of commit 70161ff336.
456 * Therefore the loop now establishes the inverse of the original intent.
458 * Unfortunately, we can't counteract the kernel change by reversing the
459 * loop; it would break existing command lines.
461 * In any case, the kernel makes no guarantee about the stability of
462 * enumeration order of virtio devices (as demonstrated by it changing
463 * between kernel versions). For reliable and stable identification
464 * of disks users must use UUIDs or similar mechanisms.
466 for (i
= 0; i
< NUM_VIRTIO_TRANSPORTS
; i
++) {
467 int irq
= vbi
->irqmap
[VIRT_MMIO
] + i
;
468 hwaddr base
= vbi
->memmap
[VIRT_MMIO
].base
+ i
* size
;
470 sysbus_create_simple("virtio-mmio", base
, pic
[irq
]);
473 /* We add dtb nodes in reverse order so that they appear in the finished
474 * device tree lowest address first.
476 * Note that this mapping is independent of the loop above. The previous
477 * loop influences virtio device to virtio transport assignment, whereas
478 * this loop controls how virtio transports are laid out in the dtb.
480 for (i
= NUM_VIRTIO_TRANSPORTS
- 1; i
>= 0; i
--) {
482 int irq
= vbi
->irqmap
[VIRT_MMIO
] + i
;
483 hwaddr base
= vbi
->memmap
[VIRT_MMIO
].base
+ i
* size
;
485 nodename
= g_strdup_printf("/virtio_mmio@%" PRIx64
, base
);
486 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
487 qemu_fdt_setprop_string(vbi
->fdt
, nodename
,
488 "compatible", "virtio,mmio");
489 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
491 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "interrupts",
492 GIC_FDT_IRQ_TYPE_SPI
, irq
,
493 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
498 static void create_one_flash(const char *name
, hwaddr flashbase
,
501 /* Create and map a single flash device. We use the same
502 * parameters as the flash devices on the Versatile Express board.
504 DriveInfo
*dinfo
= drive_get_next(IF_PFLASH
);
505 DeviceState
*dev
= qdev_create(NULL
, "cfi.pflash01");
506 const uint64_t sectorlength
= 256 * 1024;
509 qdev_prop_set_drive(dev
, "drive", blk_by_legacy_dinfo(dinfo
),
513 qdev_prop_set_uint32(dev
, "num-blocks", flashsize
/ sectorlength
);
514 qdev_prop_set_uint64(dev
, "sector-length", sectorlength
);
515 qdev_prop_set_uint8(dev
, "width", 4);
516 qdev_prop_set_uint8(dev
, "device-width", 2);
517 qdev_prop_set_uint8(dev
, "big-endian", 0);
518 qdev_prop_set_uint16(dev
, "id0", 0x89);
519 qdev_prop_set_uint16(dev
, "id1", 0x18);
520 qdev_prop_set_uint16(dev
, "id2", 0x00);
521 qdev_prop_set_uint16(dev
, "id3", 0x00);
522 qdev_prop_set_string(dev
, "name", name
);
523 qdev_init_nofail(dev
);
525 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, flashbase
);
528 static void create_flash(const VirtBoardInfo
*vbi
)
530 /* Create two flash devices to fill the VIRT_FLASH space in the memmap.
531 * Any file passed via -bios goes in the first of these.
533 hwaddr flashsize
= vbi
->memmap
[VIRT_FLASH
].size
/ 2;
534 hwaddr flashbase
= vbi
->memmap
[VIRT_FLASH
].base
;
541 if (drive_get(IF_PFLASH
, 0, 0)) {
542 error_report("The contents of the first flash device may be "
543 "specified with -bios or with -drive if=pflash... "
544 "but you cannot use both options at once");
547 fn
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
549 error_report("Could not find ROM image '%s'", bios_name
);
552 image_size
= load_image_targphys(fn
, flashbase
, flashsize
);
554 if (image_size
< 0) {
555 error_report("Could not load ROM image '%s'", bios_name
);
560 create_one_flash("virt.flash0", flashbase
, flashsize
);
561 create_one_flash("virt.flash1", flashbase
+ flashsize
, flashsize
);
563 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
564 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
565 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "compatible", "cfi-flash");
566 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
567 2, flashbase
, 2, flashsize
,
568 2, flashbase
+ flashsize
, 2, flashsize
);
569 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "bank-width", 4);
573 static void create_fw_cfg(const VirtBoardInfo
*vbi
)
575 hwaddr base
= vbi
->memmap
[VIRT_FW_CFG
].base
;
576 hwaddr size
= vbi
->memmap
[VIRT_FW_CFG
].size
;
579 fw_cfg_init_mem_wide(base
+ 8, base
, 8);
581 nodename
= g_strdup_printf("/fw-cfg@%" PRIx64
, base
);
582 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
583 qemu_fdt_setprop_string(vbi
->fdt
, nodename
,
584 "compatible", "qemu,fw-cfg-mmio");
585 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
590 static void create_pcie_irq_map(const VirtBoardInfo
*vbi
, uint32_t gic_phandle
,
591 int first_irq
, const char *nodename
)
594 uint32_t full_irq_map
[4 * 4 * 8] = { 0 };
595 uint32_t *irq_map
= full_irq_map
;
597 for (devfn
= 0; devfn
<= 0x18; devfn
+= 0x8) {
598 for (pin
= 0; pin
< 4; pin
++) {
599 int irq_type
= GIC_FDT_IRQ_TYPE_SPI
;
600 int irq_nr
= first_irq
+ ((pin
+ PCI_SLOT(devfn
)) % PCI_NUM_PINS
);
601 int irq_level
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
605 devfn
<< 8, 0, 0, /* devfn */
606 pin
+ 1, /* PCI pin */
607 gic_phandle
, irq_type
, irq_nr
, irq_level
}; /* GIC irq */
609 /* Convert map to big endian */
610 for (i
= 0; i
< 8; i
++) {
611 irq_map
[i
] = cpu_to_be32(map
[i
]);
617 qemu_fdt_setprop(vbi
->fdt
, nodename
, "interrupt-map",
618 full_irq_map
, sizeof(full_irq_map
));
620 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "interrupt-map-mask",
621 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */
625 static void create_pcie(const VirtBoardInfo
*vbi
, qemu_irq
*pic
,
626 uint32_t gic_phandle
)
628 hwaddr base
= vbi
->memmap
[VIRT_PCIE
].base
;
629 hwaddr size
= vbi
->memmap
[VIRT_PCIE
].size
;
630 hwaddr end
= base
+ size
;
632 hwaddr size_ioport
= 64 * 1024;
633 int nr_pcie_buses
= 16;
634 hwaddr size_ecam
= PCIE_MMCFG_SIZE_MIN
* nr_pcie_buses
;
635 hwaddr base_mmio
= base
;
638 int irq
= vbi
->irqmap
[VIRT_PCIE
];
639 MemoryRegion
*mmio_alias
;
640 MemoryRegion
*mmio_reg
;
641 MemoryRegion
*ecam_alias
;
642 MemoryRegion
*ecam_reg
;
647 base_ecam
= QEMU_ALIGN_DOWN(end
- size_ecam
, size_ecam
);
648 base_ioport
= QEMU_ALIGN_DOWN(base_ecam
- size_ioport
, size_ioport
);
649 size_mmio
= base_ioport
- base
;
651 dev
= qdev_create(NULL
, TYPE_GPEX_HOST
);
652 qdev_init_nofail(dev
);
654 /* Map only the first size_ecam bytes of ECAM space */
655 ecam_alias
= g_new0(MemoryRegion
, 1);
656 ecam_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0);
657 memory_region_init_alias(ecam_alias
, OBJECT(dev
), "pcie-ecam",
658 ecam_reg
, 0, size_ecam
);
659 memory_region_add_subregion(get_system_memory(), base_ecam
, ecam_alias
);
661 /* Map the MMIO window into system address space so as to expose
662 * the section of PCI MMIO space which starts at the same base address
663 * (ie 1:1 mapping for that part of PCI MMIO space visible through
666 mmio_alias
= g_new0(MemoryRegion
, 1);
667 mmio_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 1);
668 memory_region_init_alias(mmio_alias
, OBJECT(dev
), "pcie-mmio",
669 mmio_reg
, base_mmio
, size_mmio
);
670 memory_region_add_subregion(get_system_memory(), base_mmio
, mmio_alias
);
672 /* Map IO port space */
673 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 2, base_ioport
);
675 for (i
= 0; i
< GPEX_NUM_IRQS
; i
++) {
676 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
, pic
[irq
+ i
]);
679 nodename
= g_strdup_printf("/pcie@%" PRIx64
, base
);
680 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
681 qemu_fdt_setprop_string(vbi
->fdt
, nodename
,
682 "compatible", "pci-host-ecam-generic");
683 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "device_type", "pci");
684 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "#address-cells", 3);
685 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "#size-cells", 2);
686 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "bus-range", 0,
689 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
690 2, base_ecam
, 2, size_ecam
);
691 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "ranges",
692 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
693 2, base_ioport
, 2, size_ioport
,
694 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
695 2, base_mmio
, 2, size_mmio
);
697 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "#interrupt-cells", 1);
698 create_pcie_irq_map(vbi
, gic_phandle
, irq
, nodename
);
703 static void *machvirt_dtb(const struct arm_boot_info
*binfo
, int *fdt_size
)
705 const VirtBoardInfo
*board
= (const VirtBoardInfo
*)binfo
;
707 *fdt_size
= board
->fdt_size
;
711 static void machvirt_init(MachineState
*machine
)
713 VirtMachineState
*vms
= VIRT_MACHINE(machine
);
714 qemu_irq pic
[NUM_IRQS
];
715 MemoryRegion
*sysmem
= get_system_memory();
717 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
718 const char *cpu_model
= machine
->cpu_model
;
720 uint32_t gic_phandle
;
724 cpu_model
= "cortex-a15";
727 /* Separate the actual CPU model name from any appended features */
728 cpustr
= g_strsplit(cpu_model
, ",", 2);
730 vbi
= find_machine_info(cpustr
[0]);
733 error_report("mach-virt: CPU %s not supported", cpustr
[0]);
737 vbi
->smp_cpus
= smp_cpus
;
739 if (machine
->ram_size
> vbi
->memmap
[VIRT_MEM
].size
) {
740 error_report("mach-virt: cannot model more than 30GB RAM");
746 for (n
= 0; n
< smp_cpus
; n
++) {
747 ObjectClass
*oc
= cpu_class_by_name(TYPE_ARM_CPU
, cpustr
[0]);
748 CPUClass
*cc
= CPU_CLASS(oc
);
751 char *cpuopts
= g_strdup(cpustr
[1]);
754 fprintf(stderr
, "Unable to find CPU definition\n");
757 cpuobj
= object_new(object_class_get_name(oc
));
759 /* Handle any CPU options specified by the user */
760 cc
->parse_features(CPU(cpuobj
), cpuopts
, &err
);
763 error_report_err(err
);
768 object_property_set_bool(cpuobj
, false, "has_el3", NULL
);
771 object_property_set_int(cpuobj
, QEMU_PSCI_CONDUIT_HVC
, "psci-conduit",
774 /* Secondary CPUs start in PSCI powered-down state */
776 object_property_set_bool(cpuobj
, true, "start-powered-off", NULL
);
779 if (object_property_find(cpuobj
, "reset-cbar", NULL
)) {
780 object_property_set_int(cpuobj
, vbi
->memmap
[VIRT_CPUPERIPHS
].base
,
781 "reset-cbar", &error_abort
);
784 object_property_set_bool(cpuobj
, true, "realized", NULL
);
787 fdt_add_timer_nodes(vbi
);
788 fdt_add_cpu_nodes(vbi
);
789 fdt_add_psci_node(vbi
);
791 memory_region_allocate_system_memory(ram
, NULL
, "mach-virt.ram",
793 memory_region_add_subregion(sysmem
, vbi
->memmap
[VIRT_MEM
].base
, ram
);
797 gic_phandle
= create_gic(vbi
, pic
);
799 create_uart(vbi
, pic
);
801 create_rtc(vbi
, pic
);
803 create_pcie(vbi
, pic
, gic_phandle
);
805 /* Create mmio transports, so the user can create virtio backends
806 * (which will be automatically plugged in to the transports). If
807 * no backend is created the transport will just sit harmlessly idle.
809 create_virtio_devices(vbi
, pic
);
813 vbi
->bootinfo
.ram_size
= machine
->ram_size
;
814 vbi
->bootinfo
.kernel_filename
= machine
->kernel_filename
;
815 vbi
->bootinfo
.kernel_cmdline
= machine
->kernel_cmdline
;
816 vbi
->bootinfo
.initrd_filename
= machine
->initrd_filename
;
817 vbi
->bootinfo
.nb_cpus
= smp_cpus
;
818 vbi
->bootinfo
.board_id
= -1;
819 vbi
->bootinfo
.loader_start
= vbi
->memmap
[VIRT_MEM
].base
;
820 vbi
->bootinfo
.get_dtb
= machvirt_dtb
;
821 vbi
->bootinfo
.firmware_loaded
= bios_name
|| drive_get(IF_PFLASH
, 0, 0);
822 arm_load_kernel(ARM_CPU(first_cpu
), &vbi
->bootinfo
);
825 static bool virt_get_secure(Object
*obj
, Error
**errp
)
827 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
832 static void virt_set_secure(Object
*obj
, bool value
, Error
**errp
)
834 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
839 static void virt_instance_init(Object
*obj
)
841 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
843 /* EL3 is enabled by default on virt */
845 object_property_add_bool(obj
, "secure", virt_get_secure
,
846 virt_set_secure
, NULL
);
847 object_property_set_description(obj
, "secure",
848 "Set on/off to enable/disable the ARM "
849 "Security Extensions (TrustZone)",
853 static void virt_class_init(ObjectClass
*oc
, void *data
)
855 MachineClass
*mc
= MACHINE_CLASS(oc
);
857 mc
->name
= TYPE_VIRT_MACHINE
;
858 mc
->desc
= "ARM Virtual Machine",
859 mc
->init
= machvirt_init
;
863 static const TypeInfo machvirt_info
= {
864 .name
= TYPE_VIRT_MACHINE
,
865 .parent
= TYPE_MACHINE
,
866 .instance_size
= sizeof(VirtMachineState
),
867 .instance_init
= virt_instance_init
,
868 .class_size
= sizeof(VirtMachineClass
),
869 .class_init
= virt_class_init
,
872 static void machvirt_machine_init(void)
874 type_register_static(&machvirt_info
);
877 machine_init(machvirt_machine_init
);