| blob | 8f0ec01f0a1380a26ea2023934fc5df32003b8cd |
1 /*
2 * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, see <http://www.gnu.org/licenses/>.
16 */
18 #ifndef HEXAGON_GEN_TCG_H
19 #define HEXAGON_GEN_TCG_H
21 /*
22 * Here is a primer to understand the tag names for load/store instructions
23 *
24 * Data types
25 * b signed byte r0 = memb(r2+#0)
26 * ub unsigned byte r0 = memub(r2+#0)
27 * h signed half word (16 bits) r0 = memh(r2+#0)
28 * uh unsigned half word r0 = memuh(r2+#0)
29 * i integer (32 bits) r0 = memw(r2+#0)
30 * d double word (64 bits) r1:0 = memd(r2+#0)
31 *
32 * Addressing modes
33 * _io indirect with offset r0 = memw(r1+#4)
34 * _ur absolute with register offset r0 = memw(r1<<#4+##variable)
35 * _rr indirect with register offset r0 = memw(r1+r4<<#2)
36 * gp global pointer relative r0 = memw(gp+#200)
37 * _sp stack pointer relative r0 = memw(r29+#12)
38 * _ap absolute set r0 = memw(r1=##variable)
39 * _pr post increment register r0 = memw(r1++m1)
40 * _pbr post increment bit reverse r0 = memw(r1++m1:brev)
41 * _pi post increment immediate r0 = memb(r1++#1)
42 * _pci post increment circular immediate r0 = memw(r1++#4:circ(m0))
43 * _pcr post increment circular register r0 = memw(r1++I:circ(m0))
44 */
46 /* Macros for complex addressing modes */
47 #define GET_EA_ap \
48 do { \
49 fEA_IMM(UiV); \
50 tcg_gen_movi_tl(ReV, UiV); \
51 } while (0)
52 #define GET_EA_pr \
53 do { \
54 fEA_REG(RxV); \
55 fPM_M(RxV, MuV); \
56 } while (0)
57 #define GET_EA_pbr \
58 do { \
59 gen_helper_fbrev(EA, RxV); \
60 tcg_gen_add_tl(RxV, RxV, MuV); \
61 } while (0)
62 #define GET_EA_pi \
63 do { \
64 fEA_REG(RxV); \
65 fPM_I(RxV, siV); \
66 } while (0)
67 #define GET_EA_pci \
68 do { \
69 TCGv tcgv_siV = tcg_const_tl(siV); \
70 tcg_gen_mov_tl(EA, RxV); \
71 gen_helper_fcircadd(RxV, RxV, tcgv_siV, MuV, \
72 hex_gpr[HEX_REG_CS0 + MuN]); \
73 tcg_temp_free(tcgv_siV); \
74 } while (0)
75 #define GET_EA_pcr(SHIFT) \
76 do { \
77 TCGv ireg = tcg_temp_new(); \
78 tcg_gen_mov_tl(EA, RxV); \
79 gen_read_ireg(ireg, MuV, (SHIFT)); \
80 gen_helper_fcircadd(RxV, RxV, ireg, MuV, hex_gpr[HEX_REG_CS0 + MuN]); \
81 tcg_temp_free(ireg); \
82 } while (0)
84 /* Instructions with multiple definitions */
85 #define fGEN_TCG_LOAD_AP(RES, SIZE, SIGN) \
86 do { \
87 fMUST_IMMEXT(UiV); \
88 fEA_IMM(UiV); \
89 fLOAD(1, SIZE, SIGN, EA, RES); \
90 tcg_gen_movi_tl(ReV, UiV); \
91 } while (0)
93 #define fGEN_TCG_L4_loadrub_ap(SHORTCODE) \
94 fGEN_TCG_LOAD_AP(RdV, 1, u)
95 #define fGEN_TCG_L4_loadrb_ap(SHORTCODE) \
96 fGEN_TCG_LOAD_AP(RdV, 1, s)
97 #define fGEN_TCG_L4_loadruh_ap(SHORTCODE) \
98 fGEN_TCG_LOAD_AP(RdV, 2, u)
99 #define fGEN_TCG_L4_loadrh_ap(SHORTCODE) \
100 fGEN_TCG_LOAD_AP(RdV, 2, s)
101 #define fGEN_TCG_L4_loadri_ap(SHORTCODE) \
102 fGEN_TCG_LOAD_AP(RdV, 4, u)
103 #define fGEN_TCG_L4_loadrd_ap(SHORTCODE) \
104 fGEN_TCG_LOAD_AP(RddV, 8, u)
106 #define fGEN_TCG_L2_loadrub_pci(SHORTCODE) SHORTCODE
107 #define fGEN_TCG_L2_loadrb_pci(SHORTCODE) SHORTCODE
108 #define fGEN_TCG_L2_loadruh_pci(SHORTCODE) SHORTCODE
109 #define fGEN_TCG_L2_loadrh_pci(SHORTCODE) SHORTCODE
110 #define fGEN_TCG_L2_loadri_pci(SHORTCODE) SHORTCODE
111 #define fGEN_TCG_L2_loadrd_pci(SHORTCODE) SHORTCODE
113 #define fGEN_TCG_LOAD_pcr(SHIFT, LOAD) \
114 do { \
115 TCGv ireg = tcg_temp_new(); \
116 tcg_gen_mov_tl(EA, RxV); \
117 gen_read_ireg(ireg, MuV, SHIFT); \
118 gen_helper_fcircadd(RxV, RxV, ireg, MuV, hex_gpr[HEX_REG_CS0 + MuN]); \
119 LOAD; \
120 tcg_temp_free(ireg); \
121 } while (0)
123 #define fGEN_TCG_L2_loadrub_pcr(SHORTCODE) \
124 fGEN_TCG_LOAD_pcr(0, fLOAD(1, 1, u, EA, RdV))
125 #define fGEN_TCG_L2_loadrb_pcr(SHORTCODE) \
126 fGEN_TCG_LOAD_pcr(0, fLOAD(1, 1, s, EA, RdV))
127 #define fGEN_TCG_L2_loadruh_pcr(SHORTCODE) \
128 fGEN_TCG_LOAD_pcr(1, fLOAD(1, 2, u, EA, RdV))
129 #define fGEN_TCG_L2_loadrh_pcr(SHORTCODE) \
130 fGEN_TCG_LOAD_pcr(1, fLOAD(1, 2, s, EA, RdV))
131 #define fGEN_TCG_L2_loadri_pcr(SHORTCODE) \
132 fGEN_TCG_LOAD_pcr(2, fLOAD(1, 4, u, EA, RdV))
133 #define fGEN_TCG_L2_loadrd_pcr(SHORTCODE) \
134 fGEN_TCG_LOAD_pcr(3, fLOAD(1, 8, u, EA, RddV))
136 #define fGEN_TCG_L2_loadrub_pr(SHORTCODE) SHORTCODE
137 #define fGEN_TCG_L2_loadrub_pbr(SHORTCODE) SHORTCODE
138 #define fGEN_TCG_L2_loadrub_pi(SHORTCODE) SHORTCODE
139 #define fGEN_TCG_L2_loadrb_pr(SHORTCODE) SHORTCODE
140 #define fGEN_TCG_L2_loadrb_pbr(SHORTCODE) SHORTCODE
141 #define fGEN_TCG_L2_loadrb_pi(SHORTCODE) SHORTCODE
142 #define fGEN_TCG_L2_loadruh_pr(SHORTCODE) SHORTCODE
143 #define fGEN_TCG_L2_loadruh_pbr(SHORTCODE) SHORTCODE
144 #define fGEN_TCG_L2_loadruh_pi(SHORTCODE) SHORTCODE
145 #define fGEN_TCG_L2_loadrh_pr(SHORTCODE) SHORTCODE
146 #define fGEN_TCG_L2_loadrh_pbr(SHORTCODE) SHORTCODE
147 #define fGEN_TCG_L2_loadrh_pi(SHORTCODE) SHORTCODE
148 #define fGEN_TCG_L2_loadri_pr(SHORTCODE) SHORTCODE
149 #define fGEN_TCG_L2_loadri_pbr(SHORTCODE) SHORTCODE
150 #define fGEN_TCG_L2_loadri_pi(SHORTCODE) SHORTCODE
151 #define fGEN_TCG_L2_loadrd_pr(SHORTCODE) SHORTCODE
152 #define fGEN_TCG_L2_loadrd_pbr(SHORTCODE) SHORTCODE
153 #define fGEN_TCG_L2_loadrd_pi(SHORTCODE) SHORTCODE
155 /*
156 * Predicated loads
157 * Here is a primer to understand the tag names
158 *
159 * Predicate used
160 * t true "old" value if (p0) r0 = memb(r2+#0)
161 * f false "old" value if (!p0) r0 = memb(r2+#0)
162 * tnew true "new" value if (p0.new) r0 = memb(r2+#0)
163 * fnew false "new" value if (!p0.new) r0 = memb(r2+#0)
164 */
165 #define fGEN_TCG_PRED_LOAD(GET_EA, PRED, SIZE, SIGN) \
166 do { \
167 TCGv LSB = tcg_temp_local_new(); \
168 TCGLabel *label = gen_new_label(); \
169 GET_EA; \
170 PRED; \
171 PRED_LOAD_CANCEL(LSB, EA); \
172 tcg_gen_movi_tl(RdV, 0); \
173 tcg_gen_brcondi_tl(TCG_COND_EQ, LSB, 0, label); \
174 fLOAD(1, SIZE, SIGN, EA, RdV); \
175 gen_set_label(label); \
176 tcg_temp_free(LSB); \
177 } while (0)
179 #define fGEN_TCG_L2_ploadrubt_pi(SHORTCODE) \
180 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLD(PtV), 1, u)
181 #define fGEN_TCG_L2_ploadrubf_pi(SHORTCODE) \
182 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLDNOT(PtV), 1, u)
183 #define fGEN_TCG_L2_ploadrubtnew_pi(SHORTCODE) \
184 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEW(PtN), 1, u)
185 #define fGEN_TCG_L2_ploadrubfnew_pi(SHORTCODE) \
186 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEWNOT(PtN), 1, u)
187 #define fGEN_TCG_L2_ploadrbt_pi(SHORTCODE) \
188 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLD(PtV), 1, s)
189 #define fGEN_TCG_L2_ploadrbf_pi(SHORTCODE) \
190 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLDNOT(PtV), 1, s)
191 #define fGEN_TCG_L2_ploadrbtnew_pi(SHORTCODE) \
192 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEW(PtN), 1, s)
193 #define fGEN_TCG_L2_ploadrbfnew_pi(SHORTCODE) \
194 fGEN_TCG_PRED_LOAD({ fEA_REG(RxV); fPM_I(RxV, siV); }, \
195 fLSBNEWNOT(PtN), 1, s)
197 #define fGEN_TCG_L2_ploadruht_pi(SHORTCODE) \
198 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLD(PtV), 2, u)
199 #define fGEN_TCG_L2_ploadruhf_pi(SHORTCODE) \
200 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLDNOT(PtV), 2, u)
201 #define fGEN_TCG_L2_ploadruhtnew_pi(SHORTCODE) \
202 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEW(PtN), 2, u)
203 #define fGEN_TCG_L2_ploadruhfnew_pi(SHORTCODE) \
204 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEWNOT(PtN), 2, u)
205 #define fGEN_TCG_L2_ploadrht_pi(SHORTCODE) \
206 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLD(PtV), 2, s)
207 #define fGEN_TCG_L2_ploadrhf_pi(SHORTCODE) \
208 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLDNOT(PtV), 2, s)
209 #define fGEN_TCG_L2_ploadrhtnew_pi(SHORTCODE) \
210 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEW(PtN), 2, s)
211 #define fGEN_TCG_L2_ploadrhfnew_pi(SHORTCODE) \
212 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEWNOT(PtN), 2, s)
214 #define fGEN_TCG_L2_ploadrit_pi(SHORTCODE) \
215 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLD(PtV), 4, u)
216 #define fGEN_TCG_L2_ploadrif_pi(SHORTCODE) \
217 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLDNOT(PtV), 4, u)
218 #define fGEN_TCG_L2_ploadritnew_pi(SHORTCODE) \
219 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEW(PtN), 4, u)
220 #define fGEN_TCG_L2_ploadrifnew_pi(SHORTCODE) \
221 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEWNOT(PtN), 4, u)
223 /* Predicated loads into a register pair */
224 #define fGEN_TCG_PRED_LOAD_PAIR(GET_EA, PRED) \
225 do { \
226 TCGv LSB = tcg_temp_local_new(); \
227 TCGLabel *label = gen_new_label(); \
228 GET_EA; \
229 PRED; \
230 PRED_LOAD_CANCEL(LSB, EA); \
231 tcg_gen_movi_i64(RddV, 0); \
232 tcg_gen_brcondi_tl(TCG_COND_EQ, LSB, 0, label); \
233 fLOAD(1, 8, u, EA, RddV); \
234 gen_set_label(label); \
235 tcg_temp_free(LSB); \
236 } while (0)
238 #define fGEN_TCG_L2_ploadrdt_pi(SHORTCODE) \
239 fGEN_TCG_PRED_LOAD_PAIR(GET_EA_pi, fLSBOLD(PtV))
240 #define fGEN_TCG_L2_ploadrdf_pi(SHORTCODE) \
241 fGEN_TCG_PRED_LOAD_PAIR(GET_EA_pi, fLSBOLDNOT(PtV))
242 #define fGEN_TCG_L2_ploadrdtnew_pi(SHORTCODE) \
243 fGEN_TCG_PRED_LOAD_PAIR(GET_EA_pi, fLSBNEW(PtN))
244 #define fGEN_TCG_L2_ploadrdfnew_pi(SHORTCODE) \
245 fGEN_TCG_PRED_LOAD_PAIR(GET_EA_pi, fLSBNEWNOT(PtN))
247 /* load-locked and store-locked */
248 #define fGEN_TCG_L2_loadw_locked(SHORTCODE) \
249 SHORTCODE
250 #define fGEN_TCG_L4_loadd_locked(SHORTCODE) \
251 SHORTCODE
252 #define fGEN_TCG_S2_storew_locked(SHORTCODE) \
253 do { SHORTCODE; READ_PREG(PdV, PdN); } while (0)
254 #define fGEN_TCG_S4_stored_locked(SHORTCODE) \
255 do { SHORTCODE; READ_PREG(PdV, PdN); } while (0)
257 #define fGEN_TCG_STORE(SHORTCODE) \
258 do { \
259 TCGv HALF = tcg_temp_new(); \
260 TCGv BYTE = tcg_temp_new(); \
261 SHORTCODE; \
262 tcg_temp_free(HALF); \
263 tcg_temp_free(BYTE); \
264 } while (0)
266 #define fGEN_TCG_STORE_pcr(SHIFT, STORE) \
267 do { \
268 TCGv ireg = tcg_temp_new(); \
269 TCGv HALF = tcg_temp_new(); \
270 TCGv BYTE = tcg_temp_new(); \
271 tcg_gen_mov_tl(EA, RxV); \
272 gen_read_ireg(ireg, MuV, SHIFT); \
273 gen_helper_fcircadd(RxV, RxV, ireg, MuV, hex_gpr[HEX_REG_CS0 + MuN]); \
274 STORE; \
275 tcg_temp_free(ireg); \
276 tcg_temp_free(HALF); \
277 tcg_temp_free(BYTE); \
278 } while (0)
280 #define fGEN_TCG_S2_storerb_pbr(SHORTCODE) \
281 fGEN_TCG_STORE(SHORTCODE)
282 #define fGEN_TCG_S2_storerb_pci(SHORTCODE) \
283 fGEN_TCG_STORE(SHORTCODE)
284 #define fGEN_TCG_S2_storerb_pcr(SHORTCODE) \
285 fGEN_TCG_STORE_pcr(0, fSTORE(1, 1, EA, fGETBYTE(0, RtV)))
287 #define fGEN_TCG_S2_storerh_pbr(SHORTCODE) \
288 fGEN_TCG_STORE(SHORTCODE)
289 #define fGEN_TCG_S2_storerh_pci(SHORTCODE) \
290 fGEN_TCG_STORE(SHORTCODE)
291 #define fGEN_TCG_S2_storerh_pcr(SHORTCODE) \
292 fGEN_TCG_STORE_pcr(1, fSTORE(1, 2, EA, fGETHALF(0, RtV)))
294 #define fGEN_TCG_S2_storerf_pbr(SHORTCODE) \
295 fGEN_TCG_STORE(SHORTCODE)
296 #define fGEN_TCG_S2_storerf_pci(SHORTCODE) \
297 fGEN_TCG_STORE(SHORTCODE)
298 #define fGEN_TCG_S2_storerf_pcr(SHORTCODE) \
299 fGEN_TCG_STORE_pcr(1, fSTORE(1, 2, EA, fGETHALF(1, RtV)))
301 #define fGEN_TCG_S2_storeri_pbr(SHORTCODE) \
302 fGEN_TCG_STORE(SHORTCODE)
303 #define fGEN_TCG_S2_storeri_pci(SHORTCODE) \
304 fGEN_TCG_STORE(SHORTCODE)
305 #define fGEN_TCG_S2_storeri_pcr(SHORTCODE) \
306 fGEN_TCG_STORE_pcr(2, fSTORE(1, 4, EA, RtV))
308 #define fGEN_TCG_S2_storerd_pbr(SHORTCODE) \
309 fGEN_TCG_STORE(SHORTCODE)
310 #define fGEN_TCG_S2_storerd_pci(SHORTCODE) \
311 fGEN_TCG_STORE(SHORTCODE)
312 #define fGEN_TCG_S2_storerd_pcr(SHORTCODE) \
313 fGEN_TCG_STORE_pcr(3, fSTORE(1, 8, EA, RttV))
315 #define fGEN_TCG_S2_storerbnew_pbr(SHORTCODE) \
316 fGEN_TCG_STORE(SHORTCODE)
317 #define fGEN_TCG_S2_storerbnew_pci(SHORTCODE) \
318 fGEN_TCG_STORE(SHORTCODE)
319 #define fGEN_TCG_S2_storerbnew_pcr(SHORTCODE) \
320 fGEN_TCG_STORE_pcr(0, fSTORE(1, 1, EA, fGETBYTE(0, NtN)))
322 #define fGEN_TCG_S2_storerhnew_pbr(SHORTCODE) \
323 fGEN_TCG_STORE(SHORTCODE)
324 #define fGEN_TCG_S2_storerhnew_pci(SHORTCODE) \
325 fGEN_TCG_STORE(SHORTCODE)
326 #define fGEN_TCG_S2_storerhnew_pcr(SHORTCODE) \
327 fGEN_TCG_STORE_pcr(1, fSTORE(1, 2, EA, fGETHALF(0, NtN)))
329 #define fGEN_TCG_S2_storerinew_pbr(SHORTCODE) \
330 fGEN_TCG_STORE(SHORTCODE)
331 #define fGEN_TCG_S2_storerinew_pci(SHORTCODE) \
332 fGEN_TCG_STORE(SHORTCODE)
333 #define fGEN_TCG_S2_storerinew_pcr(SHORTCODE) \
334 fGEN_TCG_STORE_pcr(2, fSTORE(1, 4, EA, NtN))
336 /*
337 * Mathematical operations with more than one definition require
338 * special handling
339 */
340 #define fGEN_TCG_A5_ACS(SHORTCODE) \
341 do { \
342 gen_helper_vacsh_pred(PeV, cpu_env, RxxV, RssV, RttV); \
343 gen_helper_vacsh_val(RxxV, cpu_env, RxxV, RssV, RttV); \
344 } while (0)
346 /*
347 * Approximate reciprocal
348 * r3,p1 = sfrecipa(r0, r1)
349 *
350 * The helper packs the 2 32-bit results into a 64-bit value,
351 * so unpack them into the proper results.
352 */
353 #define fGEN_TCG_F2_sfrecipa(SHORTCODE) \
354 do { \
355 TCGv_i64 tmp = tcg_temp_new_i64(); \
356 gen_helper_sfrecipa(tmp, cpu_env, RsV, RtV); \
357 tcg_gen_extrh_i64_i32(RdV, tmp); \
358 tcg_gen_extrl_i64_i32(PeV, tmp); \
359 tcg_temp_free_i64(tmp); \
360 } while (0)
362 /*
363 * Approximation of the reciprocal square root
364 * r1,p0 = sfinvsqrta(r0)
365 *
366 * The helper packs the 2 32-bit results into a 64-bit value,
367 * so unpack them into the proper results.
368 */
369 #define fGEN_TCG_F2_sfinvsqrta(SHORTCODE) \
370 do { \
371 TCGv_i64 tmp = tcg_temp_new_i64(); \
372 gen_helper_sfinvsqrta(tmp, cpu_env, RsV); \
373 tcg_gen_extrh_i64_i32(RdV, tmp); \
374 tcg_gen_extrl_i64_i32(PeV, tmp); \
375 tcg_temp_free_i64(tmp); \
376 } while (0)
378 /*
379 * Add or subtract with carry.
380 * Predicate register is used as an extra input and output.
381 * r5:4 = add(r1:0, r3:2, p1):carry
382 */
383 #define fGEN_TCG_A4_addp_c(SHORTCODE) \
384 do { \
385 TCGv_i64 carry = tcg_temp_new_i64(); \
386 TCGv_i64 zero = tcg_const_i64(0); \
387 tcg_gen_extu_i32_i64(carry, PxV); \
388 tcg_gen_andi_i64(carry, carry, 1); \
389 tcg_gen_add2_i64(RddV, carry, RssV, zero, carry, zero); \
390 tcg_gen_add2_i64(RddV, carry, RddV, carry, RttV, zero); \
391 tcg_gen_extrl_i64_i32(PxV, carry); \
392 gen_8bitsof(PxV, PxV); \
393 tcg_temp_free_i64(carry); \
394 tcg_temp_free_i64(zero); \
395 } while (0)
397 /* r5:4 = sub(r1:0, r3:2, p1):carry */
398 #define fGEN_TCG_A4_subp_c(SHORTCODE) \
399 do { \
400 TCGv_i64 carry = tcg_temp_new_i64(); \
401 TCGv_i64 zero = tcg_const_i64(0); \
402 TCGv_i64 not_RttV = tcg_temp_new_i64(); \
403 tcg_gen_extu_i32_i64(carry, PxV); \
404 tcg_gen_andi_i64(carry, carry, 1); \
405 tcg_gen_not_i64(not_RttV, RttV); \
406 tcg_gen_add2_i64(RddV, carry, RssV, zero, carry, zero); \
407 tcg_gen_add2_i64(RddV, carry, RddV, carry, not_RttV, zero); \
408 tcg_gen_extrl_i64_i32(PxV, carry); \
409 gen_8bitsof(PxV, PxV); \
410 tcg_temp_free_i64(carry); \
411 tcg_temp_free_i64(zero); \
412 tcg_temp_free_i64(not_RttV); \
413 } while (0)
415 /*
416 * Compare each of the 8 unsigned bytes
417 * The minimum is placed in each byte of the destination.
418 * Each bit of the predicate is set true if the bit from the first operand
419 * is greater than the bit from the second operand.
420 * r5:4,p1 = vminub(r1:0, r3:2)
421 */
422 #define fGEN_TCG_A6_vminub_RdP(SHORTCODE) \
423 do { \
424 TCGv left = tcg_temp_new(); \
425 TCGv right = tcg_temp_new(); \
426 TCGv tmp = tcg_temp_new(); \
427 tcg_gen_movi_tl(PeV, 0); \
428 tcg_gen_movi_i64(RddV, 0); \
429 for (int i = 0; i < 8; i++) { \
430 gen_get_byte_i64(left, i, RttV, false); \
431 gen_get_byte_i64(right, i, RssV, false); \
432 tcg_gen_setcond_tl(TCG_COND_GT, tmp, left, right); \
433 tcg_gen_deposit_tl(PeV, PeV, tmp, i, 1); \
434 tcg_gen_umin_tl(tmp, left, right); \
435 gen_set_byte_i64(i, RddV, tmp); \
436 } \
437 tcg_temp_free(left); \
438 tcg_temp_free(right); \
439 tcg_temp_free(tmp); \
440 } while (0)
442 /* Floating point */
443 #define fGEN_TCG_F2_conv_sf2df(SHORTCODE) \
444 gen_helper_conv_sf2df(RddV, cpu_env, RsV)
445 #define fGEN_TCG_F2_conv_df2sf(SHORTCODE) \
446 gen_helper_conv_df2sf(RdV, cpu_env, RssV)
447 #define fGEN_TCG_F2_conv_uw2sf(SHORTCODE) \
448 gen_helper_conv_uw2sf(RdV, cpu_env, RsV)
449 #define fGEN_TCG_F2_conv_uw2df(SHORTCODE) \
450 gen_helper_conv_uw2df(RddV, cpu_env, RsV)
451 #define fGEN_TCG_F2_conv_w2sf(SHORTCODE) \
452 gen_helper_conv_w2sf(RdV, cpu_env, RsV)
453 #define fGEN_TCG_F2_conv_w2df(SHORTCODE) \
454 gen_helper_conv_w2df(RddV, cpu_env, RsV)
455 #define fGEN_TCG_F2_conv_ud2sf(SHORTCODE) \
456 gen_helper_conv_ud2sf(RdV, cpu_env, RssV)
457 #define fGEN_TCG_F2_conv_ud2df(SHORTCODE) \
458 gen_helper_conv_ud2df(RddV, cpu_env, RssV)
459 #define fGEN_TCG_F2_conv_d2sf(SHORTCODE) \
460 gen_helper_conv_d2sf(RdV, cpu_env, RssV)
461 #define fGEN_TCG_F2_conv_d2df(SHORTCODE) \
462 gen_helper_conv_d2df(RddV, cpu_env, RssV)
463 #define fGEN_TCG_F2_conv_sf2uw(SHORTCODE) \
464 gen_helper_conv_sf2uw(RdV, cpu_env, RsV)
465 #define fGEN_TCG_F2_conv_sf2w(SHORTCODE) \
466 gen_helper_conv_sf2w(RdV, cpu_env, RsV)
467 #define fGEN_TCG_F2_conv_sf2ud(SHORTCODE) \
468 gen_helper_conv_sf2ud(RddV, cpu_env, RsV)
469 #define fGEN_TCG_F2_conv_sf2d(SHORTCODE) \
470 gen_helper_conv_sf2d(RddV, cpu_env, RsV)
471 #define fGEN_TCG_F2_conv_df2uw(SHORTCODE) \
472 gen_helper_conv_df2uw(RdV, cpu_env, RssV)
473 #define fGEN_TCG_F2_conv_df2w(SHORTCODE) \
474 gen_helper_conv_df2w(RdV, cpu_env, RssV)
475 #define fGEN_TCG_F2_conv_df2ud(SHORTCODE) \
476 gen_helper_conv_df2ud(RddV, cpu_env, RssV)
477 #define fGEN_TCG_F2_conv_df2d(SHORTCODE) \
478 gen_helper_conv_df2d(RddV, cpu_env, RssV)
479 #define fGEN_TCG_F2_conv_sf2uw_chop(SHORTCODE) \
480 gen_helper_conv_sf2uw_chop(RdV, cpu_env, RsV)
481 #define fGEN_TCG_F2_conv_sf2w_chop(SHORTCODE) \
482 gen_helper_conv_sf2w_chop(RdV, cpu_env, RsV)
483 #define fGEN_TCG_F2_conv_sf2ud_chop(SHORTCODE) \
484 gen_helper_conv_sf2ud_chop(RddV, cpu_env, RsV)
485 #define fGEN_TCG_F2_conv_sf2d_chop(SHORTCODE) \
486 gen_helper_conv_sf2d_chop(RddV, cpu_env, RsV)
487 #define fGEN_TCG_F2_conv_df2uw_chop(SHORTCODE) \
488 gen_helper_conv_df2uw_chop(RdV, cpu_env, RssV)
489 #define fGEN_TCG_F2_conv_df2w_chop(SHORTCODE) \
490 gen_helper_conv_df2w_chop(RdV, cpu_env, RssV)
491 #define fGEN_TCG_F2_conv_df2ud_chop(SHORTCODE) \
492 gen_helper_conv_df2ud_chop(RddV, cpu_env, RssV)
493 #define fGEN_TCG_F2_conv_df2d_chop(SHORTCODE) \
494 gen_helper_conv_df2d_chop(RddV, cpu_env, RssV)
495 #define fGEN_TCG_F2_sfadd(SHORTCODE) \
496 gen_helper_sfadd(RdV, cpu_env, RsV, RtV)
497 #define fGEN_TCG_F2_sfsub(SHORTCODE) \
498 gen_helper_sfsub(RdV, cpu_env, RsV, RtV)
499 #define fGEN_TCG_F2_sfcmpeq(SHORTCODE) \
500 gen_helper_sfcmpeq(PdV, cpu_env, RsV, RtV)
501 #define fGEN_TCG_F2_sfcmpgt(SHORTCODE) \
502 gen_helper_sfcmpgt(PdV, cpu_env, RsV, RtV)
503 #define fGEN_TCG_F2_sfcmpge(SHORTCODE) \
504 gen_helper_sfcmpge(PdV, cpu_env, RsV, RtV)
505 #define fGEN_TCG_F2_sfcmpuo(SHORTCODE) \
506 gen_helper_sfcmpuo(PdV, cpu_env, RsV, RtV)
507 #define fGEN_TCG_F2_sfmax(SHORTCODE) \
508 gen_helper_sfmax(RdV, cpu_env, RsV, RtV)
509 #define fGEN_TCG_F2_sfmin(SHORTCODE) \
510 gen_helper_sfmin(RdV, cpu_env, RsV, RtV)
511 #define fGEN_TCG_F2_sfclass(SHORTCODE) \
512 do { \
513 TCGv imm = tcg_const_tl(uiV); \
514 gen_helper_sfclass(PdV, cpu_env, RsV, imm); \
515 tcg_temp_free(imm); \
516 } while (0)
517 #define fGEN_TCG_F2_sffixupn(SHORTCODE) \
518 gen_helper_sffixupn(RdV, cpu_env, RsV, RtV)
519 #define fGEN_TCG_F2_sffixupd(SHORTCODE) \
520 gen_helper_sffixupd(RdV, cpu_env, RsV, RtV)
521 #define fGEN_TCG_F2_sffixupr(SHORTCODE) \
522 gen_helper_sffixupr(RdV, cpu_env, RsV)
523 #define fGEN_TCG_F2_dfadd(SHORTCODE) \
524 gen_helper_dfadd(RddV, cpu_env, RssV, RttV)
525 #define fGEN_TCG_F2_dfsub(SHORTCODE) \
526 gen_helper_dfsub(RddV, cpu_env, RssV, RttV)
527 #define fGEN_TCG_F2_dfmax(SHORTCODE) \
528 gen_helper_dfmax(RddV, cpu_env, RssV, RttV)
529 #define fGEN_TCG_F2_dfmin(SHORTCODE) \
530 gen_helper_dfmin(RddV, cpu_env, RssV, RttV)
531 #define fGEN_TCG_F2_dfcmpeq(SHORTCODE) \
532 gen_helper_dfcmpeq(PdV, cpu_env, RssV, RttV)
533 #define fGEN_TCG_F2_dfcmpgt(SHORTCODE) \
534 gen_helper_dfcmpgt(PdV, cpu_env, RssV, RttV)
535 #define fGEN_TCG_F2_dfcmpge(SHORTCODE) \
536 gen_helper_dfcmpge(PdV, cpu_env, RssV, RttV)
537 #define fGEN_TCG_F2_dfcmpuo(SHORTCODE) \
538 gen_helper_dfcmpuo(PdV, cpu_env, RssV, RttV)
539 #define fGEN_TCG_F2_dfclass(SHORTCODE) \
540 do { \
541 TCGv imm = tcg_const_tl(uiV); \
542 gen_helper_dfclass(PdV, cpu_env, RssV, imm); \
543 tcg_temp_free(imm); \
544 } while (0)
545 #define fGEN_TCG_F2_sfmpy(SHORTCODE) \
546 gen_helper_sfmpy(RdV, cpu_env, RsV, RtV)
547 #define fGEN_TCG_F2_sffma(SHORTCODE) \
548 gen_helper_sffma(RxV, cpu_env, RxV, RsV, RtV)
549 #define fGEN_TCG_F2_sffma_sc(SHORTCODE) \
550 gen_helper_sffma_sc(RxV, cpu_env, RxV, RsV, RtV, PuV)
551 #define fGEN_TCG_F2_sffms(SHORTCODE) \
552 gen_helper_sffms(RxV, cpu_env, RxV, RsV, RtV)
553 #define fGEN_TCG_F2_sffma_lib(SHORTCODE) \
554 gen_helper_sffma_lib(RxV, cpu_env, RxV, RsV, RtV)
555 #define fGEN_TCG_F2_sffms_lib(SHORTCODE) \
556 gen_helper_sffms_lib(RxV, cpu_env, RxV, RsV, RtV)
558 #define fGEN_TCG_F2_dfmpyfix(SHORTCODE) \
559 gen_helper_dfmpyfix(RddV, cpu_env, RssV, RttV)
560 #define fGEN_TCG_F2_dfmpyhh(SHORTCODE) \
561 gen_helper_dfmpyhh(RxxV, cpu_env, RxxV, RssV, RttV)
563 #endif