hw/arm/integratorcp.c

   1 /*
   2  * ARM Integrator CP System emulation.
   3  *
   4  * Copyright (c) 2005-2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL
   8  */
   9
  10 #include "hw/sysbus.h"
  11 #include "hw/devices.h"
  12 #include "hw/boards.h"
  13 #include "hw/arm/arm.h"
  14 #include "hw/misc/arm_integrator_debug.h"
  15 #include "net/net.h"
  16 #include "exec/address-spaces.h"
  17 #include "sysemu/sysemu.h"
  18
  19 #define TYPE_INTEGRATOR_CM "integrator_core"
  20 #define INTEGRATOR_CM(obj) \
  21     OBJECT_CHECK(IntegratorCMState, (obj), TYPE_INTEGRATOR_CM)
  22
  23 typedef struct IntegratorCMState {
  24     /*< private >*/
  25     SysBusDevice parent_obj;
  26     /*< public >*/
  27
  28     MemoryRegion iomem;
  29     uint32_t memsz;
  30     MemoryRegion flash;
  31     uint32_t cm_osc;
  32     uint32_t cm_ctrl;
  33     uint32_t cm_lock;
  34     uint32_t cm_auxosc;
  35     uint32_t cm_sdram;
  36     uint32_t cm_init;
  37     uint32_t cm_flags;
  38     uint32_t cm_nvflags;
  39     uint32_t cm_refcnt_offset;
  40     uint32_t int_level;
  41     uint32_t irq_enabled;
  42     uint32_t fiq_enabled;
  43 } IntegratorCMState;
  44
  45 static uint8_t integrator_spd[128] = {
  46    128, 8, 4, 11, 9, 1, 64, 0,  2, 0xa0, 0xa0, 0, 0, 8, 0, 1,
  47    0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40
  48 };
  49
  50 static uint64_t integratorcm_read(void *opaque, hwaddr offset,
  51                                   unsigned size)
  52 {
  53     IntegratorCMState *s = opaque;
  54     if (offset >= 0x100 && offset < 0x200) {
  55         /* CM_SPD */
  56         if (offset >= 0x180)
  57             return 0;
  58         return integrator_spd[offset >> 2];
  59     }
  60     switch (offset >> 2) {
  61     case 0: /* CM_ID */
  62         return 0x411a3001;
  63     case 1: /* CM_PROC */
  64         return 0;
  65     case 2: /* CM_OSC */
  66         return s->cm_osc;
  67     case 3: /* CM_CTRL */
  68         return s->cm_ctrl;
  69     case 4: /* CM_STAT */
  70         return 0x00100000;
  71     case 5: /* CM_LOCK */
  72         if (s->cm_lock == 0xa05f) {
  73             return 0x1a05f;
  74         } else {
  75             return s->cm_lock;
  76         }
  77     case 6: /* CM_LMBUSCNT */
  78         /* ??? High frequency timer.  */
  79         hw_error("integratorcm_read: CM_LMBUSCNT");
  80     case 7: /* CM_AUXOSC */
  81         return s->cm_auxosc;
  82     case 8: /* CM_SDRAM */
  83         return s->cm_sdram;
  84     case 9: /* CM_INIT */
  85         return s->cm_init;
  86     case 10: /* CM_REFCNT */
  87         /* This register, CM_REFCNT, provides a 32-bit count value.
  88          * The count increments at the fixed reference clock frequency of 24MHz
  89          * and can be used as a real-time counter.
  90          */
  91         return (uint32_t)muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24,
  92                                   1000) - s->cm_refcnt_offset;
  93     case 12: /* CM_FLAGS */
  94         return s->cm_flags;
  95     case 14: /* CM_NVFLAGS */
  96         return s->cm_nvflags;
  97     case 16: /* CM_IRQ_STAT */
  98         return s->int_level & s->irq_enabled;
  99     case 17: /* CM_IRQ_RSTAT */
 100         return s->int_level;
 101     case 18: /* CM_IRQ_ENSET */
 102         return s->irq_enabled;
 103     case 20: /* CM_SOFT_INTSET */
 104         return s->int_level & 1;
 105     case 24: /* CM_FIQ_STAT */
 106         return s->int_level & s->fiq_enabled;
 107     case 25: /* CM_FIQ_RSTAT */
 108         return s->int_level;
 109     case 26: /* CM_FIQ_ENSET */
 110         return s->fiq_enabled;
 111     case 32: /* CM_VOLTAGE_CTL0 */
 112     case 33: /* CM_VOLTAGE_CTL1 */
 113     case 34: /* CM_VOLTAGE_CTL2 */
 114     case 35: /* CM_VOLTAGE_CTL3 */
 115         /* ??? Voltage control unimplemented.  */
 116         return 0;
 117     default:
 118         hw_error("integratorcm_read: Unimplemented offset 0x%x\n",
 119                  (int)offset);
 120         return 0;
 121     }
 122 }
 123
 124 static void integratorcm_do_remap(IntegratorCMState *s)
 125 {
 126     /* Sync memory region state with CM_CTRL REMAP bit:
 127      * bit 0 => flash at address 0; bit 1 => RAM
 128      */
 129     memory_region_set_enabled(&s->flash, !(s->cm_ctrl & 4));
 130 }
 131
 132 static void integratorcm_set_ctrl(IntegratorCMState *s, uint32_t value)
 133 {
 134     if (value & 8) {
 135         qemu_system_reset_request();
 136     }
 137     if ((s->cm_ctrl ^ value) & 1) {
 138         /* (value & 1) != 0 means the green "MISC LED" is lit.
 139          * We don't have any nice place to display LEDs. printf is a bad
 140          * idea because Linux uses the LED as a heartbeat and the output
 141          * will swamp anything else on the terminal.
 142          */
 143     }
 144     /* Note that the RESET bit [3] always reads as zero */
 145     s->cm_ctrl = (s->cm_ctrl & ~5) | (value & 5);
 146     integratorcm_do_remap(s);
 147 }
 148
 149 static void integratorcm_update(IntegratorCMState *s)
 150 {
 151     /* ??? The CPU irq/fiq is raised when either the core module or base PIC
 152        are active.  */
 153     if (s->int_level & (s->irq_enabled | s->fiq_enabled))
 154         hw_error("Core module interrupt\n");
 155 }
 156
 157 static void integratorcm_write(void *opaque, hwaddr offset,
 158                                uint64_t value, unsigned size)
 159 {
 160     IntegratorCMState *s = opaque;
 161     switch (offset >> 2) {
 162     case 2: /* CM_OSC */
 163         if (s->cm_lock == 0xa05f)
 164             s->cm_osc = value;
 165         break;
 166     case 3: /* CM_CTRL */
 167         integratorcm_set_ctrl(s, value);
 168         break;
 169     case 5: /* CM_LOCK */
 170         s->cm_lock = value & 0xffff;
 171         break;
 172     case 7: /* CM_AUXOSC */
 173         if (s->cm_lock == 0xa05f)
 174             s->cm_auxosc = value;
 175         break;
 176     case 8: /* CM_SDRAM */
 177         s->cm_sdram = value;
 178         break;
 179     case 9: /* CM_INIT */
 180         /* ??? This can change the memory bus frequency.  */
 181         s->cm_init = value;
 182         break;
 183     case 12: /* CM_FLAGSS */
 184         s->cm_flags |= value;
 185         break;
 186     case 13: /* CM_FLAGSC */
 187         s->cm_flags &= ~value;
 188         break;
 189     case 14: /* CM_NVFLAGSS */
 190         s->cm_nvflags |= value;
 191         break;
 192     case 15: /* CM_NVFLAGSS */
 193         s->cm_nvflags &= ~value;
 194         break;
 195     case 18: /* CM_IRQ_ENSET */
 196         s->irq_enabled |= value;
 197         integratorcm_update(s);
 198         break;
 199     case 19: /* CM_IRQ_ENCLR */
 200         s->irq_enabled &= ~value;
 201         integratorcm_update(s);
 202         break;
 203     case 20: /* CM_SOFT_INTSET */
 204         s->int_level |= (value & 1);
 205         integratorcm_update(s);
 206         break;
 207     case 21: /* CM_SOFT_INTCLR */
 208         s->int_level &= ~(value & 1);
 209         integratorcm_update(s);
 210         break;
 211     case 26: /* CM_FIQ_ENSET */
 212         s->fiq_enabled |= value;
 213         integratorcm_update(s);
 214         break;
 215     case 27: /* CM_FIQ_ENCLR */
 216         s->fiq_enabled &= ~value;
 217         integratorcm_update(s);
 218         break;
 219     case 32: /* CM_VOLTAGE_CTL0 */
 220     case 33: /* CM_VOLTAGE_CTL1 */
 221     case 34: /* CM_VOLTAGE_CTL2 */
 222     case 35: /* CM_VOLTAGE_CTL3 */
 223         /* ??? Voltage control unimplemented.  */
 224         break;
 225     default:
 226         hw_error("integratorcm_write: Unimplemented offset 0x%x\n",
 227                  (int)offset);
 228         break;
 229     }
 230 }
 231
 232 /* Integrator/CM control registers.  */
 233
 234 static const MemoryRegionOps integratorcm_ops = {
 235     .read = integratorcm_read,
 236     .write = integratorcm_write,
 237     .endianness = DEVICE_NATIVE_ENDIAN,
 238 };
 239
 240 static int integratorcm_init(SysBusDevice *dev)
 241 {
 242     IntegratorCMState *s = INTEGRATOR_CM(dev);
 243
 244     s->cm_osc = 0x01000048;
 245     /* ??? What should the high bits of this value be?  */
 246     s->cm_auxosc = 0x0007feff;
 247     s->cm_sdram = 0x00011122;
 248     if (s->memsz >= 256) {
 249         integrator_spd[31] = 64;
 250         s->cm_sdram |= 0x10;
 251     } else if (s->memsz >= 128) {
 252         integrator_spd[31] = 32;
 253         s->cm_sdram |= 0x0c;
 254     } else if (s->memsz >= 64) {
 255         integrator_spd[31] = 16;
 256         s->cm_sdram |= 0x08;
 257     } else if (s->memsz >= 32) {
 258         integrator_spd[31] = 4;
 259         s->cm_sdram |= 0x04;
 260     } else {
 261         integrator_spd[31] = 2;
 262     }
 263     memcpy(integrator_spd + 73, "QEMU-MEMORY", 11);
 264     s->cm_init = 0x00000112;
 265     s->cm_refcnt_offset = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24,
 266                                    1000);
 267     memory_region_init_ram(&s->flash, OBJECT(s), "integrator.flash", 0x100000,
 268                            &error_abort);
 269     vmstate_register_ram_global(&s->flash);
 270
 271     memory_region_init_io(&s->iomem, OBJECT(s), &integratorcm_ops, s,
 272                           "integratorcm", 0x00800000);
 273     sysbus_init_mmio(dev, &s->iomem);
 274
 275     integratorcm_do_remap(s);
 276     /* ??? Save/restore.  */
 277     return 0;
 278 }
 279
 280 /* Integrator/CP hardware emulation.  */
 281 /* Primary interrupt controller.  */
 282
 283 #define TYPE_INTEGRATOR_PIC "integrator_pic"
 284 #define INTEGRATOR_PIC(obj) \
 285    OBJECT_CHECK(icp_pic_state, (obj), TYPE_INTEGRATOR_PIC)
 286
 287 typedef struct icp_pic_state {
 288     /*< private >*/
 289     SysBusDevice parent_obj;
 290     /*< public >*/
 291
 292     MemoryRegion iomem;
 293     uint32_t level;
 294     uint32_t irq_enabled;
 295     uint32_t fiq_enabled;
 296     qemu_irq parent_irq;
 297     qemu_irq parent_fiq;
 298 } icp_pic_state;
 299
 300 static void icp_pic_update(icp_pic_state *s)
 301 {
 302     uint32_t flags;
 303
 304     flags = (s->level & s->irq_enabled);
 305     qemu_set_irq(s->parent_irq, flags != 0);
 306     flags = (s->level & s->fiq_enabled);
 307     qemu_set_irq(s->parent_fiq, flags != 0);
 308 }
 309
 310 static void icp_pic_set_irq(void *opaque, int irq, int level)
 311 {
 312     icp_pic_state *s = (icp_pic_state *)opaque;
 313     if (level)
 314         s->level |= 1 << irq;
 315     else
 316         s->level &= ~(1 << irq);
 317     icp_pic_update(s);
 318 }
 319
 320 static uint64_t icp_pic_read(void *opaque, hwaddr offset,
 321                              unsigned size)
 322 {
 323     icp_pic_state *s = (icp_pic_state *)opaque;
 324
 325     switch (offset >> 2) {
 326     case 0: /* IRQ_STATUS */
 327         return s->level & s->irq_enabled;
 328     case 1: /* IRQ_RAWSTAT */
 329         return s->level;
 330     case 2: /* IRQ_ENABLESET */
 331         return s->irq_enabled;
 332     case 4: /* INT_SOFTSET */
 333         return s->level & 1;
 334     case 8: /* FRQ_STATUS */
 335         return s->level & s->fiq_enabled;
 336     case 9: /* FRQ_RAWSTAT */
 337         return s->level;
 338     case 10: /* FRQ_ENABLESET */
 339         return s->fiq_enabled;
 340     case 3: /* IRQ_ENABLECLR */
 341     case 5: /* INT_SOFTCLR */
 342     case 11: /* FRQ_ENABLECLR */
 343     default:
 344         printf ("icp_pic_read: Bad register offset 0x%x\n", (int)offset);
 345         return 0;
 346     }
 347 }
 348
 349 static void icp_pic_write(void *opaque, hwaddr offset,
 350                           uint64_t value, unsigned size)
 351 {
 352     icp_pic_state *s = (icp_pic_state *)opaque;
 353
 354     switch (offset >> 2) {
 355     case 2: /* IRQ_ENABLESET */
 356         s->irq_enabled |= value;
 357         break;
 358     case 3: /* IRQ_ENABLECLR */
 359         s->irq_enabled &= ~value;
 360         break;
 361     case 4: /* INT_SOFTSET */
 362         if (value & 1)
 363             icp_pic_set_irq(s, 0, 1);
 364         break;
 365     case 5: /* INT_SOFTCLR */
 366         if (value & 1)
 367             icp_pic_set_irq(s, 0, 0);
 368         break;
 369     case 10: /* FRQ_ENABLESET */
 370         s->fiq_enabled |= value;
 371         break;
 372     case 11: /* FRQ_ENABLECLR */
 373         s->fiq_enabled &= ~value;
 374         break;
 375     case 0: /* IRQ_STATUS */
 376     case 1: /* IRQ_RAWSTAT */
 377     case 8: /* FRQ_STATUS */
 378     case 9: /* FRQ_RAWSTAT */
 379     default:
 380         printf ("icp_pic_write: Bad register offset 0x%x\n", (int)offset);
 381         return;
 382     }
 383     icp_pic_update(s);
 384 }
 385
 386 static const MemoryRegionOps icp_pic_ops = {
 387     .read = icp_pic_read,
 388     .write = icp_pic_write,
 389     .endianness = DEVICE_NATIVE_ENDIAN,
 390 };
 391
 392 static int icp_pic_init(SysBusDevice *sbd)
 393 {
 394     DeviceState *dev = DEVICE(sbd);
 395     icp_pic_state *s = INTEGRATOR_PIC(dev);
 396
 397     qdev_init_gpio_in(dev, icp_pic_set_irq, 32);
 398     sysbus_init_irq(sbd, &s->parent_irq);
 399     sysbus_init_irq(sbd, &s->parent_fiq);
 400     memory_region_init_io(&s->iomem, OBJECT(s), &icp_pic_ops, s,
 401                           "icp-pic", 0x00800000);
 402     sysbus_init_mmio(sbd, &s->iomem);
 403     return 0;
 404 }
 405
 406 /* CP control registers.  */
 407
 408 static uint64_t icp_control_read(void *opaque, hwaddr offset,
 409                                  unsigned size)
 410 {
 411     switch (offset >> 2) {
 412     case 0: /* CP_IDFIELD */
 413         return 0x41034003;
 414     case 1: /* CP_FLASHPROG */
 415         return 0;
 416     case 2: /* CP_INTREG */
 417         return 0;
 418     case 3: /* CP_DECODE */
 419         return 0x11;
 420     default:
 421         hw_error("icp_control_read: Bad offset %x\n", (int)offset);
 422         return 0;
 423     }
 424 }
 425
 426 static void icp_control_write(void *opaque, hwaddr offset,
 427                           uint64_t value, unsigned size)
 428 {
 429     switch (offset >> 2) {
 430     case 1: /* CP_FLASHPROG */
 431     case 2: /* CP_INTREG */
 432     case 3: /* CP_DECODE */
 433         /* Nothing interesting implemented yet.  */
 434         break;
 435     default:
 436         hw_error("icp_control_write: Bad offset %x\n", (int)offset);
 437     }
 438 }
 439
 440 static const MemoryRegionOps icp_control_ops = {
 441     .read = icp_control_read,
 442     .write = icp_control_write,
 443     .endianness = DEVICE_NATIVE_ENDIAN,
 444 };
 445
 446 static void icp_control_init(hwaddr base)
 447 {
 448     MemoryRegion *io;
 449
 450     io = (MemoryRegion *)g_malloc0(sizeof(MemoryRegion));
 451     memory_region_init_io(io, NULL, &icp_control_ops, NULL,
 452                           "control", 0x00800000);
 453     memory_region_add_subregion(get_system_memory(), base, io);
 454     /* ??? Save/restore.  */
 455 }
 456
 457
 458 /* Board init.  */
 459
 460 static struct arm_boot_info integrator_binfo = {
 461     .loader_start = 0x0,
 462     .board_id = 0x113,
 463 };
 464
 465 static void integratorcp_init(MachineState *machine)
 466 {
 467     ram_addr_t ram_size = machine->ram_size;
 468     const char *cpu_model = machine->cpu_model;
 469     const char *kernel_filename = machine->kernel_filename;
 470     const char *kernel_cmdline = machine->kernel_cmdline;
 471     const char *initrd_filename = machine->initrd_filename;
 472     ARMCPU *cpu;
 473     MemoryRegion *address_space_mem = get_system_memory();
 474     MemoryRegion *ram = g_new(MemoryRegion, 1);
 475     MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
 476     qemu_irq pic[32];
 477     DeviceState *dev;
 478     int i;
 479
 480     if (!cpu_model) {
 481         cpu_model = "arm926";
 482     }
 483     cpu = cpu_arm_init(cpu_model);
 484     if (!cpu) {
 485         fprintf(stderr, "Unable to find CPU definition\n");
 486         exit(1);
 487     }
 488
 489     memory_region_init_ram(ram, NULL, "integrator.ram", ram_size, &error_abort);
 490     vmstate_register_ram_global(ram);
 491     /* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash.  */
 492     /* ??? RAM should repeat to fill physical memory space.  */
 493     /* SDRAM at address zero*/
 494     memory_region_add_subregion(address_space_mem, 0, ram);
 495     /* And again at address 0x80000000 */
 496     memory_region_init_alias(ram_alias, NULL, "ram.alias", ram, 0, ram_size);
 497     memory_region_add_subregion(address_space_mem, 0x80000000, ram_alias);
 498
 499     dev = qdev_create(NULL, TYPE_INTEGRATOR_CM);
 500     qdev_prop_set_uint32(dev, "memsz", ram_size >> 20);
 501     qdev_init_nofail(dev);
 502     sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000);
 503
 504     dev = sysbus_create_varargs(TYPE_INTEGRATOR_PIC, 0x14000000,
 505                                 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ),
 506                                 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ),
 507                                 NULL);
 508     for (i = 0; i < 32; i++) {
 509         pic[i] = qdev_get_gpio_in(dev, i);
 510     }
 511     sysbus_create_simple(TYPE_INTEGRATOR_PIC, 0xca000000, pic[26]);
 512     sysbus_create_varargs("integrator_pit", 0x13000000,
 513                           pic[5], pic[6], pic[7], NULL);
 514     sysbus_create_simple("pl031", 0x15000000, pic[8]);
 515     sysbus_create_simple("pl011", 0x16000000, pic[1]);
 516     sysbus_create_simple("pl011", 0x17000000, pic[2]);
 517     icp_control_init(0xcb000000);
 518     sysbus_create_simple("pl050_keyboard", 0x18000000, pic[3]);
 519     sysbus_create_simple("pl050_mouse", 0x19000000, pic[4]);
 520     sysbus_create_simple(TYPE_INTEGRATOR_DEBUG, 0x1a000000, 0);
 521     sysbus_create_varargs("pl181", 0x1c000000, pic[23], pic[24], NULL);
 522     if (nd_table[0].used)
 523         smc91c111_init(&nd_table[0], 0xc8000000, pic[27]);
 524
 525     sysbus_create_simple("pl110", 0xc0000000, pic[22]);
 526
 527     integrator_binfo.ram_size = ram_size;
 528     integrator_binfo.kernel_filename = kernel_filename;
 529     integrator_binfo.kernel_cmdline = kernel_cmdline;
 530     integrator_binfo.initrd_filename = initrd_filename;
 531     arm_load_kernel(cpu, &integrator_binfo);
 532 }
 533
 534 static QEMUMachine integratorcp_machine = {
 535     .name = "integratorcp",
 536     .desc = "ARM Integrator/CP (ARM926EJ-S)",
 537     .init = integratorcp_init,
 538 };
 539
 540 static void integratorcp_machine_init(void)
 541 {
 542     qemu_register_machine(&integratorcp_machine);
 543 }
 544
 545 machine_init(integratorcp_machine_init);
 546
 547 static Property core_properties[] = {
 548     DEFINE_PROP_UINT32("memsz", IntegratorCMState, memsz, 0),
 549     DEFINE_PROP_END_OF_LIST(),
 550 };
 551
 552 static void core_class_init(ObjectClass *klass, void *data)
 553 {
 554     DeviceClass *dc = DEVICE_CLASS(klass);
 555     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 556
 557     k->init = integratorcm_init;
 558     dc->props = core_properties;
 559 }
 560
 561 static const TypeInfo core_info = {
 562     .name          = TYPE_INTEGRATOR_CM,
 563     .parent        = TYPE_SYS_BUS_DEVICE,
 564     .instance_size = sizeof(IntegratorCMState),
 565     .class_init    = core_class_init,
 566 };
 567
 568 static void icp_pic_class_init(ObjectClass *klass, void *data)
 569 {
 570     SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
 571
 572     sdc->init = icp_pic_init;
 573 }
 574
 575 static const TypeInfo icp_pic_info = {
 576     .name          = TYPE_INTEGRATOR_PIC,
 577     .parent        = TYPE_SYS_BUS_DEVICE,
 578     .instance_size = sizeof(icp_pic_state),
 579     .class_init    = icp_pic_class_init,
 580 };
 581
 582 static void integratorcp_register_types(void)
 583 {
 584     type_register_static(&icp_pic_info);
 585     type_register_static(&core_info);
 586 }
 587
 588 type_init(integratorcp_register_types)