2 * ARM mach-virt emulation
4 * Copyright (c) 2013 Linaro Limited
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
18 * Emulate a virtual board which works by passing Linux all the information
19 * it needs about what devices are present via the device tree.
20 * There are some restrictions about what we can do here:
21 * + we can only present devices whose Linux drivers will work based
22 * purely on the device tree with no platform data at all
23 * + we want to present a very stripped-down minimalist platform,
24 * both because this reduces the security attack surface from the guest
25 * and also because it reduces our exposure to being broken when
26 * the kernel updates its device tree bindings and requires further
27 * information in a device binding that we aren't providing.
28 * This is essentially the same approach kvmtool uses.
31 #include "qemu/osdep.h"
32 #include "qapi/error.h"
33 #include "hw/sysbus.h"
34 #include "hw/arm/arm.h"
35 #include "hw/arm/primecell.h"
36 #include "hw/arm/virt.h"
37 #include "hw/devices.h"
39 #include "sysemu/block-backend.h"
40 #include "sysemu/device_tree.h"
41 #include "sysemu/numa.h"
42 #include "sysemu/sysemu.h"
43 #include "sysemu/kvm.h"
44 #include "hw/boards.h"
45 #include "hw/loader.h"
46 #include "exec/address-spaces.h"
47 #include "qemu/bitops.h"
48 #include "qemu/error-report.h"
49 #include "hw/pci-host/gpex.h"
50 #include "hw/arm/virt-acpi-build.h"
51 #include "hw/arm/sysbus-fdt.h"
52 #include "hw/platform-bus.h"
53 #include "hw/arm/fdt.h"
54 #include "hw/intc/arm_gic_common.h"
56 #include "hw/smbios/smbios.h"
57 #include "qapi/visitor.h"
58 #include "standard-headers/linux/input.h"
60 /* Number of external interrupt lines to configure the GIC with */
63 #define PLATFORM_BUS_NUM_IRQS 64
65 static ARMPlatformBusSystemParams platform_bus_params
;
67 typedef struct VirtBoardInfo
{
68 struct arm_boot_info bootinfo
;
69 const char *cpu_model
;
70 const MemMapEntry
*memmap
;
75 uint32_t clock_phandle
;
83 VirtBoardInfo
*daughterboard
;
93 #define TYPE_VIRT_MACHINE MACHINE_TYPE_NAME("virt")
94 #define VIRT_MACHINE(obj) \
95 OBJECT_CHECK(VirtMachineState, (obj), TYPE_VIRT_MACHINE)
96 #define VIRT_MACHINE_GET_CLASS(obj) \
97 OBJECT_GET_CLASS(VirtMachineClass, obj, TYPE_VIRT_MACHINE)
98 #define VIRT_MACHINE_CLASS(klass) \
99 OBJECT_CLASS_CHECK(VirtMachineClass, klass, TYPE_VIRT_MACHINE)
102 #define DEFINE_VIRT_MACHINE(major, minor) \
103 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
106 MachineClass *mc = MACHINE_CLASS(oc); \
107 virt_machine_##major##_##minor##_options(mc); \
108 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \
110 static const TypeInfo machvirt_##major##_##minor##_info = { \
111 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
112 .parent = TYPE_VIRT_MACHINE, \
113 .instance_init = virt_##major##_##minor##_instance_init, \
114 .class_init = virt_##major##_##minor##_class_init, \
116 static void machvirt_machine_##major##_##minor##_init(void) \
118 type_register_static(&machvirt_##major##_##minor##_info); \
120 type_init(machvirt_machine_##major##_##minor##_init);
123 /* RAM limit in GB. Since VIRT_MEM starts at the 1GB mark, this means
124 * RAM can go up to the 256GB mark, leaving 256GB of the physical
125 * address space unallocated and free for future use between 256G and 512G.
126 * If we need to provide more RAM to VMs in the future then we need to:
127 * * allocate a second bank of RAM starting at 2TB and working up
128 * * fix the DT and ACPI table generation code in QEMU to correctly
129 * report two split lumps of RAM to the guest
130 * * fix KVM in the host kernel to allow guests with >40 bit address spaces
131 * (We don't want to fill all the way up to 512GB with RAM because
132 * we might want it for non-RAM purposes later. Conversely it seems
133 * reasonable to assume that anybody configuring a VM with a quarter
134 * of a terabyte of RAM will be doing it on a host with more than a
135 * terabyte of physical address space.)
137 #define RAMLIMIT_GB 255
138 #define RAMLIMIT_BYTES (RAMLIMIT_GB * 1024ULL * 1024 * 1024)
140 /* Addresses and sizes of our components.
141 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
142 * 128MB..256MB is used for miscellaneous device I/O.
143 * 256MB..1GB is reserved for possible future PCI support (ie where the
144 * PCI memory window will go if we add a PCI host controller).
145 * 1GB and up is RAM (which may happily spill over into the
146 * high memory region beyond 4GB).
147 * This represents a compromise between how much RAM can be given to
148 * a 32 bit VM and leaving space for expansion and in particular for PCI.
149 * Note that devices should generally be placed at multiples of 0x10000,
150 * to accommodate guests using 64K pages.
152 static const MemMapEntry a15memmap
[] = {
153 /* Space up to 0x8000000 is reserved for a boot ROM */
154 [VIRT_FLASH
] = { 0, 0x08000000 },
155 [VIRT_CPUPERIPHS
] = { 0x08000000, 0x00020000 },
156 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
157 [VIRT_GIC_DIST
] = { 0x08000000, 0x00010000 },
158 [VIRT_GIC_CPU
] = { 0x08010000, 0x00010000 },
159 [VIRT_GIC_V2M
] = { 0x08020000, 0x00001000 },
160 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
161 [VIRT_GIC_ITS
] = { 0x08080000, 0x00020000 },
162 /* This redistributor space allows up to 2*64kB*123 CPUs */
163 [VIRT_GIC_REDIST
] = { 0x080A0000, 0x00F60000 },
164 [VIRT_UART
] = { 0x09000000, 0x00001000 },
165 [VIRT_RTC
] = { 0x09010000, 0x00001000 },
166 [VIRT_FW_CFG
] = { 0x09020000, 0x00000018 },
167 [VIRT_GPIO
] = { 0x09030000, 0x00001000 },
168 [VIRT_SECURE_UART
] = { 0x09040000, 0x00001000 },
169 [VIRT_MMIO
] = { 0x0a000000, 0x00000200 },
170 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
171 [VIRT_PLATFORM_BUS
] = { 0x0c000000, 0x02000000 },
172 [VIRT_SECURE_MEM
] = { 0x0e000000, 0x01000000 },
173 [VIRT_PCIE_MMIO
] = { 0x10000000, 0x2eff0000 },
174 [VIRT_PCIE_PIO
] = { 0x3eff0000, 0x00010000 },
175 [VIRT_PCIE_ECAM
] = { 0x3f000000, 0x01000000 },
176 [VIRT_MEM
] = { 0x40000000, RAMLIMIT_BYTES
},
177 /* Second PCIe window, 512GB wide at the 512GB boundary */
178 [VIRT_PCIE_MMIO_HIGH
] = { 0x8000000000ULL
, 0x8000000000ULL
},
181 static const int a15irqmap
[] = {
184 [VIRT_PCIE
] = 3, /* ... to 6 */
186 [VIRT_SECURE_UART
] = 8,
187 [VIRT_MMIO
] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
188 [VIRT_GIC_V2M
] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
189 [VIRT_PLATFORM_BUS
] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
192 static VirtBoardInfo machines
[] = {
194 .cpu_model
= "cortex-a15",
199 .cpu_model
= "cortex-a53",
204 .cpu_model
= "cortex-a57",
215 static VirtBoardInfo
*find_machine_info(const char *cpu
)
219 for (i
= 0; i
< ARRAY_SIZE(machines
); i
++) {
220 if (strcmp(cpu
, machines
[i
].cpu_model
) == 0) {
227 static void create_fdt(VirtBoardInfo
*vbi
)
229 void *fdt
= create_device_tree(&vbi
->fdt_size
);
232 error_report("create_device_tree() failed");
239 qemu_fdt_setprop_string(fdt
, "/", "compatible", "linux,dummy-virt");
240 qemu_fdt_setprop_cell(fdt
, "/", "#address-cells", 0x2);
241 qemu_fdt_setprop_cell(fdt
, "/", "#size-cells", 0x2);
244 * /chosen and /memory nodes must exist for load_dtb
245 * to fill in necessary properties later
247 qemu_fdt_add_subnode(fdt
, "/chosen");
248 qemu_fdt_add_subnode(fdt
, "/memory");
249 qemu_fdt_setprop_string(fdt
, "/memory", "device_type", "memory");
251 /* Clock node, for the benefit of the UART. The kernel device tree
252 * binding documentation claims the PL011 node clock properties are
253 * optional but in practice if you omit them the kernel refuses to
254 * probe for the device.
256 vbi
->clock_phandle
= qemu_fdt_alloc_phandle(fdt
);
257 qemu_fdt_add_subnode(fdt
, "/apb-pclk");
258 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "compatible", "fixed-clock");
259 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "#clock-cells", 0x0);
260 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "clock-frequency", 24000000);
261 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "clock-output-names",
263 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "phandle", vbi
->clock_phandle
);
267 static void fdt_add_psci_node(const VirtBoardInfo
*vbi
)
269 uint32_t cpu_suspend_fn
;
273 void *fdt
= vbi
->fdt
;
274 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(0));
276 if (!vbi
->using_psci
) {
280 qemu_fdt_add_subnode(fdt
, "/psci");
281 if (armcpu
->psci_version
== 2) {
282 const char comp
[] = "arm,psci-0.2\0arm,psci";
283 qemu_fdt_setprop(fdt
, "/psci", "compatible", comp
, sizeof(comp
));
285 cpu_off_fn
= QEMU_PSCI_0_2_FN_CPU_OFF
;
286 if (arm_feature(&armcpu
->env
, ARM_FEATURE_AARCH64
)) {
287 cpu_suspend_fn
= QEMU_PSCI_0_2_FN64_CPU_SUSPEND
;
288 cpu_on_fn
= QEMU_PSCI_0_2_FN64_CPU_ON
;
289 migrate_fn
= QEMU_PSCI_0_2_FN64_MIGRATE
;
291 cpu_suspend_fn
= QEMU_PSCI_0_2_FN_CPU_SUSPEND
;
292 cpu_on_fn
= QEMU_PSCI_0_2_FN_CPU_ON
;
293 migrate_fn
= QEMU_PSCI_0_2_FN_MIGRATE
;
296 qemu_fdt_setprop_string(fdt
, "/psci", "compatible", "arm,psci");
298 cpu_suspend_fn
= QEMU_PSCI_0_1_FN_CPU_SUSPEND
;
299 cpu_off_fn
= QEMU_PSCI_0_1_FN_CPU_OFF
;
300 cpu_on_fn
= QEMU_PSCI_0_1_FN_CPU_ON
;
301 migrate_fn
= QEMU_PSCI_0_1_FN_MIGRATE
;
304 /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer
305 * to the instruction that should be used to invoke PSCI functions.
306 * However, the device tree binding uses 'method' instead, so that is
307 * what we should use here.
309 qemu_fdt_setprop_string(fdt
, "/psci", "method", "hvc");
311 qemu_fdt_setprop_cell(fdt
, "/psci", "cpu_suspend", cpu_suspend_fn
);
312 qemu_fdt_setprop_cell(fdt
, "/psci", "cpu_off", cpu_off_fn
);
313 qemu_fdt_setprop_cell(fdt
, "/psci", "cpu_on", cpu_on_fn
);
314 qemu_fdt_setprop_cell(fdt
, "/psci", "migrate", migrate_fn
);
317 static void fdt_add_timer_nodes(const VirtBoardInfo
*vbi
, int gictype
)
319 /* Note that on A15 h/w these interrupts are level-triggered,
320 * but for the GIC implementation provided by both QEMU and KVM
321 * they are edge-triggered.
324 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
;
327 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
328 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
329 (1 << vbi
->smp_cpus
) - 1);
332 qemu_fdt_add_subnode(vbi
->fdt
, "/timer");
334 armcpu
= ARM_CPU(qemu_get_cpu(0));
335 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
336 const char compat
[] = "arm,armv8-timer\0arm,armv7-timer";
337 qemu_fdt_setprop(vbi
->fdt
, "/timer", "compatible",
338 compat
, sizeof(compat
));
340 qemu_fdt_setprop_string(vbi
->fdt
, "/timer", "compatible",
343 qemu_fdt_setprop(vbi
->fdt
, "/timer", "always-on", NULL
, 0);
344 qemu_fdt_setprop_cells(vbi
->fdt
, "/timer", "interrupts",
345 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_S_EL1_IRQ
, irqflags
,
346 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL1_IRQ
, irqflags
,
347 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_VIRT_IRQ
, irqflags
,
348 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL2_IRQ
, irqflags
);
351 static void fdt_add_cpu_nodes(const VirtBoardInfo
*vbi
)
358 * From Documentation/devicetree/bindings/arm/cpus.txt
359 * On ARM v8 64-bit systems value should be set to 2,
360 * that corresponds to the MPIDR_EL1 register size.
361 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
362 * in the system, #address-cells can be set to 1, since
363 * MPIDR_EL1[63:32] bits are not used for CPUs
366 * Here we actually don't know whether our system is 32- or 64-bit one.
367 * The simplest way to go is to examine affinity IDs of all our CPUs. If
368 * at least one of them has Aff3 populated, we set #address-cells to 2.
370 for (cpu
= 0; cpu
< vbi
->smp_cpus
; cpu
++) {
371 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
373 if (armcpu
->mp_affinity
& ARM_AFF3_MASK
) {
379 qemu_fdt_add_subnode(vbi
->fdt
, "/cpus");
380 qemu_fdt_setprop_cell(vbi
->fdt
, "/cpus", "#address-cells", addr_cells
);
381 qemu_fdt_setprop_cell(vbi
->fdt
, "/cpus", "#size-cells", 0x0);
383 for (cpu
= vbi
->smp_cpus
- 1; cpu
>= 0; cpu
--) {
384 char *nodename
= g_strdup_printf("/cpus/cpu@%d", cpu
);
385 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
387 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
388 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "device_type", "cpu");
389 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "compatible",
390 armcpu
->dtb_compatible
);
392 if (vbi
->using_psci
&& vbi
->smp_cpus
> 1) {
393 qemu_fdt_setprop_string(vbi
->fdt
, nodename
,
394 "enable-method", "psci");
397 if (addr_cells
== 2) {
398 qemu_fdt_setprop_u64(vbi
->fdt
, nodename
, "reg",
399 armcpu
->mp_affinity
);
401 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "reg",
402 armcpu
->mp_affinity
);
405 for (i
= 0; i
< nb_numa_nodes
; i
++) {
406 if (test_bit(cpu
, numa_info
[i
].node_cpu
)) {
407 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "numa-node-id", i
);
415 static void fdt_add_v2m_gic_node(VirtBoardInfo
*vbi
)
417 vbi
->v2m_phandle
= qemu_fdt_alloc_phandle(vbi
->fdt
);
418 qemu_fdt_add_subnode(vbi
->fdt
, "/intc/v2m");
419 qemu_fdt_setprop_string(vbi
->fdt
, "/intc/v2m", "compatible",
420 "arm,gic-v2m-frame");
421 qemu_fdt_setprop(vbi
->fdt
, "/intc/v2m", "msi-controller", NULL
, 0);
422 qemu_fdt_setprop_sized_cells(vbi
->fdt
, "/intc/v2m", "reg",
423 2, vbi
->memmap
[VIRT_GIC_V2M
].base
,
424 2, vbi
->memmap
[VIRT_GIC_V2M
].size
);
425 qemu_fdt_setprop_cell(vbi
->fdt
, "/intc/v2m", "phandle", vbi
->v2m_phandle
);
428 static void fdt_add_gic_node(VirtBoardInfo
*vbi
, int type
)
430 vbi
->gic_phandle
= qemu_fdt_alloc_phandle(vbi
->fdt
);
431 qemu_fdt_setprop_cell(vbi
->fdt
, "/", "interrupt-parent", vbi
->gic_phandle
);
433 qemu_fdt_add_subnode(vbi
->fdt
, "/intc");
434 qemu_fdt_setprop_cell(vbi
->fdt
, "/intc", "#interrupt-cells", 3);
435 qemu_fdt_setprop(vbi
->fdt
, "/intc", "interrupt-controller", NULL
, 0);
436 qemu_fdt_setprop_cell(vbi
->fdt
, "/intc", "#address-cells", 0x2);
437 qemu_fdt_setprop_cell(vbi
->fdt
, "/intc", "#size-cells", 0x2);
438 qemu_fdt_setprop(vbi
->fdt
, "/intc", "ranges", NULL
, 0);
440 qemu_fdt_setprop_string(vbi
->fdt
, "/intc", "compatible",
442 qemu_fdt_setprop_sized_cells(vbi
->fdt
, "/intc", "reg",
443 2, vbi
->memmap
[VIRT_GIC_DIST
].base
,
444 2, vbi
->memmap
[VIRT_GIC_DIST
].size
,
445 2, vbi
->memmap
[VIRT_GIC_REDIST
].base
,
446 2, vbi
->memmap
[VIRT_GIC_REDIST
].size
);
448 /* 'cortex-a15-gic' means 'GIC v2' */
449 qemu_fdt_setprop_string(vbi
->fdt
, "/intc", "compatible",
450 "arm,cortex-a15-gic");
451 qemu_fdt_setprop_sized_cells(vbi
->fdt
, "/intc", "reg",
452 2, vbi
->memmap
[VIRT_GIC_DIST
].base
,
453 2, vbi
->memmap
[VIRT_GIC_DIST
].size
,
454 2, vbi
->memmap
[VIRT_GIC_CPU
].base
,
455 2, vbi
->memmap
[VIRT_GIC_CPU
].size
);
458 qemu_fdt_setprop_cell(vbi
->fdt
, "/intc", "phandle", vbi
->gic_phandle
);
461 static void fdt_add_pmu_nodes(const VirtBoardInfo
*vbi
, int gictype
)
465 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
468 armcpu
= ARM_CPU(cpu
);
469 if (!armcpu
->has_pmu
||
470 !kvm_arm_pmu_create(cpu
, PPI(VIRTUAL_PMU_IRQ
))) {
476 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
477 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
478 (1 << vbi
->smp_cpus
) - 1);
481 armcpu
= ARM_CPU(qemu_get_cpu(0));
482 qemu_fdt_add_subnode(vbi
->fdt
, "/pmu");
483 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
484 const char compat
[] = "arm,armv8-pmuv3";
485 qemu_fdt_setprop(vbi
->fdt
, "/pmu", "compatible",
486 compat
, sizeof(compat
));
487 qemu_fdt_setprop_cells(vbi
->fdt
, "/pmu", "interrupts",
488 GIC_FDT_IRQ_TYPE_PPI
, VIRTUAL_PMU_IRQ
, irqflags
);
492 static void create_v2m(VirtBoardInfo
*vbi
, qemu_irq
*pic
)
495 int irq
= vbi
->irqmap
[VIRT_GIC_V2M
];
498 dev
= qdev_create(NULL
, "arm-gicv2m");
499 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vbi
->memmap
[VIRT_GIC_V2M
].base
);
500 qdev_prop_set_uint32(dev
, "base-spi", irq
);
501 qdev_prop_set_uint32(dev
, "num-spi", NUM_GICV2M_SPIS
);
502 qdev_init_nofail(dev
);
504 for (i
= 0; i
< NUM_GICV2M_SPIS
; i
++) {
505 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
, pic
[irq
+ i
]);
508 fdt_add_v2m_gic_node(vbi
);
511 static void create_gic(VirtBoardInfo
*vbi
, qemu_irq
*pic
, int type
, bool secure
)
513 /* We create a standalone GIC */
515 SysBusDevice
*gicbusdev
;
519 gictype
= (type
== 3) ? gicv3_class_name() : gic_class_name();
521 gicdev
= qdev_create(NULL
, gictype
);
522 qdev_prop_set_uint32(gicdev
, "revision", type
);
523 qdev_prop_set_uint32(gicdev
, "num-cpu", smp_cpus
);
524 /* Note that the num-irq property counts both internal and external
525 * interrupts; there are always 32 of the former (mandated by GIC spec).
527 qdev_prop_set_uint32(gicdev
, "num-irq", NUM_IRQS
+ 32);
528 if (!kvm_irqchip_in_kernel()) {
529 qdev_prop_set_bit(gicdev
, "has-security-extensions", secure
);
531 qdev_init_nofail(gicdev
);
532 gicbusdev
= SYS_BUS_DEVICE(gicdev
);
533 sysbus_mmio_map(gicbusdev
, 0, vbi
->memmap
[VIRT_GIC_DIST
].base
);
535 sysbus_mmio_map(gicbusdev
, 1, vbi
->memmap
[VIRT_GIC_REDIST
].base
);
537 sysbus_mmio_map(gicbusdev
, 1, vbi
->memmap
[VIRT_GIC_CPU
].base
);
540 /* Wire the outputs from each CPU's generic timer to the
541 * appropriate GIC PPI inputs, and the GIC's IRQ output to
542 * the CPU's IRQ input.
544 for (i
= 0; i
< smp_cpus
; i
++) {
545 DeviceState
*cpudev
= DEVICE(qemu_get_cpu(i
));
546 int ppibase
= NUM_IRQS
+ i
* GIC_INTERNAL
+ GIC_NR_SGIS
;
548 /* Mapping from the output timer irq lines from the CPU to the
549 * GIC PPI inputs we use for the virt board.
551 const int timer_irq
[] = {
552 [GTIMER_PHYS
] = ARCH_TIMER_NS_EL1_IRQ
,
553 [GTIMER_VIRT
] = ARCH_TIMER_VIRT_IRQ
,
554 [GTIMER_HYP
] = ARCH_TIMER_NS_EL2_IRQ
,
555 [GTIMER_SEC
] = ARCH_TIMER_S_EL1_IRQ
,
558 for (irq
= 0; irq
< ARRAY_SIZE(timer_irq
); irq
++) {
559 qdev_connect_gpio_out(cpudev
, irq
,
560 qdev_get_gpio_in(gicdev
,
561 ppibase
+ timer_irq
[irq
]));
564 sysbus_connect_irq(gicbusdev
, i
, qdev_get_gpio_in(cpudev
, ARM_CPU_IRQ
));
565 sysbus_connect_irq(gicbusdev
, i
+ smp_cpus
,
566 qdev_get_gpio_in(cpudev
, ARM_CPU_FIQ
));
569 for (i
= 0; i
< NUM_IRQS
; i
++) {
570 pic
[i
] = qdev_get_gpio_in(gicdev
, i
);
573 fdt_add_gic_node(vbi
, type
);
576 create_v2m(vbi
, pic
);
580 static void create_uart(const VirtBoardInfo
*vbi
, qemu_irq
*pic
, int uart
,
581 MemoryRegion
*mem
, CharDriverState
*chr
)
584 hwaddr base
= vbi
->memmap
[uart
].base
;
585 hwaddr size
= vbi
->memmap
[uart
].size
;
586 int irq
= vbi
->irqmap
[uart
];
587 const char compat
[] = "arm,pl011\0arm,primecell";
588 const char clocknames
[] = "uartclk\0apb_pclk";
589 DeviceState
*dev
= qdev_create(NULL
, "pl011");
590 SysBusDevice
*s
= SYS_BUS_DEVICE(dev
);
592 qdev_prop_set_chr(dev
, "chardev", chr
);
593 qdev_init_nofail(dev
);
594 memory_region_add_subregion(mem
, base
,
595 sysbus_mmio_get_region(s
, 0));
596 sysbus_connect_irq(s
, 0, pic
[irq
]);
598 nodename
= g_strdup_printf("/pl011@%" PRIx64
, base
);
599 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
600 /* Note that we can't use setprop_string because of the embedded NUL */
601 qemu_fdt_setprop(vbi
->fdt
, nodename
, "compatible",
602 compat
, sizeof(compat
));
603 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
605 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "interrupts",
606 GIC_FDT_IRQ_TYPE_SPI
, irq
,
607 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
608 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "clocks",
609 vbi
->clock_phandle
, vbi
->clock_phandle
);
610 qemu_fdt_setprop(vbi
->fdt
, nodename
, "clock-names",
611 clocknames
, sizeof(clocknames
));
613 if (uart
== VIRT_UART
) {
614 qemu_fdt_setprop_string(vbi
->fdt
, "/chosen", "stdout-path", nodename
);
616 /* Mark as not usable by the normal world */
617 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "status", "disabled");
618 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "secure-status", "okay");
624 static void create_rtc(const VirtBoardInfo
*vbi
, qemu_irq
*pic
)
627 hwaddr base
= vbi
->memmap
[VIRT_RTC
].base
;
628 hwaddr size
= vbi
->memmap
[VIRT_RTC
].size
;
629 int irq
= vbi
->irqmap
[VIRT_RTC
];
630 const char compat
[] = "arm,pl031\0arm,primecell";
632 sysbus_create_simple("pl031", base
, pic
[irq
]);
634 nodename
= g_strdup_printf("/pl031@%" PRIx64
, base
);
635 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
636 qemu_fdt_setprop(vbi
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
637 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
639 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "interrupts",
640 GIC_FDT_IRQ_TYPE_SPI
, irq
,
641 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
642 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "clocks", vbi
->clock_phandle
);
643 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "clock-names", "apb_pclk");
647 static DeviceState
*gpio_key_dev
;
648 static void virt_powerdown_req(Notifier
*n
, void *opaque
)
650 /* use gpio Pin 3 for power button event */
651 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev
, 0), 1);
654 static Notifier virt_system_powerdown_notifier
= {
655 .notify
= virt_powerdown_req
658 static void create_gpio(const VirtBoardInfo
*vbi
, qemu_irq
*pic
)
661 DeviceState
*pl061_dev
;
662 hwaddr base
= vbi
->memmap
[VIRT_GPIO
].base
;
663 hwaddr size
= vbi
->memmap
[VIRT_GPIO
].size
;
664 int irq
= vbi
->irqmap
[VIRT_GPIO
];
665 const char compat
[] = "arm,pl061\0arm,primecell";
667 pl061_dev
= sysbus_create_simple("pl061", base
, pic
[irq
]);
669 uint32_t phandle
= qemu_fdt_alloc_phandle(vbi
->fdt
);
670 nodename
= g_strdup_printf("/pl061@%" PRIx64
, base
);
671 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
672 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
674 qemu_fdt_setprop(vbi
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
675 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "#gpio-cells", 2);
676 qemu_fdt_setprop(vbi
->fdt
, nodename
, "gpio-controller", NULL
, 0);
677 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "interrupts",
678 GIC_FDT_IRQ_TYPE_SPI
, irq
,
679 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
680 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "clocks", vbi
->clock_phandle
);
681 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "clock-names", "apb_pclk");
682 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "phandle", phandle
);
684 gpio_key_dev
= sysbus_create_simple("gpio-key", -1,
685 qdev_get_gpio_in(pl061_dev
, 3));
686 qemu_fdt_add_subnode(vbi
->fdt
, "/gpio-keys");
687 qemu_fdt_setprop_string(vbi
->fdt
, "/gpio-keys", "compatible", "gpio-keys");
688 qemu_fdt_setprop_cell(vbi
->fdt
, "/gpio-keys", "#size-cells", 0);
689 qemu_fdt_setprop_cell(vbi
->fdt
, "/gpio-keys", "#address-cells", 1);
691 qemu_fdt_add_subnode(vbi
->fdt
, "/gpio-keys/poweroff");
692 qemu_fdt_setprop_string(vbi
->fdt
, "/gpio-keys/poweroff",
693 "label", "GPIO Key Poweroff");
694 qemu_fdt_setprop_cell(vbi
->fdt
, "/gpio-keys/poweroff", "linux,code",
696 qemu_fdt_setprop_cells(vbi
->fdt
, "/gpio-keys/poweroff",
697 "gpios", phandle
, 3, 0);
699 /* connect powerdown request */
700 qemu_register_powerdown_notifier(&virt_system_powerdown_notifier
);
705 static void create_virtio_devices(const VirtBoardInfo
*vbi
, qemu_irq
*pic
)
708 hwaddr size
= vbi
->memmap
[VIRT_MMIO
].size
;
710 /* We create the transports in forwards order. Since qbus_realize()
711 * prepends (not appends) new child buses, the incrementing loop below will
712 * create a list of virtio-mmio buses with decreasing base addresses.
714 * When a -device option is processed from the command line,
715 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
716 * order. The upshot is that -device options in increasing command line
717 * order are mapped to virtio-mmio buses with decreasing base addresses.
719 * When this code was originally written, that arrangement ensured that the
720 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
721 * the first -device on the command line. (The end-to-end order is a
722 * function of this loop, qbus_realize(), qbus_find_recursive(), and the
723 * guest kernel's name-to-address assignment strategy.)
725 * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
726 * the message, if not necessarily the code, of commit 70161ff336.
727 * Therefore the loop now establishes the inverse of the original intent.
729 * Unfortunately, we can't counteract the kernel change by reversing the
730 * loop; it would break existing command lines.
732 * In any case, the kernel makes no guarantee about the stability of
733 * enumeration order of virtio devices (as demonstrated by it changing
734 * between kernel versions). For reliable and stable identification
735 * of disks users must use UUIDs or similar mechanisms.
737 for (i
= 0; i
< NUM_VIRTIO_TRANSPORTS
; i
++) {
738 int irq
= vbi
->irqmap
[VIRT_MMIO
] + i
;
739 hwaddr base
= vbi
->memmap
[VIRT_MMIO
].base
+ i
* size
;
741 sysbus_create_simple("virtio-mmio", base
, pic
[irq
]);
744 /* We add dtb nodes in reverse order so that they appear in the finished
745 * device tree lowest address first.
747 * Note that this mapping is independent of the loop above. The previous
748 * loop influences virtio device to virtio transport assignment, whereas
749 * this loop controls how virtio transports are laid out in the dtb.
751 for (i
= NUM_VIRTIO_TRANSPORTS
- 1; i
>= 0; i
--) {
753 int irq
= vbi
->irqmap
[VIRT_MMIO
] + i
;
754 hwaddr base
= vbi
->memmap
[VIRT_MMIO
].base
+ i
* size
;
756 nodename
= g_strdup_printf("/virtio_mmio@%" PRIx64
, base
);
757 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
758 qemu_fdt_setprop_string(vbi
->fdt
, nodename
,
759 "compatible", "virtio,mmio");
760 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
762 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "interrupts",
763 GIC_FDT_IRQ_TYPE_SPI
, irq
,
764 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
769 static void create_one_flash(const char *name
, hwaddr flashbase
,
770 hwaddr flashsize
, const char *file
,
771 MemoryRegion
*sysmem
)
773 /* Create and map a single flash device. We use the same
774 * parameters as the flash devices on the Versatile Express board.
776 DriveInfo
*dinfo
= drive_get_next(IF_PFLASH
);
777 DeviceState
*dev
= qdev_create(NULL
, "cfi.pflash01");
778 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
779 const uint64_t sectorlength
= 256 * 1024;
782 qdev_prop_set_drive(dev
, "drive", blk_by_legacy_dinfo(dinfo
),
786 qdev_prop_set_uint32(dev
, "num-blocks", flashsize
/ sectorlength
);
787 qdev_prop_set_uint64(dev
, "sector-length", sectorlength
);
788 qdev_prop_set_uint8(dev
, "width", 4);
789 qdev_prop_set_uint8(dev
, "device-width", 2);
790 qdev_prop_set_bit(dev
, "big-endian", false);
791 qdev_prop_set_uint16(dev
, "id0", 0x89);
792 qdev_prop_set_uint16(dev
, "id1", 0x18);
793 qdev_prop_set_uint16(dev
, "id2", 0x00);
794 qdev_prop_set_uint16(dev
, "id3", 0x00);
795 qdev_prop_set_string(dev
, "name", name
);
796 qdev_init_nofail(dev
);
798 memory_region_add_subregion(sysmem
, flashbase
,
799 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0));
805 if (drive_get(IF_PFLASH
, 0, 0)) {
806 error_report("The contents of the first flash device may be "
807 "specified with -bios or with -drive if=pflash... "
808 "but you cannot use both options at once");
811 fn
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, file
);
813 error_report("Could not find ROM image '%s'", file
);
816 image_size
= load_image_mr(fn
, sysbus_mmio_get_region(sbd
, 0));
818 if (image_size
< 0) {
819 error_report("Could not load ROM image '%s'", file
);
825 static void create_flash(const VirtBoardInfo
*vbi
,
826 MemoryRegion
*sysmem
,
827 MemoryRegion
*secure_sysmem
)
829 /* Create two flash devices to fill the VIRT_FLASH space in the memmap.
830 * Any file passed via -bios goes in the first of these.
831 * sysmem is the system memory space. secure_sysmem is the secure view
832 * of the system, and the first flash device should be made visible only
833 * there. The second flash device is visible to both secure and nonsecure.
834 * If sysmem == secure_sysmem this means there is no separate Secure
835 * address space and both flash devices are generally visible.
837 hwaddr flashsize
= vbi
->memmap
[VIRT_FLASH
].size
/ 2;
838 hwaddr flashbase
= vbi
->memmap
[VIRT_FLASH
].base
;
841 create_one_flash("virt.flash0", flashbase
, flashsize
,
842 bios_name
, secure_sysmem
);
843 create_one_flash("virt.flash1", flashbase
+ flashsize
, flashsize
,
846 if (sysmem
== secure_sysmem
) {
847 /* Report both flash devices as a single node in the DT */
848 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
849 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
850 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "compatible", "cfi-flash");
851 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
852 2, flashbase
, 2, flashsize
,
853 2, flashbase
+ flashsize
, 2, flashsize
);
854 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "bank-width", 4);
857 /* Report the devices as separate nodes so we can mark one as
858 * only visible to the secure world.
860 nodename
= g_strdup_printf("/secflash@%" PRIx64
, flashbase
);
861 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
862 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "compatible", "cfi-flash");
863 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
864 2, flashbase
, 2, flashsize
);
865 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "bank-width", 4);
866 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "status", "disabled");
867 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "secure-status", "okay");
870 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
871 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
872 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "compatible", "cfi-flash");
873 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
874 2, flashbase
+ flashsize
, 2, flashsize
);
875 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "bank-width", 4);
880 static void create_fw_cfg(const VirtBoardInfo
*vbi
, AddressSpace
*as
)
882 hwaddr base
= vbi
->memmap
[VIRT_FW_CFG
].base
;
883 hwaddr size
= vbi
->memmap
[VIRT_FW_CFG
].size
;
886 fw_cfg_init_mem_wide(base
+ 8, base
, 8, base
+ 16, as
);
888 nodename
= g_strdup_printf("/fw-cfg@%" PRIx64
, base
);
889 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
890 qemu_fdt_setprop_string(vbi
->fdt
, nodename
,
891 "compatible", "qemu,fw-cfg-mmio");
892 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
897 static void create_pcie_irq_map(const VirtBoardInfo
*vbi
, uint32_t gic_phandle
,
898 int first_irq
, const char *nodename
)
901 uint32_t full_irq_map
[4 * 4 * 10] = { 0 };
902 uint32_t *irq_map
= full_irq_map
;
904 for (devfn
= 0; devfn
<= 0x18; devfn
+= 0x8) {
905 for (pin
= 0; pin
< 4; pin
++) {
906 int irq_type
= GIC_FDT_IRQ_TYPE_SPI
;
907 int irq_nr
= first_irq
+ ((pin
+ PCI_SLOT(devfn
)) % PCI_NUM_PINS
);
908 int irq_level
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
912 devfn
<< 8, 0, 0, /* devfn */
913 pin
+ 1, /* PCI pin */
914 gic_phandle
, 0, 0, irq_type
, irq_nr
, irq_level
}; /* GIC irq */
916 /* Convert map to big endian */
917 for (i
= 0; i
< 10; i
++) {
918 irq_map
[i
] = cpu_to_be32(map
[i
]);
924 qemu_fdt_setprop(vbi
->fdt
, nodename
, "interrupt-map",
925 full_irq_map
, sizeof(full_irq_map
));
927 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "interrupt-map-mask",
928 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */
932 static void create_pcie(const VirtBoardInfo
*vbi
, qemu_irq
*pic
,
935 hwaddr base_mmio
= vbi
->memmap
[VIRT_PCIE_MMIO
].base
;
936 hwaddr size_mmio
= vbi
->memmap
[VIRT_PCIE_MMIO
].size
;
937 hwaddr base_mmio_high
= vbi
->memmap
[VIRT_PCIE_MMIO_HIGH
].base
;
938 hwaddr size_mmio_high
= vbi
->memmap
[VIRT_PCIE_MMIO_HIGH
].size
;
939 hwaddr base_pio
= vbi
->memmap
[VIRT_PCIE_PIO
].base
;
940 hwaddr size_pio
= vbi
->memmap
[VIRT_PCIE_PIO
].size
;
941 hwaddr base_ecam
= vbi
->memmap
[VIRT_PCIE_ECAM
].base
;
942 hwaddr size_ecam
= vbi
->memmap
[VIRT_PCIE_ECAM
].size
;
943 hwaddr base
= base_mmio
;
944 int nr_pcie_buses
= size_ecam
/ PCIE_MMCFG_SIZE_MIN
;
945 int irq
= vbi
->irqmap
[VIRT_PCIE
];
946 MemoryRegion
*mmio_alias
;
947 MemoryRegion
*mmio_reg
;
948 MemoryRegion
*ecam_alias
;
949 MemoryRegion
*ecam_reg
;
955 dev
= qdev_create(NULL
, TYPE_GPEX_HOST
);
956 qdev_init_nofail(dev
);
958 /* Map only the first size_ecam bytes of ECAM space */
959 ecam_alias
= g_new0(MemoryRegion
, 1);
960 ecam_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0);
961 memory_region_init_alias(ecam_alias
, OBJECT(dev
), "pcie-ecam",
962 ecam_reg
, 0, size_ecam
);
963 memory_region_add_subregion(get_system_memory(), base_ecam
, ecam_alias
);
965 /* Map the MMIO window into system address space so as to expose
966 * the section of PCI MMIO space which starts at the same base address
967 * (ie 1:1 mapping for that part of PCI MMIO space visible through
970 mmio_alias
= g_new0(MemoryRegion
, 1);
971 mmio_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 1);
972 memory_region_init_alias(mmio_alias
, OBJECT(dev
), "pcie-mmio",
973 mmio_reg
, base_mmio
, size_mmio
);
974 memory_region_add_subregion(get_system_memory(), base_mmio
, mmio_alias
);
977 /* Map high MMIO space */
978 MemoryRegion
*high_mmio_alias
= g_new0(MemoryRegion
, 1);
980 memory_region_init_alias(high_mmio_alias
, OBJECT(dev
), "pcie-mmio-high",
981 mmio_reg
, base_mmio_high
, size_mmio_high
);
982 memory_region_add_subregion(get_system_memory(), base_mmio_high
,
986 /* Map IO port space */
987 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 2, base_pio
);
989 for (i
= 0; i
< GPEX_NUM_IRQS
; i
++) {
990 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
, pic
[irq
+ i
]);
993 pci
= PCI_HOST_BRIDGE(dev
);
995 for (i
= 0; i
< nb_nics
; i
++) {
996 NICInfo
*nd
= &nd_table
[i
];
999 nd
->model
= g_strdup("virtio");
1002 pci_nic_init_nofail(nd
, pci
->bus
, nd
->model
, NULL
);
1006 nodename
= g_strdup_printf("/pcie@%" PRIx64
, base
);
1007 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
1008 qemu_fdt_setprop_string(vbi
->fdt
, nodename
,
1009 "compatible", "pci-host-ecam-generic");
1010 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "device_type", "pci");
1011 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "#address-cells", 3);
1012 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "#size-cells", 2);
1013 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "bus-range", 0,
1016 if (vbi
->v2m_phandle
) {
1017 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "msi-parent",
1021 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
1022 2, base_ecam
, 2, size_ecam
);
1025 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "ranges",
1026 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1027 2, base_pio
, 2, size_pio
,
1028 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1029 2, base_mmio
, 2, size_mmio
,
1030 1, FDT_PCI_RANGE_MMIO_64BIT
,
1032 2, base_mmio_high
, 2, size_mmio_high
);
1034 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "ranges",
1035 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1036 2, base_pio
, 2, size_pio
,
1037 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1038 2, base_mmio
, 2, size_mmio
);
1041 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "#interrupt-cells", 1);
1042 create_pcie_irq_map(vbi
, vbi
->gic_phandle
, irq
, nodename
);
1047 static void create_platform_bus(VirtBoardInfo
*vbi
, qemu_irq
*pic
)
1052 ARMPlatformBusFDTParams
*fdt_params
= g_new(ARMPlatformBusFDTParams
, 1);
1053 MemoryRegion
*sysmem
= get_system_memory();
1055 platform_bus_params
.platform_bus_base
= vbi
->memmap
[VIRT_PLATFORM_BUS
].base
;
1056 platform_bus_params
.platform_bus_size
= vbi
->memmap
[VIRT_PLATFORM_BUS
].size
;
1057 platform_bus_params
.platform_bus_first_irq
= vbi
->irqmap
[VIRT_PLATFORM_BUS
];
1058 platform_bus_params
.platform_bus_num_irqs
= PLATFORM_BUS_NUM_IRQS
;
1060 fdt_params
->system_params
= &platform_bus_params
;
1061 fdt_params
->binfo
= &vbi
->bootinfo
;
1062 fdt_params
->intc
= "/intc";
1064 * register a machine init done notifier that creates the device tree
1065 * nodes of the platform bus and its children dynamic sysbus devices
1067 arm_register_platform_bus_fdt_creator(fdt_params
);
1069 dev
= qdev_create(NULL
, TYPE_PLATFORM_BUS_DEVICE
);
1070 dev
->id
= TYPE_PLATFORM_BUS_DEVICE
;
1071 qdev_prop_set_uint32(dev
, "num_irqs",
1072 platform_bus_params
.platform_bus_num_irqs
);
1073 qdev_prop_set_uint32(dev
, "mmio_size",
1074 platform_bus_params
.platform_bus_size
);
1075 qdev_init_nofail(dev
);
1076 s
= SYS_BUS_DEVICE(dev
);
1078 for (i
= 0; i
< platform_bus_params
.platform_bus_num_irqs
; i
++) {
1079 int irqn
= platform_bus_params
.platform_bus_first_irq
+ i
;
1080 sysbus_connect_irq(s
, i
, pic
[irqn
]);
1083 memory_region_add_subregion(sysmem
,
1084 platform_bus_params
.platform_bus_base
,
1085 sysbus_mmio_get_region(s
, 0));
1088 static void create_secure_ram(VirtBoardInfo
*vbi
, MemoryRegion
*secure_sysmem
)
1090 MemoryRegion
*secram
= g_new(MemoryRegion
, 1);
1092 hwaddr base
= vbi
->memmap
[VIRT_SECURE_MEM
].base
;
1093 hwaddr size
= vbi
->memmap
[VIRT_SECURE_MEM
].size
;
1095 memory_region_init_ram(secram
, NULL
, "virt.secure-ram", size
, &error_fatal
);
1096 vmstate_register_ram_global(secram
);
1097 memory_region_add_subregion(secure_sysmem
, base
, secram
);
1099 nodename
= g_strdup_printf("/secram@%" PRIx64
, base
);
1100 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
1101 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "device_type", "memory");
1102 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg", 2, base
, 2, size
);
1103 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "status", "disabled");
1104 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "secure-status", "okay");
1109 static void *machvirt_dtb(const struct arm_boot_info
*binfo
, int *fdt_size
)
1111 const VirtBoardInfo
*board
= (const VirtBoardInfo
*)binfo
;
1113 *fdt_size
= board
->fdt_size
;
1117 static void virt_build_smbios(VirtGuestInfo
*guest_info
)
1119 FWCfgState
*fw_cfg
= guest_info
->fw_cfg
;
1120 uint8_t *smbios_tables
, *smbios_anchor
;
1121 size_t smbios_tables_len
, smbios_anchor_len
;
1122 const char *product
= "QEMU Virtual Machine";
1128 if (kvm_enabled()) {
1129 product
= "KVM Virtual Machine";
1132 smbios_set_defaults("QEMU", product
,
1133 "1.0", false, true, SMBIOS_ENTRY_POINT_30
);
1135 smbios_get_tables(NULL
, 0, &smbios_tables
, &smbios_tables_len
,
1136 &smbios_anchor
, &smbios_anchor_len
);
1138 if (smbios_anchor
) {
1139 fw_cfg_add_file(fw_cfg
, "etc/smbios/smbios-tables",
1140 smbios_tables
, smbios_tables_len
);
1141 fw_cfg_add_file(fw_cfg
, "etc/smbios/smbios-anchor",
1142 smbios_anchor
, smbios_anchor_len
);
1147 void virt_guest_info_machine_done(Notifier
*notifier
, void *data
)
1149 VirtGuestInfoState
*guest_info_state
= container_of(notifier
,
1150 VirtGuestInfoState
, machine_done
);
1151 virt_acpi_setup(&guest_info_state
->info
);
1152 virt_build_smbios(&guest_info_state
->info
);
1155 static void machvirt_init(MachineState
*machine
)
1157 VirtMachineState
*vms
= VIRT_MACHINE(machine
);
1158 qemu_irq pic
[NUM_IRQS
];
1159 MemoryRegion
*sysmem
= get_system_memory();
1160 MemoryRegion
*secure_sysmem
= NULL
;
1161 int gic_version
= vms
->gic_version
;
1162 int n
, virt_max_cpus
;
1163 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
1164 const char *cpu_model
= machine
->cpu_model
;
1166 VirtGuestInfoState
*guest_info_state
= g_malloc0(sizeof *guest_info_state
);
1167 VirtGuestInfo
*guest_info
= &guest_info_state
->info
;
1169 bool firmware_loaded
= bios_name
|| drive_get(IF_PFLASH
, 0, 0);
1172 cpu_model
= "cortex-a15";
1175 /* We can probe only here because during property set
1176 * KVM is not available yet
1179 if (!kvm_enabled()) {
1180 error_report("gic-version=host requires KVM");
1184 gic_version
= kvm_arm_vgic_probe();
1186 error_report("Unable to determine GIC version supported by host");
1191 /* Separate the actual CPU model name from any appended features */
1192 cpustr
= g_strsplit(cpu_model
, ",", 2);
1194 vbi
= find_machine_info(cpustr
[0]);
1197 error_report("mach-virt: CPU %s not supported", cpustr
[0]);
1201 /* If we have an EL3 boot ROM then the assumption is that it will
1202 * implement PSCI itself, so disable QEMU's internal implementation
1203 * so it doesn't get in the way. Instead of starting secondary
1204 * CPUs in PSCI powerdown state we will start them all running and
1205 * let the boot ROM sort them out.
1206 * The usual case is that we do use QEMU's PSCI implementation.
1208 vbi
->using_psci
= !(vms
->secure
&& firmware_loaded
);
1210 /* The maximum number of CPUs depends on the GIC version, or on how
1211 * many redistributors we can fit into the memory map.
1213 if (gic_version
== 3) {
1214 virt_max_cpus
= vbi
->memmap
[VIRT_GIC_REDIST
].size
/ 0x20000;
1216 virt_max_cpus
= GIC_NCPU
;
1219 if (max_cpus
> virt_max_cpus
) {
1220 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
1221 "supported by machine 'mach-virt' (%d)",
1222 max_cpus
, virt_max_cpus
);
1226 vbi
->smp_cpus
= smp_cpus
;
1228 if (machine
->ram_size
> vbi
->memmap
[VIRT_MEM
].size
) {
1229 error_report("mach-virt: cannot model more than %dGB RAM", RAMLIMIT_GB
);
1234 if (kvm_enabled()) {
1235 error_report("mach-virt: KVM does not support Security extensions");
1239 /* The Secure view of the world is the same as the NonSecure,
1240 * but with a few extra devices. Create it as a container region
1241 * containing the system memory at low priority; any secure-only
1242 * devices go in at higher priority and take precedence.
1244 secure_sysmem
= g_new(MemoryRegion
, 1);
1245 memory_region_init(secure_sysmem
, OBJECT(machine
), "secure-memory",
1247 memory_region_add_subregion_overlap(secure_sysmem
, 0, sysmem
, -1);
1252 for (n
= 0; n
< smp_cpus
; n
++) {
1253 ObjectClass
*oc
= cpu_class_by_name(TYPE_ARM_CPU
, cpustr
[0]);
1254 CPUClass
*cc
= CPU_CLASS(oc
);
1257 char *cpuopts
= g_strdup(cpustr
[1]);
1260 error_report("Unable to find CPU definition");
1263 cpuobj
= object_new(object_class_get_name(oc
));
1265 /* Handle any CPU options specified by the user */
1266 cc
->parse_features(CPU(cpuobj
), cpuopts
, &err
);
1269 error_report_err(err
);
1274 object_property_set_bool(cpuobj
, false, "has_el3", NULL
);
1277 if (vbi
->using_psci
) {
1278 object_property_set_int(cpuobj
, QEMU_PSCI_CONDUIT_HVC
,
1279 "psci-conduit", NULL
);
1281 /* Secondary CPUs start in PSCI powered-down state */
1283 object_property_set_bool(cpuobj
, true,
1284 "start-powered-off", NULL
);
1288 if (object_property_find(cpuobj
, "reset-cbar", NULL
)) {
1289 object_property_set_int(cpuobj
, vbi
->memmap
[VIRT_CPUPERIPHS
].base
,
1290 "reset-cbar", &error_abort
);
1293 object_property_set_link(cpuobj
, OBJECT(sysmem
), "memory",
1296 object_property_set_link(cpuobj
, OBJECT(secure_sysmem
),
1297 "secure-memory", &error_abort
);
1300 object_property_set_bool(cpuobj
, true, "realized", NULL
);
1303 fdt_add_timer_nodes(vbi
, gic_version
);
1304 fdt_add_cpu_nodes(vbi
);
1305 fdt_add_psci_node(vbi
);
1307 memory_region_allocate_system_memory(ram
, NULL
, "mach-virt.ram",
1309 memory_region_add_subregion(sysmem
, vbi
->memmap
[VIRT_MEM
].base
, ram
);
1311 create_flash(vbi
, sysmem
, secure_sysmem
? secure_sysmem
: sysmem
);
1313 create_gic(vbi
, pic
, gic_version
, vms
->secure
);
1315 fdt_add_pmu_nodes(vbi
, gic_version
);
1317 create_uart(vbi
, pic
, VIRT_UART
, sysmem
, serial_hds
[0]);
1320 create_secure_ram(vbi
, secure_sysmem
);
1321 create_uart(vbi
, pic
, VIRT_SECURE_UART
, secure_sysmem
, serial_hds
[1]);
1324 create_rtc(vbi
, pic
);
1326 create_pcie(vbi
, pic
, vms
->highmem
);
1328 create_gpio(vbi
, pic
);
1330 /* Create mmio transports, so the user can create virtio backends
1331 * (which will be automatically plugged in to the transports). If
1332 * no backend is created the transport will just sit harmlessly idle.
1334 create_virtio_devices(vbi
, pic
);
1336 create_fw_cfg(vbi
, &address_space_memory
);
1337 rom_set_fw(fw_cfg_find());
1339 guest_info
->smp_cpus
= smp_cpus
;
1340 guest_info
->fw_cfg
= fw_cfg_find();
1341 guest_info
->memmap
= vbi
->memmap
;
1342 guest_info
->irqmap
= vbi
->irqmap
;
1343 guest_info
->use_highmem
= vms
->highmem
;
1344 guest_info
->gic_version
= gic_version
;
1345 guest_info_state
->machine_done
.notify
= virt_guest_info_machine_done
;
1346 qemu_add_machine_init_done_notifier(&guest_info_state
->machine_done
);
1348 vbi
->bootinfo
.ram_size
= machine
->ram_size
;
1349 vbi
->bootinfo
.kernel_filename
= machine
->kernel_filename
;
1350 vbi
->bootinfo
.kernel_cmdline
= machine
->kernel_cmdline
;
1351 vbi
->bootinfo
.initrd_filename
= machine
->initrd_filename
;
1352 vbi
->bootinfo
.nb_cpus
= smp_cpus
;
1353 vbi
->bootinfo
.board_id
= -1;
1354 vbi
->bootinfo
.loader_start
= vbi
->memmap
[VIRT_MEM
].base
;
1355 vbi
->bootinfo
.get_dtb
= machvirt_dtb
;
1356 vbi
->bootinfo
.firmware_loaded
= firmware_loaded
;
1357 arm_load_kernel(ARM_CPU(first_cpu
), &vbi
->bootinfo
);
1360 * arm_load_kernel machine init done notifier registration must
1361 * happen before the platform_bus_create call. In this latter,
1362 * another notifier is registered which adds platform bus nodes.
1363 * Notifiers are executed in registration reverse order.
1365 create_platform_bus(vbi
, pic
);
1368 static bool virt_get_secure(Object
*obj
, Error
**errp
)
1370 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1375 static void virt_set_secure(Object
*obj
, bool value
, Error
**errp
)
1377 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1379 vms
->secure
= value
;
1382 static bool virt_get_highmem(Object
*obj
, Error
**errp
)
1384 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1386 return vms
->highmem
;
1389 static void virt_set_highmem(Object
*obj
, bool value
, Error
**errp
)
1391 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1393 vms
->highmem
= value
;
1396 static char *virt_get_gic_version(Object
*obj
, Error
**errp
)
1398 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1399 const char *val
= vms
->gic_version
== 3 ? "3" : "2";
1401 return g_strdup(val
);
1404 static void virt_set_gic_version(Object
*obj
, const char *value
, Error
**errp
)
1406 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1408 if (!strcmp(value
, "3")) {
1409 vms
->gic_version
= 3;
1410 } else if (!strcmp(value
, "2")) {
1411 vms
->gic_version
= 2;
1412 } else if (!strcmp(value
, "host")) {
1413 vms
->gic_version
= 0; /* Will probe later */
1415 error_setg(errp
, "Invalid gic-version value");
1416 error_append_hint(errp
, "Valid values are 3, 2, host.\n");
1420 static void virt_machine_class_init(ObjectClass
*oc
, void *data
)
1422 MachineClass
*mc
= MACHINE_CLASS(oc
);
1424 mc
->init
= machvirt_init
;
1425 /* Start max_cpus at the maximum QEMU supports. We'll further restrict
1426 * it later in machvirt_init, where we have more information about the
1427 * configuration of the particular instance.
1429 mc
->max_cpus
= MAX_CPUMASK_BITS
;
1430 mc
->has_dynamic_sysbus
= true;
1431 mc
->block_default_type
= IF_VIRTIO
;
1433 mc
->pci_allow_0_address
= true;
1436 static const TypeInfo virt_machine_info
= {
1437 .name
= TYPE_VIRT_MACHINE
,
1438 .parent
= TYPE_MACHINE
,
1440 .instance_size
= sizeof(VirtMachineState
),
1441 .class_size
= sizeof(VirtMachineClass
),
1442 .class_init
= virt_machine_class_init
,
1445 static void machvirt_machine_init(void)
1447 type_register_static(&virt_machine_info
);
1449 type_init(machvirt_machine_init
);
1451 static void virt_2_6_instance_init(Object
*obj
)
1453 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1455 /* EL3 is disabled by default on virt: this makes us consistent
1456 * between KVM and TCG for this board, and it also allows us to
1457 * boot UEFI blobs which assume no TrustZone support.
1459 vms
->secure
= false;
1460 object_property_add_bool(obj
, "secure", virt_get_secure
,
1461 virt_set_secure
, NULL
);
1462 object_property_set_description(obj
, "secure",
1463 "Set on/off to enable/disable the ARM "
1464 "Security Extensions (TrustZone)",
1467 /* High memory is enabled by default */
1468 vms
->highmem
= true;
1469 object_property_add_bool(obj
, "highmem", virt_get_highmem
,
1470 virt_set_highmem
, NULL
);
1471 object_property_set_description(obj
, "highmem",
1472 "Set on/off to enable/disable using "
1473 "physical address space above 32 bits",
1475 /* Default GIC type is v2 */
1476 vms
->gic_version
= 2;
1477 object_property_add_str(obj
, "gic-version", virt_get_gic_version
,
1478 virt_set_gic_version
, NULL
);
1479 object_property_set_description(obj
, "gic-version",
1481 "Valid values are 2, 3 and host", NULL
);
1484 static void virt_machine_2_6_options(MachineClass
*mc
)
1488 DEFINE_VIRT_MACHINE(2, 6)