2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * * Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * * Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * * Neither the name of the Open Source and Linux Lab nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 #include "qemu/osdep.h"
30 #include "exec/helper-proto.h"
31 #include "qemu/host-utils.h"
32 #include "exec/exec-all.h"
33 #include "exec/cpu_ldst.h"
34 #include "exec/address-spaces.h"
35 #include "qemu/timer.h"
37 void xtensa_cpu_do_unaligned_access(CPUState
*cs
,
38 vaddr addr
, MMUAccessType access_type
,
39 int mmu_idx
, uintptr_t retaddr
)
41 XtensaCPU
*cpu
= XTENSA_CPU(cs
);
42 CPUXtensaState
*env
= &cpu
->env
;
44 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_UNALIGNED_EXCEPTION
) &&
45 !xtensa_option_enabled(env
->config
, XTENSA_OPTION_HW_ALIGNMENT
)) {
46 cpu_restore_state(CPU(cpu
), retaddr
);
47 HELPER(exception_cause_vaddr
)(env
,
48 env
->pc
, LOAD_STORE_ALIGNMENT_CAUSE
, addr
);
52 void tlb_fill(CPUState
*cs
, target_ulong vaddr
, MMUAccessType access_type
,
53 int mmu_idx
, uintptr_t retaddr
)
55 XtensaCPU
*cpu
= XTENSA_CPU(cs
);
56 CPUXtensaState
*env
= &cpu
->env
;
60 int ret
= xtensa_get_physical_addr(env
, true, vaddr
, access_type
, mmu_idx
,
61 &paddr
, &page_size
, &access
);
63 qemu_log_mask(CPU_LOG_MMU
, "%s(%08x, %d, %d) -> %08x, ret = %d\n",
64 __func__
, vaddr
, access_type
, mmu_idx
, paddr
, ret
);
68 vaddr
& TARGET_PAGE_MASK
,
69 paddr
& TARGET_PAGE_MASK
,
70 access
, mmu_idx
, page_size
);
72 cpu_restore_state(cs
, retaddr
);
73 HELPER(exception_cause_vaddr
)(env
, env
->pc
, ret
, vaddr
);
77 void xtensa_cpu_do_unassigned_access(CPUState
*cs
, hwaddr addr
,
78 bool is_write
, bool is_exec
, int opaque
,
81 XtensaCPU
*cpu
= XTENSA_CPU(cs
);
82 CPUXtensaState
*env
= &cpu
->env
;
84 HELPER(exception_cause_vaddr
)(env
, env
->pc
,
86 INSTR_PIF_ADDR_ERROR_CAUSE
:
87 LOAD_STORE_PIF_ADDR_ERROR_CAUSE
,
88 is_exec
? addr
: cs
->mem_io_vaddr
);
91 static void tb_invalidate_virtual_addr(CPUXtensaState
*env
, uint32_t vaddr
)
96 int ret
= xtensa_get_physical_addr(env
, false, vaddr
, 2, 0,
97 &paddr
, &page_size
, &access
);
99 tb_invalidate_phys_addr(&address_space_memory
, paddr
);
103 void HELPER(exception
)(CPUXtensaState
*env
, uint32_t excp
)
105 CPUState
*cs
= CPU(xtensa_env_get_cpu(env
));
107 cs
->exception_index
= excp
;
108 if (excp
== EXCP_DEBUG
) {
109 env
->exception_taken
= 0;
114 void HELPER(exception_cause
)(CPUXtensaState
*env
, uint32_t pc
, uint32_t cause
)
119 if (env
->sregs
[PS
] & PS_EXCM
) {
120 if (env
->config
->ndepc
) {
121 env
->sregs
[DEPC
] = pc
;
123 env
->sregs
[EPC1
] = pc
;
127 env
->sregs
[EPC1
] = pc
;
128 vector
= (env
->sregs
[PS
] & PS_UM
) ? EXC_USER
: EXC_KERNEL
;
131 env
->sregs
[EXCCAUSE
] = cause
;
132 env
->sregs
[PS
] |= PS_EXCM
;
134 HELPER(exception
)(env
, vector
);
137 void HELPER(exception_cause_vaddr
)(CPUXtensaState
*env
,
138 uint32_t pc
, uint32_t cause
, uint32_t vaddr
)
140 env
->sregs
[EXCVADDR
] = vaddr
;
141 HELPER(exception_cause
)(env
, pc
, cause
);
144 void debug_exception_env(CPUXtensaState
*env
, uint32_t cause
)
146 if (xtensa_get_cintlevel(env
) < env
->config
->debug_level
) {
147 HELPER(debug_exception
)(env
, env
->pc
, cause
);
151 void HELPER(debug_exception
)(CPUXtensaState
*env
, uint32_t pc
, uint32_t cause
)
153 unsigned level
= env
->config
->debug_level
;
156 env
->sregs
[DEBUGCAUSE
] = cause
;
157 env
->sregs
[EPC1
+ level
- 1] = pc
;
158 env
->sregs
[EPS2
+ level
- 2] = env
->sregs
[PS
];
159 env
->sregs
[PS
] = (env
->sregs
[PS
] & ~PS_INTLEVEL
) | PS_EXCM
|
160 (level
<< PS_INTLEVEL_SHIFT
);
161 HELPER(exception
)(env
, EXC_DEBUG
);
164 static void copy_window_from_phys(CPUXtensaState
*env
,
165 uint32_t window
, uint32_t phys
, uint32_t n
)
167 assert(phys
< env
->config
->nareg
);
168 if (phys
+ n
<= env
->config
->nareg
) {
169 memcpy(env
->regs
+ window
, env
->phys_regs
+ phys
,
170 n
* sizeof(uint32_t));
172 uint32_t n1
= env
->config
->nareg
- phys
;
173 memcpy(env
->regs
+ window
, env
->phys_regs
+ phys
,
174 n1
* sizeof(uint32_t));
175 memcpy(env
->regs
+ window
+ n1
, env
->phys_regs
,
176 (n
- n1
) * sizeof(uint32_t));
180 static void copy_phys_from_window(CPUXtensaState
*env
,
181 uint32_t phys
, uint32_t window
, uint32_t n
)
183 assert(phys
< env
->config
->nareg
);
184 if (phys
+ n
<= env
->config
->nareg
) {
185 memcpy(env
->phys_regs
+ phys
, env
->regs
+ window
,
186 n
* sizeof(uint32_t));
188 uint32_t n1
= env
->config
->nareg
- phys
;
189 memcpy(env
->phys_regs
+ phys
, env
->regs
+ window
,
190 n1
* sizeof(uint32_t));
191 memcpy(env
->phys_regs
, env
->regs
+ window
+ n1
,
192 (n
- n1
) * sizeof(uint32_t));
197 static inline unsigned windowbase_bound(unsigned a
, const CPUXtensaState
*env
)
199 return a
& (env
->config
->nareg
/ 4 - 1);
202 static inline unsigned windowstart_bit(unsigned a
, const CPUXtensaState
*env
)
204 return 1 << windowbase_bound(a
, env
);
207 void xtensa_sync_window_from_phys(CPUXtensaState
*env
)
209 copy_window_from_phys(env
, 0, env
->sregs
[WINDOW_BASE
] * 4, 16);
212 void xtensa_sync_phys_from_window(CPUXtensaState
*env
)
214 copy_phys_from_window(env
, env
->sregs
[WINDOW_BASE
] * 4, 0, 16);
217 static void rotate_window_abs(CPUXtensaState
*env
, uint32_t position
)
219 xtensa_sync_phys_from_window(env
);
220 env
->sregs
[WINDOW_BASE
] = windowbase_bound(position
, env
);
221 xtensa_sync_window_from_phys(env
);
224 static void rotate_window(CPUXtensaState
*env
, uint32_t delta
)
226 rotate_window_abs(env
, env
->sregs
[WINDOW_BASE
] + delta
);
229 void HELPER(wsr_windowbase
)(CPUXtensaState
*env
, uint32_t v
)
231 rotate_window_abs(env
, v
);
234 void HELPER(entry
)(CPUXtensaState
*env
, uint32_t pc
, uint32_t s
, uint32_t imm
)
236 int callinc
= (env
->sregs
[PS
] & PS_CALLINC
) >> PS_CALLINC_SHIFT
;
237 if (s
> 3 || ((env
->sregs
[PS
] & (PS_WOE
| PS_EXCM
)) ^ PS_WOE
) != 0) {
238 qemu_log_mask(LOG_GUEST_ERROR
, "Illegal entry instruction(pc = %08x), PS = %08x\n",
240 HELPER(exception_cause
)(env
, pc
, ILLEGAL_INSTRUCTION_CAUSE
);
242 uint32_t windowstart
= xtensa_replicate_windowstart(env
) >>
243 (env
->sregs
[WINDOW_BASE
] + 1);
245 if (windowstart
& ((1 << callinc
) - 1)) {
246 HELPER(window_check
)(env
, pc
, callinc
);
248 env
->regs
[(callinc
<< 2) | (s
& 3)] = env
->regs
[s
] - (imm
<< 3);
249 rotate_window(env
, callinc
);
250 env
->sregs
[WINDOW_START
] |=
251 windowstart_bit(env
->sregs
[WINDOW_BASE
], env
);
255 void HELPER(window_check
)(CPUXtensaState
*env
, uint32_t pc
, uint32_t w
)
257 uint32_t windowbase
= windowbase_bound(env
->sregs
[WINDOW_BASE
], env
);
258 uint32_t windowstart
= xtensa_replicate_windowstart(env
) >>
259 (env
->sregs
[WINDOW_BASE
] + 1);
260 uint32_t n
= ctz32(windowstart
) + 1;
264 rotate_window(env
, n
);
265 env
->sregs
[PS
] = (env
->sregs
[PS
] & ~PS_OWB
) |
266 (windowbase
<< PS_OWB_SHIFT
) | PS_EXCM
;
267 env
->sregs
[EPC1
] = env
->pc
= pc
;
269 switch (ctz32(windowstart
>> n
)) {
271 HELPER(exception
)(env
, EXC_WINDOW_OVERFLOW4
);
274 HELPER(exception
)(env
, EXC_WINDOW_OVERFLOW8
);
277 HELPER(exception
)(env
, EXC_WINDOW_OVERFLOW12
);
282 uint32_t HELPER(retw
)(CPUXtensaState
*env
, uint32_t pc
)
284 int n
= (env
->regs
[0] >> 30) & 0x3;
286 uint32_t windowbase
= windowbase_bound(env
->sregs
[WINDOW_BASE
], env
);
287 uint32_t windowstart
= env
->sregs
[WINDOW_START
];
290 if (windowstart
& windowstart_bit(windowbase
- 1, env
)) {
292 } else if (windowstart
& windowstart_bit(windowbase
- 2, env
)) {
294 } else if (windowstart
& windowstart_bit(windowbase
- 3, env
)) {
298 if (n
== 0 || (m
!= 0 && m
!= n
) ||
299 ((env
->sregs
[PS
] & (PS_WOE
| PS_EXCM
)) ^ PS_WOE
) != 0) {
300 qemu_log_mask(LOG_GUEST_ERROR
, "Illegal retw instruction(pc = %08x), "
301 "PS = %08x, m = %d, n = %d\n",
302 pc
, env
->sregs
[PS
], m
, n
);
303 HELPER(exception_cause
)(env
, pc
, ILLEGAL_INSTRUCTION_CAUSE
);
305 int owb
= windowbase
;
307 ret_pc
= (pc
& 0xc0000000) | (env
->regs
[0] & 0x3fffffff);
309 rotate_window(env
, -n
);
310 if (windowstart
& windowstart_bit(env
->sregs
[WINDOW_BASE
], env
)) {
311 env
->sregs
[WINDOW_START
] &= ~windowstart_bit(owb
, env
);
313 /* window underflow */
314 env
->sregs
[PS
] = (env
->sregs
[PS
] & ~PS_OWB
) |
315 (windowbase
<< PS_OWB_SHIFT
) | PS_EXCM
;
316 env
->sregs
[EPC1
] = env
->pc
= pc
;
319 HELPER(exception
)(env
, EXC_WINDOW_UNDERFLOW4
);
321 HELPER(exception
)(env
, EXC_WINDOW_UNDERFLOW8
);
323 HELPER(exception
)(env
, EXC_WINDOW_UNDERFLOW12
);
330 void HELPER(rotw
)(CPUXtensaState
*env
, uint32_t imm4
)
332 rotate_window(env
, imm4
);
335 void HELPER(restore_owb
)(CPUXtensaState
*env
)
337 rotate_window_abs(env
, (env
->sregs
[PS
] & PS_OWB
) >> PS_OWB_SHIFT
);
340 void HELPER(movsp
)(CPUXtensaState
*env
, uint32_t pc
)
342 if ((env
->sregs
[WINDOW_START
] &
343 (windowstart_bit(env
->sregs
[WINDOW_BASE
] - 3, env
) |
344 windowstart_bit(env
->sregs
[WINDOW_BASE
] - 2, env
) |
345 windowstart_bit(env
->sregs
[WINDOW_BASE
] - 1, env
))) == 0) {
346 HELPER(exception_cause
)(env
, pc
, ALLOCA_CAUSE
);
350 void HELPER(wsr_lbeg
)(CPUXtensaState
*env
, uint32_t v
)
352 if (env
->sregs
[LBEG
] != v
) {
353 tb_invalidate_virtual_addr(env
, env
->sregs
[LEND
] - 1);
354 env
->sregs
[LBEG
] = v
;
358 void HELPER(wsr_lend
)(CPUXtensaState
*env
, uint32_t v
)
360 if (env
->sregs
[LEND
] != v
) {
361 tb_invalidate_virtual_addr(env
, env
->sregs
[LEND
] - 1);
362 env
->sregs
[LEND
] = v
;
363 tb_invalidate_virtual_addr(env
, env
->sregs
[LEND
] - 1);
367 void HELPER(dump_state
)(CPUXtensaState
*env
)
369 XtensaCPU
*cpu
= xtensa_env_get_cpu(env
);
371 cpu_dump_state(CPU(cpu
), stderr
, fprintf
, 0);
374 void HELPER(waiti
)(CPUXtensaState
*env
, uint32_t pc
, uint32_t intlevel
)
379 env
->sregs
[PS
] = (env
->sregs
[PS
] & ~PS_INTLEVEL
) |
380 (intlevel
<< PS_INTLEVEL_SHIFT
);
381 check_interrupts(env
);
382 if (env
->pending_irq_level
) {
383 cpu_loop_exit(CPU(xtensa_env_get_cpu(env
)));
387 cpu
= CPU(xtensa_env_get_cpu(env
));
388 env
->halt_clock
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
390 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_TIMER_INTERRUPT
)) {
391 xtensa_rearm_ccompare_timer(env
);
393 HELPER(exception
)(env
, EXCP_HLT
);
396 void HELPER(timer_irq
)(CPUXtensaState
*env
, uint32_t id
, uint32_t active
)
398 xtensa_timer_irq(env
, id
, active
);
401 void HELPER(advance_ccount
)(CPUXtensaState
*env
, uint32_t d
)
403 xtensa_advance_ccount(env
, d
);
406 void HELPER(check_interrupts
)(CPUXtensaState
*env
)
408 check_interrupts(env
);
411 void HELPER(itlb_hit_test
)(CPUXtensaState
*env
, uint32_t vaddr
)
413 get_page_addr_code(env
, vaddr
);
417 * Check vaddr accessibility/cache attributes and raise an exception if
418 * specified by the ATOMCTL SR.
420 * Note: local memory exclusion is not implemented
422 void HELPER(check_atomctl
)(CPUXtensaState
*env
, uint32_t pc
, uint32_t vaddr
)
424 uint32_t paddr
, page_size
, access
;
425 uint32_t atomctl
= env
->sregs
[ATOMCTL
];
426 int rc
= xtensa_get_physical_addr(env
, true, vaddr
, 1,
427 xtensa_get_cring(env
), &paddr
, &page_size
, &access
);
430 * s32c1i never causes LOAD_PROHIBITED_CAUSE exceptions,
431 * see opcode description in the ISA
434 (access
& (PAGE_READ
| PAGE_WRITE
)) != (PAGE_READ
| PAGE_WRITE
)) {
435 rc
= STORE_PROHIBITED_CAUSE
;
439 HELPER(exception_cause_vaddr
)(env
, pc
, rc
, vaddr
);
443 * When data cache is not configured use ATOMCTL bypass field.
444 * See ISA, 4.3.12.4 The Atomic Operation Control Register (ATOMCTL)
445 * under the Conditional Store Option.
447 if (!xtensa_option_enabled(env
->config
, XTENSA_OPTION_DCACHE
)) {
448 access
= PAGE_CACHE_BYPASS
;
451 switch (access
& PAGE_CACHE_MASK
) {
458 case PAGE_CACHE_BYPASS
:
459 if ((atomctl
& 0x3) == 0) {
460 HELPER(exception_cause_vaddr
)(env
, pc
,
461 LOAD_STORE_ERROR_CAUSE
, vaddr
);
465 case PAGE_CACHE_ISOLATE
:
466 HELPER(exception_cause_vaddr
)(env
, pc
,
467 LOAD_STORE_ERROR_CAUSE
, vaddr
);
475 void HELPER(wsr_rasid
)(CPUXtensaState
*env
, uint32_t v
)
477 XtensaCPU
*cpu
= xtensa_env_get_cpu(env
);
479 v
= (v
& 0xffffff00) | 0x1;
480 if (v
!= env
->sregs
[RASID
]) {
481 env
->sregs
[RASID
] = v
;
486 static uint32_t get_page_size(const CPUXtensaState
*env
, bool dtlb
, uint32_t way
)
488 uint32_t tlbcfg
= env
->sregs
[dtlb
? DTLBCFG
: ITLBCFG
];
492 return (tlbcfg
>> 16) & 0x3;
495 return (tlbcfg
>> 20) & 0x1;
498 return (tlbcfg
>> 24) & 0x1;
506 * Get bit mask for the virtual address bits translated by the TLB way
508 uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState
*env
, bool dtlb
, uint32_t way
)
510 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_MMU
)) {
511 bool varway56
= dtlb
?
512 env
->config
->dtlb
.varway56
:
513 env
->config
->itlb
.varway56
;
517 return 0xfff00000 << get_page_size(env
, dtlb
, way
) * 2;
521 return 0xf8000000 << get_page_size(env
, dtlb
, way
);
528 return 0xf0000000 << (1 - get_page_size(env
, dtlb
, way
));
537 return REGION_PAGE_MASK
;
542 * Get bit mask for the 'VPN without index' field.
543 * See ISA, 4.6.5.6, data format for RxTLB0
545 static uint32_t get_vpn_mask(const CPUXtensaState
*env
, bool dtlb
, uint32_t way
)
549 env
->config
->dtlb
.nrefillentries
:
550 env
->config
->itlb
.nrefillentries
) == 32;
551 return is32
? 0xffff8000 : 0xffffc000;
552 } else if (way
== 4) {
553 return xtensa_tlb_get_addr_mask(env
, dtlb
, way
) << 2;
554 } else if (way
<= 6) {
555 uint32_t mask
= xtensa_tlb_get_addr_mask(env
, dtlb
, way
);
556 bool varway56
= dtlb
?
557 env
->config
->dtlb
.varway56
:
558 env
->config
->itlb
.varway56
;
561 return mask
<< (way
== 5 ? 2 : 3);
571 * Split virtual address into VPN (with index) and entry index
572 * for the given TLB way
574 void split_tlb_entry_spec_way(const CPUXtensaState
*env
, uint32_t v
, bool dtlb
,
575 uint32_t *vpn
, uint32_t wi
, uint32_t *ei
)
577 bool varway56
= dtlb
?
578 env
->config
->dtlb
.varway56
:
579 env
->config
->itlb
.varway56
;
587 env
->config
->dtlb
.nrefillentries
:
588 env
->config
->itlb
.nrefillentries
) == 32;
589 *ei
= (v
>> 12) & (is32
? 0x7 : 0x3);
594 uint32_t eibase
= 20 + get_page_size(env
, dtlb
, wi
) * 2;
595 *ei
= (v
>> eibase
) & 0x3;
601 uint32_t eibase
= 27 + get_page_size(env
, dtlb
, wi
);
602 *ei
= (v
>> eibase
) & 0x3;
604 *ei
= (v
>> 27) & 0x1;
610 uint32_t eibase
= 29 - get_page_size(env
, dtlb
, wi
);
611 *ei
= (v
>> eibase
) & 0x7;
613 *ei
= (v
>> 28) & 0x1;
622 *vpn
= v
& xtensa_tlb_get_addr_mask(env
, dtlb
, wi
);
626 * Split TLB address into TLB way, entry index and VPN (with index).
627 * See ISA, 4.6.5.5 - 4.6.5.8 for the TLB addressing format
629 static void split_tlb_entry_spec(CPUXtensaState
*env
, uint32_t v
, bool dtlb
,
630 uint32_t *vpn
, uint32_t *wi
, uint32_t *ei
)
632 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_MMU
)) {
633 *wi
= v
& (dtlb
? 0xf : 0x7);
634 split_tlb_entry_spec_way(env
, v
, dtlb
, vpn
, *wi
, ei
);
636 *vpn
= v
& REGION_PAGE_MASK
;
638 *ei
= (v
>> 29) & 0x7;
642 static xtensa_tlb_entry
*get_tlb_entry(CPUXtensaState
*env
,
643 uint32_t v
, bool dtlb
, uint32_t *pwi
)
649 split_tlb_entry_spec(env
, v
, dtlb
, &vpn
, &wi
, &ei
);
653 return xtensa_tlb_get_entry(env
, dtlb
, wi
, ei
);
656 uint32_t HELPER(rtlb0
)(CPUXtensaState
*env
, uint32_t v
, uint32_t dtlb
)
658 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_MMU
)) {
660 const xtensa_tlb_entry
*entry
= get_tlb_entry(env
, v
, dtlb
, &wi
);
661 return (entry
->vaddr
& get_vpn_mask(env
, dtlb
, wi
)) | entry
->asid
;
663 return v
& REGION_PAGE_MASK
;
667 uint32_t HELPER(rtlb1
)(CPUXtensaState
*env
, uint32_t v
, uint32_t dtlb
)
669 const xtensa_tlb_entry
*entry
= get_tlb_entry(env
, v
, dtlb
, NULL
);
670 return entry
->paddr
| entry
->attr
;
673 void HELPER(itlb
)(CPUXtensaState
*env
, uint32_t v
, uint32_t dtlb
)
675 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_MMU
)) {
677 xtensa_tlb_entry
*entry
= get_tlb_entry(env
, v
, dtlb
, &wi
);
678 if (entry
->variable
&& entry
->asid
) {
679 tlb_flush_page(CPU(xtensa_env_get_cpu(env
)), entry
->vaddr
);
685 uint32_t HELPER(ptlb
)(CPUXtensaState
*env
, uint32_t v
, uint32_t dtlb
)
687 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_MMU
)) {
691 int res
= xtensa_tlb_lookup(env
, v
, dtlb
, &wi
, &ei
, &ring
);
695 if (ring
>= xtensa_get_ring(env
)) {
696 return (v
& 0xfffff000) | wi
| (dtlb
? 0x10 : 0x8);
700 case INST_TLB_MULTI_HIT_CAUSE
:
701 case LOAD_STORE_TLB_MULTI_HIT_CAUSE
:
702 HELPER(exception_cause_vaddr
)(env
, env
->pc
, res
, v
);
707 return (v
& REGION_PAGE_MASK
) | 0x1;
711 void xtensa_tlb_set_entry_mmu(const CPUXtensaState
*env
,
712 xtensa_tlb_entry
*entry
, bool dtlb
,
713 unsigned wi
, unsigned ei
, uint32_t vpn
, uint32_t pte
)
716 entry
->paddr
= pte
& xtensa_tlb_get_addr_mask(env
, dtlb
, wi
);
717 entry
->asid
= (env
->sregs
[RASID
] >> ((pte
>> 1) & 0x18)) & 0xff;
718 entry
->attr
= pte
& 0xf;
721 void xtensa_tlb_set_entry(CPUXtensaState
*env
, bool dtlb
,
722 unsigned wi
, unsigned ei
, uint32_t vpn
, uint32_t pte
)
724 XtensaCPU
*cpu
= xtensa_env_get_cpu(env
);
725 CPUState
*cs
= CPU(cpu
);
726 xtensa_tlb_entry
*entry
= xtensa_tlb_get_entry(env
, dtlb
, wi
, ei
);
728 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_MMU
)) {
729 if (entry
->variable
) {
731 tlb_flush_page(cs
, entry
->vaddr
);
733 xtensa_tlb_set_entry_mmu(env
, entry
, dtlb
, wi
, ei
, vpn
, pte
);
734 tlb_flush_page(cs
, entry
->vaddr
);
736 qemu_log_mask(LOG_GUEST_ERROR
, "%s %d, %d, %d trying to set immutable entry\n",
737 __func__
, dtlb
, wi
, ei
);
740 tlb_flush_page(cs
, entry
->vaddr
);
741 if (xtensa_option_enabled(env
->config
,
742 XTENSA_OPTION_REGION_TRANSLATION
)) {
743 entry
->paddr
= pte
& REGION_PAGE_MASK
;
745 entry
->attr
= pte
& 0xf;
749 void HELPER(wtlb
)(CPUXtensaState
*env
, uint32_t p
, uint32_t v
, uint32_t dtlb
)
754 split_tlb_entry_spec(env
, v
, dtlb
, &vpn
, &wi
, &ei
);
755 xtensa_tlb_set_entry(env
, dtlb
, wi
, ei
, vpn
, p
);
759 void HELPER(wsr_ibreakenable
)(CPUXtensaState
*env
, uint32_t v
)
761 uint32_t change
= v
^ env
->sregs
[IBREAKENABLE
];
764 for (i
= 0; i
< env
->config
->nibreak
; ++i
) {
765 if (change
& (1 << i
)) {
766 tb_invalidate_virtual_addr(env
, env
->sregs
[IBREAKA
+ i
]);
769 env
->sregs
[IBREAKENABLE
] = v
& ((1 << env
->config
->nibreak
) - 1);
772 void HELPER(wsr_ibreaka
)(CPUXtensaState
*env
, uint32_t i
, uint32_t v
)
774 if (env
->sregs
[IBREAKENABLE
] & (1 << i
) && env
->sregs
[IBREAKA
+ i
] != v
) {
775 tb_invalidate_virtual_addr(env
, env
->sregs
[IBREAKA
+ i
]);
776 tb_invalidate_virtual_addr(env
, v
);
778 env
->sregs
[IBREAKA
+ i
] = v
;
781 static void set_dbreak(CPUXtensaState
*env
, unsigned i
, uint32_t dbreaka
,
784 CPUState
*cs
= CPU(xtensa_env_get_cpu(env
));
785 int flags
= BP_CPU
| BP_STOP_BEFORE_ACCESS
;
786 uint32_t mask
= dbreakc
| ~DBREAKC_MASK
;
788 if (env
->cpu_watchpoint
[i
]) {
789 cpu_watchpoint_remove_by_ref(cs
, env
->cpu_watchpoint
[i
]);
791 if (dbreakc
& DBREAKC_SB
) {
792 flags
|= BP_MEM_WRITE
;
794 if (dbreakc
& DBREAKC_LB
) {
795 flags
|= BP_MEM_READ
;
797 /* contiguous mask after inversion is one less than some power of 2 */
798 if ((~mask
+ 1) & ~mask
) {
799 qemu_log_mask(LOG_GUEST_ERROR
, "DBREAKC mask is not contiguous: 0x%08x\n", dbreakc
);
800 /* cut mask after the first zero bit */
801 mask
= 0xffffffff << (32 - clo32(mask
));
803 if (cpu_watchpoint_insert(cs
, dbreaka
& mask
, ~mask
+ 1,
804 flags
, &env
->cpu_watchpoint
[i
])) {
805 env
->cpu_watchpoint
[i
] = NULL
;
806 qemu_log_mask(LOG_GUEST_ERROR
, "Failed to set data breakpoint at 0x%08x/%d\n",
807 dbreaka
& mask
, ~mask
+ 1);
811 void HELPER(wsr_dbreaka
)(CPUXtensaState
*env
, uint32_t i
, uint32_t v
)
813 uint32_t dbreakc
= env
->sregs
[DBREAKC
+ i
];
815 if ((dbreakc
& DBREAKC_SB_LB
) &&
816 env
->sregs
[DBREAKA
+ i
] != v
) {
817 set_dbreak(env
, i
, v
, dbreakc
);
819 env
->sregs
[DBREAKA
+ i
] = v
;
822 void HELPER(wsr_dbreakc
)(CPUXtensaState
*env
, uint32_t i
, uint32_t v
)
824 if ((env
->sregs
[DBREAKC
+ i
] ^ v
) & (DBREAKC_SB_LB
| DBREAKC_MASK
)) {
825 if (v
& DBREAKC_SB_LB
) {
826 set_dbreak(env
, i
, env
->sregs
[DBREAKA
+ i
], v
);
828 if (env
->cpu_watchpoint
[i
]) {
829 CPUState
*cs
= CPU(xtensa_env_get_cpu(env
));
831 cpu_watchpoint_remove_by_ref(cs
, env
->cpu_watchpoint
[i
]);
832 env
->cpu_watchpoint
[i
] = NULL
;
836 env
->sregs
[DBREAKC
+ i
] = v
;
839 void HELPER(wur_fcr
)(CPUXtensaState
*env
, uint32_t v
)
841 static const int rounding_mode
[] = {
842 float_round_nearest_even
,
848 env
->uregs
[FCR
] = v
& 0xfffff07f;
849 set_float_rounding_mode(rounding_mode
[v
& 3], &env
->fp_status
);
852 float32
HELPER(abs_s
)(float32 v
)
854 return float32_abs(v
);
857 float32
HELPER(neg_s
)(float32 v
)
859 return float32_chs(v
);
862 float32
HELPER(add_s
)(CPUXtensaState
*env
, float32 a
, float32 b
)
864 return float32_add(a
, b
, &env
->fp_status
);
867 float32
HELPER(sub_s
)(CPUXtensaState
*env
, float32 a
, float32 b
)
869 return float32_sub(a
, b
, &env
->fp_status
);
872 float32
HELPER(mul_s
)(CPUXtensaState
*env
, float32 a
, float32 b
)
874 return float32_mul(a
, b
, &env
->fp_status
);
877 float32
HELPER(madd_s
)(CPUXtensaState
*env
, float32 a
, float32 b
, float32 c
)
879 return float32_muladd(b
, c
, a
, 0,
883 float32
HELPER(msub_s
)(CPUXtensaState
*env
, float32 a
, float32 b
, float32 c
)
885 return float32_muladd(b
, c
, a
, float_muladd_negate_product
,
889 uint32_t HELPER(ftoi
)(float32 v
, uint32_t rounding_mode
, uint32_t scale
)
891 float_status fp_status
= {0};
893 set_float_rounding_mode(rounding_mode
, &fp_status
);
894 return float32_to_int32(
895 float32_scalbn(v
, scale
, &fp_status
), &fp_status
);
898 uint32_t HELPER(ftoui
)(float32 v
, uint32_t rounding_mode
, uint32_t scale
)
900 float_status fp_status
= {0};
903 set_float_rounding_mode(rounding_mode
, &fp_status
);
905 res
= float32_scalbn(v
, scale
, &fp_status
);
907 if (float32_is_neg(v
) && !float32_is_any_nan(v
)) {
908 return float32_to_int32(res
, &fp_status
);
910 return float32_to_uint32(res
, &fp_status
);
914 float32
HELPER(itof
)(CPUXtensaState
*env
, uint32_t v
, uint32_t scale
)
916 return float32_scalbn(int32_to_float32(v
, &env
->fp_status
),
917 (int32_t)scale
, &env
->fp_status
);
920 float32
HELPER(uitof
)(CPUXtensaState
*env
, uint32_t v
, uint32_t scale
)
922 return float32_scalbn(uint32_to_float32(v
, &env
->fp_status
),
923 (int32_t)scale
, &env
->fp_status
);
926 static inline void set_br(CPUXtensaState
*env
, bool v
, uint32_t br
)
929 env
->sregs
[BR
] |= br
;
931 env
->sregs
[BR
] &= ~br
;
935 void HELPER(un_s
)(CPUXtensaState
*env
, uint32_t br
, float32 a
, float32 b
)
937 set_br(env
, float32_unordered_quiet(a
, b
, &env
->fp_status
), br
);
940 void HELPER(oeq_s
)(CPUXtensaState
*env
, uint32_t br
, float32 a
, float32 b
)
942 set_br(env
, float32_eq_quiet(a
, b
, &env
->fp_status
), br
);
945 void HELPER(ueq_s
)(CPUXtensaState
*env
, uint32_t br
, float32 a
, float32 b
)
947 int v
= float32_compare_quiet(a
, b
, &env
->fp_status
);
948 set_br(env
, v
== float_relation_equal
|| v
== float_relation_unordered
, br
);
951 void HELPER(olt_s
)(CPUXtensaState
*env
, uint32_t br
, float32 a
, float32 b
)
953 set_br(env
, float32_lt_quiet(a
, b
, &env
->fp_status
), br
);
956 void HELPER(ult_s
)(CPUXtensaState
*env
, uint32_t br
, float32 a
, float32 b
)
958 int v
= float32_compare_quiet(a
, b
, &env
->fp_status
);
959 set_br(env
, v
== float_relation_less
|| v
== float_relation_unordered
, br
);
962 void HELPER(ole_s
)(CPUXtensaState
*env
, uint32_t br
, float32 a
, float32 b
)
964 set_br(env
, float32_le_quiet(a
, b
, &env
->fp_status
), br
);
967 void HELPER(ule_s
)(CPUXtensaState
*env
, uint32_t br
, float32 a
, float32 b
)
969 int v
= float32_compare_quiet(a
, b
, &env
->fp_status
);
970 set_br(env
, v
!= float_relation_greater
, br
);