| commit | aa1b3111b3f3c53b9290ecade02f31acfc579c16 | |
| author | Peter Maydell <peter.maydell@linaro.org> | |
| Fri, 20 Jan 2017 11:15:09 +0000 (20 11:15 +0000) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Fri, 20 Jan 2017 11:15:09 +0000 (20 11:15 +0000) | ||
| tree | 00185b041c22c9e3b6f652e9d0f97c61f1c3b231 | treesnapshot (tar.gz zip) |
| parent | 6a228959081c12cc8a4f268ed00f77dbd0755404 | commitdiff |
target-arm: Expose output GPIO line for VCPU maintenance interrupt
The GICv3 support for virtualization includes an outbound
maintenance interrupt signal which is asserted when the
CPU interface wants to signal to the hypervisor that it
needs attention. Expose this as an outbound GPIO line from
the CPU object which can be wired up as a physical interrupt
line by the board code (as we do already for the CPU timers).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Message-id: 1483977924-14522-4-git-send-email-peter.maydell@linaro.org
The GICv3 support for virtualization includes an outbound
maintenance interrupt signal which is asserted when the
CPU interface wants to signal to the hypervisor that it
needs attention. Expose this as an outbound GPIO line from
the CPU object which can be wired up as a physical interrupt
line by the board code (as we do already for the CPU timers).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Message-id: 1483977924-14522-4-git-send-email-peter.maydell@linaro.org
| target/arm/cpu.c | diffblobblamehistory | |
| target/arm/cpu.h | diffblobblamehistory |