hw/timer/imx_gpt.c

   1 /*
   2  * IMX GPT Timer
   3  *
   4  * Copyright (c) 2008 OK Labs
   5  * Copyright (c) 2011 NICTA Pty Ltd
   6  * Originally written by Hans Jiang
   7  * Updated by Peter Chubb
   8  * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
   9  *
  10  * This code is licensed under GPL version 2 or later.  See
  11  * the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include "qemu/osdep.h"
  16 #include "hw/timer/imx_gpt.h"
  17 #include "qemu/main-loop.h"
  18 #include "qemu/log.h"
  19
  20 #ifndef DEBUG_IMX_GPT
  21 #define DEBUG_IMX_GPT 0
  22 #endif
  23
  24 #define DPRINTF(fmt, args...) \
  25     do { \
  26         if (DEBUG_IMX_GPT) { \
  27             fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_GPT, \
  28                                              __func__, ##args); \
  29         } \
  30     } while (0)
  31
  32 static const char *imx_gpt_reg_name(uint32_t reg)
  33 {
  34     switch (reg) {
  35     case 0:
  36         return "CR";
  37     case 1:
  38         return "PR";
  39     case 2:
  40         return "SR";
  41     case 3:
  42         return "IR";
  43     case 4:
  44         return "OCR1";
  45     case 5:
  46         return "OCR2";
  47     case 6:
  48         return "OCR3";
  49     case 7:
  50         return "ICR1";
  51     case 8:
  52         return "ICR2";
  53     case 9:
  54         return "CNT";
  55     default:
  56         return "[?]";
  57     }
  58 }
  59
  60 static const VMStateDescription vmstate_imx_timer_gpt = {
  61     .name = TYPE_IMX_GPT,
  62     .version_id = 3,
  63     .minimum_version_id = 3,
  64     .fields = (VMStateField[]) {
  65         VMSTATE_UINT32(cr, IMXGPTState),
  66         VMSTATE_UINT32(pr, IMXGPTState),
  67         VMSTATE_UINT32(sr, IMXGPTState),
  68         VMSTATE_UINT32(ir, IMXGPTState),
  69         VMSTATE_UINT32(ocr1, IMXGPTState),
  70         VMSTATE_UINT32(ocr2, IMXGPTState),
  71         VMSTATE_UINT32(ocr3, IMXGPTState),
  72         VMSTATE_UINT32(icr1, IMXGPTState),
  73         VMSTATE_UINT32(icr2, IMXGPTState),
  74         VMSTATE_UINT32(cnt, IMXGPTState),
  75         VMSTATE_UINT32(next_timeout, IMXGPTState),
  76         VMSTATE_UINT32(next_int, IMXGPTState),
  77         VMSTATE_UINT32(freq, IMXGPTState),
  78         VMSTATE_PTIMER(timer, IMXGPTState),
  79         VMSTATE_END_OF_LIST()
  80     }
  81 };
  82
  83 static const IMXClk imx25_gpt_clocks[] = {
  84     CLK_NONE,      /* 000 No clock source */
  85     CLK_IPG,       /* 001 ipg_clk, 532MHz*/
  86     CLK_IPG_HIGH,  /* 010 ipg_clk_highfreq */
  87     CLK_NONE,      /* 011 not defined */
  88     CLK_32k,       /* 100 ipg_clk_32k */
  89     CLK_32k,       /* 101 ipg_clk_32k */
  90     CLK_32k,       /* 110 ipg_clk_32k */
  91     CLK_32k,       /* 111 ipg_clk_32k */
  92 };
  93
  94 static const IMXClk imx31_gpt_clocks[] = {
  95     CLK_NONE,      /* 000 No clock source */
  96     CLK_IPG,       /* 001 ipg_clk, 532MHz*/
  97     CLK_IPG_HIGH,  /* 010 ipg_clk_highfreq */
  98     CLK_NONE,      /* 011 not defined */
  99     CLK_32k,       /* 100 ipg_clk_32k */
 100     CLK_NONE,      /* 101 not defined */
 101     CLK_NONE,      /* 110 not defined */
 102     CLK_NONE,      /* 111 not defined */
 103 };
 104
 105 static const IMXClk imx6_gpt_clocks[] = {
 106     CLK_NONE,      /* 000 No clock source */
 107     CLK_IPG,       /* 001 ipg_clk, 532MHz*/
 108     CLK_IPG_HIGH,  /* 010 ipg_clk_highfreq */
 109     CLK_EXT,       /* 011 External clock */
 110     CLK_32k,       /* 100 ipg_clk_32k */
 111     CLK_HIGH_DIV,  /* 101 reference clock / 8 */
 112     CLK_NONE,      /* 110 not defined */
 113     CLK_HIGH,      /* 111 reference clock */
 114 };
 115
 116 static void imx_gpt_set_freq(IMXGPTState *s)
 117 {
 118     uint32_t clksrc = extract32(s->cr, GPT_CR_CLKSRC_SHIFT, 3);
 119
 120     s->freq = imx_ccm_get_clock_frequency(s->ccm,
 121                                           s->clocks[clksrc]) / (1 + s->pr);
 122
 123     DPRINTF("Setting clksrc %d to frequency %d\n", clksrc, s->freq);
 124
 125     if (s->freq) {
 126         ptimer_set_freq(s->timer, s->freq);
 127     }
 128 }
 129
 130 static void imx_gpt_update_int(IMXGPTState *s)
 131 {
 132     if ((s->sr & s->ir) && (s->cr & GPT_CR_EN)) {
 133         qemu_irq_raise(s->irq);
 134     } else {
 135         qemu_irq_lower(s->irq);
 136     }
 137 }
 138
 139 static uint32_t imx_gpt_update_count(IMXGPTState *s)
 140 {
 141     s->cnt = s->next_timeout - (uint32_t)ptimer_get_count(s->timer);
 142
 143     return s->cnt;
 144 }
 145
 146 static inline uint32_t imx_gpt_find_limit(uint32_t count, uint32_t reg,
 147                                           uint32_t timeout)
 148 {
 149     if ((count < reg) && (timeout > reg)) {
 150         timeout = reg;
 151     }
 152
 153     return timeout;
 154 }
 155
 156 static void imx_gpt_compute_next_timeout(IMXGPTState *s, bool event)
 157 {
 158     uint32_t timeout = GPT_TIMER_MAX;
 159     uint32_t count;
 160     long long limit;
 161
 162     if (!(s->cr & GPT_CR_EN)) {
 163         /* if not enabled just return */
 164         return;
 165     }
 166
 167     /* update the count */
 168     count = imx_gpt_update_count(s);
 169
 170     if (event) {
 171         /*
 172          * This is an event (the ptimer reached 0 and stopped), and the
 173          * timer counter is now equal to s->next_timeout.
 174          */
 175         if (!(s->cr & GPT_CR_FRR) && (count == s->ocr1)) {
 176             /* We are in restart mode and we crossed the compare channel 1
 177              * value. We need to reset the counter to 0.
 178              */
 179             count = s->cnt = s->next_timeout = 0;
 180         } else if (count == GPT_TIMER_MAX) {
 181             /* We reached GPT_TIMER_MAX so we need to rollover */
 182             count = s->cnt = s->next_timeout = 0;
 183         }
 184     }
 185
 186     /* now, find the next timeout related to count */
 187
 188     if (s->ir & GPT_IR_OF1IE) {
 189         timeout = imx_gpt_find_limit(count, s->ocr1, timeout);
 190     }
 191     if (s->ir & GPT_IR_OF2IE) {
 192         timeout = imx_gpt_find_limit(count, s->ocr2, timeout);
 193     }
 194     if (s->ir & GPT_IR_OF3IE) {
 195         timeout = imx_gpt_find_limit(count, s->ocr3, timeout);
 196     }
 197
 198     /* find the next set of interrupts to raise for next timer event */
 199
 200     s->next_int = 0;
 201     if ((s->ir & GPT_IR_OF1IE) && (timeout == s->ocr1)) {
 202         s->next_int |= GPT_SR_OF1;
 203     }
 204     if ((s->ir & GPT_IR_OF2IE) && (timeout == s->ocr2)) {
 205         s->next_int |= GPT_SR_OF2;
 206     }
 207     if ((s->ir & GPT_IR_OF3IE) && (timeout == s->ocr3)) {
 208         s->next_int |= GPT_SR_OF3;
 209     }
 210     if ((s->ir & GPT_IR_ROVIE) && (timeout == GPT_TIMER_MAX)) {
 211         s->next_int |= GPT_SR_ROV;
 212     }
 213
 214     /* the new range to count down from */
 215     limit = timeout - imx_gpt_update_count(s);
 216
 217     if (limit < 0) {
 218         /*
 219          * if we reach here, then QEMU is running too slow and we pass the
 220          * timeout limit while computing it. Let's deliver the interrupt
 221          * and compute a new limit.
 222          */
 223         s->sr |= s->next_int;
 224
 225         imx_gpt_compute_next_timeout(s, event);
 226
 227         imx_gpt_update_int(s);
 228     } else {
 229         /* New timeout value */
 230         s->next_timeout = timeout;
 231
 232         /* reset the limit to the computed range */
 233         ptimer_set_limit(s->timer, limit, 1);
 234     }
 235 }
 236
 237 static uint64_t imx_gpt_read(void *opaque, hwaddr offset, unsigned size)
 238 {
 239     IMXGPTState *s = IMX_GPT(opaque);
 240     uint32_t reg_value = 0;
 241
 242     switch (offset >> 2) {
 243     case 0: /* Control Register */
 244         reg_value = s->cr;
 245         break;
 246
 247     case 1: /* prescaler */
 248         reg_value = s->pr;
 249         break;
 250
 251     case 2: /* Status Register */
 252         reg_value = s->sr;
 253         break;
 254
 255     case 3: /* Interrupt Register */
 256         reg_value = s->ir;
 257         break;
 258
 259     case 4: /* Output Compare Register 1 */
 260         reg_value = s->ocr1;
 261         break;
 262
 263     case 5: /* Output Compare Register 2 */
 264         reg_value = s->ocr2;
 265         break;
 266
 267     case 6: /* Output Compare Register 3 */
 268         reg_value = s->ocr3;
 269         break;
 270
 271     case 7: /* input Capture Register 1 */
 272         qemu_log_mask(LOG_UNIMP, "[%s]%s: icr1 feature is not implemented\n",
 273                       TYPE_IMX_GPT, __func__);
 274         reg_value = s->icr1;
 275         break;
 276
 277     case 8: /* input Capture Register 2 */
 278         qemu_log_mask(LOG_UNIMP, "[%s]%s: icr2 feature is not implemented\n",
 279                       TYPE_IMX_GPT, __func__);
 280         reg_value = s->icr2;
 281         break;
 282
 283     case 9: /* cnt */
 284         imx_gpt_update_count(s);
 285         reg_value = s->cnt;
 286         break;
 287
 288     default:
 289         qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
 290                       HWADDR_PRIx "\n", TYPE_IMX_GPT, __func__, offset);
 291         break;
 292     }
 293
 294     DPRINTF("(%s) = 0x%08x\n", imx_gpt_reg_name(offset >> 2), reg_value);
 295
 296     return reg_value;
 297 }
 298
 299 static void imx_gpt_reset(DeviceState *dev)
 300 {
 301     IMXGPTState *s = IMX_GPT(dev);
 302
 303     /* stop timer */
 304     ptimer_stop(s->timer);
 305
 306     /*
 307      * Soft reset doesn't touch some bits; hard reset clears them
 308      */
 309     s->cr &= ~(GPT_CR_EN|GPT_CR_ENMOD|GPT_CR_STOPEN|GPT_CR_DOZEN|
 310                GPT_CR_WAITEN|GPT_CR_DBGEN);
 311     s->sr = 0;
 312     s->pr = 0;
 313     s->ir = 0;
 314     s->cnt = 0;
 315     s->ocr1 = GPT_TIMER_MAX;
 316     s->ocr2 = GPT_TIMER_MAX;
 317     s->ocr3 = GPT_TIMER_MAX;
 318     s->icr1 = 0;
 319     s->icr2 = 0;
 320
 321     s->next_timeout = GPT_TIMER_MAX;
 322     s->next_int = 0;
 323
 324     /* compute new freq */
 325     imx_gpt_set_freq(s);
 326
 327     /* reset the limit to GPT_TIMER_MAX */
 328     ptimer_set_limit(s->timer, GPT_TIMER_MAX, 1);
 329
 330     /* if the timer is still enabled, restart it */
 331     if (s->freq && (s->cr & GPT_CR_EN)) {
 332         ptimer_run(s->timer, 1);
 333     }
 334 }
 335
 336 static void imx_gpt_write(void *opaque, hwaddr offset, uint64_t value,
 337                           unsigned size)
 338 {
 339     IMXGPTState *s = IMX_GPT(opaque);
 340     uint32_t oldreg;
 341
 342     DPRINTF("(%s, value = 0x%08x)\n", imx_gpt_reg_name(offset >> 2),
 343             (uint32_t)value);
 344
 345     switch (offset >> 2) {
 346     case 0:
 347         oldreg = s->cr;
 348         s->cr = value & ~0x7c14;
 349         if (s->cr & GPT_CR_SWR) { /* force reset */
 350             /* handle the reset */
 351             imx_gpt_reset(DEVICE(s));
 352         } else {
 353             /* set our freq, as the source might have changed */
 354             imx_gpt_set_freq(s);
 355
 356             if ((oldreg ^ s->cr) & GPT_CR_EN) {
 357                 if (s->cr & GPT_CR_EN) {
 358                     if (s->cr & GPT_CR_ENMOD) {
 359                         s->next_timeout = GPT_TIMER_MAX;
 360                         ptimer_set_count(s->timer, GPT_TIMER_MAX);
 361                         imx_gpt_compute_next_timeout(s, false);
 362                     }
 363                     ptimer_run(s->timer, 1);
 364                 } else {
 365                     /* stop timer */
 366                     ptimer_stop(s->timer);
 367                 }
 368             }
 369         }
 370         break;
 371
 372     case 1: /* Prescaler */
 373         s->pr = value & 0xfff;
 374         imx_gpt_set_freq(s);
 375         break;
 376
 377     case 2: /* SR */
 378         s->sr &= ~(value & 0x3f);
 379         imx_gpt_update_int(s);
 380         break;
 381
 382     case 3: /* IR -- interrupt register */
 383         s->ir = value & 0x3f;
 384         imx_gpt_update_int(s);
 385
 386         imx_gpt_compute_next_timeout(s, false);
 387
 388         break;
 389
 390     case 4: /* OCR1 -- output compare register */
 391         s->ocr1 = value;
 392
 393         /* In non-freerun mode, reset count when this register is written */
 394         if (!(s->cr & GPT_CR_FRR)) {
 395             s->next_timeout = GPT_TIMER_MAX;
 396             ptimer_set_limit(s->timer, GPT_TIMER_MAX, 1);
 397         }
 398
 399         /* compute the new timeout */
 400         imx_gpt_compute_next_timeout(s, false);
 401
 402         break;
 403
 404     case 5: /* OCR2 -- output compare register */
 405         s->ocr2 = value;
 406
 407         /* compute the new timeout */
 408         imx_gpt_compute_next_timeout(s, false);
 409
 410         break;
 411
 412     case 6: /* OCR3 -- output compare register */
 413         s->ocr3 = value;
 414
 415         /* compute the new timeout */
 416         imx_gpt_compute_next_timeout(s, false);
 417
 418         break;
 419
 420     default:
 421         qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
 422                       HWADDR_PRIx "\n", TYPE_IMX_GPT, __func__, offset);
 423         break;
 424     }
 425 }
 426
 427 static void imx_gpt_timeout(void *opaque)
 428 {
 429     IMXGPTState *s = IMX_GPT(opaque);
 430
 431     DPRINTF("\n");
 432
 433     s->sr |= s->next_int;
 434     s->next_int = 0;
 435
 436     imx_gpt_compute_next_timeout(s, true);
 437
 438     imx_gpt_update_int(s);
 439
 440     if (s->freq && (s->cr & GPT_CR_EN)) {
 441         ptimer_run(s->timer, 1);
 442     }
 443 }
 444
 445 static const MemoryRegionOps imx_gpt_ops = {
 446     .read = imx_gpt_read,
 447     .write = imx_gpt_write,
 448     .endianness = DEVICE_NATIVE_ENDIAN,
 449 };
 450
 451
 452 static void imx_gpt_realize(DeviceState *dev, Error **errp)
 453 {
 454     IMXGPTState *s = IMX_GPT(dev);
 455     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 456     QEMUBH *bh;
 457
 458     sysbus_init_irq(sbd, &s->irq);
 459     memory_region_init_io(&s->iomem, OBJECT(s), &imx_gpt_ops, s, TYPE_IMX_GPT,
 460                           0x00001000);
 461     sysbus_init_mmio(sbd, &s->iomem);
 462
 463     bh = qemu_bh_new(imx_gpt_timeout, s);
 464     s->timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT);
 465 }
 466
 467 static void imx_gpt_class_init(ObjectClass *klass, void *data)
 468 {
 469     DeviceClass *dc = DEVICE_CLASS(klass);
 470
 471     dc->realize = imx_gpt_realize;
 472     dc->reset = imx_gpt_reset;
 473     dc->vmsd = &vmstate_imx_timer_gpt;
 474     dc->desc = "i.MX general timer";
 475 }
 476
 477 static void imx25_gpt_init(Object *obj)
 478 {
 479     IMXGPTState *s = IMX_GPT(obj);
 480
 481     s->clocks = imx25_gpt_clocks;
 482 }
 483
 484 static void imx31_gpt_init(Object *obj)
 485 {
 486     IMXGPTState *s = IMX_GPT(obj);
 487
 488     s->clocks = imx31_gpt_clocks;
 489 }
 490
 491 static void imx6_gpt_init(Object *obj)
 492 {
 493     IMXGPTState *s = IMX_GPT(obj);
 494
 495     s->clocks = imx6_gpt_clocks;
 496 }
 497
 498 static const TypeInfo imx25_gpt_info = {
 499     .name = TYPE_IMX25_GPT,
 500     .parent = TYPE_SYS_BUS_DEVICE,
 501     .instance_size = sizeof(IMXGPTState),
 502     .instance_init = imx25_gpt_init,
 503     .class_init = imx_gpt_class_init,
 504 };
 505
 506 static const TypeInfo imx31_gpt_info = {
 507     .name = TYPE_IMX31_GPT,
 508     .parent = TYPE_IMX25_GPT,
 509     .instance_init = imx31_gpt_init,
 510 };
 511
 512 static const TypeInfo imx6_gpt_info = {
 513     .name = TYPE_IMX6_GPT,
 514     .parent = TYPE_IMX25_GPT,
 515     .instance_init = imx6_gpt_init,
 516 };
 517
 518 static void imx_gpt_register_types(void)
 519 {
 520     type_register_static(&imx25_gpt_info);
 521     type_register_static(&imx31_gpt_info);
 522     type_register_static(&imx6_gpt_info);
 523 }
 524
 525 type_init(imx_gpt_register_types)