hw/net/dp8393x.c

   1 /*
   2  * QEMU NS SONIC DP8393x netcard
   3  *
   4  * Copyright (c) 2008-2009 Herve Poussineau
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along
  17  * with this program; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "hw/irq.h"
  22 #include "hw/qdev-properties.h"
  23 #include "hw/sysbus.h"
  24 #include "migration/vmstate.h"
  25 #include "net/net.h"
  26 #include "qapi/error.h"
  27 #include "qemu/module.h"
  28 #include "qemu/timer.h"
  29 #include <zlib.h>
  30 #include "qom/object.h"
  31
  32 //#define DEBUG_SONIC
  33
  34 #define SONIC_PROM_SIZE 0x1000
  35
  36 #ifdef DEBUG_SONIC
  37 #define DPRINTF(fmt, ...) \
  38 do { printf("sonic: " fmt , ##  __VA_ARGS__); } while (0)
  39 static const char* reg_names[] = {
  40     "CR", "DCR", "RCR", "TCR", "IMR", "ISR", "UTDA", "CTDA",
  41     "TPS", "TFC", "TSA0", "TSA1", "TFS", "URDA", "CRDA", "CRBA0",
  42     "CRBA1", "RBWC0", "RBWC1", "EOBC", "URRA", "RSA", "REA", "RRP",
  43     "RWP", "TRBA0", "TRBA1", "0x1b", "0x1c", "0x1d", "0x1e", "LLFA",
  44     "TTDA", "CEP", "CAP2", "CAP1", "CAP0", "CE", "CDP", "CDC",
  45     "SR", "WT0", "WT1", "RSC", "CRCT", "FAET", "MPT", "MDT",
  46     "0x30", "0x31", "0x32", "0x33", "0x34", "0x35", "0x36", "0x37",
  47     "0x38", "0x39", "0x3a", "0x3b", "0x3c", "0x3d", "0x3e", "DCR2" };
  48 #else
  49 #define DPRINTF(fmt, ...) do {} while (0)
  50 #endif
  51
  52 #define SONIC_ERROR(fmt, ...) \
  53 do { printf("sonic ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
  54
  55 #define SONIC_CR     0x00
  56 #define SONIC_DCR    0x01
  57 #define SONIC_RCR    0x02
  58 #define SONIC_TCR    0x03
  59 #define SONIC_IMR    0x04
  60 #define SONIC_ISR    0x05
  61 #define SONIC_UTDA   0x06
  62 #define SONIC_CTDA   0x07
  63 #define SONIC_TPS    0x08
  64 #define SONIC_TFC    0x09
  65 #define SONIC_TSA0   0x0a
  66 #define SONIC_TSA1   0x0b
  67 #define SONIC_TFS    0x0c
  68 #define SONIC_URDA   0x0d
  69 #define SONIC_CRDA   0x0e
  70 #define SONIC_CRBA0  0x0f
  71 #define SONIC_CRBA1  0x10
  72 #define SONIC_RBWC0  0x11
  73 #define SONIC_RBWC1  0x12
  74 #define SONIC_EOBC   0x13
  75 #define SONIC_URRA   0x14
  76 #define SONIC_RSA    0x15
  77 #define SONIC_REA    0x16
  78 #define SONIC_RRP    0x17
  79 #define SONIC_RWP    0x18
  80 #define SONIC_TRBA0  0x19
  81 #define SONIC_TRBA1  0x1a
  82 #define SONIC_LLFA   0x1f
  83 #define SONIC_TTDA   0x20
  84 #define SONIC_CEP    0x21
  85 #define SONIC_CAP2   0x22
  86 #define SONIC_CAP1   0x23
  87 #define SONIC_CAP0   0x24
  88 #define SONIC_CE     0x25
  89 #define SONIC_CDP    0x26
  90 #define SONIC_CDC    0x27
  91 #define SONIC_SR     0x28
  92 #define SONIC_WT0    0x29
  93 #define SONIC_WT1    0x2a
  94 #define SONIC_RSC    0x2b
  95 #define SONIC_CRCT   0x2c
  96 #define SONIC_FAET   0x2d
  97 #define SONIC_MPT    0x2e
  98 #define SONIC_MDT    0x2f
  99 #define SONIC_DCR2   0x3f
 100
 101 #define SONIC_CR_HTX     0x0001
 102 #define SONIC_CR_TXP     0x0002
 103 #define SONIC_CR_RXDIS   0x0004
 104 #define SONIC_CR_RXEN    0x0008
 105 #define SONIC_CR_STP     0x0010
 106 #define SONIC_CR_ST      0x0020
 107 #define SONIC_CR_RST     0x0080
 108 #define SONIC_CR_RRRA    0x0100
 109 #define SONIC_CR_LCAM    0x0200
 110 #define SONIC_CR_MASK    0x03bf
 111
 112 #define SONIC_DCR_DW     0x0020
 113 #define SONIC_DCR_LBR    0x2000
 114 #define SONIC_DCR_EXBUS  0x8000
 115
 116 #define SONIC_RCR_PRX    0x0001
 117 #define SONIC_RCR_LBK    0x0002
 118 #define SONIC_RCR_FAER   0x0004
 119 #define SONIC_RCR_CRCR   0x0008
 120 #define SONIC_RCR_CRS    0x0020
 121 #define SONIC_RCR_LPKT   0x0040
 122 #define SONIC_RCR_BC     0x0080
 123 #define SONIC_RCR_MC     0x0100
 124 #define SONIC_RCR_LB0    0x0200
 125 #define SONIC_RCR_LB1    0x0400
 126 #define SONIC_RCR_AMC    0x0800
 127 #define SONIC_RCR_PRO    0x1000
 128 #define SONIC_RCR_BRD    0x2000
 129 #define SONIC_RCR_RNT    0x4000
 130
 131 #define SONIC_TCR_PTX    0x0001
 132 #define SONIC_TCR_BCM    0x0002
 133 #define SONIC_TCR_FU     0x0004
 134 #define SONIC_TCR_EXC    0x0040
 135 #define SONIC_TCR_CRSL   0x0080
 136 #define SONIC_TCR_NCRS   0x0100
 137 #define SONIC_TCR_EXD    0x0400
 138 #define SONIC_TCR_CRCI   0x2000
 139 #define SONIC_TCR_PINT   0x8000
 140
 141 #define SONIC_ISR_RBAE   0x0010
 142 #define SONIC_ISR_RBE    0x0020
 143 #define SONIC_ISR_RDE    0x0040
 144 #define SONIC_ISR_TC     0x0080
 145 #define SONIC_ISR_TXDN   0x0200
 146 #define SONIC_ISR_PKTRX  0x0400
 147 #define SONIC_ISR_PINT   0x0800
 148 #define SONIC_ISR_LCD    0x1000
 149
 150 #define SONIC_DESC_EOL   0x0001
 151 #define SONIC_DESC_ADDR  0xFFFE
 152
 153 #define TYPE_DP8393X "dp8393x"
 154 typedef struct dp8393xState dp8393xState;
 155 DECLARE_INSTANCE_CHECKER(dp8393xState, DP8393X,
 156                          TYPE_DP8393X)
 157
 158 struct dp8393xState {
 159     SysBusDevice parent_obj;
 160
 161     /* Hardware */
 162     uint8_t it_shift;
 163     bool big_endian;
 164     bool last_rba_is_full;
 165     qemu_irq irq;
 166 #ifdef DEBUG_SONIC
 167     int irq_level;
 168 #endif
 169     QEMUTimer *watchdog;
 170     int64_t wt_last_update;
 171     NICConf conf;
 172     NICState *nic;
 173     MemoryRegion mmio;
 174     MemoryRegion prom;
 175
 176     /* Registers */
 177     uint8_t cam[16][6];
 178     uint16_t regs[0x40];
 179
 180     /* Temporaries */
 181     uint8_t tx_buffer[0x10000];
 182     uint16_t data[12];
 183     int loopback_packet;
 184
 185     /* Memory access */
 186     MemoryRegion *dma_mr;
 187     AddressSpace as;
 188 };
 189
 190 /* Accessor functions for values which are formed by
 191  * concatenating two 16 bit device registers. By putting these
 192  * in their own functions with a uint32_t return type we avoid the
 193  * pitfall of implicit sign extension where ((x << 16) | y) is a
 194  * signed 32 bit integer that might get sign-extended to a 64 bit integer.
 195  */
 196 static uint32_t dp8393x_cdp(dp8393xState *s)
 197 {
 198     return (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_CDP];
 199 }
 200
 201 static uint32_t dp8393x_crba(dp8393xState *s)
 202 {
 203     return (s->regs[SONIC_CRBA1] << 16) | s->regs[SONIC_CRBA0];
 204 }
 205
 206 static uint32_t dp8393x_crda(dp8393xState *s)
 207 {
 208     return (s->regs[SONIC_URDA] << 16) |
 209            (s->regs[SONIC_CRDA] & SONIC_DESC_ADDR);
 210 }
 211
 212 static uint32_t dp8393x_rbwc(dp8393xState *s)
 213 {
 214     return (s->regs[SONIC_RBWC1] << 16) | s->regs[SONIC_RBWC0];
 215 }
 216
 217 static uint32_t dp8393x_rrp(dp8393xState *s)
 218 {
 219     return (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_RRP];
 220 }
 221
 222 static uint32_t dp8393x_tsa(dp8393xState *s)
 223 {
 224     return (s->regs[SONIC_TSA1] << 16) | s->regs[SONIC_TSA0];
 225 }
 226
 227 static uint32_t dp8393x_ttda(dp8393xState *s)
 228 {
 229     return (s->regs[SONIC_UTDA] << 16) |
 230            (s->regs[SONIC_TTDA] & SONIC_DESC_ADDR);
 231 }
 232
 233 static uint32_t dp8393x_wt(dp8393xState *s)
 234 {
 235     return s->regs[SONIC_WT1] << 16 | s->regs[SONIC_WT0];
 236 }
 237
 238 static uint16_t dp8393x_get(dp8393xState *s, int width, int offset)
 239 {
 240     uint16_t val;
 241
 242     if (s->big_endian) {
 243         val = be16_to_cpu(s->data[offset * width + width - 1]);
 244     } else {
 245         val = le16_to_cpu(s->data[offset * width]);
 246     }
 247     return val;
 248 }
 249
 250 static void dp8393x_put(dp8393xState *s, int width, int offset,
 251                         uint16_t val)
 252 {
 253     if (s->big_endian) {
 254         if (width == 2) {
 255             s->data[offset * 2] = 0;
 256             s->data[offset * 2 + 1] = cpu_to_be16(val);
 257         } else {
 258             s->data[offset] = cpu_to_be16(val);
 259         }
 260     } else {
 261         if (width == 2) {
 262             s->data[offset * 2] = cpu_to_le16(val);
 263             s->data[offset * 2 + 1] = 0;
 264         } else {
 265             s->data[offset] = cpu_to_le16(val);
 266         }
 267     }
 268 }
 269
 270 static void dp8393x_update_irq(dp8393xState *s)
 271 {
 272     int level = (s->regs[SONIC_IMR] & s->regs[SONIC_ISR]) ? 1 : 0;
 273
 274 #ifdef DEBUG_SONIC
 275     if (level != s->irq_level) {
 276         s->irq_level = level;
 277         if (level) {
 278             DPRINTF("raise irq, isr is 0x%04x\n", s->regs[SONIC_ISR]);
 279         } else {
 280             DPRINTF("lower irq\n");
 281         }
 282     }
 283 #endif
 284
 285     qemu_set_irq(s->irq, level);
 286 }
 287
 288 static void dp8393x_do_load_cam(dp8393xState *s)
 289 {
 290     int width, size;
 291     uint16_t index = 0;
 292
 293     width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
 294     size = sizeof(uint16_t) * 4 * width;
 295
 296     while (s->regs[SONIC_CDC] & 0x1f) {
 297         /* Fill current entry */
 298         address_space_read(&s->as, dp8393x_cdp(s),
 299                            MEMTXATTRS_UNSPECIFIED, s->data, size);
 300         s->cam[index][0] = dp8393x_get(s, width, 1) & 0xff;
 301         s->cam[index][1] = dp8393x_get(s, width, 1) >> 8;
 302         s->cam[index][2] = dp8393x_get(s, width, 2) & 0xff;
 303         s->cam[index][3] = dp8393x_get(s, width, 2) >> 8;
 304         s->cam[index][4] = dp8393x_get(s, width, 3) & 0xff;
 305         s->cam[index][5] = dp8393x_get(s, width, 3) >> 8;
 306         DPRINTF("load cam[%d] with %02x%02x%02x%02x%02x%02x\n", index,
 307             s->cam[index][0], s->cam[index][1], s->cam[index][2],
 308             s->cam[index][3], s->cam[index][4], s->cam[index][5]);
 309         /* Move to next entry */
 310         s->regs[SONIC_CDC]--;
 311         s->regs[SONIC_CDP] += size;
 312         index++;
 313     }
 314
 315     /* Read CAM enable */
 316     address_space_read(&s->as, dp8393x_cdp(s),
 317                        MEMTXATTRS_UNSPECIFIED, s->data, size);
 318     s->regs[SONIC_CE] = dp8393x_get(s, width, 0);
 319     DPRINTF("load cam done. cam enable mask 0x%04x\n", s->regs[SONIC_CE]);
 320
 321     /* Done */
 322     s->regs[SONIC_CR] &= ~SONIC_CR_LCAM;
 323     s->regs[SONIC_ISR] |= SONIC_ISR_LCD;
 324     dp8393x_update_irq(s);
 325 }
 326
 327 static void dp8393x_do_read_rra(dp8393xState *s)
 328 {
 329     int width, size;
 330
 331     /* Read memory */
 332     width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
 333     size = sizeof(uint16_t) * 4 * width;
 334     address_space_read(&s->as, dp8393x_rrp(s),
 335                        MEMTXATTRS_UNSPECIFIED, s->data, size);
 336
 337     /* Update SONIC registers */
 338     s->regs[SONIC_CRBA0] = dp8393x_get(s, width, 0);
 339     s->regs[SONIC_CRBA1] = dp8393x_get(s, width, 1);
 340     s->regs[SONIC_RBWC0] = dp8393x_get(s, width, 2);
 341     s->regs[SONIC_RBWC1] = dp8393x_get(s, width, 3);
 342     DPRINTF("CRBA0/1: 0x%04x/0x%04x, RBWC0/1: 0x%04x/0x%04x\n",
 343         s->regs[SONIC_CRBA0], s->regs[SONIC_CRBA1],
 344         s->regs[SONIC_RBWC0], s->regs[SONIC_RBWC1]);
 345
 346     /* Go to next entry */
 347     s->regs[SONIC_RRP] += size;
 348
 349     /* Handle wrap */
 350     if (s->regs[SONIC_RRP] == s->regs[SONIC_REA]) {
 351         s->regs[SONIC_RRP] = s->regs[SONIC_RSA];
 352     }
 353
 354     /* Warn the host if CRBA now has the last available resource */
 355     if (s->regs[SONIC_RRP] == s->regs[SONIC_RWP])
 356     {
 357         s->regs[SONIC_ISR] |= SONIC_ISR_RBE;
 358         dp8393x_update_irq(s);
 359     }
 360
 361     /* Allow packet reception */
 362     s->last_rba_is_full = false;
 363 }
 364
 365 static void dp8393x_do_software_reset(dp8393xState *s)
 366 {
 367     timer_del(s->watchdog);
 368
 369     s->regs[SONIC_CR] &= ~(SONIC_CR_LCAM | SONIC_CR_RRRA | SONIC_CR_TXP | SONIC_CR_HTX);
 370     s->regs[SONIC_CR] |= SONIC_CR_RST | SONIC_CR_RXDIS;
 371 }
 372
 373 static void dp8393x_set_next_tick(dp8393xState *s)
 374 {
 375     uint32_t ticks;
 376     int64_t delay;
 377
 378     if (s->regs[SONIC_CR] & SONIC_CR_STP) {
 379         timer_del(s->watchdog);
 380         return;
 381     }
 382
 383     ticks = dp8393x_wt(s);
 384     s->wt_last_update = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 385     delay = NANOSECONDS_PER_SECOND * ticks / 5000000;
 386     timer_mod(s->watchdog, s->wt_last_update + delay);
 387 }
 388
 389 static void dp8393x_update_wt_regs(dp8393xState *s)
 390 {
 391     int64_t elapsed;
 392     uint32_t val;
 393
 394     if (s->regs[SONIC_CR] & SONIC_CR_STP) {
 395         timer_del(s->watchdog);
 396         return;
 397     }
 398
 399     elapsed = s->wt_last_update - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 400     val = dp8393x_wt(s);
 401     val -= elapsed / 5000000;
 402     s->regs[SONIC_WT1] = (val >> 16) & 0xffff;
 403     s->regs[SONIC_WT0] = (val >> 0)  & 0xffff;
 404     dp8393x_set_next_tick(s);
 405
 406 }
 407
 408 static void dp8393x_do_start_timer(dp8393xState *s)
 409 {
 410     s->regs[SONIC_CR] &= ~SONIC_CR_STP;
 411     dp8393x_set_next_tick(s);
 412 }
 413
 414 static void dp8393x_do_stop_timer(dp8393xState *s)
 415 {
 416     s->regs[SONIC_CR] &= ~SONIC_CR_ST;
 417     dp8393x_update_wt_regs(s);
 418 }
 419
 420 static bool dp8393x_can_receive(NetClientState *nc);
 421
 422 static void dp8393x_do_receiver_enable(dp8393xState *s)
 423 {
 424     s->regs[SONIC_CR] &= ~SONIC_CR_RXDIS;
 425     if (dp8393x_can_receive(s->nic->ncs)) {
 426         qemu_flush_queued_packets(qemu_get_queue(s->nic));
 427     }
 428 }
 429
 430 static void dp8393x_do_receiver_disable(dp8393xState *s)
 431 {
 432     s->regs[SONIC_CR] &= ~SONIC_CR_RXEN;
 433 }
 434
 435 static void dp8393x_do_transmit_packets(dp8393xState *s)
 436 {
 437     NetClientState *nc = qemu_get_queue(s->nic);
 438     int width, size;
 439     int tx_len, len;
 440     uint16_t i;
 441
 442     width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
 443
 444     while (1) {
 445         /* Read memory */
 446         size = sizeof(uint16_t) * 6 * width;
 447         s->regs[SONIC_TTDA] = s->regs[SONIC_CTDA];
 448         DPRINTF("Transmit packet at %08x\n", dp8393x_ttda(s));
 449         address_space_read(&s->as, dp8393x_ttda(s) + sizeof(uint16_t) * width,
 450                            MEMTXATTRS_UNSPECIFIED, s->data, size);
 451         tx_len = 0;
 452
 453         /* Update registers */
 454         s->regs[SONIC_TCR] = dp8393x_get(s, width, 0) & 0xf000;
 455         s->regs[SONIC_TPS] = dp8393x_get(s, width, 1);
 456         s->regs[SONIC_TFC] = dp8393x_get(s, width, 2);
 457         s->regs[SONIC_TSA0] = dp8393x_get(s, width, 3);
 458         s->regs[SONIC_TSA1] = dp8393x_get(s, width, 4);
 459         s->regs[SONIC_TFS] = dp8393x_get(s, width, 5);
 460
 461         /* Handle programmable interrupt */
 462         if (s->regs[SONIC_TCR] & SONIC_TCR_PINT) {
 463             s->regs[SONIC_ISR] |= SONIC_ISR_PINT;
 464         } else {
 465             s->regs[SONIC_ISR] &= ~SONIC_ISR_PINT;
 466         }
 467
 468         for (i = 0; i < s->regs[SONIC_TFC]; ) {
 469             /* Append fragment */
 470             len = s->regs[SONIC_TFS];
 471             if (tx_len + len > sizeof(s->tx_buffer)) {
 472                 len = sizeof(s->tx_buffer) - tx_len;
 473             }
 474             address_space_read(&s->as, dp8393x_tsa(s), MEMTXATTRS_UNSPECIFIED,
 475                                &s->tx_buffer[tx_len], len);
 476             tx_len += len;
 477
 478             i++;
 479             if (i != s->regs[SONIC_TFC]) {
 480                 /* Read next fragment details */
 481                 size = sizeof(uint16_t) * 3 * width;
 482                 address_space_read(&s->as,
 483                                    dp8393x_ttda(s)
 484                                    + sizeof(uint16_t) * width * (4 + 3 * i),
 485                                    MEMTXATTRS_UNSPECIFIED, s->data,
 486                                    size);
 487                 s->regs[SONIC_TSA0] = dp8393x_get(s, width, 0);
 488                 s->regs[SONIC_TSA1] = dp8393x_get(s, width, 1);
 489                 s->regs[SONIC_TFS] = dp8393x_get(s, width, 2);
 490             }
 491         }
 492
 493         /* Handle Ethernet checksum */
 494         if (!(s->regs[SONIC_TCR] & SONIC_TCR_CRCI)) {
 495             /* Don't append FCS there, to look like slirp packets
 496              * which don't have one */
 497         } else {
 498             /* Remove existing FCS */
 499             tx_len -= 4;
 500         }
 501
 502         if (s->regs[SONIC_RCR] & (SONIC_RCR_LB1 | SONIC_RCR_LB0)) {
 503             /* Loopback */
 504             s->regs[SONIC_TCR] |= SONIC_TCR_CRSL;
 505             if (nc->info->can_receive(nc)) {
 506                 s->loopback_packet = 1;
 507                 nc->info->receive(nc, s->tx_buffer, tx_len);
 508             }
 509         } else {
 510             /* Transmit packet */
 511             qemu_send_packet(nc, s->tx_buffer, tx_len);
 512         }
 513         s->regs[SONIC_TCR] |= SONIC_TCR_PTX;
 514
 515         /* Write status */
 516         dp8393x_put(s, width, 0,
 517                     s->regs[SONIC_TCR] & 0x0fff); /* status */
 518         size = sizeof(uint16_t) * width;
 519         address_space_write(&s->as, dp8393x_ttda(s),
 520                             MEMTXATTRS_UNSPECIFIED, s->data, size);
 521
 522         if (!(s->regs[SONIC_CR] & SONIC_CR_HTX)) {
 523             /* Read footer of packet */
 524             size = sizeof(uint16_t) * width;
 525             address_space_read(&s->as,
 526                                dp8393x_ttda(s)
 527                                + sizeof(uint16_t) * width
 528                                  * (4 + 3 * s->regs[SONIC_TFC]),
 529                                MEMTXATTRS_UNSPECIFIED, s->data,
 530                                size);
 531             s->regs[SONIC_CTDA] = dp8393x_get(s, width, 0);
 532             if (s->regs[SONIC_CTDA] & SONIC_DESC_EOL) {
 533                 /* EOL detected */
 534                 break;
 535             }
 536         }
 537     }
 538
 539     /* Done */
 540     s->regs[SONIC_CR] &= ~SONIC_CR_TXP;
 541     s->regs[SONIC_ISR] |= SONIC_ISR_TXDN;
 542     dp8393x_update_irq(s);
 543 }
 544
 545 static void dp8393x_do_halt_transmission(dp8393xState *s)
 546 {
 547     /* Nothing to do */
 548 }
 549
 550 static void dp8393x_do_command(dp8393xState *s, uint16_t command)
 551 {
 552     if ((s->regs[SONIC_CR] & SONIC_CR_RST) && !(command & SONIC_CR_RST)) {
 553         s->regs[SONIC_CR] &= ~SONIC_CR_RST;
 554         return;
 555     }
 556
 557     s->regs[SONIC_CR] |= (command & SONIC_CR_MASK);
 558
 559     if (command & SONIC_CR_HTX)
 560         dp8393x_do_halt_transmission(s);
 561     if (command & SONIC_CR_TXP)
 562         dp8393x_do_transmit_packets(s);
 563     if (command & SONIC_CR_RXDIS)
 564         dp8393x_do_receiver_disable(s);
 565     if (command & SONIC_CR_RXEN)
 566         dp8393x_do_receiver_enable(s);
 567     if (command & SONIC_CR_STP)
 568         dp8393x_do_stop_timer(s);
 569     if (command & SONIC_CR_ST)
 570         dp8393x_do_start_timer(s);
 571     if (command & SONIC_CR_RST)
 572         dp8393x_do_software_reset(s);
 573     if (command & SONIC_CR_RRRA) {
 574         dp8393x_do_read_rra(s);
 575         s->regs[SONIC_CR] &= ~SONIC_CR_RRRA;
 576     }
 577     if (command & SONIC_CR_LCAM)
 578         dp8393x_do_load_cam(s);
 579 }
 580
 581 static uint64_t dp8393x_read(void *opaque, hwaddr addr, unsigned int size)
 582 {
 583     dp8393xState *s = opaque;
 584     int reg = addr >> s->it_shift;
 585     uint16_t val = 0;
 586
 587     switch (reg) {
 588         /* Update data before reading it */
 589         case SONIC_WT0:
 590         case SONIC_WT1:
 591             dp8393x_update_wt_regs(s);
 592             val = s->regs[reg];
 593             break;
 594         /* Accept read to some registers only when in reset mode */
 595         case SONIC_CAP2:
 596         case SONIC_CAP1:
 597         case SONIC_CAP0:
 598             if (s->regs[SONIC_CR] & SONIC_CR_RST) {
 599                 val = s->cam[s->regs[SONIC_CEP] & 0xf][2* (SONIC_CAP0 - reg) + 1] << 8;
 600                 val |= s->cam[s->regs[SONIC_CEP] & 0xf][2* (SONIC_CAP0 - reg)];
 601             }
 602             break;
 603         /* All other registers have no special contrainst */
 604         default:
 605             val = s->regs[reg];
 606     }
 607
 608     DPRINTF("read 0x%04x from reg %s\n", val, reg_names[reg]);
 609
 610     return s->big_endian ? val << 16 : val;
 611 }
 612
 613 static void dp8393x_write(void *opaque, hwaddr addr, uint64_t data,
 614                           unsigned int size)
 615 {
 616     dp8393xState *s = opaque;
 617     int reg = addr >> s->it_shift;
 618     uint32_t val = s->big_endian ? data >> 16 : data;
 619
 620     DPRINTF("write 0x%04x to reg %s\n", (uint16_t)val, reg_names[reg]);
 621
 622     switch (reg) {
 623         /* Command register */
 624         case SONIC_CR:
 625             dp8393x_do_command(s, val);
 626             break;
 627         /* Prevent write to read-only registers */
 628         case SONIC_CAP2:
 629         case SONIC_CAP1:
 630         case SONIC_CAP0:
 631         case SONIC_SR:
 632         case SONIC_MDT:
 633             DPRINTF("writing to reg %d invalid\n", reg);
 634             break;
 635         /* Accept write to some registers only when in reset mode */
 636         case SONIC_DCR:
 637             if (s->regs[SONIC_CR] & SONIC_CR_RST) {
 638                 s->regs[reg] = val & 0xbfff;
 639             } else {
 640                 DPRINTF("writing to DCR invalid\n");
 641             }
 642             break;
 643         case SONIC_DCR2:
 644             if (s->regs[SONIC_CR] & SONIC_CR_RST) {
 645                 s->regs[reg] = val & 0xf017;
 646             } else {
 647                 DPRINTF("writing to DCR2 invalid\n");
 648             }
 649             break;
 650         /* 12 lower bytes are Read Only */
 651         case SONIC_TCR:
 652             s->regs[reg] = val & 0xf000;
 653             break;
 654         /* 9 lower bytes are Read Only */
 655         case SONIC_RCR:
 656             s->regs[reg] = val & 0xffe0;
 657             break;
 658         /* Ignore most significant bit */
 659         case SONIC_IMR:
 660             s->regs[reg] = val & 0x7fff;
 661             dp8393x_update_irq(s);
 662             break;
 663         /* Clear bits by writing 1 to them */
 664         case SONIC_ISR:
 665             val &= s->regs[reg];
 666             s->regs[reg] &= ~val;
 667             if (val & SONIC_ISR_RBE) {
 668                 dp8393x_do_read_rra(s);
 669             }
 670             dp8393x_update_irq(s);
 671             break;
 672         /* The guest is required to store aligned pointers here */
 673         case SONIC_RSA:
 674         case SONIC_REA:
 675         case SONIC_RRP:
 676         case SONIC_RWP:
 677             if (s->regs[SONIC_DCR] & SONIC_DCR_DW) {
 678                 s->regs[reg] = val & 0xfffc;
 679             } else {
 680                 s->regs[reg] = val & 0xfffe;
 681             }
 682             break;
 683         /* Invert written value for some registers */
 684         case SONIC_CRCT:
 685         case SONIC_FAET:
 686         case SONIC_MPT:
 687             s->regs[reg] = val ^ 0xffff;
 688             break;
 689         /* All other registers have no special contrainst */
 690         default:
 691             s->regs[reg] = val;
 692     }
 693
 694     if (reg == SONIC_WT0 || reg == SONIC_WT1) {
 695         dp8393x_set_next_tick(s);
 696     }
 697 }
 698
 699 static const MemoryRegionOps dp8393x_ops = {
 700     .read = dp8393x_read,
 701     .write = dp8393x_write,
 702     .impl.min_access_size = 4,
 703     .impl.max_access_size = 4,
 704     .endianness = DEVICE_NATIVE_ENDIAN,
 705 };
 706
 707 static void dp8393x_watchdog(void *opaque)
 708 {
 709     dp8393xState *s = opaque;
 710
 711     if (s->regs[SONIC_CR] & SONIC_CR_STP) {
 712         return;
 713     }
 714
 715     s->regs[SONIC_WT1] = 0xffff;
 716     s->regs[SONIC_WT0] = 0xffff;
 717     dp8393x_set_next_tick(s);
 718
 719     /* Signal underflow */
 720     s->regs[SONIC_ISR] |= SONIC_ISR_TC;
 721     dp8393x_update_irq(s);
 722 }
 723
 724 static bool dp8393x_can_receive(NetClientState *nc)
 725 {
 726     dp8393xState *s = qemu_get_nic_opaque(nc);
 727
 728     return !!(s->regs[SONIC_CR] & SONIC_CR_RXEN);
 729 }
 730
 731 static int dp8393x_receive_filter(dp8393xState *s, const uint8_t * buf,
 732                                   int size)
 733 {
 734     static const uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
 735     int i;
 736
 737     /* Check promiscuous mode */
 738     if ((s->regs[SONIC_RCR] & SONIC_RCR_PRO) && (buf[0] & 1) == 0) {
 739         return 0;
 740     }
 741
 742     /* Check multicast packets */
 743     if ((s->regs[SONIC_RCR] & SONIC_RCR_AMC) && (buf[0] & 1) == 1) {
 744         return SONIC_RCR_MC;
 745     }
 746
 747     /* Check broadcast */
 748     if ((s->regs[SONIC_RCR] & SONIC_RCR_BRD) && !memcmp(buf, bcast, sizeof(bcast))) {
 749         return SONIC_RCR_BC;
 750     }
 751
 752     /* Check CAM */
 753     for (i = 0; i < 16; i++) {
 754         if (s->regs[SONIC_CE] & (1 << i)) {
 755              /* Entry enabled */
 756              if (!memcmp(buf, s->cam[i], sizeof(s->cam[i]))) {
 757                  return 0;
 758              }
 759         }
 760     }
 761
 762     return -1;
 763 }
 764
 765 static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
 766                                size_t pkt_size)
 767 {
 768     dp8393xState *s = qemu_get_nic_opaque(nc);
 769     int packet_type;
 770     uint32_t available, address;
 771     int width, rx_len, padded_len;
 772     uint32_t checksum;
 773     int size;
 774
 775     s->regs[SONIC_RCR] &= ~(SONIC_RCR_PRX | SONIC_RCR_LBK | SONIC_RCR_FAER |
 776         SONIC_RCR_CRCR | SONIC_RCR_LPKT | SONIC_RCR_BC | SONIC_RCR_MC);
 777
 778     if (s->last_rba_is_full) {
 779         return pkt_size;
 780     }
 781
 782     rx_len = pkt_size + sizeof(checksum);
 783     if (s->regs[SONIC_DCR] & SONIC_DCR_DW) {
 784         width = 2;
 785         padded_len = ((rx_len - 1) | 3) + 1;
 786     } else {
 787         width = 1;
 788         padded_len = ((rx_len - 1) | 1) + 1;
 789     }
 790
 791     if (padded_len > dp8393x_rbwc(s) * 2) {
 792         DPRINTF("oversize packet, pkt_size is %d\n", pkt_size);
 793         s->regs[SONIC_ISR] |= SONIC_ISR_RBAE;
 794         dp8393x_update_irq(s);
 795         s->regs[SONIC_RCR] |= SONIC_RCR_LPKT;
 796         goto done;
 797     }
 798
 799     packet_type = dp8393x_receive_filter(s, buf, pkt_size);
 800     if (packet_type < 0) {
 801         DPRINTF("packet not for netcard\n");
 802         return -1;
 803     }
 804
 805     /* Check for EOL */
 806     if (s->regs[SONIC_LLFA] & SONIC_DESC_EOL) {
 807         /* Are we still in resource exhaustion? */
 808         size = sizeof(uint16_t) * 1 * width;
 809         address = dp8393x_crda(s) + sizeof(uint16_t) * 5 * width;
 810         address_space_read(&s->as, address, MEMTXATTRS_UNSPECIFIED,
 811                            s->data, size);
 812         s->regs[SONIC_LLFA] = dp8393x_get(s, width, 0);
 813         if (s->regs[SONIC_LLFA] & SONIC_DESC_EOL) {
 814             /* Still EOL ; stop reception */
 815             return -1;
 816         }
 817         /* Link has been updated by host */
 818
 819         /* Clear in_use */
 820         size = sizeof(uint16_t) * width;
 821         address = dp8393x_crda(s) + sizeof(uint16_t) * 6 * width;
 822         dp8393x_put(s, width, 0, 0);
 823         address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED,
 824                          (uint8_t *)s->data, size, 1);
 825
 826         /* Move to next descriptor */
 827         s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA];
 828         s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX;
 829     }
 830
 831     /* Save current position */
 832     s->regs[SONIC_TRBA1] = s->regs[SONIC_CRBA1];
 833     s->regs[SONIC_TRBA0] = s->regs[SONIC_CRBA0];
 834
 835     /* Calculate the ethernet checksum */
 836     checksum = cpu_to_le32(crc32(0, buf, pkt_size));
 837
 838     /* Put packet into RBA */
 839     DPRINTF("Receive packet at %08x\n", dp8393x_crba(s));
 840     address = dp8393x_crba(s);
 841     address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED,
 842                         buf, pkt_size);
 843     address += pkt_size;
 844
 845     /* Put frame checksum into RBA */
 846     address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED,
 847                         &checksum, sizeof(checksum));
 848     address += sizeof(checksum);
 849
 850     /* Pad short packets to keep pointers aligned */
 851     if (rx_len < padded_len) {
 852         size = padded_len - rx_len;
 853         address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED,
 854             (uint8_t *)"\xFF\xFF\xFF", size, 1);
 855         address += size;
 856     }
 857
 858     s->regs[SONIC_CRBA1] = address >> 16;
 859     s->regs[SONIC_CRBA0] = address & 0xffff;
 860     available = dp8393x_rbwc(s);
 861     available -= padded_len >> 1;
 862     s->regs[SONIC_RBWC1] = available >> 16;
 863     s->regs[SONIC_RBWC0] = available & 0xffff;
 864
 865     /* Update status */
 866     if (dp8393x_rbwc(s) < s->regs[SONIC_EOBC]) {
 867         s->regs[SONIC_RCR] |= SONIC_RCR_LPKT;
 868     }
 869     s->regs[SONIC_RCR] |= packet_type;
 870     s->regs[SONIC_RCR] |= SONIC_RCR_PRX;
 871     if (s->loopback_packet) {
 872         s->regs[SONIC_RCR] |= SONIC_RCR_LBK;
 873         s->loopback_packet = 0;
 874     }
 875
 876     /* Write status to memory */
 877     DPRINTF("Write status at %08x\n", dp8393x_crda(s));
 878     dp8393x_put(s, width, 0, s->regs[SONIC_RCR]); /* status */
 879     dp8393x_put(s, width, 1, rx_len); /* byte count */
 880     dp8393x_put(s, width, 2, s->regs[SONIC_TRBA0]); /* pkt_ptr0 */
 881     dp8393x_put(s, width, 3, s->regs[SONIC_TRBA1]); /* pkt_ptr1 */
 882     dp8393x_put(s, width, 4, s->regs[SONIC_RSC]); /* seq_no */
 883     size = sizeof(uint16_t) * 5 * width;
 884     address_space_write(&s->as, dp8393x_crda(s),
 885                         MEMTXATTRS_UNSPECIFIED,
 886                         s->data, size);
 887
 888     /* Check link field */
 889     size = sizeof(uint16_t) * width;
 890     address_space_read(&s->as,
 891                        dp8393x_crda(s) + sizeof(uint16_t) * 5 * width,
 892                        MEMTXATTRS_UNSPECIFIED, s->data, size);
 893     s->regs[SONIC_LLFA] = dp8393x_get(s, width, 0);
 894     if (s->regs[SONIC_LLFA] & SONIC_DESC_EOL) {
 895         /* EOL detected */
 896         s->regs[SONIC_ISR] |= SONIC_ISR_RDE;
 897     } else {
 898         /* Clear in_use */
 899         size = sizeof(uint16_t) * width;
 900         address = dp8393x_crda(s) + sizeof(uint16_t) * 6 * width;
 901         dp8393x_put(s, width, 0, 0);
 902         address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED,
 903                             s->data, size);
 904
 905         /* Move to next descriptor */
 906         s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA];
 907         s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX;
 908     }
 909
 910     dp8393x_update_irq(s);
 911
 912     s->regs[SONIC_RSC] = (s->regs[SONIC_RSC] & 0xff00) |
 913                          ((s->regs[SONIC_RSC] + 1) & 0x00ff);
 914
 915 done:
 916
 917     if (s->regs[SONIC_RCR] & SONIC_RCR_LPKT) {
 918         if (s->regs[SONIC_RRP] == s->regs[SONIC_RWP]) {
 919             /* Stop packet reception */
 920             s->last_rba_is_full = true;
 921         } else {
 922             /* Read next resource */
 923             dp8393x_do_read_rra(s);
 924         }
 925     }
 926
 927     return pkt_size;
 928 }
 929
 930 static void dp8393x_reset(DeviceState *dev)
 931 {
 932     dp8393xState *s = DP8393X(dev);
 933     timer_del(s->watchdog);
 934
 935     memset(s->regs, 0, sizeof(s->regs));
 936     s->regs[SONIC_SR] = 0x0004; /* only revision recognized by Linux/mips */
 937     s->regs[SONIC_CR] = SONIC_CR_RST | SONIC_CR_STP | SONIC_CR_RXDIS;
 938     s->regs[SONIC_DCR] &= ~(SONIC_DCR_EXBUS | SONIC_DCR_LBR);
 939     s->regs[SONIC_RCR] &= ~(SONIC_RCR_LB0 | SONIC_RCR_LB1 | SONIC_RCR_BRD | SONIC_RCR_RNT);
 940     s->regs[SONIC_TCR] |= SONIC_TCR_NCRS | SONIC_TCR_PTX;
 941     s->regs[SONIC_TCR] &= ~SONIC_TCR_BCM;
 942     s->regs[SONIC_IMR] = 0;
 943     s->regs[SONIC_ISR] = 0;
 944     s->regs[SONIC_DCR2] = 0;
 945     s->regs[SONIC_EOBC] = 0x02F8;
 946     s->regs[SONIC_RSC] = 0;
 947     s->regs[SONIC_CE] = 0;
 948     s->regs[SONIC_RSC] = 0;
 949
 950     /* Network cable is connected */
 951     s->regs[SONIC_RCR] |= SONIC_RCR_CRS;
 952
 953     dp8393x_update_irq(s);
 954 }
 955
 956 static NetClientInfo net_dp83932_info = {
 957     .type = NET_CLIENT_DRIVER_NIC,
 958     .size = sizeof(NICState),
 959     .can_receive = dp8393x_can_receive,
 960     .receive = dp8393x_receive,
 961 };
 962
 963 static void dp8393x_instance_init(Object *obj)
 964 {
 965     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 966     dp8393xState *s = DP8393X(obj);
 967
 968     sysbus_init_mmio(sbd, &s->mmio);
 969     sysbus_init_mmio(sbd, &s->prom);
 970     sysbus_init_irq(sbd, &s->irq);
 971 }
 972
 973 static void dp8393x_realize(DeviceState *dev, Error **errp)
 974 {
 975     dp8393xState *s = DP8393X(dev);
 976     int i, checksum;
 977     uint8_t *prom;
 978     Error *local_err = NULL;
 979
 980     address_space_init(&s->as, s->dma_mr, "dp8393x");
 981     memory_region_init_io(&s->mmio, OBJECT(dev), &dp8393x_ops, s,
 982                           "dp8393x-regs", 0x40 << s->it_shift);
 983
 984     s->nic = qemu_new_nic(&net_dp83932_info, &s->conf,
 985                           object_get_typename(OBJECT(dev)), dev->id, s);
 986     qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
 987
 988     s->watchdog = timer_new_ns(QEMU_CLOCK_VIRTUAL, dp8393x_watchdog, s);
 989
 990     memory_region_init_rom(&s->prom, OBJECT(dev), "dp8393x-prom",
 991                            SONIC_PROM_SIZE, &local_err);
 992     if (local_err) {
 993         error_propagate(errp, local_err);
 994         return;
 995     }
 996     prom = memory_region_get_ram_ptr(&s->prom);
 997     checksum = 0;
 998     for (i = 0; i < 6; i++) {
 999         prom[i] = s->conf.macaddr.a[i];
1000         checksum += prom[i];
1001         if (checksum > 0xff) {
1002             checksum = (checksum + 1) & 0xff;
1003         }
1004     }
1005     prom[7] = 0xff - checksum;
1006 }
1007
1008 static const VMStateDescription vmstate_dp8393x = {
1009     .name = "dp8393x",
1010     .version_id = 0,
1011     .minimum_version_id = 0,
1012     .fields = (VMStateField []) {
1013         VMSTATE_BUFFER_UNSAFE(cam, dp8393xState, 0, 16 * 6),
1014         VMSTATE_UINT16_ARRAY(regs, dp8393xState, 0x40),
1015         VMSTATE_END_OF_LIST()
1016     }
1017 };
1018
1019 static Property dp8393x_properties[] = {
1020     DEFINE_NIC_PROPERTIES(dp8393xState, conf),
1021     DEFINE_PROP_LINK("dma_mr", dp8393xState, dma_mr,
1022                      TYPE_MEMORY_REGION, MemoryRegion *),
1023     DEFINE_PROP_UINT8("it_shift", dp8393xState, it_shift, 0),
1024     DEFINE_PROP_BOOL("big_endian", dp8393xState, big_endian, false),
1025     DEFINE_PROP_END_OF_LIST(),
1026 };
1027
1028 static void dp8393x_class_init(ObjectClass *klass, void *data)
1029 {
1030     DeviceClass *dc = DEVICE_CLASS(klass);
1031
1032     set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
1033     dc->realize = dp8393x_realize;
1034     dc->reset = dp8393x_reset;
1035     dc->vmsd = &vmstate_dp8393x;
1036     device_class_set_props(dc, dp8393x_properties);
1037 }
1038
1039 static const TypeInfo dp8393x_info = {
1040     .name          = TYPE_DP8393X,
1041     .parent        = TYPE_SYS_BUS_DEVICE,
1042     .instance_size = sizeof(dp8393xState),
1043     .instance_init = dp8393x_instance_init,
1044     .class_init    = dp8393x_class_init,
1045 };
1046
1047 static void dp8393x_register_types(void)
1048 {
1049     type_register_static(&dp8393x_info);
1050 }
1051
1052 type_init(dp8393x_register_types)