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Merge tag 'v9.0.0-rc3'
[qemu/ar7.git] / hw / net / dp8393x.c
blobbf0652da1b49f970f6bb11d4dbe2d4a73978337b
1 /*
2 * QEMU NS SONIC DP8393x netcard
3 *
4 * Copyright (c) 2008-2009 Herve Poussineau
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "hw/irq.h"
22 #include "hw/qdev-properties.h"
23 #include "hw/net/dp8393x.h"
24 #include "hw/sysbus.h"
25 #include "migration/vmstate.h"
26 #include "net/net.h"
27 #include "qapi/error.h"
28 #include "qemu/module.h"
29 #include "qemu/timer.h"
30 #include <zlib.h>
31 #include "qom/object.h"
32 #include "trace.h"
33
34 static const char *reg_names[] = {
35 "CR", "DCR", "RCR", "TCR", "IMR", "ISR", "UTDA", "CTDA",
36 "TPS", "TFC", "TSA0", "TSA1", "TFS", "URDA", "CRDA", "CRBA0",
37 "CRBA1", "RBWC0", "RBWC1", "EOBC", "URRA", "RSA", "REA", "RRP",
38 "RWP", "TRBA0", "TRBA1", "0x1b", "0x1c", "0x1d", "0x1e", "LLFA",
39 "TTDA", "CEP", "CAP2", "CAP1", "CAP0", "CE", "CDP", "CDC",
40 "SR", "WT0", "WT1", "RSC", "CRCT", "FAET", "MPT", "MDT",
41 "0x30", "0x31", "0x32", "0x33", "0x34", "0x35", "0x36", "0x37",
42 "0x38", "0x39", "0x3a", "0x3b", "0x3c", "0x3d", "0x3e", "DCR2" };
43
44 #define SONIC_CR 0x00
45 #define SONIC_DCR 0x01
46 #define SONIC_RCR 0x02
47 #define SONIC_TCR 0x03
48 #define SONIC_IMR 0x04
49 #define SONIC_ISR 0x05
50 #define SONIC_UTDA 0x06
51 #define SONIC_CTDA 0x07
52 #define SONIC_TPS 0x08
53 #define SONIC_TFC 0x09
54 #define SONIC_TSA0 0x0a
55 #define SONIC_TSA1 0x0b
56 #define SONIC_TFS 0x0c
57 #define SONIC_URDA 0x0d
58 #define SONIC_CRDA 0x0e
59 #define SONIC_CRBA0 0x0f
60 #define SONIC_CRBA1 0x10
61 #define SONIC_RBWC0 0x11
62 #define SONIC_RBWC1 0x12
63 #define SONIC_EOBC 0x13
64 #define SONIC_URRA 0x14
65 #define SONIC_RSA 0x15
66 #define SONIC_REA 0x16
67 #define SONIC_RRP 0x17
68 #define SONIC_RWP 0x18
69 #define SONIC_TRBA0 0x19
70 #define SONIC_TRBA1 0x1a
71 #define SONIC_LLFA 0x1f
72 #define SONIC_TTDA 0x20
73 #define SONIC_CEP 0x21
74 #define SONIC_CAP2 0x22
75 #define SONIC_CAP1 0x23
76 #define SONIC_CAP0 0x24
77 #define SONIC_CE 0x25
78 #define SONIC_CDP 0x26
79 #define SONIC_CDC 0x27
80 #define SONIC_SR 0x28
81 #define SONIC_WT0 0x29
82 #define SONIC_WT1 0x2a
83 #define SONIC_RSC 0x2b
84 #define SONIC_CRCT 0x2c
85 #define SONIC_FAET 0x2d
86 #define SONIC_MPT 0x2e
87 #define SONIC_MDT 0x2f
88 #define SONIC_DCR2 0x3f
89
90 #define SONIC_CR_HTX 0x0001
91 #define SONIC_CR_TXP 0x0002
92 #define SONIC_CR_RXDIS 0x0004
93 #define SONIC_CR_RXEN 0x0008
94 #define SONIC_CR_STP 0x0010
95 #define SONIC_CR_ST 0x0020
96 #define SONIC_CR_RST 0x0080
97 #define SONIC_CR_RRRA 0x0100
98 #define SONIC_CR_LCAM 0x0200
99 #define SONIC_CR_MASK 0x03bf
100
101 #define SONIC_DCR_DW 0x0020
102 #define SONIC_DCR_LBR 0x2000
103 #define SONIC_DCR_EXBUS 0x8000
104
105 #define SONIC_RCR_PRX 0x0001
106 #define SONIC_RCR_LBK 0x0002
107 #define SONIC_RCR_FAER 0x0004
108 #define SONIC_RCR_CRCR 0x0008
109 #define SONIC_RCR_CRS 0x0020
110 #define SONIC_RCR_LPKT 0x0040
111 #define SONIC_RCR_BC 0x0080
112 #define SONIC_RCR_MC 0x0100
113 #define SONIC_RCR_LB0 0x0200
114 #define SONIC_RCR_LB1 0x0400
115 #define SONIC_RCR_AMC 0x0800
116 #define SONIC_RCR_PRO 0x1000
117 #define SONIC_RCR_BRD 0x2000
118 #define SONIC_RCR_RNT 0x4000
119
120 #define SONIC_TCR_PTX 0x0001
121 #define SONIC_TCR_BCM 0x0002
122 #define SONIC_TCR_FU 0x0004
123 #define SONIC_TCR_EXC 0x0040
124 #define SONIC_TCR_CRSL 0x0080
125 #define SONIC_TCR_NCRS 0x0100
126 #define SONIC_TCR_EXD 0x0400
127 #define SONIC_TCR_CRCI 0x2000
128 #define SONIC_TCR_PINT 0x8000
129
130 #define SONIC_ISR_RBAE 0x0010
131 #define SONIC_ISR_RBE 0x0020
132 #define SONIC_ISR_RDE 0x0040
133 #define SONIC_ISR_TC 0x0080
134 #define SONIC_ISR_TXDN 0x0200
135 #define SONIC_ISR_PKTRX 0x0400
136 #define SONIC_ISR_PINT 0x0800
137 #define SONIC_ISR_LCD 0x1000
138
139 #define SONIC_DESC_EOL 0x0001
140 #define SONIC_DESC_ADDR 0xFFFE
141
142
143 /*
144 * Accessor functions for values which are formed by
145 * concatenating two 16 bit device registers. By putting these
146 * in their own functions with a uint32_t return type we avoid the
147 * pitfall of implicit sign extension where ((x << 16) | y) is a
148 * signed 32 bit integer that might get sign-extended to a 64 bit integer.
149 */
150 static uint32_t dp8393x_cdp(dp8393xState *s)
151 {
152 return (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_CDP];
153 }
154
155 static uint32_t dp8393x_crba(dp8393xState *s)
156 {
157 return (s->regs[SONIC_CRBA1] << 16) | s->regs[SONIC_CRBA0];
158 }
159
160 static uint32_t dp8393x_crda(dp8393xState *s)
161 {
162 return (s->regs[SONIC_URDA] << 16) |
163 (s->regs[SONIC_CRDA] & SONIC_DESC_ADDR);
164 }
165
166 static uint32_t dp8393x_rbwc(dp8393xState *s)
167 {
168 return (s->regs[SONIC_RBWC1] << 16) | s->regs[SONIC_RBWC0];
169 }
170
171 static uint32_t dp8393x_rrp(dp8393xState *s)
172 {
173 return (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_RRP];
174 }
175
176 static uint32_t dp8393x_tsa(dp8393xState *s)
177 {
178 return (s->regs[SONIC_TSA1] << 16) | s->regs[SONIC_TSA0];
179 }
180
181 static uint32_t dp8393x_ttda(dp8393xState *s)
182 {
183 return (s->regs[SONIC_UTDA] << 16) |
184 (s->regs[SONIC_TTDA] & SONIC_DESC_ADDR);
185 }
186
187 static uint32_t dp8393x_wt(dp8393xState *s)
188 {
189 return s->regs[SONIC_WT1] << 16 | s->regs[SONIC_WT0];
190 }
191
192 static uint16_t dp8393x_get(dp8393xState *s, hwaddr addr, int offset)
193 {
194 const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
195 uint16_t val;
196
197 if (s->regs[SONIC_DCR] & SONIC_DCR_DW) {
198 addr += offset << 2;
199 if (s->big_endian) {
200 val = address_space_ldl_be(&s->as, addr, attrs, NULL);
201 } else {
202 val = address_space_ldl_le(&s->as, addr, attrs, NULL);
203 }
204 } else {
205 addr += offset << 1;
206 if (s->big_endian) {
207 val = address_space_lduw_be(&s->as, addr, attrs, NULL);
208 } else {
209 val = address_space_lduw_le(&s->as, addr, attrs, NULL);
210 }
211 }
212
213 return val;
214 }
215
216 static void dp8393x_put(dp8393xState *s,
217 hwaddr addr, int offset, uint16_t val)
218 {
219 const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
220
221 if (s->regs[SONIC_DCR] & SONIC_DCR_DW) {
222 addr += offset << 2;
223 if (s->big_endian) {
224 address_space_stl_be(&s->as, addr, val, attrs, NULL);
225 } else {
226 address_space_stl_le(&s->as, addr, val, attrs, NULL);
227 }
228 } else {
229 addr += offset << 1;
230 if (s->big_endian) {
231 address_space_stw_be(&s->as, addr, val, attrs, NULL);
232 } else {
233 address_space_stw_le(&s->as, addr, val, attrs, NULL);
234 }
235 }
236 }
237
238 static void dp8393x_update_irq(dp8393xState *s)
239 {
240 int level = (s->regs[SONIC_IMR] & s->regs[SONIC_ISR]) ? 1 : 0;
241
242 if (level != s->irq_level) {
243 s->irq_level = level;
244 if (level) {
245 trace_dp8393x_raise_irq(s->regs[SONIC_ISR]);
246 } else {
247 trace_dp8393x_lower_irq();
248 }
249 }
250
251 qemu_set_irq(s->irq, level);
252 }
253
254 static void dp8393x_do_load_cam(dp8393xState *s)
255 {
256 int width, size;
257 uint16_t index;
258
259 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
260 size = sizeof(uint16_t) * 4 * width;
261
262 while (s->regs[SONIC_CDC] & 0x1f) {
263 /* Fill current entry */
264 index = dp8393x_get(s, dp8393x_cdp(s), 0) & 0xf;
265 s->cam[index][0] = dp8393x_get(s, dp8393x_cdp(s), 1);
266 s->cam[index][1] = dp8393x_get(s, dp8393x_cdp(s), 2);
267 s->cam[index][2] = dp8393x_get(s, dp8393x_cdp(s), 3);
268 trace_dp8393x_load_cam(index,
269 s->cam[index][0] >> 8, s->cam[index][0] & 0xff,
270 s->cam[index][1] >> 8, s->cam[index][1] & 0xff,
271 s->cam[index][2] >> 8, s->cam[index][2] & 0xff);
272 /* Move to next entry */
273 s->regs[SONIC_CDC]--;
274 s->regs[SONIC_CDP] += size;
275 }
276
277 /* Read CAM enable */
278 s->regs[SONIC_CE] = dp8393x_get(s, dp8393x_cdp(s), 0);
279 trace_dp8393x_load_cam_done(s->regs[SONIC_CE]);
280
281 /* Done */
282 s->regs[SONIC_CR] &= ~SONIC_CR_LCAM;
283 s->regs[SONIC_ISR] |= SONIC_ISR_LCD;
284 dp8393x_update_irq(s);
285 }
286
287 static void dp8393x_do_read_rra(dp8393xState *s)
288 {
289 int width, size;
290
291 /* Read memory */
292 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
293 size = sizeof(uint16_t) * 4 * width;
294
295 /* Update SONIC registers */
296 s->regs[SONIC_CRBA0] = dp8393x_get(s, dp8393x_rrp(s), 0);
297 s->regs[SONIC_CRBA1] = dp8393x_get(s, dp8393x_rrp(s), 1);
298 s->regs[SONIC_RBWC0] = dp8393x_get(s, dp8393x_rrp(s), 2);
299 s->regs[SONIC_RBWC1] = dp8393x_get(s, dp8393x_rrp(s), 3);
300 trace_dp8393x_read_rra_regs(s->regs[SONIC_CRBA0], s->regs[SONIC_CRBA1],
301 s->regs[SONIC_RBWC0], s->regs[SONIC_RBWC1]);
302
303 /* Go to next entry */
304 s->regs[SONIC_RRP] += size;
305
306 /* Handle wrap */
307 if (s->regs[SONIC_RRP] == s->regs[SONIC_REA]) {
308 s->regs[SONIC_RRP] = s->regs[SONIC_RSA];
309 }
310
311 /* Warn the host if CRBA now has the last available resource */
312 if (s->regs[SONIC_RRP] == s->regs[SONIC_RWP]) {
313 s->regs[SONIC_ISR] |= SONIC_ISR_RBE;
314 dp8393x_update_irq(s);
315 }
316
317 /* Allow packet reception */
318 s->last_rba_is_full = false;
319 }
320
321 static void dp8393x_do_software_reset(dp8393xState *s)
322 {
323 timer_del(s->watchdog);
324
325 s->regs[SONIC_CR] &= ~(SONIC_CR_LCAM | SONIC_CR_RRRA | SONIC_CR_TXP |
326 SONIC_CR_HTX);
327 s->regs[SONIC_CR] |= SONIC_CR_RST | SONIC_CR_RXDIS;
328 }
329
330 static void dp8393x_set_next_tick(dp8393xState *s)
331 {
332 uint32_t ticks;
333 int64_t delay;
334
335 if (s->regs[SONIC_CR] & SONIC_CR_STP) {
336 timer_del(s->watchdog);
337 return;
338 }
339
340 ticks = dp8393x_wt(s);
341 s->wt_last_update = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
342 delay = NANOSECONDS_PER_SECOND * ticks / 5000000;
343 timer_mod(s->watchdog, s->wt_last_update + delay);
344 }
345
346 static void dp8393x_update_wt_regs(dp8393xState *s)
347 {
348 int64_t elapsed;
349 uint32_t val;
350
351 if (s->regs[SONIC_CR] & SONIC_CR_STP) {
352 timer_del(s->watchdog);
353 return;
354 }
355
356 elapsed = s->wt_last_update - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
357 val = dp8393x_wt(s);
358 val -= elapsed / 5000000;
359 s->regs[SONIC_WT1] = (val >> 16) & 0xffff;
360 s->regs[SONIC_WT0] = (val >> 0) & 0xffff;
361 dp8393x_set_next_tick(s);
362
363 }
364
365 static void dp8393x_do_start_timer(dp8393xState *s)
366 {
367 s->regs[SONIC_CR] &= ~SONIC_CR_STP;
368 dp8393x_set_next_tick(s);
369 }
370
371 static void dp8393x_do_stop_timer(dp8393xState *s)
372 {
373 s->regs[SONIC_CR] &= ~SONIC_CR_ST;
374 dp8393x_update_wt_regs(s);
375 }
376
377 static bool dp8393x_can_receive(NetClientState *nc);
378
379 static void dp8393x_do_receiver_enable(dp8393xState *s)
380 {
381 s->regs[SONIC_CR] &= ~SONIC_CR_RXDIS;
382 if (dp8393x_can_receive(s->nic->ncs)) {
383 qemu_flush_queued_packets(qemu_get_queue(s->nic));
384 }
385 }
386
387 static void dp8393x_do_receiver_disable(dp8393xState *s)
388 {
389 s->regs[SONIC_CR] &= ~SONIC_CR_RXEN;
390 }
391
392 static void dp8393x_do_transmit_packets(dp8393xState *s)
393 {
394 NetClientState *nc = qemu_get_queue(s->nic);
395 int tx_len, len;
396 uint16_t i;
397
398 while (1) {
399 /* Read memory */
400 s->regs[SONIC_TTDA] = s->regs[SONIC_CTDA];
401 trace_dp8393x_transmit_packet(dp8393x_ttda(s));
402 tx_len = 0;
403
404 /* Update registers */
405 s->regs[SONIC_TCR] = dp8393x_get(s, dp8393x_ttda(s), 1) & 0xf000;
406 s->regs[SONIC_TPS] = dp8393x_get(s, dp8393x_ttda(s), 2);
407 s->regs[SONIC_TFC] = dp8393x_get(s, dp8393x_ttda(s), 3);
408 s->regs[SONIC_TSA0] = dp8393x_get(s, dp8393x_ttda(s), 4);
409 s->regs[SONIC_TSA1] = dp8393x_get(s, dp8393x_ttda(s), 5);
410 s->regs[SONIC_TFS] = dp8393x_get(s, dp8393x_ttda(s), 6);
411
412 /* Handle programmable interrupt */
413 if (s->regs[SONIC_TCR] & SONIC_TCR_PINT) {
414 s->regs[SONIC_ISR] |= SONIC_ISR_PINT;
415 } else {
416 s->regs[SONIC_ISR] &= ~SONIC_ISR_PINT;
417 }
418
419 for (i = 0; i < s->regs[SONIC_TFC]; ) {
420 /* Append fragment */
421 len = s->regs[SONIC_TFS];
422 if (tx_len + len > sizeof(s->tx_buffer)) {
423 len = sizeof(s->tx_buffer) - tx_len;
424 }
425 address_space_read(&s->as, dp8393x_tsa(s), MEMTXATTRS_UNSPECIFIED,
426 &s->tx_buffer[tx_len], len);
427 tx_len += len;
428
429 i++;
430 if (i != s->regs[SONIC_TFC]) {
431 /* Read next fragment details */
432 s->regs[SONIC_TSA0] = dp8393x_get(s, dp8393x_ttda(s),
433 4 + 3 * i);
434 s->regs[SONIC_TSA1] = dp8393x_get(s, dp8393x_ttda(s),
435 5 + 3 * i);
436 s->regs[SONIC_TFS] = dp8393x_get(s, dp8393x_ttda(s),
437 6 + 3 * i);
438 }
439 }
440
441 /* Handle Ethernet checksum */
442 if (!(s->regs[SONIC_TCR] & SONIC_TCR_CRCI)) {
443 /*
444 * Don't append FCS there, to look like slirp packets
445 * which don't have one
446 */
447 } else {
448 /* Remove existing FCS */
449 tx_len -= 4;
450 if (tx_len < 0) {
451 trace_dp8393x_transmit_txlen_error(tx_len);
452 break;
453 }
454 }
455
456 if (s->regs[SONIC_RCR] & (SONIC_RCR_LB1 | SONIC_RCR_LB0)) {
457 /* Loopback */
458 s->regs[SONIC_TCR] |= SONIC_TCR_CRSL;
459 if (nc->info->can_receive(nc)) {
460 s->loopback_packet = 1;
461 qemu_receive_packet(nc, s->tx_buffer, tx_len);
462 }
463 } else {
464 /* Transmit packet */
465 qemu_send_packet(nc, s->tx_buffer, tx_len);
466 }
467 s->regs[SONIC_TCR] |= SONIC_TCR_PTX;
468
469 /* Write status */
470 dp8393x_put(s, dp8393x_ttda(s), 0, s->regs[SONIC_TCR] & 0x0fff);
471
472 if (!(s->regs[SONIC_CR] & SONIC_CR_HTX)) {
473 /* Read footer of packet */
474 s->regs[SONIC_CTDA] = dp8393x_get(s, dp8393x_ttda(s),
475 4 + 3 * s->regs[SONIC_TFC]);
476 if (s->regs[SONIC_CTDA] & SONIC_DESC_EOL) {
477 /* EOL detected */
478 break;
479 }
480 }
481 }
482
483 /* Done */
484 s->regs[SONIC_CR] &= ~SONIC_CR_TXP;
485 s->regs[SONIC_ISR] |= SONIC_ISR_TXDN;
486 dp8393x_update_irq(s);
487 }
488
489 static void dp8393x_do_halt_transmission(dp8393xState *s)
490 {
491 /* Nothing to do */
492 }
493
494 static void dp8393x_do_command(dp8393xState *s, uint16_t command)
495 {
496 if ((s->regs[SONIC_CR] & SONIC_CR_RST) && !(command & SONIC_CR_RST)) {
497 s->regs[SONIC_CR] &= ~SONIC_CR_RST;
498 return;
499 }
500
501 s->regs[SONIC_CR] |= (command & SONIC_CR_MASK);
502
503 if (command & SONIC_CR_HTX) {
504 dp8393x_do_halt_transmission(s);
505 }
506 if (command & SONIC_CR_TXP) {
507 dp8393x_do_transmit_packets(s);
508 }
509 if (command & SONIC_CR_RXDIS) {
510 dp8393x_do_receiver_disable(s);
511 }
512 if (command & SONIC_CR_RXEN) {
513 dp8393x_do_receiver_enable(s);
514 }
515 if (command & SONIC_CR_STP) {
516 dp8393x_do_stop_timer(s);
517 }
518 if (command & SONIC_CR_ST) {
519 dp8393x_do_start_timer(s);
520 }
521 if (command & SONIC_CR_RST) {
522 dp8393x_do_software_reset(s);
523 }
524 if (command & SONIC_CR_RRRA) {
525 dp8393x_do_read_rra(s);
526 s->regs[SONIC_CR] &= ~SONIC_CR_RRRA;
527 }
528 if (command & SONIC_CR_LCAM) {
529 dp8393x_do_load_cam(s);
530 }
531 }
532
533 static uint64_t dp8393x_read(void *opaque, hwaddr addr, unsigned int size)
534 {
535 dp8393xState *s = opaque;
536 int reg = addr >> s->it_shift;
537 uint16_t val = 0;
538
539 switch (reg) {
540 /* Update data before reading it */
541 case SONIC_WT0:
542 case SONIC_WT1:
543 dp8393x_update_wt_regs(s);
544 val = s->regs[reg];
545 break;
546 /* Accept read to some registers only when in reset mode */
547 case SONIC_CAP2:
548 case SONIC_CAP1:
549 case SONIC_CAP0:
550 if (s->regs[SONIC_CR] & SONIC_CR_RST) {
551 val = s->cam[s->regs[SONIC_CEP] & 0xf][SONIC_CAP0 - reg];
552 }
553 break;
554 /* All other registers have no special constraints */
555 default:
556 val = s->regs[reg];
557 }
558
559 trace_dp8393x_read(reg, reg_names[reg], val, size);
560
561 return val;
562 }
563
564 static void dp8393x_write(void *opaque, hwaddr addr, uint64_t val,
565 unsigned int size)
566 {
567 dp8393xState *s = opaque;
568 int reg = addr >> s->it_shift;
569
570 trace_dp8393x_write(reg, reg_names[reg], val, size);
571
572 switch (reg) {
573 /* Command register */
574 case SONIC_CR:
575 dp8393x_do_command(s, val);
576 break;
577 /* Prevent write to read-only registers */
578 case SONIC_CAP2:
579 case SONIC_CAP1:
580 case SONIC_CAP0:
581 case SONIC_SR:
582 case SONIC_MDT:
583 trace_dp8393x_write_invalid(reg);
584 break;
585 /* Accept write to some registers only when in reset mode */
586 case SONIC_DCR:
587 if (s->regs[SONIC_CR] & SONIC_CR_RST) {
588 s->regs[reg] = val & 0xbfff;
589 } else {
590 trace_dp8393x_write_invalid_dcr("DCR");
591 }
592 break;
593 case SONIC_DCR2:
594 if (s->regs[SONIC_CR] & SONIC_CR_RST) {
595 s->regs[reg] = val & 0xf017;
596 } else {
597 trace_dp8393x_write_invalid_dcr("DCR2");
598 }
599 break;
600 /* 12 lower bytes are Read Only */
601 case SONIC_TCR:
602 s->regs[reg] = val & 0xf000;
603 break;
604 /* 9 lower bytes are Read Only */
605 case SONIC_RCR:
606 s->regs[reg] = val & 0xffe0;
607 break;
608 /* Ignore most significant bit */
609 case SONIC_IMR:
610 s->regs[reg] = val & 0x7fff;
611 dp8393x_update_irq(s);
612 break;
613 /* Clear bits by writing 1 to them */
614 case SONIC_ISR:
615 val &= s->regs[reg];
616 s->regs[reg] &= ~val;
617 if (val & SONIC_ISR_RBE) {
618 dp8393x_do_read_rra(s);
619 }
620 dp8393x_update_irq(s);
621 break;
622 /* The guest is required to store aligned pointers here */
623 case SONIC_RSA:
624 case SONIC_REA:
625 case SONIC_RRP:
626 case SONIC_RWP:
627 if (s->regs[SONIC_DCR] & SONIC_DCR_DW) {
628 s->regs[reg] = val & 0xfffc;
629 } else {
630 s->regs[reg] = val & 0xfffe;
631 }
632 break;
633 /* Invert written value for some registers */
634 case SONIC_CRCT:
635 case SONIC_FAET:
636 case SONIC_MPT:
637 s->regs[reg] = val ^ 0xffff;
638 break;
639 /* All other registers have no special contrainst */
640 default:
641 s->regs[reg] = val;
642 }
643
644 if (reg == SONIC_WT0 || reg == SONIC_WT1) {
645 dp8393x_set_next_tick(s);
646 }
647 }
648
649 /*
650 * Since .impl.max_access_size is effectively controlled by the it_shift
651 * property, leave it unspecified for now to allow the memory API to
652 * correctly zero extend the 16-bit register values to the access size up to and
653 * including it_shift.
654 */
655 static const MemoryRegionOps dp8393x_ops = {
656 .read = dp8393x_read,
657 .write = dp8393x_write,
658 .impl.min_access_size = 2,
659 .endianness = DEVICE_NATIVE_ENDIAN,
660 };
661
662 static void dp8393x_watchdog(void *opaque)
663 {
664 dp8393xState *s = opaque;
665
666 if (s->regs[SONIC_CR] & SONIC_CR_STP) {
667 return;
668 }
669
670 s->regs[SONIC_WT1] = 0xffff;
671 s->regs[SONIC_WT0] = 0xffff;
672 dp8393x_set_next_tick(s);
673
674 /* Signal underflow */
675 s->regs[SONIC_ISR] |= SONIC_ISR_TC;
676 dp8393x_update_irq(s);
677 }
678
679 static bool dp8393x_can_receive(NetClientState *nc)
680 {
681 dp8393xState *s = qemu_get_nic_opaque(nc);
682
683 return !!(s->regs[SONIC_CR] & SONIC_CR_RXEN);
684 }
685
686 static int dp8393x_receive_filter(dp8393xState *s, const uint8_t * buf,
687 int size)
688 {
689 static const uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
690 int i;
691
692 /* Check promiscuous mode */
693 if ((s->regs[SONIC_RCR] & SONIC_RCR_PRO) && (buf[0] & 1) == 0) {
694 return 0;
695 }
696
697 /* Check multicast packets */
698 if ((s->regs[SONIC_RCR] & SONIC_RCR_AMC) && (buf[0] & 1) == 1) {
699 return SONIC_RCR_MC;
700 }
701
702 /* Check broadcast */
703 if ((s->regs[SONIC_RCR] & SONIC_RCR_BRD) &&
704 !memcmp(buf, bcast, sizeof(bcast))) {
705 return SONIC_RCR_BC;
706 }
707
708 /* Check CAM */
709 for (i = 0; i < 16; i++) {
710 if (s->regs[SONIC_CE] & (1 << i)) {
711 /* Entry enabled */
712 if (!memcmp(buf, s->cam[i], sizeof(s->cam[i]))) {
713 return 0;
714 }
715 }
716 }
717
718 return -1;
719 }
720
721 static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
722 size_t pkt_size)
723 {
724 dp8393xState *s = qemu_get_nic_opaque(nc);
725 int packet_type;
726 uint32_t available, address;
727 int rx_len, padded_len;
728 uint32_t checksum;
729 int size;
730
731 s->regs[SONIC_RCR] &= ~(SONIC_RCR_PRX | SONIC_RCR_LBK | SONIC_RCR_FAER |
732 SONIC_RCR_CRCR | SONIC_RCR_LPKT | SONIC_RCR_BC | SONIC_RCR_MC);
733
734 if (s->last_rba_is_full) {
735 return pkt_size;
736 }
737
738 rx_len = pkt_size + sizeof(checksum);
739 if (s->regs[SONIC_DCR] & SONIC_DCR_DW) {
740 padded_len = ((rx_len - 1) | 3) + 1;
741 } else {
742 padded_len = ((rx_len - 1) | 1) + 1;
743 }
744
745 if (padded_len > dp8393x_rbwc(s) * 2) {
746 trace_dp8393x_receive_oversize(pkt_size);
747 s->regs[SONIC_ISR] |= SONIC_ISR_RBAE;
748 dp8393x_update_irq(s);
749 s->regs[SONIC_RCR] |= SONIC_RCR_LPKT;
750 goto done;
751 }
752
753 packet_type = dp8393x_receive_filter(s, buf, pkt_size);
754 if (packet_type < 0) {
755 trace_dp8393x_receive_not_netcard();
756 return -1;
757 }
758
759 /* Check for EOL */
760 if (s->regs[SONIC_LLFA] & SONIC_DESC_EOL) {
761 /* Are we still in resource exhaustion? */
762 s->regs[SONIC_LLFA] = dp8393x_get(s, dp8393x_crda(s), 5);
763 if (s->regs[SONIC_LLFA] & SONIC_DESC_EOL) {
764 /* Still EOL ; stop reception */
765 return -1;
766 }
767 /* Link has been updated by host */
768
769 /* Clear in_use */
770 dp8393x_put(s, dp8393x_crda(s), 6, 0x0000);
771
772 /* Move to next descriptor */
773 s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA];
774 s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX;
775 }
776
777 /* Save current position */
778 s->regs[SONIC_TRBA1] = s->regs[SONIC_CRBA1];
779 s->regs[SONIC_TRBA0] = s->regs[SONIC_CRBA0];
780
781 /* Calculate the ethernet checksum */
782 checksum = cpu_to_le32(crc32(0, buf, pkt_size));
783
784 /* Put packet into RBA */
785 trace_dp8393x_receive_packet(dp8393x_crba(s));
786 address = dp8393x_crba(s);
787 address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED,
788 buf, pkt_size);
789 address += pkt_size;
790
791 /* Put frame checksum into RBA */
792 address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED,
793 &checksum, sizeof(checksum));
794 address += sizeof(checksum);
795
796 /* Pad short packets to keep pointers aligned */
797 if (rx_len < padded_len) {
798 size = padded_len - rx_len;
799 address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED,
800 "\xFF\xFF\xFF", size);
801 address += size;
802 }
803
804 s->regs[SONIC_CRBA1] = address >> 16;
805 s->regs[SONIC_CRBA0] = address & 0xffff;
806 available = dp8393x_rbwc(s);
807 available -= padded_len >> 1;
808 s->regs[SONIC_RBWC1] = available >> 16;
809 s->regs[SONIC_RBWC0] = available & 0xffff;
810
811 /* Update status */
812 if (dp8393x_rbwc(s) < s->regs[SONIC_EOBC]) {
813 s->regs[SONIC_RCR] |= SONIC_RCR_LPKT;
814 }
815 s->regs[SONIC_RCR] |= packet_type;
816 s->regs[SONIC_RCR] |= SONIC_RCR_PRX;
817 if (s->loopback_packet) {
818 s->regs[SONIC_RCR] |= SONIC_RCR_LBK;
819 s->loopback_packet = 0;
820 }
821
822 /* Write status to memory */
823 trace_dp8393x_receive_write_status(dp8393x_crda(s));
824 dp8393x_put(s, dp8393x_crda(s), 0, s->regs[SONIC_RCR]); /* status */
825 dp8393x_put(s, dp8393x_crda(s), 1, rx_len); /* byte count */
826 dp8393x_put(s, dp8393x_crda(s), 2, s->regs[SONIC_TRBA0]); /* pkt_ptr0 */
827 dp8393x_put(s, dp8393x_crda(s), 3, s->regs[SONIC_TRBA1]); /* pkt_ptr1 */
828 dp8393x_put(s, dp8393x_crda(s), 4, s->regs[SONIC_RSC]); /* seq_no */
829
830 /* Check link field */
831 s->regs[SONIC_LLFA] = dp8393x_get(s, dp8393x_crda(s), 5);
832 if (s->regs[SONIC_LLFA] & SONIC_DESC_EOL) {
833 /* EOL detected */
834 s->regs[SONIC_ISR] |= SONIC_ISR_RDE;
835 } else {
836 /* Clear in_use */
837 dp8393x_put(s, dp8393x_crda(s), 6, 0x0000);
838
839 /* Move to next descriptor */
840 s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA];
841 s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX;
842 }
843
844 dp8393x_update_irq(s);
845
846 s->regs[SONIC_RSC] = (s->regs[SONIC_RSC] & 0xff00) |
847 ((s->regs[SONIC_RSC] + 1) & 0x00ff);
848
849 done:
850
851 if (s->regs[SONIC_RCR] & SONIC_RCR_LPKT) {
852 if (s->regs[SONIC_RRP] == s->regs[SONIC_RWP]) {
853 /* Stop packet reception */
854 s->last_rba_is_full = true;
855 } else {
856 /* Read next resource */
857 dp8393x_do_read_rra(s);
858 }
859 }
860
861 return pkt_size;
862 }
863
864 static void dp8393x_reset(DeviceState *dev)
865 {
866 dp8393xState *s = DP8393X(dev);
867 timer_del(s->watchdog);
868
869 memset(s->regs, 0, sizeof(s->regs));
870 s->regs[SONIC_SR] = 0x0004; /* only revision recognized by Linux/mips */
871 s->regs[SONIC_CR] = SONIC_CR_RST | SONIC_CR_STP | SONIC_CR_RXDIS;
872 s->regs[SONIC_DCR] &= ~(SONIC_DCR_EXBUS | SONIC_DCR_LBR);
873 s->regs[SONIC_RCR] &= ~(SONIC_RCR_LB0 | SONIC_RCR_LB1 | SONIC_RCR_BRD |
874 SONIC_RCR_RNT);
875 s->regs[SONIC_TCR] |= SONIC_TCR_NCRS | SONIC_TCR_PTX;
876 s->regs[SONIC_TCR] &= ~SONIC_TCR_BCM;
877 s->regs[SONIC_IMR] = 0;
878 s->regs[SONIC_ISR] = 0;
879 s->regs[SONIC_DCR2] = 0;
880 s->regs[SONIC_EOBC] = 0x02F8;
881 s->regs[SONIC_RSC] = 0;
882 s->regs[SONIC_CE] = 0;
883 s->regs[SONIC_RSC] = 0;
884
885 /* Network cable is connected */
886 s->regs[SONIC_RCR] |= SONIC_RCR_CRS;
887
888 dp8393x_update_irq(s);
889 }
890
891 static NetClientInfo net_dp83932_info = {
892 .type = NET_CLIENT_DRIVER_NIC,
893 .size = sizeof(NICState),
894 .can_receive = dp8393x_can_receive,
895 .receive = dp8393x_receive,
896 };
897
898 static void dp8393x_instance_init(Object *obj)
899 {
900 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
901 dp8393xState *s = DP8393X(obj);
902
903 sysbus_init_mmio(sbd, &s->mmio);
904 sysbus_init_irq(sbd, &s->irq);
905 }
906
907 static void dp8393x_realize(DeviceState *dev, Error **errp)
908 {
909 dp8393xState *s = DP8393X(dev);
910
911 address_space_init(&s->as, s->dma_mr, "dp8393x");
912 memory_region_init_io(&s->mmio, OBJECT(dev), &dp8393x_ops, s,
913 "dp8393x-regs", SONIC_REG_COUNT << s->it_shift);
914
915 s->nic = qemu_new_nic(&net_dp83932_info, &s->conf,
916 object_get_typename(OBJECT(dev)), dev->id,
917 &dev->mem_reentrancy_guard, s);
918 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
919
920 s->watchdog = timer_new_ns(QEMU_CLOCK_VIRTUAL, dp8393x_watchdog, s);
921 }
922
923 static const VMStateDescription vmstate_dp8393x = {
924 .name = "dp8393x",
925 .version_id = 1,
926 .minimum_version_id = 1,
927 .fields = (const VMStateField []) {
928 VMSTATE_UINT16_2DARRAY(cam, dp8393xState, 16, 3),
929 VMSTATE_UINT16_ARRAY(regs, dp8393xState, SONIC_REG_COUNT),
930 VMSTATE_END_OF_LIST()
931 }
932 };
933
934 static Property dp8393x_properties[] = {
935 DEFINE_NIC_PROPERTIES(dp8393xState, conf),
936 DEFINE_PROP_LINK("dma_mr", dp8393xState, dma_mr,
937 TYPE_MEMORY_REGION, MemoryRegion *),
938 DEFINE_PROP_UINT8("it_shift", dp8393xState, it_shift, 0),
939 DEFINE_PROP_BOOL("big_endian", dp8393xState, big_endian, false),
940 DEFINE_PROP_END_OF_LIST(),
941 };
942
943 static void dp8393x_class_init(ObjectClass *klass, void *data)
944 {
945 DeviceClass *dc = DEVICE_CLASS(klass);
946
947 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
948 dc->realize = dp8393x_realize;
949 dc->reset = dp8393x_reset;
950 dc->vmsd = &vmstate_dp8393x;
951 device_class_set_props(dc, dp8393x_properties);
952 }
953
954 static const TypeInfo dp8393x_info = {
955 .name = TYPE_DP8393X,
956 .parent = TYPE_SYS_BUS_DEVICE,
957 .instance_size = sizeof(dp8393xState),
958 .instance_init = dp8393x_instance_init,
959 .class_init = dp8393x_class_init,
960 };
961
962 static void dp8393x_register_types(void)
963 {
964 type_register_static(&dp8393x_info);
965 }
966
967 type_init(dp8393x_register_types)
AR7 emulation for QEMU