hw/arm/integratorcp.c

   1 /*
   2  * ARM Integrator CP System emulation.
   3  *
   4  * Copyright (c) 2005-2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "qapi/error.h"
  12 #include "cpu.h"
  13 #include "hw/sysbus.h"
  14 #include "migration/vmstate.h"
  15 #include "hw/boards.h"
  16 #include "hw/arm/boot.h"
  17 #include "hw/misc/arm_integrator_debug.h"
  18 #include "hw/net/smc91c111.h"
  19 #include "net/net.h"
  20 #include "exec/address-spaces.h"
  21 #include "sysemu/runstate.h"
  22 #include "sysemu/sysemu.h"
  23 #include "qemu/log.h"
  24 #include "qemu/error-report.h"
  25 #include "hw/char/pl011.h"
  26 #include "hw/hw.h"
  27 #include "hw/irq.h"
  28 #include "hw/sd/sd.h"
  29 #include "qom/object.h"
  30
  31 #define TYPE_INTEGRATOR_CM "integrator_core"
  32 typedef struct IntegratorCMState IntegratorCMState;
  33 DECLARE_INSTANCE_CHECKER(IntegratorCMState, INTEGRATOR_CM,
  34                          TYPE_INTEGRATOR_CM)
  35
  36 struct IntegratorCMState {
  37     /*< private >*/
  38     SysBusDevice parent_obj;
  39     /*< public >*/
  40
  41     MemoryRegion iomem;
  42     uint32_t memsz;
  43     MemoryRegion flash;
  44     uint32_t cm_osc;
  45     uint32_t cm_ctrl;
  46     uint32_t cm_lock;
  47     uint32_t cm_auxosc;
  48     uint32_t cm_sdram;
  49     uint32_t cm_init;
  50     uint32_t cm_flags;
  51     uint32_t cm_nvflags;
  52     uint32_t cm_refcnt_offset;
  53     uint32_t int_level;
  54     uint32_t irq_enabled;
  55     uint32_t fiq_enabled;
  56 };
  57
  58 static uint8_t integrator_spd[128] = {
  59    128, 8, 4, 11, 9, 1, 64, 0,  2, 0xa0, 0xa0, 0, 0, 8, 0, 1,
  60    0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40
  61 };
  62
  63 static const VMStateDescription vmstate_integratorcm = {
  64     .name = "integratorcm",
  65     .version_id = 1,
  66     .minimum_version_id = 1,
  67     .fields      = (VMStateField[]) {
  68         VMSTATE_UINT32(cm_osc, IntegratorCMState),
  69         VMSTATE_UINT32(cm_ctrl, IntegratorCMState),
  70         VMSTATE_UINT32(cm_lock, IntegratorCMState),
  71         VMSTATE_UINT32(cm_auxosc, IntegratorCMState),
  72         VMSTATE_UINT32(cm_sdram, IntegratorCMState),
  73         VMSTATE_UINT32(cm_init, IntegratorCMState),
  74         VMSTATE_UINT32(cm_flags, IntegratorCMState),
  75         VMSTATE_UINT32(cm_nvflags, IntegratorCMState),
  76         VMSTATE_UINT32(int_level, IntegratorCMState),
  77         VMSTATE_UINT32(irq_enabled, IntegratorCMState),
  78         VMSTATE_UINT32(fiq_enabled, IntegratorCMState),
  79         VMSTATE_END_OF_LIST()
  80     }
  81 };
  82
  83 static uint64_t integratorcm_read(void *opaque, hwaddr offset,
  84                                   unsigned size)
  85 {
  86     IntegratorCMState *s = opaque;
  87     if (offset >= 0x100 && offset < 0x200) {
  88         /* CM_SPD */
  89         if (offset >= 0x180)
  90             return 0;
  91         return integrator_spd[offset >> 2];
  92     }
  93     switch (offset >> 2) {
  94     case 0: /* CM_ID */
  95         return 0x411a3001;
  96     case 1: /* CM_PROC */
  97         return 0;
  98     case 2: /* CM_OSC */
  99         return s->cm_osc;
 100     case 3: /* CM_CTRL */
 101         return s->cm_ctrl;
 102     case 4: /* CM_STAT */
 103         return 0x00100000;
 104     case 5: /* CM_LOCK */
 105         if (s->cm_lock == 0xa05f) {
 106             return 0x1a05f;
 107         } else {
 108             return s->cm_lock;
 109         }
 110     case 6: /* CM_LMBUSCNT */
 111         /* ??? High frequency timer.  */
 112         hw_error("integratorcm_read: CM_LMBUSCNT");
 113     case 7: /* CM_AUXOSC */
 114         return s->cm_auxosc;
 115     case 8: /* CM_SDRAM */
 116         return s->cm_sdram;
 117     case 9: /* CM_INIT */
 118         return s->cm_init;
 119     case 10: /* CM_REFCNT */
 120         /* This register, CM_REFCNT, provides a 32-bit count value.
 121          * The count increments at the fixed reference clock frequency of 24MHz
 122          * and can be used as a real-time counter.
 123          */
 124         return (uint32_t)muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24,
 125                                   1000) - s->cm_refcnt_offset;
 126     case 12: /* CM_FLAGS */
 127         return s->cm_flags;
 128     case 14: /* CM_NVFLAGS */
 129         return s->cm_nvflags;
 130     case 16: /* CM_IRQ_STAT */
 131         return s->int_level & s->irq_enabled;
 132     case 17: /* CM_IRQ_RSTAT */
 133         return s->int_level;
 134     case 18: /* CM_IRQ_ENSET */
 135         return s->irq_enabled;
 136     case 20: /* CM_SOFT_INTSET */
 137         return s->int_level & 1;
 138     case 24: /* CM_FIQ_STAT */
 139         return s->int_level & s->fiq_enabled;
 140     case 25: /* CM_FIQ_RSTAT */
 141         return s->int_level;
 142     case 26: /* CM_FIQ_ENSET */
 143         return s->fiq_enabled;
 144     case 32: /* CM_VOLTAGE_CTL0 */
 145     case 33: /* CM_VOLTAGE_CTL1 */
 146     case 34: /* CM_VOLTAGE_CTL2 */
 147     case 35: /* CM_VOLTAGE_CTL3 */
 148         /* ??? Voltage control unimplemented.  */
 149         return 0;
 150     default:
 151         qemu_log_mask(LOG_UNIMP,
 152                       "%s: Unimplemented offset 0x%" HWADDR_PRIX "\n",
 153                       __func__, offset);
 154         return 0;
 155     }
 156 }
 157
 158 static void integratorcm_do_remap(IntegratorCMState *s)
 159 {
 160     /* Sync memory region state with CM_CTRL REMAP bit:
 161      * bit 0 => flash at address 0; bit 1 => RAM
 162      */
 163     memory_region_set_enabled(&s->flash, !(s->cm_ctrl & 4));
 164 }
 165
 166 static void integratorcm_set_ctrl(IntegratorCMState *s, uint32_t value)
 167 {
 168     if (value & 8) {
 169         qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 170     }
 171     if ((s->cm_ctrl ^ value) & 1) {
 172         /* (value & 1) != 0 means the green "MISC LED" is lit.
 173          * We don't have any nice place to display LEDs. printf is a bad
 174          * idea because Linux uses the LED as a heartbeat and the output
 175          * will swamp anything else on the terminal.
 176          */
 177     }
 178     /* Note that the RESET bit [3] always reads as zero */
 179     s->cm_ctrl = (s->cm_ctrl & ~5) | (value & 5);
 180     integratorcm_do_remap(s);
 181 }
 182
 183 static void integratorcm_update(IntegratorCMState *s)
 184 {
 185     /* ??? The CPU irq/fiq is raised when either the core module or base PIC
 186        are active.  */
 187     if (s->int_level & (s->irq_enabled | s->fiq_enabled))
 188         hw_error("Core module interrupt\n");
 189 }
 190
 191 static void integratorcm_write(void *opaque, hwaddr offset,
 192                                uint64_t value, unsigned size)
 193 {
 194     IntegratorCMState *s = opaque;
 195     switch (offset >> 2) {
 196     case 2: /* CM_OSC */
 197         if (s->cm_lock == 0xa05f)
 198             s->cm_osc = value;
 199         break;
 200     case 3: /* CM_CTRL */
 201         integratorcm_set_ctrl(s, value);
 202         break;
 203     case 5: /* CM_LOCK */
 204         s->cm_lock = value & 0xffff;
 205         break;
 206     case 7: /* CM_AUXOSC */
 207         if (s->cm_lock == 0xa05f)
 208             s->cm_auxosc = value;
 209         break;
 210     case 8: /* CM_SDRAM */
 211         s->cm_sdram = value;
 212         break;
 213     case 9: /* CM_INIT */
 214         /* ??? This can change the memory bus frequency.  */
 215         s->cm_init = value;
 216         break;
 217     case 12: /* CM_FLAGSS */
 218         s->cm_flags |= value;
 219         break;
 220     case 13: /* CM_FLAGSC */
 221         s->cm_flags &= ~value;
 222         break;
 223     case 14: /* CM_NVFLAGSS */
 224         s->cm_nvflags |= value;
 225         break;
 226     case 15: /* CM_NVFLAGSS */
 227         s->cm_nvflags &= ~value;
 228         break;
 229     case 18: /* CM_IRQ_ENSET */
 230         s->irq_enabled |= value;
 231         integratorcm_update(s);
 232         break;
 233     case 19: /* CM_IRQ_ENCLR */
 234         s->irq_enabled &= ~value;
 235         integratorcm_update(s);
 236         break;
 237     case 20: /* CM_SOFT_INTSET */
 238         s->int_level |= (value & 1);
 239         integratorcm_update(s);
 240         break;
 241     case 21: /* CM_SOFT_INTCLR */
 242         s->int_level &= ~(value & 1);
 243         integratorcm_update(s);
 244         break;
 245     case 26: /* CM_FIQ_ENSET */
 246         s->fiq_enabled |= value;
 247         integratorcm_update(s);
 248         break;
 249     case 27: /* CM_FIQ_ENCLR */
 250         s->fiq_enabled &= ~value;
 251         integratorcm_update(s);
 252         break;
 253     case 32: /* CM_VOLTAGE_CTL0 */
 254     case 33: /* CM_VOLTAGE_CTL1 */
 255     case 34: /* CM_VOLTAGE_CTL2 */
 256     case 35: /* CM_VOLTAGE_CTL3 */
 257         /* ??? Voltage control unimplemented.  */
 258         break;
 259     default:
 260         qemu_log_mask(LOG_UNIMP,
 261                       "%s: Unimplemented offset 0x%" HWADDR_PRIX "\n",
 262                       __func__, offset);
 263         break;
 264     }
 265 }
 266
 267 /* Integrator/CM control registers.  */
 268
 269 static const MemoryRegionOps integratorcm_ops = {
 270     .read = integratorcm_read,
 271     .write = integratorcm_write,
 272     .endianness = DEVICE_NATIVE_ENDIAN,
 273 };
 274
 275 static void integratorcm_init(Object *obj)
 276 {
 277     IntegratorCMState *s = INTEGRATOR_CM(obj);
 278
 279     s->cm_osc = 0x01000048;
 280     /* ??? What should the high bits of this value be?  */
 281     s->cm_auxosc = 0x0007feff;
 282     s->cm_sdram = 0x00011122;
 283     memcpy(integrator_spd + 73, "QEMU-MEMORY", 11);
 284     s->cm_init = 0x00000112;
 285     s->cm_refcnt_offset = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24,
 286                                    1000);
 287
 288     /* ??? Save/restore.  */
 289 }
 290
 291 static void integratorcm_realize(DeviceState *d, Error **errp)
 292 {
 293     IntegratorCMState *s = INTEGRATOR_CM(d);
 294     SysBusDevice *dev = SYS_BUS_DEVICE(d);
 295     Error *local_err = NULL;
 296
 297     memory_region_init_ram(&s->flash, OBJECT(d), "integrator.flash", 0x100000,
 298                            &local_err);
 299     if (local_err) {
 300         error_propagate(errp, local_err);
 301         return;
 302     }
 303
 304     memory_region_init_io(&s->iomem, OBJECT(d), &integratorcm_ops, s,
 305                           "integratorcm", 0x00800000);
 306     sysbus_init_mmio(dev, &s->iomem);
 307
 308     integratorcm_do_remap(s);
 309
 310     if (s->memsz >= 256) {
 311         integrator_spd[31] = 64;
 312         s->cm_sdram |= 0x10;
 313     } else if (s->memsz >= 128) {
 314         integrator_spd[31] = 32;
 315         s->cm_sdram |= 0x0c;
 316     } else if (s->memsz >= 64) {
 317         integrator_spd[31] = 16;
 318         s->cm_sdram |= 0x08;
 319     } else if (s->memsz >= 32) {
 320         integrator_spd[31] = 4;
 321         s->cm_sdram |= 0x04;
 322     } else {
 323         integrator_spd[31] = 2;
 324     }
 325 }
 326
 327 /* Integrator/CP hardware emulation.  */
 328 /* Primary interrupt controller.  */
 329
 330 #define TYPE_INTEGRATOR_PIC "integrator_pic"
 331 typedef struct icp_pic_state icp_pic_state;
 332 DECLARE_INSTANCE_CHECKER(icp_pic_state, INTEGRATOR_PIC,
 333                          TYPE_INTEGRATOR_PIC)
 334
 335 struct icp_pic_state {
 336     /*< private >*/
 337     SysBusDevice parent_obj;
 338     /*< public >*/
 339
 340     MemoryRegion iomem;
 341     uint32_t level;
 342     uint32_t irq_enabled;
 343     uint32_t fiq_enabled;
 344     qemu_irq parent_irq;
 345     qemu_irq parent_fiq;
 346 };
 347
 348 static const VMStateDescription vmstate_icp_pic = {
 349     .name = "icp_pic",
 350     .version_id = 1,
 351     .minimum_version_id = 1,
 352     .fields      = (VMStateField[]) {
 353         VMSTATE_UINT32(level, icp_pic_state),
 354         VMSTATE_UINT32(irq_enabled, icp_pic_state),
 355         VMSTATE_UINT32(fiq_enabled, icp_pic_state),
 356         VMSTATE_END_OF_LIST()
 357     }
 358 };
 359
 360 static void icp_pic_update(icp_pic_state *s)
 361 {
 362     uint32_t flags;
 363
 364     flags = (s->level & s->irq_enabled);
 365     qemu_set_irq(s->parent_irq, flags != 0);
 366     flags = (s->level & s->fiq_enabled);
 367     qemu_set_irq(s->parent_fiq, flags != 0);
 368 }
 369
 370 static void icp_pic_set_irq(void *opaque, int irq, int level)
 371 {
 372     icp_pic_state *s = (icp_pic_state *)opaque;
 373     if (level)
 374         s->level |= 1 << irq;
 375     else
 376         s->level &= ~(1 << irq);
 377     icp_pic_update(s);
 378 }
 379
 380 static uint64_t icp_pic_read(void *opaque, hwaddr offset,
 381                              unsigned size)
 382 {
 383     icp_pic_state *s = (icp_pic_state *)opaque;
 384
 385     switch (offset >> 2) {
 386     case 0: /* IRQ_STATUS */
 387         return s->level & s->irq_enabled;
 388     case 1: /* IRQ_RAWSTAT */
 389         return s->level;
 390     case 2: /* IRQ_ENABLESET */
 391         return s->irq_enabled;
 392     case 4: /* INT_SOFTSET */
 393         return s->level & 1;
 394     case 8: /* FRQ_STATUS */
 395         return s->level & s->fiq_enabled;
 396     case 9: /* FRQ_RAWSTAT */
 397         return s->level;
 398     case 10: /* FRQ_ENABLESET */
 399         return s->fiq_enabled;
 400     case 3: /* IRQ_ENABLECLR */
 401     case 5: /* INT_SOFTCLR */
 402     case 11: /* FRQ_ENABLECLR */
 403     default:
 404         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
 405                       __func__, offset);
 406         return 0;
 407     }
 408 }
 409
 410 static void icp_pic_write(void *opaque, hwaddr offset,
 411                           uint64_t value, unsigned size)
 412 {
 413     icp_pic_state *s = (icp_pic_state *)opaque;
 414
 415     switch (offset >> 2) {
 416     case 2: /* IRQ_ENABLESET */
 417         s->irq_enabled |= value;
 418         break;
 419     case 3: /* IRQ_ENABLECLR */
 420         s->irq_enabled &= ~value;
 421         break;
 422     case 4: /* INT_SOFTSET */
 423         if (value & 1)
 424             icp_pic_set_irq(s, 0, 1);
 425         break;
 426     case 5: /* INT_SOFTCLR */
 427         if (value & 1)
 428             icp_pic_set_irq(s, 0, 0);
 429         break;
 430     case 10: /* FRQ_ENABLESET */
 431         s->fiq_enabled |= value;
 432         break;
 433     case 11: /* FRQ_ENABLECLR */
 434         s->fiq_enabled &= ~value;
 435         break;
 436     case 0: /* IRQ_STATUS */
 437     case 1: /* IRQ_RAWSTAT */
 438     case 8: /* FRQ_STATUS */
 439     case 9: /* FRQ_RAWSTAT */
 440     default:
 441         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
 442                       __func__, offset);
 443         return;
 444     }
 445     icp_pic_update(s);
 446 }
 447
 448 static const MemoryRegionOps icp_pic_ops = {
 449     .read = icp_pic_read,
 450     .write = icp_pic_write,
 451     .endianness = DEVICE_NATIVE_ENDIAN,
 452 };
 453
 454 static void icp_pic_init(Object *obj)
 455 {
 456     DeviceState *dev = DEVICE(obj);
 457     icp_pic_state *s = INTEGRATOR_PIC(obj);
 458     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 459
 460     qdev_init_gpio_in(dev, icp_pic_set_irq, 32);
 461     sysbus_init_irq(sbd, &s->parent_irq);
 462     sysbus_init_irq(sbd, &s->parent_fiq);
 463     memory_region_init_io(&s->iomem, obj, &icp_pic_ops, s,
 464                           "icp-pic", 0x00800000);
 465     sysbus_init_mmio(sbd, &s->iomem);
 466 }
 467
 468 /* CP control registers.  */
 469
 470 #define TYPE_ICP_CONTROL_REGS "icp-ctrl-regs"
 471 typedef struct ICPCtrlRegsState ICPCtrlRegsState;
 472 DECLARE_INSTANCE_CHECKER(ICPCtrlRegsState, ICP_CONTROL_REGS,
 473                          TYPE_ICP_CONTROL_REGS)
 474
 475 struct ICPCtrlRegsState {
 476     /*< private >*/
 477     SysBusDevice parent_obj;
 478     /*< public >*/
 479
 480     MemoryRegion iomem;
 481
 482     qemu_irq mmc_irq;
 483     uint32_t intreg_state;
 484 };
 485
 486 #define ICP_GPIO_MMC_WPROT      "mmc-wprot"
 487 #define ICP_GPIO_MMC_CARDIN     "mmc-cardin"
 488
 489 #define ICP_INTREG_WPROT        (1 << 0)
 490 #define ICP_INTREG_CARDIN       (1 << 3)
 491
 492 static const VMStateDescription vmstate_icp_control = {
 493     .name = "icp_control",
 494     .version_id = 1,
 495     .minimum_version_id = 1,
 496     .fields      = (VMStateField[]) {
 497         VMSTATE_UINT32(intreg_state, ICPCtrlRegsState),
 498         VMSTATE_END_OF_LIST()
 499     }
 500 };
 501
 502 static uint64_t icp_control_read(void *opaque, hwaddr offset,
 503                                  unsigned size)
 504 {
 505     ICPCtrlRegsState *s = opaque;
 506
 507     switch (offset >> 2) {
 508     case 0: /* CP_IDFIELD */
 509         return 0x41034003;
 510     case 1: /* CP_FLASHPROG */
 511         return 0;
 512     case 2: /* CP_INTREG */
 513         return s->intreg_state;
 514     case 3: /* CP_DECODE */
 515         return 0x11;
 516     default:
 517         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
 518                       __func__, offset);
 519         return 0;
 520     }
 521 }
 522
 523 static void icp_control_write(void *opaque, hwaddr offset,
 524                           uint64_t value, unsigned size)
 525 {
 526     ICPCtrlRegsState *s = opaque;
 527
 528     switch (offset >> 2) {
 529     case 2: /* CP_INTREG */
 530         s->intreg_state &= ~(value & ICP_INTREG_CARDIN);
 531         qemu_set_irq(s->mmc_irq, !!(s->intreg_state & ICP_INTREG_CARDIN));
 532         break;
 533     case 1: /* CP_FLASHPROG */
 534     case 3: /* CP_DECODE */
 535         /* Nothing interesting implemented yet.  */
 536         break;
 537     default:
 538         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
 539                       __func__, offset);
 540     }
 541 }
 542
 543 static const MemoryRegionOps icp_control_ops = {
 544     .read = icp_control_read,
 545     .write = icp_control_write,
 546     .endianness = DEVICE_NATIVE_ENDIAN,
 547 };
 548
 549 static void icp_control_mmc_wprot(void *opaque, int line, int level)
 550 {
 551     ICPCtrlRegsState *s = opaque;
 552
 553     s->intreg_state &= ~ICP_INTREG_WPROT;
 554     if (level) {
 555         s->intreg_state |= ICP_INTREG_WPROT;
 556     }
 557 }
 558
 559 static void icp_control_mmc_cardin(void *opaque, int line, int level)
 560 {
 561     ICPCtrlRegsState *s = opaque;
 562
 563     /* line is released by writing to CP_INTREG */
 564     if (level) {
 565         s->intreg_state |= ICP_INTREG_CARDIN;
 566         qemu_set_irq(s->mmc_irq, 1);
 567     }
 568 }
 569
 570 static void icp_control_init(Object *obj)
 571 {
 572     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 573     ICPCtrlRegsState *s = ICP_CONTROL_REGS(obj);
 574     DeviceState *dev = DEVICE(obj);
 575
 576     memory_region_init_io(&s->iomem, OBJECT(s), &icp_control_ops, s,
 577                           "icp_ctrl_regs", 0x00800000);
 578     sysbus_init_mmio(sbd, &s->iomem);
 579
 580     qdev_init_gpio_in_named(dev, icp_control_mmc_wprot, ICP_GPIO_MMC_WPROT, 1);
 581     qdev_init_gpio_in_named(dev, icp_control_mmc_cardin,
 582                             ICP_GPIO_MMC_CARDIN, 1);
 583     sysbus_init_irq(sbd, &s->mmc_irq);
 584 }
 585
 586
 587 /* Board init.  */
 588
 589 static struct arm_boot_info integrator_binfo = {
 590     .loader_start = 0x0,
 591     .board_id = 0x113,
 592 };
 593
 594 static void integratorcp_init(MachineState *machine)
 595 {
 596     ram_addr_t ram_size = machine->ram_size;
 597     Object *cpuobj;
 598     ARMCPU *cpu;
 599     MemoryRegion *address_space_mem = get_system_memory();
 600     MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
 601     qemu_irq pic[32];
 602     DeviceState *dev, *sic, *icp;
 603     DriveInfo *dinfo;
 604     int i;
 605
 606     cpuobj = object_new(machine->cpu_type);
 607
 608     /* By default ARM1176 CPUs have EL3 enabled.  This board does not
 609      * currently support EL3 so the CPU EL3 property is disabled before
 610      * realization.
 611      */
 612     if (object_property_find(cpuobj, "has_el3", NULL)) {
 613         object_property_set_bool(cpuobj, "has_el3", false, &error_fatal);
 614     }
 615
 616     qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
 617
 618     cpu = ARM_CPU(cpuobj);
 619
 620     /* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash.  */
 621     /* ??? RAM should repeat to fill physical memory space.  */
 622     /* SDRAM at address zero*/
 623     memory_region_add_subregion(address_space_mem, 0, machine->ram);
 624     /* And again at address 0x80000000 */
 625     memory_region_init_alias(ram_alias, NULL, "ram.alias", machine->ram,
 626                              0, ram_size);
 627     memory_region_add_subregion(address_space_mem, 0x80000000, ram_alias);
 628
 629     dev = qdev_new(TYPE_INTEGRATOR_CM);
 630     qdev_prop_set_uint32(dev, "memsz", ram_size >> 20);
 631     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 632     sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000);
 633
 634     dev = sysbus_create_varargs(TYPE_INTEGRATOR_PIC, 0x14000000,
 635                                 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ),
 636                                 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ),
 637                                 NULL);
 638     for (i = 0; i < 32; i++) {
 639         pic[i] = qdev_get_gpio_in(dev, i);
 640     }
 641     sic = sysbus_create_simple(TYPE_INTEGRATOR_PIC, 0xca000000, pic[26]);
 642     sysbus_create_varargs("integrator_pit", 0x13000000,
 643                           pic[5], pic[6], pic[7], NULL);
 644     sysbus_create_simple("pl031", 0x15000000, pic[8]);
 645     pl011_create(0x16000000, pic[1], serial_hd(0));
 646     pl011_create(0x17000000, pic[2], serial_hd(1));
 647     icp = sysbus_create_simple(TYPE_ICP_CONTROL_REGS, 0xcb000000,
 648                                qdev_get_gpio_in(sic, 3));
 649     sysbus_create_simple("pl050_keyboard", 0x18000000, pic[3]);
 650     sysbus_create_simple("pl050_mouse", 0x19000000, pic[4]);
 651     sysbus_create_simple(TYPE_INTEGRATOR_DEBUG, 0x1a000000, 0);
 652
 653     dev = sysbus_create_varargs("pl181", 0x1c000000, pic[23], pic[24], NULL);
 654     qdev_connect_gpio_out_named(dev, "card-read-only", 0,
 655                           qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_WPROT, 0));
 656     qdev_connect_gpio_out_named(dev, "card-inserted", 0,
 657                           qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_CARDIN, 0));
 658     dinfo = drive_get_next(IF_SD);
 659     if (dinfo) {
 660         DeviceState *card;
 661
 662         card = qdev_new(TYPE_SD_CARD);
 663         qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
 664                                 &error_fatal);
 665         qdev_realize_and_unref(card, qdev_get_child_bus(dev, "sd-bus"),
 666                                &error_fatal);
 667     }
 668
 669     sysbus_create_varargs("pl041", 0x1d000000, pic[25], NULL);
 670
 671     if (nd_table[0].used)
 672         smc91c111_init(&nd_table[0], 0xc8000000, pic[27]);
 673
 674     sysbus_create_simple("pl110", 0xc0000000, pic[22]);
 675
 676     integrator_binfo.ram_size = ram_size;
 677     arm_load_kernel(cpu, machine, &integrator_binfo);
 678 }
 679
 680 static void integratorcp_machine_init(MachineClass *mc)
 681 {
 682     mc->desc = "ARM Integrator/CP (ARM926EJ-S)";
 683     mc->init = integratorcp_init;
 684     mc->ignore_memory_transaction_failures = true;
 685     mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926");
 686     mc->default_ram_id = "integrator.ram";
 687 }
 688
 689 DEFINE_MACHINE("integratorcp", integratorcp_machine_init)
 690
 691 static Property core_properties[] = {
 692     DEFINE_PROP_UINT32("memsz", IntegratorCMState, memsz, 0),
 693     DEFINE_PROP_END_OF_LIST(),
 694 };
 695
 696 static void core_class_init(ObjectClass *klass, void *data)
 697 {
 698     DeviceClass *dc = DEVICE_CLASS(klass);
 699
 700     device_class_set_props(dc, core_properties);
 701     dc->realize = integratorcm_realize;
 702     dc->vmsd = &vmstate_integratorcm;
 703 }
 704
 705 static void icp_pic_class_init(ObjectClass *klass, void *data)
 706 {
 707     DeviceClass *dc = DEVICE_CLASS(klass);
 708
 709     dc->vmsd = &vmstate_icp_pic;
 710 }
 711
 712 static void icp_control_class_init(ObjectClass *klass, void *data)
 713 {
 714     DeviceClass *dc = DEVICE_CLASS(klass);
 715
 716     dc->vmsd = &vmstate_icp_control;
 717 }
 718
 719 static const TypeInfo core_info = {
 720     .name          = TYPE_INTEGRATOR_CM,
 721     .parent        = TYPE_SYS_BUS_DEVICE,
 722     .instance_size = sizeof(IntegratorCMState),
 723     .instance_init = integratorcm_init,
 724     .class_init    = core_class_init,
 725 };
 726
 727 static const TypeInfo icp_pic_info = {
 728     .name          = TYPE_INTEGRATOR_PIC,
 729     .parent        = TYPE_SYS_BUS_DEVICE,
 730     .instance_size = sizeof(icp_pic_state),
 731     .instance_init = icp_pic_init,
 732     .class_init    = icp_pic_class_init,
 733 };
 734
 735 static const TypeInfo icp_ctrl_regs_info = {
 736     .name          = TYPE_ICP_CONTROL_REGS,
 737     .parent        = TYPE_SYS_BUS_DEVICE,
 738     .instance_size = sizeof(ICPCtrlRegsState),
 739     .instance_init = icp_control_init,
 740     .class_init    = icp_control_class_init,
 741 };
 742
 743 static void integratorcp_register_types(void)
 744 {
 745     type_register_static(&icp_pic_info);
 746     type_register_static(&core_info);
 747     type_register_static(&icp_ctrl_regs_info);
 748 }
 749
 750 type_init(integratorcp_register_types)