include/hw/pci/pci.h

   1 #ifndef QEMU_PCI_H
   2 #define QEMU_PCI_H
   3
   4 #include "hw/qdev.h"
   5 #include "exec/memory.h"
   6 #include "sysemu/dma.h"
   7
   8 /* PCI includes legacy ISA access.  */
   9 #include "hw/isa/isa.h"
  10
  11 #include "hw/pci/pcie.h"
  12
  13 /* PCI bus */
  14
  15 #define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
  16 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  17 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
  18 #define PCI_SLOT_MAX            32
  19 #define PCI_FUNC_MAX            8
  20
  21 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
  22 #include "hw/pci/pci_ids.h"
  23
  24 /* QEMU-specific Vendor and Device ID definitions */
  25
  26 /* IBM (0x1014) */
  27 #define PCI_DEVICE_ID_IBM_440GX          0x027f
  28 #define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff
  29
  30 /* Hitachi (0x1054) */
  31 #define PCI_VENDOR_ID_HITACHI            0x1054
  32 #define PCI_DEVICE_ID_HITACHI_SH7751R    0x350e
  33
  34 /* Apple (0x106b) */
  35 #define PCI_DEVICE_ID_APPLE_343S1201     0x0010
  36 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
  37 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
  38 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
  39 #define PCI_DEVICE_ID_APPLE_IPID_USB     0x003f
  40
  41 /* Realtek (0x10ec) */
  42 #define PCI_DEVICE_ID_REALTEK_8029       0x8029
  43
  44 /* Xilinx (0x10ee) */
  45 #define PCI_DEVICE_ID_XILINX_XC2VP30     0x0300
  46
  47 /* Marvell (0x11ab) */
  48 #define PCI_DEVICE_ID_MARVELL_GT6412X    0x4620
  49
  50 /* QEMU/Bochs VGA (0x1234) */
  51 #define PCI_VENDOR_ID_QEMU               0x1234
  52 #define PCI_DEVICE_ID_QEMU_VGA           0x1111
  53
  54 /* VMWare (0x15ad) */
  55 #define PCI_VENDOR_ID_VMWARE             0x15ad
  56 #define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
  57 #define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
  58 #define PCI_DEVICE_ID_VMWARE_NET         0x0720
  59 #define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
  60 #define PCI_DEVICE_ID_VMWARE_PVSCSI      0x07C0
  61 #define PCI_DEVICE_ID_VMWARE_IDE         0x1729
  62 #define PCI_DEVICE_ID_VMWARE_VMXNET3     0x07B0
  63
  64 /* Intel (0x8086) */
  65 #define PCI_DEVICE_ID_INTEL_82551IT      0x1209
  66 #define PCI_DEVICE_ID_INTEL_82557        0x1229
  67 #define PCI_DEVICE_ID_INTEL_82801IR      0x2922
  68
  69 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
  70 #define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
  71 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
  72 #define PCI_SUBDEVICE_ID_QEMU            0x1100
  73
  74 #define PCI_DEVICE_ID_VIRTIO_NET         0x1000
  75 #define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
  76 #define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
  77 #define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
  78 #define PCI_DEVICE_ID_VIRTIO_SCSI        0x1004
  79 #define PCI_DEVICE_ID_VIRTIO_RNG         0x1005
  80 #define PCI_DEVICE_ID_VIRTIO_9P          0x1009
  81
  82 #define PCI_VENDOR_ID_REDHAT             0x1b36
  83 #define PCI_DEVICE_ID_REDHAT_BRIDGE      0x0001
  84 #define PCI_DEVICE_ID_REDHAT_SERIAL      0x0002
  85 #define PCI_DEVICE_ID_REDHAT_SERIAL2     0x0003
  86 #define PCI_DEVICE_ID_REDHAT_SERIAL4     0x0004
  87 #define PCI_DEVICE_ID_REDHAT_TEST        0x0005
  88 #define PCI_DEVICE_ID_REDHAT_ROCKER      0x0006
  89 #define PCI_DEVICE_ID_REDHAT_SDHCI       0x0007
  90 #define PCI_DEVICE_ID_REDHAT_PCIE_HOST   0x0008
  91 #define PCI_DEVICE_ID_REDHAT_PXB         0x0009
  92 #define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a
  93 #define PCI_DEVICE_ID_REDHAT_PXB_PCIE    0x000b
  94 #define PCI_DEVICE_ID_REDHAT_QXL         0x0100
  95
  96 #define FMT_PCIBUS                      PRIx64
  97
  98 typedef uint64_t pcibus_t;
  99
 100 struct PCIHostDeviceAddress {
 101     unsigned int domain;
 102     unsigned int bus;
 103     unsigned int slot;
 104     unsigned int function;
 105 };
 106
 107 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
 108                                 uint32_t address, uint32_t data, int len);
 109 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
 110                                    uint32_t address, int len);
 111 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
 112                                 pcibus_t addr, pcibus_t size, int type);
 113 typedef void PCIUnregisterFunc(PCIDevice *pci_dev);
 114
 115 typedef struct PCIIORegion {
 116     pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
 117 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
 118     pcibus_t size;
 119     uint8_t type;
 120     MemoryRegion *memory;
 121     MemoryRegion *address_space;
 122 } PCIIORegion;
 123
 124 #define PCI_ROM_SLOT 6
 125 #define PCI_NUM_REGIONS 7
 126
 127 enum {
 128     QEMU_PCI_VGA_MEM,
 129     QEMU_PCI_VGA_IO_LO,
 130     QEMU_PCI_VGA_IO_HI,
 131     QEMU_PCI_VGA_NUM_REGIONS,
 132 };
 133
 134 #define QEMU_PCI_VGA_MEM_BASE 0xa0000
 135 #define QEMU_PCI_VGA_MEM_SIZE 0x20000
 136 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0
 137 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc
 138 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0
 139 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20
 140
 141 #include "hw/pci/pci_regs.h"
 142
 143 /* PCI HEADER_TYPE */
 144 #define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
 145
 146 /* Size of the standard PCI config header */
 147 #define PCI_CONFIG_HEADER_SIZE 0x40
 148 /* Size of the standard PCI config space */
 149 #define PCI_CONFIG_SPACE_SIZE 0x100
 150 /* Size of the standard PCIe config space: 4KB */
 151 #define PCIE_CONFIG_SPACE_SIZE  0x1000
 152
 153 #define PCI_NUM_PINS 4 /* A-D */
 154
 155 /* Bits in cap_present field. */
 156 enum {
 157     QEMU_PCI_CAP_MSI = 0x1,
 158     QEMU_PCI_CAP_MSIX = 0x2,
 159     QEMU_PCI_CAP_EXPRESS = 0x4,
 160
 161     /* multifunction capable device */
 162 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR        3
 163     QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
 164
 165     /* command register SERR bit enabled */
 166 #define QEMU_PCI_CAP_SERR_BITNR 4
 167     QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
 168     /* Standard hot plug controller. */
 169 #define QEMU_PCI_SHPC_BITNR 5
 170     QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),
 171 #define QEMU_PCI_SLOTID_BITNR 6
 172     QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR),
 173     /* PCI Express capability - Power Controller Present */
 174 #define QEMU_PCIE_SLTCAP_PCP_BITNR 7
 175     QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR),
 176 };
 177
 178 #define TYPE_PCI_DEVICE "pci-device"
 179 #define PCI_DEVICE(obj) \
 180      OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE)
 181 #define PCI_DEVICE_CLASS(klass) \
 182      OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE)
 183 #define PCI_DEVICE_GET_CLASS(obj) \
 184      OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE)
 185
 186 typedef struct PCIINTxRoute {
 187     enum {
 188         PCI_INTX_ENABLED,
 189         PCI_INTX_INVERTED,
 190         PCI_INTX_DISABLED,
 191     } mode;
 192     int irq;
 193 } PCIINTxRoute;
 194
 195 typedef struct PCIDeviceClass {
 196     DeviceClass parent_class;
 197
 198     void (*realize)(PCIDevice *dev, Error **errp);
 199     int (*init)(PCIDevice *dev);/* TODO convert to realize() and remove */
 200     PCIUnregisterFunc *exit;
 201     PCIConfigReadFunc *config_read;
 202     PCIConfigWriteFunc *config_write;
 203
 204     uint16_t vendor_id;
 205     uint16_t device_id;
 206     uint8_t revision;
 207     uint16_t class_id;
 208     uint16_t subsystem_vendor_id;       /* only for header type = 0 */
 209     uint16_t subsystem_id;              /* only for header type = 0 */
 210
 211     /*
 212      * pci-to-pci bridge or normal device.
 213      * This doesn't mean pci host switch.
 214      * When card bus bridge is supported, this would be enhanced.
 215      */
 216     int is_bridge;
 217
 218     /* pcie stuff */
 219     int is_express;   /* is this device pci express? */
 220
 221     /* rom bar */
 222     const char *romfile;
 223 } PCIDeviceClass;
 224
 225 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev);
 226 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector,
 227                                       MSIMessage msg);
 228 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector);
 229 typedef void (*MSIVectorPollNotifier)(PCIDevice *dev,
 230                                       unsigned int vector_start,
 231                                       unsigned int vector_end);
 232
 233 struct PCIDevice {
 234     DeviceState qdev;
 235
 236     /* PCI config space */
 237     uint8_t *config;
 238
 239     /* Used to enable config checks on load. Note that writable bits are
 240      * never checked even if set in cmask. */
 241     uint8_t *cmask;
 242
 243     /* Used to implement R/W bytes */
 244     uint8_t *wmask;
 245
 246     /* Used to implement RW1C(Write 1 to Clear) bytes */
 247     uint8_t *w1cmask;
 248
 249     /* Used to allocate config space for capabilities. */
 250     uint8_t *used;
 251
 252     /* the following fields are read only */
 253     PCIBus *bus;
 254     int32_t devfn;
 255     char name[64];
 256     PCIIORegion io_regions[PCI_NUM_REGIONS];
 257     AddressSpace bus_master_as;
 258     MemoryRegion bus_master_enable_region;
 259
 260     /* do not access the following fields */
 261     PCIConfigReadFunc *config_read;
 262     PCIConfigWriteFunc *config_write;
 263
 264     /* Legacy PCI VGA regions */
 265     MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS];
 266     bool has_vga;
 267
 268     /* Current IRQ levels.  Used internally by the generic PCI code.  */
 269     uint8_t irq_state;
 270
 271     /* Capability bits */
 272     uint32_t cap_present;
 273
 274     /* Offset of MSI-X capability in config space */
 275     uint8_t msix_cap;
 276
 277     /* MSI-X entries */
 278     int msix_entries_nr;
 279
 280     /* Space to store MSIX table & pending bit array */
 281     uint8_t *msix_table;
 282     uint8_t *msix_pba;
 283     /* MemoryRegion container for msix exclusive BAR setup */
 284     MemoryRegion msix_exclusive_bar;
 285     /* Memory Regions for MSIX table and pending bit entries. */
 286     MemoryRegion msix_table_mmio;
 287     MemoryRegion msix_pba_mmio;
 288     /* Reference-count for entries actually in use by driver. */
 289     unsigned *msix_entry_used;
 290     /* MSIX function mask set or MSIX disabled */
 291     bool msix_function_masked;
 292     /* Version id needed for VMState */
 293     int32_t version_id;
 294
 295     /* Offset of MSI capability in config space */
 296     uint8_t msi_cap;
 297
 298     /* PCI Express */
 299     PCIExpressDevice exp;
 300
 301     /* SHPC */
 302     SHPCDevice *shpc;
 303
 304     /* Location of option rom */
 305     char *romfile;
 306     bool has_rom;
 307     MemoryRegion rom;
 308     uint32_t rom_bar;
 309
 310     /* INTx routing notifier */
 311     PCIINTxRoutingNotifier intx_routing_notifier;
 312
 313     /* MSI-X notifiers */
 314     MSIVectorUseNotifier msix_vector_use_notifier;
 315     MSIVectorReleaseNotifier msix_vector_release_notifier;
 316     MSIVectorPollNotifier msix_vector_poll_notifier;
 317 };
 318
 319 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 320                       uint8_t attr, MemoryRegion *memory);
 321 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
 322                       MemoryRegion *io_lo, MemoryRegion *io_hi);
 323 void pci_unregister_vga(PCIDevice *pci_dev);
 324 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
 325
 326 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
 327                        uint8_t offset, uint8_t size);
 328 int pci_add_capability2(PCIDevice *pdev, uint8_t cap_id,
 329                        uint8_t offset, uint8_t size,
 330                        Error **errp);
 331
 332 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 333
 334 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
 335
 336
 337 uint32_t pci_default_read_config(PCIDevice *d,
 338                                  uint32_t address, int len);
 339 void pci_default_write_config(PCIDevice *d,
 340                               uint32_t address, uint32_t val, int len);
 341 void pci_device_save(PCIDevice *s, QEMUFile *f);
 342 int pci_device_load(PCIDevice *s, QEMUFile *f);
 343 MemoryRegion *pci_address_space(PCIDevice *dev);
 344 MemoryRegion *pci_address_space_io(PCIDevice *dev);
 345
 346 /*
 347  * Should not normally be used by devices. For use by sPAPR target
 348  * where QEMU emulates firmware.
 349  */
 350 int pci_bar(PCIDevice *d, int reg);
 351
 352 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
 353 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 354 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin);
 355
 356 #define TYPE_PCI_BUS "PCI"
 357 #define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS)
 358 #define PCI_BUS_CLASS(klass) OBJECT_CLASS_CHECK(PCIBusClass, (klass), TYPE_PCI_BUS)
 359 #define PCI_BUS_GET_CLASS(obj) OBJECT_GET_CLASS(PCIBusClass, (obj), TYPE_PCI_BUS)
 360 #define TYPE_PCIE_BUS "PCIE"
 361
 362 bool pci_bus_is_express(PCIBus *bus);
 363 bool pci_bus_is_root(PCIBus *bus);
 364 void pci_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
 365                          const char *name,
 366                          MemoryRegion *address_space_mem,
 367                          MemoryRegion *address_space_io,
 368                          uint8_t devfn_min, const char *typename);
 369 PCIBus *pci_bus_new(DeviceState *parent, const char *name,
 370                     MemoryRegion *address_space_mem,
 371                     MemoryRegion *address_space_io,
 372                     uint8_t devfn_min, const char *typename);
 373 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 374                   void *irq_opaque, int nirq);
 375 int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
 376 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */
 377 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin);
 378 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 379                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 380                          void *irq_opaque,
 381                          MemoryRegion *address_space_mem,
 382                          MemoryRegion *address_space_io,
 383                          uint8_t devfn_min, int nirq, const char *typename);
 384 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn);
 385 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin);
 386 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new);
 387 void pci_bus_fire_intx_routing_notifier(PCIBus *bus);
 388 void pci_device_set_intx_routing_notifier(PCIDevice *dev,
 389                                           PCIINTxRoutingNotifier notifier);
 390 void pci_device_reset(PCIDevice *dev);
 391
 392 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus,
 393                                const char *default_model,
 394                                const char *default_devaddr);
 395
 396 PCIDevice *pci_vga_init(PCIBus *bus);
 397
 398 int pci_bus_num(PCIBus *s);
 399 int pci_bus_numa_node(PCIBus *bus);
 400 void pci_for_each_device(PCIBus *bus, int bus_num,
 401                          void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque),
 402                          void *opaque);
 403 void pci_for_each_bus_depth_first(PCIBus *bus,
 404                                   void *(*begin)(PCIBus *bus, void *parent_state),
 405                                   void (*end)(PCIBus *bus, void *state),
 406                                   void *parent_state);
 407 PCIDevice *pci_get_function_0(PCIDevice *pci_dev);
 408
 409 /* Use this wrapper when specific scan order is not required. */
 410 static inline
 411 void pci_for_each_bus(PCIBus *bus,
 412                       void (*fn)(PCIBus *bus, void *opaque),
 413                       void *opaque)
 414 {
 415     pci_for_each_bus_depth_first(bus, NULL, fn, opaque);
 416 }
 417
 418 PCIBus *pci_find_primary_bus(void);
 419 PCIBus *pci_device_root_bus(const PCIDevice *d);
 420 const char *pci_root_bus_path(PCIDevice *dev);
 421 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
 422 int pci_qdev_find_device(const char *id, PCIDevice **pdev);
 423 void pci_bus_get_w64_range(PCIBus *bus, Range *range);
 424
 425 void pci_device_deassert_intx(PCIDevice *dev);
 426
 427 typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int);
 428
 429 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev);
 430 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque);
 431
 432 static inline void
 433 pci_set_byte(uint8_t *config, uint8_t val)
 434 {
 435     *config = val;
 436 }
 437
 438 static inline uint8_t
 439 pci_get_byte(const uint8_t *config)
 440 {
 441     return *config;
 442 }
 443
 444 static inline void
 445 pci_set_word(uint8_t *config, uint16_t val)
 446 {
 447     stw_le_p(config, val);
 448 }
 449
 450 static inline uint16_t
 451 pci_get_word(const uint8_t *config)
 452 {
 453     return lduw_le_p(config);
 454 }
 455
 456 static inline void
 457 pci_set_long(uint8_t *config, uint32_t val)
 458 {
 459     stl_le_p(config, val);
 460 }
 461
 462 static inline uint32_t
 463 pci_get_long(const uint8_t *config)
 464 {
 465     return ldl_le_p(config);
 466 }
 467
 468 static inline void
 469 pci_set_quad(uint8_t *config, uint64_t val)
 470 {
 471     cpu_to_le64w((uint64_t *)config, val);
 472 }
 473
 474 static inline uint64_t
 475 pci_get_quad(const uint8_t *config)
 476 {
 477     return le64_to_cpup((const uint64_t *)config);
 478 }
 479
 480 static inline void
 481 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
 482 {
 483     pci_set_word(&pci_config[PCI_VENDOR_ID], val);
 484 }
 485
 486 static inline void
 487 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
 488 {
 489     pci_set_word(&pci_config[PCI_DEVICE_ID], val);
 490 }
 491
 492 static inline void
 493 pci_config_set_revision(uint8_t *pci_config, uint8_t val)
 494 {
 495     pci_set_byte(&pci_config[PCI_REVISION_ID], val);
 496 }
 497
 498 static inline void
 499 pci_config_set_class(uint8_t *pci_config, uint16_t val)
 500 {
 501     pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
 502 }
 503
 504 static inline void
 505 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
 506 {
 507     pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
 508 }
 509
 510 static inline void
 511 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
 512 {
 513     pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
 514 }
 515
 516 /*
 517  * helper functions to do bit mask operation on configuration space.
 518  * Just to set bit, use test-and-set and discard returned value.
 519  * Just to clear bit, use test-and-clear and discard returned value.
 520  * NOTE: They aren't atomic.
 521  */
 522 static inline uint8_t
 523 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
 524 {
 525     uint8_t val = pci_get_byte(config);
 526     pci_set_byte(config, val & ~mask);
 527     return val & mask;
 528 }
 529
 530 static inline uint8_t
 531 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
 532 {
 533     uint8_t val = pci_get_byte(config);
 534     pci_set_byte(config, val | mask);
 535     return val & mask;
 536 }
 537
 538 static inline uint16_t
 539 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
 540 {
 541     uint16_t val = pci_get_word(config);
 542     pci_set_word(config, val & ~mask);
 543     return val & mask;
 544 }
 545
 546 static inline uint16_t
 547 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
 548 {
 549     uint16_t val = pci_get_word(config);
 550     pci_set_word(config, val | mask);
 551     return val & mask;
 552 }
 553
 554 static inline uint32_t
 555 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
 556 {
 557     uint32_t val = pci_get_long(config);
 558     pci_set_long(config, val & ~mask);
 559     return val & mask;
 560 }
 561
 562 static inline uint32_t
 563 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
 564 {
 565     uint32_t val = pci_get_long(config);
 566     pci_set_long(config, val | mask);
 567     return val & mask;
 568 }
 569
 570 static inline uint64_t
 571 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
 572 {
 573     uint64_t val = pci_get_quad(config);
 574     pci_set_quad(config, val & ~mask);
 575     return val & mask;
 576 }
 577
 578 static inline uint64_t
 579 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
 580 {
 581     uint64_t val = pci_get_quad(config);
 582     pci_set_quad(config, val | mask);
 583     return val & mask;
 584 }
 585
 586 /* Access a register specified by a mask */
 587 static inline void
 588 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg)
 589 {
 590     uint8_t val = pci_get_byte(config);
 591     uint8_t rval = reg << ctz32(mask);
 592     pci_set_byte(config, (~mask & val) | (mask & rval));
 593 }
 594
 595 static inline uint8_t
 596 pci_get_byte_by_mask(uint8_t *config, uint8_t mask)
 597 {
 598     uint8_t val = pci_get_byte(config);
 599     return (val & mask) >> ctz32(mask);
 600 }
 601
 602 static inline void
 603 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg)
 604 {
 605     uint16_t val = pci_get_word(config);
 606     uint16_t rval = reg << ctz32(mask);
 607     pci_set_word(config, (~mask & val) | (mask & rval));
 608 }
 609
 610 static inline uint16_t
 611 pci_get_word_by_mask(uint8_t *config, uint16_t mask)
 612 {
 613     uint16_t val = pci_get_word(config);
 614     return (val & mask) >> ctz32(mask);
 615 }
 616
 617 static inline void
 618 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg)
 619 {
 620     uint32_t val = pci_get_long(config);
 621     uint32_t rval = reg << ctz32(mask);
 622     pci_set_long(config, (~mask & val) | (mask & rval));
 623 }
 624
 625 static inline uint32_t
 626 pci_get_long_by_mask(uint8_t *config, uint32_t mask)
 627 {
 628     uint32_t val = pci_get_long(config);
 629     return (val & mask) >> ctz32(mask);
 630 }
 631
 632 static inline void
 633 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg)
 634 {
 635     uint64_t val = pci_get_quad(config);
 636     uint64_t rval = reg << ctz32(mask);
 637     pci_set_quad(config, (~mask & val) | (mask & rval));
 638 }
 639
 640 static inline uint64_t
 641 pci_get_quad_by_mask(uint8_t *config, uint64_t mask)
 642 {
 643     uint64_t val = pci_get_quad(config);
 644     return (val & mask) >> ctz32(mask);
 645 }
 646
 647 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
 648                                     const char *name);
 649 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
 650                                            bool multifunction,
 651                                            const char *name);
 652 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
 653 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
 654
 655 qemu_irq pci_allocate_irq(PCIDevice *pci_dev);
 656 void pci_set_irq(PCIDevice *pci_dev, int level);
 657
 658 static inline void pci_irq_assert(PCIDevice *pci_dev)
 659 {
 660     pci_set_irq(pci_dev, 1);
 661 }
 662
 663 static inline void pci_irq_deassert(PCIDevice *pci_dev)
 664 {
 665     pci_set_irq(pci_dev, 0);
 666 }
 667
 668 /*
 669  * FIXME: PCI does not work this way.
 670  * All the callers to this method should be fixed.
 671  */
 672 static inline void pci_irq_pulse(PCIDevice *pci_dev)
 673 {
 674     pci_irq_assert(pci_dev);
 675     pci_irq_deassert(pci_dev);
 676 }
 677
 678 static inline int pci_is_express(const PCIDevice *d)
 679 {
 680     return d->cap_present & QEMU_PCI_CAP_EXPRESS;
 681 }
 682
 683 static inline uint32_t pci_config_size(const PCIDevice *d)
 684 {
 685     return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
 686 }
 687
 688 static inline uint16_t pci_requester_id(PCIDevice *dev)
 689 {
 690     return (pci_bus_num(dev->bus) << 8) | dev->devfn;
 691 }
 692
 693 /* DMA access functions */
 694 static inline AddressSpace *pci_get_address_space(PCIDevice *dev)
 695 {
 696     return &dev->bus_master_as;
 697 }
 698
 699 static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
 700                              void *buf, dma_addr_t len, DMADirection dir)
 701 {
 702     dma_memory_rw(pci_get_address_space(dev), addr, buf, len, dir);
 703     return 0;
 704 }
 705
 706 static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr,
 707                                void *buf, dma_addr_t len)
 708 {
 709     return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE);
 710 }
 711
 712 static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr,
 713                                 const void *buf, dma_addr_t len)
 714 {
 715     return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE);
 716 }
 717
 718 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits)                              \
 719     static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev,      \
 720                                                    dma_addr_t addr)     \
 721     {                                                                   \
 722         return ld##_l##_dma(pci_get_address_space(dev), addr);          \
 723     }                                                                   \
 724     static inline void st##_s##_pci_dma(PCIDevice *dev,                 \
 725                                         dma_addr_t addr, uint##_bits##_t val) \
 726     {                                                                   \
 727         st##_s##_dma(pci_get_address_space(dev), addr, val);            \
 728     }
 729
 730 PCI_DMA_DEFINE_LDST(ub, b, 8);
 731 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16)
 732 PCI_DMA_DEFINE_LDST(l_le, l_le, 32);
 733 PCI_DMA_DEFINE_LDST(q_le, q_le, 64);
 734 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16)
 735 PCI_DMA_DEFINE_LDST(l_be, l_be, 32);
 736 PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
 737
 738 #undef PCI_DMA_DEFINE_LDST
 739
 740 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr,
 741                                 dma_addr_t *plen, DMADirection dir)
 742 {
 743     void *buf;
 744
 745     buf = dma_memory_map(pci_get_address_space(dev), addr, plen, dir);
 746     return buf;
 747 }
 748
 749 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len,
 750                                  DMADirection dir, dma_addr_t access_len)
 751 {
 752     dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len);
 753 }
 754
 755 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev,
 756                                        int alloc_hint)
 757 {
 758     qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev));
 759 }
 760
 761 extern const VMStateDescription vmstate_pci_device;
 762
 763 #define VMSTATE_PCI_DEVICE(_field, _state) {                         \
 764     .name       = (stringify(_field)),                               \
 765     .size       = sizeof(PCIDevice),                                 \
 766     .vmsd       = &vmstate_pci_device,                               \
 767     .flags      = VMS_STRUCT,                                        \
 768     .offset     = vmstate_offset_value(_state, _field, PCIDevice),   \
 769 }
 770
 771 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) {                 \
 772     .name       = (stringify(_field)),                               \
 773     .size       = sizeof(PCIDevice),                                 \
 774     .vmsd       = &vmstate_pci_device,                               \
 775     .flags      = VMS_STRUCT|VMS_POINTER,                            \
 776     .offset     = vmstate_offset_pointer(_state, _field, PCIDevice), \
 777 }
 778
 779 #endif