2 * QEMU PowerPC PowerNV machine model
4 * Copyright (c) 2016, IBM Corporation.
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu/datadir.h"
22 #include "qemu/units.h"
23 #include "qemu/cutils.h"
24 #include "qapi/error.h"
25 #include "sysemu/qtest.h"
26 #include "sysemu/sysemu.h"
27 #include "sysemu/numa.h"
28 #include "sysemu/reset.h"
29 #include "sysemu/runstate.h"
30 #include "sysemu/cpus.h"
31 #include "sysemu/device_tree.h"
32 #include "sysemu/hw_accel.h"
33 #include "target/ppc/cpu.h"
34 #include "hw/ppc/fdt.h"
35 #include "hw/ppc/ppc.h"
36 #include "hw/ppc/pnv.h"
37 #include "hw/ppc/pnv_core.h"
38 #include "hw/loader.h"
40 #include "qapi/visitor.h"
41 #include "monitor/monitor.h"
42 #include "hw/intc/intc.h"
43 #include "hw/ipmi/ipmi.h"
44 #include "target/ppc/mmu-hash64.h"
45 #include "hw/pci/msi.h"
46 #include "hw/pci-host/pnv_phb.h"
47 #include "hw/pci-host/pnv_phb3.h"
48 #include "hw/pci-host/pnv_phb4.h"
50 #include "hw/ppc/xics.h"
51 #include "hw/qdev-properties.h"
52 #include "hw/ppc/pnv_chip.h"
53 #include "hw/ppc/pnv_xscom.h"
54 #include "hw/ppc/pnv_pnor.h"
56 #include "hw/isa/isa.h"
57 #include "hw/char/serial.h"
58 #include "hw/rtc/mc146818rtc.h"
62 #define FDT_MAX_SIZE (1 * MiB)
64 #define FW_FILE_NAME "skiboot.lid"
65 #define FW_LOAD_ADDR 0x0
66 #define FW_MAX_SIZE (16 * MiB)
68 #define KERNEL_LOAD_ADDR 0x20000000
69 #define KERNEL_MAX_SIZE (128 * MiB)
70 #define INITRD_LOAD_ADDR 0x28000000
71 #define INITRD_MAX_SIZE (128 * MiB)
73 static const char *pnv_chip_core_typename(const PnvChip
*o
)
75 const char *chip_type
= object_class_get_name(object_get_class(OBJECT(o
)));
76 int len
= strlen(chip_type
) - strlen(PNV_CHIP_TYPE_SUFFIX
);
77 char *s
= g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len
, chip_type
);
78 const char *core_type
= object_class_get_name(object_class_by_name(s
));
84 * On Power Systems E880 (POWER8), the max cpus (threads) should be :
85 * 4 * 4 sockets * 12 cores * 8 threads = 1536
91 * Memory nodes are created by hostboot, one for each range of memory
92 * that has a different "affinity". In practice, it means one range
95 static void pnv_dt_memory(void *fdt
, int chip_id
, hwaddr start
, hwaddr size
)
98 uint64_t mem_reg_property
[2];
101 mem_reg_property
[0] = cpu_to_be64(start
);
102 mem_reg_property
[1] = cpu_to_be64(size
);
104 mem_name
= g_strdup_printf("memory@%"HWADDR_PRIx
, start
);
105 off
= fdt_add_subnode(fdt
, 0, mem_name
);
108 _FDT((fdt_setprop_string(fdt
, off
, "device_type", "memory")));
109 _FDT((fdt_setprop(fdt
, off
, "reg", mem_reg_property
,
110 sizeof(mem_reg_property
))));
111 _FDT((fdt_setprop_cell(fdt
, off
, "ibm,chip-id", chip_id
)));
114 static int get_cpus_node(void *fdt
)
116 int cpus_offset
= fdt_path_offset(fdt
, "/cpus");
118 if (cpus_offset
< 0) {
119 cpus_offset
= fdt_add_subnode(fdt
, 0, "cpus");
121 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#address-cells", 0x1)));
122 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#size-cells", 0x0)));
130 * The PowerNV cores (and threads) need to use real HW ids and not an
131 * incremental index like it has been done on other platforms. This HW
132 * id is stored in the CPU PIR, it is used to create cpu nodes in the
133 * device tree, used in XSCOM to address cores and in interrupt
136 static void pnv_dt_core(PnvChip
*chip
, PnvCore
*pc
, void *fdt
)
138 PowerPCCPU
*cpu
= pc
->threads
[0];
139 CPUState
*cs
= CPU(cpu
);
140 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
141 int smt_threads
= CPU_CORE(pc
)->nr_threads
;
142 CPUPPCState
*env
= &cpu
->env
;
143 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cs
);
144 g_autofree
uint32_t *servers_prop
= g_new(uint32_t, smt_threads
);
146 uint32_t segs
[] = {cpu_to_be32(28), cpu_to_be32(40),
147 0xffffffff, 0xffffffff};
148 uint32_t tbfreq
= PNV_TIMEBASE_FREQ
;
149 uint32_t cpufreq
= 1000000000;
150 uint32_t page_sizes_prop
[64];
151 size_t page_sizes_prop_size
;
152 const uint8_t pa_features
[] = { 24, 0,
153 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0,
154 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
155 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
156 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
159 int cpus_offset
= get_cpus_node(fdt
);
161 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, pc
->pir
);
162 offset
= fdt_add_subnode(fdt
, cpus_offset
, nodename
);
166 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,chip-id", chip
->chip_id
)));
168 _FDT((fdt_setprop_cell(fdt
, offset
, "reg", pc
->pir
)));
169 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,pir", pc
->pir
)));
170 _FDT((fdt_setprop_string(fdt
, offset
, "device_type", "cpu")));
172 _FDT((fdt_setprop_cell(fdt
, offset
, "cpu-version", env
->spr
[SPR_PVR
])));
173 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-block-size",
174 env
->dcache_line_size
)));
175 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-line-size",
176 env
->dcache_line_size
)));
177 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-block-size",
178 env
->icache_line_size
)));
179 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-line-size",
180 env
->icache_line_size
)));
182 if (pcc
->l1_dcache_size
) {
183 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-size",
184 pcc
->l1_dcache_size
)));
186 warn_report("Unknown L1 dcache size for cpu");
188 if (pcc
->l1_icache_size
) {
189 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-size",
190 pcc
->l1_icache_size
)));
192 warn_report("Unknown L1 icache size for cpu");
195 _FDT((fdt_setprop_cell(fdt
, offset
, "timebase-frequency", tbfreq
)));
196 _FDT((fdt_setprop_cell(fdt
, offset
, "clock-frequency", cpufreq
)));
197 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,slb-size",
198 cpu
->hash64_opts
->slb_size
)));
199 _FDT((fdt_setprop_string(fdt
, offset
, "status", "okay")));
200 _FDT((fdt_setprop(fdt
, offset
, "64-bit", NULL
, 0)));
202 if (ppc_has_spr(cpu
, SPR_PURR
)) {
203 _FDT((fdt_setprop(fdt
, offset
, "ibm,purr", NULL
, 0)));
206 if (ppc_hash64_has(cpu
, PPC_HASH64_1TSEG
)) {
207 _FDT((fdt_setprop(fdt
, offset
, "ibm,processor-segment-sizes",
208 segs
, sizeof(segs
))));
212 * Advertise VMX/VSX (vector extensions) if available
213 * 0 / no property == no vector extensions
214 * 1 == VMX / Altivec available
217 if (env
->insns_flags
& PPC_ALTIVEC
) {
218 uint32_t vmx
= (env
->insns_flags2
& PPC2_VSX
) ? 2 : 1;
220 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,vmx", vmx
)));
224 * Advertise DFP (Decimal Floating Point) if available
225 * 0 / no property == no DFP
228 if (env
->insns_flags2
& PPC2_DFP
) {
229 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,dfp", 1)));
232 page_sizes_prop_size
= ppc_create_page_sizes_prop(cpu
, page_sizes_prop
,
233 sizeof(page_sizes_prop
));
234 if (page_sizes_prop_size
) {
235 _FDT((fdt_setprop(fdt
, offset
, "ibm,segment-page-sizes",
236 page_sizes_prop
, page_sizes_prop_size
)));
239 _FDT((fdt_setprop(fdt
, offset
, "ibm,pa-features",
240 pa_features
, sizeof(pa_features
))));
242 /* Build interrupt servers properties */
243 for (i
= 0; i
< smt_threads
; i
++) {
244 servers_prop
[i
] = cpu_to_be32(pc
->pir
+ i
);
246 _FDT((fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-server#s",
247 servers_prop
, sizeof(*servers_prop
) * smt_threads
)));
250 static void pnv_dt_icp(PnvChip
*chip
, void *fdt
, uint32_t pir
,
253 uint64_t addr
= PNV_ICP_BASE(chip
) | (pir
<< 12);
255 const char compat
[] = "IBM,power8-icp\0IBM,ppc-xicp";
256 uint32_t irange
[2], i
, rsize
;
260 irange
[0] = cpu_to_be32(pir
);
261 irange
[1] = cpu_to_be32(nr_threads
);
263 rsize
= sizeof(uint64_t) * 2 * nr_threads
;
264 reg
= g_malloc(rsize
);
265 for (i
= 0; i
< nr_threads
; i
++) {
266 reg
[i
* 2] = cpu_to_be64(addr
| ((pir
+ i
) * 0x1000));
267 reg
[i
* 2 + 1] = cpu_to_be64(0x1000);
270 name
= g_strdup_printf("interrupt-controller@%"PRIX64
, addr
);
271 offset
= fdt_add_subnode(fdt
, 0, name
);
275 _FDT((fdt_setprop(fdt
, offset
, "compatible", compat
, sizeof(compat
))));
276 _FDT((fdt_setprop(fdt
, offset
, "reg", reg
, rsize
)));
277 _FDT((fdt_setprop_string(fdt
, offset
, "device_type",
278 "PowerPC-External-Interrupt-Presentation")));
279 _FDT((fdt_setprop(fdt
, offset
, "interrupt-controller", NULL
, 0)));
280 _FDT((fdt_setprop(fdt
, offset
, "ibm,interrupt-server-ranges",
281 irange
, sizeof(irange
))));
282 _FDT((fdt_setprop_cell(fdt
, offset
, "#interrupt-cells", 1)));
283 _FDT((fdt_setprop_cell(fdt
, offset
, "#address-cells", 0)));
288 * Adds a PnvPHB to the chip on P8.
289 * Implemented here, like for defaults PHBs
291 PnvChip
*pnv_chip_add_phb(PnvChip
*chip
, PnvPHB
*phb
)
293 Pnv8Chip
*chip8
= PNV8_CHIP(chip
);
297 chip8
->phbs
[chip8
->num_phbs
] = phb
;
302 static void pnv_chip_power8_dt_populate(PnvChip
*chip
, void *fdt
)
304 static const char compat
[] = "ibm,power8-xscom\0ibm,xscom";
307 pnv_dt_xscom(chip
, fdt
, 0,
308 cpu_to_be64(PNV_XSCOM_BASE(chip
)),
309 cpu_to_be64(PNV_XSCOM_SIZE
),
310 compat
, sizeof(compat
));
312 for (i
= 0; i
< chip
->nr_cores
; i
++) {
313 PnvCore
*pnv_core
= chip
->cores
[i
];
315 pnv_dt_core(chip
, pnv_core
, fdt
);
317 /* Interrupt Control Presenters (ICP). One per core. */
318 pnv_dt_icp(chip
, fdt
, pnv_core
->pir
, CPU_CORE(pnv_core
)->nr_threads
);
321 if (chip
->ram_size
) {
322 pnv_dt_memory(fdt
, chip
->chip_id
, chip
->ram_start
, chip
->ram_size
);
326 static void pnv_chip_power9_dt_populate(PnvChip
*chip
, void *fdt
)
328 static const char compat
[] = "ibm,power9-xscom\0ibm,xscom";
331 pnv_dt_xscom(chip
, fdt
, 0,
332 cpu_to_be64(PNV9_XSCOM_BASE(chip
)),
333 cpu_to_be64(PNV9_XSCOM_SIZE
),
334 compat
, sizeof(compat
));
336 for (i
= 0; i
< chip
->nr_cores
; i
++) {
337 PnvCore
*pnv_core
= chip
->cores
[i
];
339 pnv_dt_core(chip
, pnv_core
, fdt
);
342 if (chip
->ram_size
) {
343 pnv_dt_memory(fdt
, chip
->chip_id
, chip
->ram_start
, chip
->ram_size
);
346 pnv_dt_lpc(chip
, fdt
, 0, PNV9_LPCM_BASE(chip
), PNV9_LPCM_SIZE
);
349 static void pnv_chip_power10_dt_populate(PnvChip
*chip
, void *fdt
)
351 static const char compat
[] = "ibm,power10-xscom\0ibm,xscom";
354 pnv_dt_xscom(chip
, fdt
, 0,
355 cpu_to_be64(PNV10_XSCOM_BASE(chip
)),
356 cpu_to_be64(PNV10_XSCOM_SIZE
),
357 compat
, sizeof(compat
));
359 for (i
= 0; i
< chip
->nr_cores
; i
++) {
360 PnvCore
*pnv_core
= chip
->cores
[i
];
362 pnv_dt_core(chip
, pnv_core
, fdt
);
365 if (chip
->ram_size
) {
366 pnv_dt_memory(fdt
, chip
->chip_id
, chip
->ram_start
, chip
->ram_size
);
369 pnv_dt_lpc(chip
, fdt
, 0, PNV10_LPCM_BASE(chip
), PNV10_LPCM_SIZE
);
372 static void pnv_dt_rtc(ISADevice
*d
, void *fdt
, int lpc_off
)
374 uint32_t io_base
= d
->ioport_id
;
375 uint32_t io_regs
[] = {
377 cpu_to_be32(io_base
),
383 name
= g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d
)), io_base
);
384 node
= fdt_add_subnode(fdt
, lpc_off
, name
);
388 _FDT((fdt_setprop(fdt
, node
, "reg", io_regs
, sizeof(io_regs
))));
389 _FDT((fdt_setprop_string(fdt
, node
, "compatible", "pnpPNP,b00")));
392 static void pnv_dt_serial(ISADevice
*d
, void *fdt
, int lpc_off
)
394 const char compatible
[] = "ns16550\0pnpPNP,501";
395 uint32_t io_base
= d
->ioport_id
;
396 uint32_t io_regs
[] = {
398 cpu_to_be32(io_base
),
405 irq
= object_property_get_uint(OBJECT(d
), "irq", &error_fatal
);
407 name
= g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d
)), io_base
);
408 node
= fdt_add_subnode(fdt
, lpc_off
, name
);
412 _FDT((fdt_setprop(fdt
, node
, "reg", io_regs
, sizeof(io_regs
))));
413 _FDT((fdt_setprop(fdt
, node
, "compatible", compatible
,
414 sizeof(compatible
))));
416 _FDT((fdt_setprop_cell(fdt
, node
, "clock-frequency", 1843200)));
417 _FDT((fdt_setprop_cell(fdt
, node
, "current-speed", 115200)));
418 _FDT((fdt_setprop_cell(fdt
, node
, "interrupts", irq
)));
419 _FDT((fdt_setprop_cell(fdt
, node
, "interrupt-parent",
420 fdt_get_phandle(fdt
, lpc_off
))));
422 /* This is needed by Linux */
423 _FDT((fdt_setprop_string(fdt
, node
, "device_type", "serial")));
426 static void pnv_dt_ipmi_bt(ISADevice
*d
, void *fdt
, int lpc_off
)
428 const char compatible
[] = "bt\0ipmi-bt";
430 uint32_t io_regs
[] = {
432 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */
439 io_base
= object_property_get_int(OBJECT(d
), "ioport", &error_fatal
);
440 io_regs
[1] = cpu_to_be32(io_base
);
442 irq
= object_property_get_int(OBJECT(d
), "irq", &error_fatal
);
444 name
= g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d
)), io_base
);
445 node
= fdt_add_subnode(fdt
, lpc_off
, name
);
449 _FDT((fdt_setprop(fdt
, node
, "reg", io_regs
, sizeof(io_regs
))));
450 _FDT((fdt_setprop(fdt
, node
, "compatible", compatible
,
451 sizeof(compatible
))));
453 /* Mark it as reserved to avoid Linux trying to claim it */
454 _FDT((fdt_setprop_string(fdt
, node
, "status", "reserved")));
455 _FDT((fdt_setprop_cell(fdt
, node
, "interrupts", irq
)));
456 _FDT((fdt_setprop_cell(fdt
, node
, "interrupt-parent",
457 fdt_get_phandle(fdt
, lpc_off
))));
460 typedef struct ForeachPopulateArgs
{
463 } ForeachPopulateArgs
;
465 static int pnv_dt_isa_device(DeviceState
*dev
, void *opaque
)
467 ForeachPopulateArgs
*args
= opaque
;
468 ISADevice
*d
= ISA_DEVICE(dev
);
470 if (object_dynamic_cast(OBJECT(dev
), TYPE_MC146818_RTC
)) {
471 pnv_dt_rtc(d
, args
->fdt
, args
->offset
);
472 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_ISA_SERIAL
)) {
473 pnv_dt_serial(d
, args
->fdt
, args
->offset
);
474 } else if (object_dynamic_cast(OBJECT(dev
), "isa-ipmi-bt")) {
475 pnv_dt_ipmi_bt(d
, args
->fdt
, args
->offset
);
477 error_report("unknown isa device %s@i%x", qdev_fw_name(dev
),
485 * The default LPC bus of a multichip system is on chip 0. It's
486 * recognized by the firmware (skiboot) using a "primary" property.
488 static void pnv_dt_isa(PnvMachineState
*pnv
, void *fdt
)
490 int isa_offset
= fdt_path_offset(fdt
, pnv
->chips
[0]->dt_isa_nodename
);
491 ForeachPopulateArgs args
= {
493 .offset
= isa_offset
,
497 _FDT((fdt_setprop(fdt
, isa_offset
, "primary", NULL
, 0)));
499 phandle
= qemu_fdt_alloc_phandle(fdt
);
501 _FDT((fdt_setprop_cell(fdt
, isa_offset
, "phandle", phandle
)));
504 * ISA devices are not necessarily parented to the ISA bus so we
505 * can not use object_child_foreach()
507 qbus_walk_children(BUS(pnv
->isa_bus
), pnv_dt_isa_device
, NULL
, NULL
, NULL
,
511 static void pnv_dt_power_mgt(PnvMachineState
*pnv
, void *fdt
)
515 off
= fdt_add_subnode(fdt
, 0, "ibm,opal");
516 off
= fdt_add_subnode(fdt
, off
, "power-mgt");
518 _FDT(fdt_setprop_cell(fdt
, off
, "ibm,enabled-stop-levels", 0xc0000000));
521 static void *pnv_dt_create(MachineState
*machine
)
523 PnvMachineClass
*pmc
= PNV_MACHINE_GET_CLASS(machine
);
524 PnvMachineState
*pnv
= PNV_MACHINE(machine
);
530 fdt
= g_malloc0(FDT_MAX_SIZE
);
531 _FDT((fdt_create_empty_tree(fdt
, FDT_MAX_SIZE
)));
534 _FDT((fdt_add_subnode(fdt
, 0, "qemu")));
537 _FDT((fdt_setprop_cell(fdt
, 0, "#address-cells", 0x2)));
538 _FDT((fdt_setprop_cell(fdt
, 0, "#size-cells", 0x2)));
539 _FDT((fdt_setprop_string(fdt
, 0, "model",
540 "IBM PowerNV (emulated by qemu)")));
541 _FDT((fdt_setprop(fdt
, 0, "compatible", pmc
->compat
, pmc
->compat_size
)));
543 buf
= qemu_uuid_unparse_strdup(&qemu_uuid
);
544 _FDT((fdt_setprop_string(fdt
, 0, "vm,uuid", buf
)));
546 _FDT((fdt_setprop_string(fdt
, 0, "system-id", buf
)));
550 off
= fdt_add_subnode(fdt
, 0, "chosen");
551 if (machine
->kernel_cmdline
) {
552 _FDT((fdt_setprop_string(fdt
, off
, "bootargs",
553 machine
->kernel_cmdline
)));
556 if (pnv
->initrd_size
) {
557 uint32_t start_prop
= cpu_to_be32(pnv
->initrd_base
);
558 uint32_t end_prop
= cpu_to_be32(pnv
->initrd_base
+ pnv
->initrd_size
);
560 _FDT((fdt_setprop(fdt
, off
, "linux,initrd-start",
561 &start_prop
, sizeof(start_prop
))));
562 _FDT((fdt_setprop(fdt
, off
, "linux,initrd-end",
563 &end_prop
, sizeof(end_prop
))));
566 /* Populate device tree for each chip */
567 for (i
= 0; i
< pnv
->num_chips
; i
++) {
568 PNV_CHIP_GET_CLASS(pnv
->chips
[i
])->dt_populate(pnv
->chips
[i
], fdt
);
571 /* Populate ISA devices on chip 0 */
572 pnv_dt_isa(pnv
, fdt
);
575 pnv_dt_bmc_sensors(pnv
->bmc
, fdt
);
578 /* Create an extra node for power management on machines that support it */
579 if (pmc
->dt_power_mgt
) {
580 pmc
->dt_power_mgt(pnv
, fdt
);
586 static void pnv_powerdown_notify(Notifier
*n
, void *opaque
)
588 PnvMachineState
*pnv
= container_of(n
, PnvMachineState
, powerdown_notifier
);
591 pnv_bmc_powerdown(pnv
->bmc
);
595 static void pnv_reset(MachineState
*machine
, ShutdownCause reason
)
597 PnvMachineState
*pnv
= PNV_MACHINE(machine
);
601 qemu_devices_reset(reason
);
604 * The machine should provide by default an internal BMC simulator.
605 * If not, try to use the BMC device that was provided on the command
608 bmc
= pnv_bmc_find(&error_fatal
);
611 if (!qtest_enabled()) {
612 warn_report("machine has no BMC device. Use '-device "
613 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' "
617 pnv_bmc_set_pnor(bmc
, pnv
->pnor
);
622 fdt
= pnv_dt_create(machine
);
624 /* Pack resulting tree */
625 _FDT((fdt_pack(fdt
)));
627 qemu_fdt_dumpdtb(fdt
, fdt_totalsize(fdt
));
628 cpu_physical_memory_write(PNV_FDT_ADDR
, fdt
, fdt_totalsize(fdt
));
631 * Set machine->fdt for 'dumpdtb' QMP/HMP command. Free
632 * the existing machine->fdt to avoid leaking it during
635 g_free(machine
->fdt
);
639 static ISABus
*pnv_chip_power8_isa_create(PnvChip
*chip
, Error
**errp
)
641 Pnv8Chip
*chip8
= PNV8_CHIP(chip
);
642 qemu_irq irq
= qdev_get_gpio_in(DEVICE(&chip8
->psi
), PSIHB_IRQ_EXTERNAL
);
644 qdev_connect_gpio_out(DEVICE(&chip8
->lpc
), 0, irq
);
645 return pnv_lpc_isa_create(&chip8
->lpc
, true, errp
);
648 static ISABus
*pnv_chip_power8nvl_isa_create(PnvChip
*chip
, Error
**errp
)
650 Pnv8Chip
*chip8
= PNV8_CHIP(chip
);
651 qemu_irq irq
= qdev_get_gpio_in(DEVICE(&chip8
->psi
), PSIHB_IRQ_LPC_I2C
);
653 qdev_connect_gpio_out(DEVICE(&chip8
->lpc
), 0, irq
);
654 return pnv_lpc_isa_create(&chip8
->lpc
, false, errp
);
657 static ISABus
*pnv_chip_power9_isa_create(PnvChip
*chip
, Error
**errp
)
659 Pnv9Chip
*chip9
= PNV9_CHIP(chip
);
660 qemu_irq irq
= qdev_get_gpio_in(DEVICE(&chip9
->psi
), PSIHB9_IRQ_LPCHC
);
662 qdev_connect_gpio_out(DEVICE(&chip9
->lpc
), 0, irq
);
663 return pnv_lpc_isa_create(&chip9
->lpc
, false, errp
);
666 static ISABus
*pnv_chip_power10_isa_create(PnvChip
*chip
, Error
**errp
)
668 Pnv10Chip
*chip10
= PNV10_CHIP(chip
);
669 qemu_irq irq
= qdev_get_gpio_in(DEVICE(&chip10
->psi
), PSIHB9_IRQ_LPCHC
);
671 qdev_connect_gpio_out(DEVICE(&chip10
->lpc
), 0, irq
);
672 return pnv_lpc_isa_create(&chip10
->lpc
, false, errp
);
675 static ISABus
*pnv_isa_create(PnvChip
*chip
, Error
**errp
)
677 return PNV_CHIP_GET_CLASS(chip
)->isa_create(chip
, errp
);
680 static void pnv_chip_power8_pic_print_info(PnvChip
*chip
, Monitor
*mon
)
682 Pnv8Chip
*chip8
= PNV8_CHIP(chip
);
685 ics_pic_print_info(&chip8
->psi
.ics
, mon
);
687 for (i
= 0; i
< chip8
->num_phbs
; i
++) {
688 PnvPHB
*phb
= chip8
->phbs
[i
];
689 PnvPHB3
*phb3
= PNV_PHB3(phb
->backend
);
691 pnv_phb3_msi_pic_print_info(&phb3
->msis
, mon
);
692 ics_pic_print_info(&phb3
->lsis
, mon
);
696 static int pnv_chip_power9_pic_print_info_child(Object
*child
, void *opaque
)
698 Monitor
*mon
= opaque
;
699 PnvPHB
*phb
= (PnvPHB
*) object_dynamic_cast(child
, TYPE_PNV_PHB
);
705 pnv_phb4_pic_print_info(PNV_PHB4(phb
->backend
), mon
);
710 static void pnv_chip_power9_pic_print_info(PnvChip
*chip
, Monitor
*mon
)
712 Pnv9Chip
*chip9
= PNV9_CHIP(chip
);
714 pnv_xive_pic_print_info(&chip9
->xive
, mon
);
715 pnv_psi_pic_print_info(&chip9
->psi
, mon
);
717 object_child_foreach_recursive(OBJECT(chip
),
718 pnv_chip_power9_pic_print_info_child
, mon
);
721 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip
*chip
,
724 return PNV_XSCOM_EX_BASE(core_id
);
727 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip
*chip
,
730 return PNV9_XSCOM_EC_BASE(core_id
);
733 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip
*chip
,
736 return PNV10_XSCOM_EC_BASE(core_id
);
739 static bool pnv_match_cpu(const char *default_type
, const char *cpu_type
)
741 PowerPCCPUClass
*ppc_default
=
742 POWERPC_CPU_CLASS(object_class_by_name(default_type
));
743 PowerPCCPUClass
*ppc
=
744 POWERPC_CPU_CLASS(object_class_by_name(cpu_type
));
746 return ppc_default
->pvr_match(ppc_default
, ppc
->pvr
, false);
749 static void pnv_ipmi_bt_init(ISABus
*bus
, IPMIBmc
*bmc
, uint32_t irq
)
751 ISADevice
*dev
= isa_new("isa-ipmi-bt");
753 object_property_set_link(OBJECT(dev
), "bmc", OBJECT(bmc
), &error_fatal
);
754 object_property_set_int(OBJECT(dev
), "irq", irq
, &error_fatal
);
755 isa_realize_and_unref(dev
, bus
, &error_fatal
);
758 static void pnv_chip_power10_pic_print_info(PnvChip
*chip
, Monitor
*mon
)
760 Pnv10Chip
*chip10
= PNV10_CHIP(chip
);
762 pnv_xive2_pic_print_info(&chip10
->xive
, mon
);
763 pnv_psi_pic_print_info(&chip10
->psi
, mon
);
765 object_child_foreach_recursive(OBJECT(chip
),
766 pnv_chip_power9_pic_print_info_child
, mon
);
769 /* Always give the first 1GB to chip 0 else we won't boot */
770 static uint64_t pnv_chip_get_ram_size(PnvMachineState
*pnv
, int chip_id
)
772 MachineState
*machine
= MACHINE(pnv
);
773 uint64_t ram_per_chip
;
775 assert(machine
->ram_size
>= 1 * GiB
);
777 ram_per_chip
= machine
->ram_size
/ pnv
->num_chips
;
778 if (ram_per_chip
>= 1 * GiB
) {
779 return QEMU_ALIGN_DOWN(ram_per_chip
, 1 * MiB
);
782 assert(pnv
->num_chips
> 1);
784 ram_per_chip
= (machine
->ram_size
- 1 * GiB
) / (pnv
->num_chips
- 1);
785 return chip_id
== 0 ? 1 * GiB
: QEMU_ALIGN_DOWN(ram_per_chip
, 1 * MiB
);
788 static void pnv_init(MachineState
*machine
)
790 const char *bios_name
= machine
->firmware
?: FW_FILE_NAME
;
791 PnvMachineState
*pnv
= PNV_MACHINE(machine
);
792 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
793 PnvMachineClass
*pmc
= PNV_MACHINE_GET_CLASS(machine
);
796 uint64_t chip_ram_start
= 0;
799 DriveInfo
*pnor
= drive_get(IF_MTD
, 0, 0);
803 error_report("machine %s does not support the KVM accelerator",
809 if (machine
->ram_size
< mc
->default_ram_size
) {
810 char *sz
= size_to_str(mc
->default_ram_size
);
811 error_report("Invalid RAM size, should be bigger than %s", sz
);
815 memory_region_add_subregion(get_system_memory(), 0, machine
->ram
);
818 * Create our simple PNOR device
820 dev
= qdev_new(TYPE_PNV_PNOR
);
822 qdev_prop_set_drive(dev
, "drive", blk_by_legacy_dinfo(pnor
));
824 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
825 pnv
->pnor
= PNV_PNOR(dev
);
827 /* load skiboot firmware */
828 fw_filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
830 error_report("Could not find OPAL firmware '%s'", bios_name
);
834 fw_size
= load_image_targphys(fw_filename
, pnv
->fw_load_addr
, FW_MAX_SIZE
);
836 error_report("Could not load OPAL firmware '%s'", fw_filename
);
842 if (machine
->kernel_filename
) {
845 kernel_size
= load_image_targphys(machine
->kernel_filename
,
846 KERNEL_LOAD_ADDR
, KERNEL_MAX_SIZE
);
847 if (kernel_size
< 0) {
848 error_report("Could not load kernel '%s'",
849 machine
->kernel_filename
);
855 if (machine
->initrd_filename
) {
856 pnv
->initrd_base
= INITRD_LOAD_ADDR
;
857 pnv
->initrd_size
= load_image_targphys(machine
->initrd_filename
,
858 pnv
->initrd_base
, INITRD_MAX_SIZE
);
859 if (pnv
->initrd_size
< 0) {
860 error_report("Could not load initial ram disk '%s'",
861 machine
->initrd_filename
);
866 /* MSIs are supported on this platform */
867 msi_nonbroken
= true;
870 * Check compatibility of the specified CPU with the machine
873 if (!pnv_match_cpu(mc
->default_cpu_type
, machine
->cpu_type
)) {
874 error_report("invalid CPU model '%s' for %s machine",
875 machine
->cpu_type
, mc
->name
);
879 /* Create the processor chips */
880 i
= strlen(machine
->cpu_type
) - strlen(POWERPC_CPU_TYPE_SUFFIX
);
881 chip_typename
= g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"),
882 i
, machine
->cpu_type
);
883 if (!object_class_by_name(chip_typename
)) {
884 error_report("invalid chip model '%.*s' for %s machine",
885 i
, machine
->cpu_type
, mc
->name
);
890 machine
->smp
.max_cpus
/ (machine
->smp
.cores
* machine
->smp
.threads
);
892 if (machine
->smp
.threads
> 8) {
893 error_report("Cannot support more than 8 threads/core "
894 "on a powernv machine");
897 if (!is_power_of_2(machine
->smp
.threads
)) {
898 error_report("Cannot support %d threads/core on a powernv"
899 "machine because it must be a power of 2",
900 machine
->smp
.threads
);
904 * TODO: should we decide on how many chips we can create based
905 * on #cores and Venice vs. Murano vs. Naples chip type etc...,
907 if (!is_power_of_2(pnv
->num_chips
) || pnv
->num_chips
> 16) {
908 error_report("invalid number of chips: '%d'", pnv
->num_chips
);
910 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n");
914 pnv
->chips
= g_new0(PnvChip
*, pnv
->num_chips
);
915 for (i
= 0; i
< pnv
->num_chips
; i
++) {
917 Object
*chip
= OBJECT(qdev_new(chip_typename
));
918 uint64_t chip_ram_size
= pnv_chip_get_ram_size(pnv
, i
);
920 pnv
->chips
[i
] = PNV_CHIP(chip
);
922 /* Distribute RAM among the chips */
923 object_property_set_int(chip
, "ram-start", chip_ram_start
,
925 object_property_set_int(chip
, "ram-size", chip_ram_size
,
927 chip_ram_start
+= chip_ram_size
;
929 snprintf(chip_name
, sizeof(chip_name
), "chip[%d]", i
);
930 object_property_add_child(OBJECT(pnv
), chip_name
, chip
);
931 object_property_set_int(chip
, "chip-id", i
, &error_fatal
);
932 object_property_set_int(chip
, "nr-cores", machine
->smp
.cores
,
934 object_property_set_int(chip
, "nr-threads", machine
->smp
.threads
,
937 * The POWER8 machine use the XICS interrupt interface.
938 * Propagate the XICS fabric to the chip and its controllers.
940 if (object_dynamic_cast(OBJECT(pnv
), TYPE_XICS_FABRIC
)) {
941 object_property_set_link(chip
, "xics", OBJECT(pnv
), &error_abort
);
943 if (object_dynamic_cast(OBJECT(pnv
), TYPE_XIVE_FABRIC
)) {
944 object_property_set_link(chip
, "xive-fabric", OBJECT(pnv
),
947 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip
), &error_fatal
);
949 g_free(chip_typename
);
951 /* Instantiate ISA bus on chip 0 */
952 pnv
->isa_bus
= pnv_isa_create(pnv
->chips
[0], &error_fatal
);
954 /* Create serial port */
955 serial_hds_isa_init(pnv
->isa_bus
, 0, MAX_ISA_SERIAL_PORTS
);
957 /* Create an RTC ISA device too */
958 mc146818_rtc_init(pnv
->isa_bus
, 2000, NULL
);
961 * Create the machine BMC simulator and the IPMI BT device for
962 * communication with the BMC
964 if (defaults_enabled()) {
965 pnv
->bmc
= pnv_bmc_create(pnv
->pnor
);
966 pnv_ipmi_bt_init(pnv
->isa_bus
, pnv
->bmc
, 10);
970 * The PNOR is mapped on the LPC FW address space by the BMC.
971 * Since we can not reach the remote BMC machine with LPC memops,
972 * map it always for now.
974 memory_region_add_subregion(pnv
->chips
[0]->fw_mr
, PNOR_SPI_OFFSET
,
978 * OpenPOWER systems use a IPMI SEL Event message to notify the
981 pnv
->powerdown_notifier
.notify
= pnv_powerdown_notify
;
982 qemu_register_powerdown_notifier(&pnv
->powerdown_notifier
);
985 * Create/Connect any machine-specific I2C devices
993 * 0:21 Reserved - Read as zeros
998 static uint32_t pnv_chip_core_pir_p8(PnvChip
*chip
, uint32_t core_id
)
1000 return (chip
->chip_id
<< 7) | (core_id
<< 3);
1003 static void pnv_chip_power8_intc_create(PnvChip
*chip
, PowerPCCPU
*cpu
,
1006 Pnv8Chip
*chip8
= PNV8_CHIP(chip
);
1007 Error
*local_err
= NULL
;
1009 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
1011 obj
= icp_create(OBJECT(cpu
), TYPE_PNV_ICP
, chip8
->xics
, &local_err
);
1013 error_propagate(errp
, local_err
);
1017 pnv_cpu
->intc
= obj
;
1021 static void pnv_chip_power8_intc_reset(PnvChip
*chip
, PowerPCCPU
*cpu
)
1023 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
1025 icp_reset(ICP(pnv_cpu
->intc
));
1028 static void pnv_chip_power8_intc_destroy(PnvChip
*chip
, PowerPCCPU
*cpu
)
1030 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
1032 icp_destroy(ICP(pnv_cpu
->intc
));
1033 pnv_cpu
->intc
= NULL
;
1036 static void pnv_chip_power8_intc_print_info(PnvChip
*chip
, PowerPCCPU
*cpu
,
1039 icp_pic_print_info(ICP(pnv_cpu_state(cpu
)->intc
), mon
);
1043 * 0:48 Reserved - Read as zeroes
1046 * 56 Reserved - Read as zero
1050 * We only care about the lower bits. uint32_t is fine for the moment.
1052 static uint32_t pnv_chip_core_pir_p9(PnvChip
*chip
, uint32_t core_id
)
1054 return (chip
->chip_id
<< 8) | (core_id
<< 2);
1057 static uint32_t pnv_chip_core_pir_p10(PnvChip
*chip
, uint32_t core_id
)
1059 return (chip
->chip_id
<< 8) | (core_id
<< 2);
1062 static void pnv_chip_power9_intc_create(PnvChip
*chip
, PowerPCCPU
*cpu
,
1065 Pnv9Chip
*chip9
= PNV9_CHIP(chip
);
1066 Error
*local_err
= NULL
;
1068 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
1071 * The core creates its interrupt presenter but the XIVE interrupt
1072 * controller object is initialized afterwards. Hopefully, it's
1073 * only used at runtime.
1075 obj
= xive_tctx_create(OBJECT(cpu
), XIVE_PRESENTER(&chip9
->xive
),
1078 error_propagate(errp
, local_err
);
1082 pnv_cpu
->intc
= obj
;
1085 static void pnv_chip_power9_intc_reset(PnvChip
*chip
, PowerPCCPU
*cpu
)
1087 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
1089 xive_tctx_reset(XIVE_TCTX(pnv_cpu
->intc
));
1092 static void pnv_chip_power9_intc_destroy(PnvChip
*chip
, PowerPCCPU
*cpu
)
1094 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
1096 xive_tctx_destroy(XIVE_TCTX(pnv_cpu
->intc
));
1097 pnv_cpu
->intc
= NULL
;
1100 static void pnv_chip_power9_intc_print_info(PnvChip
*chip
, PowerPCCPU
*cpu
,
1103 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu
)->intc
), mon
);
1106 static void pnv_chip_power10_intc_create(PnvChip
*chip
, PowerPCCPU
*cpu
,
1109 Pnv10Chip
*chip10
= PNV10_CHIP(chip
);
1110 Error
*local_err
= NULL
;
1112 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
1115 * The core creates its interrupt presenter but the XIVE2 interrupt
1116 * controller object is initialized afterwards. Hopefully, it's
1117 * only used at runtime.
1119 obj
= xive_tctx_create(OBJECT(cpu
), XIVE_PRESENTER(&chip10
->xive
),
1122 error_propagate(errp
, local_err
);
1126 pnv_cpu
->intc
= obj
;
1129 static void pnv_chip_power10_intc_reset(PnvChip
*chip
, PowerPCCPU
*cpu
)
1131 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
1133 xive_tctx_reset(XIVE_TCTX(pnv_cpu
->intc
));
1136 static void pnv_chip_power10_intc_destroy(PnvChip
*chip
, PowerPCCPU
*cpu
)
1138 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
1140 xive_tctx_destroy(XIVE_TCTX(pnv_cpu
->intc
));
1141 pnv_cpu
->intc
= NULL
;
1144 static void pnv_chip_power10_intc_print_info(PnvChip
*chip
, PowerPCCPU
*cpu
,
1147 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu
)->intc
), mon
);
1151 * Allowed core identifiers on a POWER8 Processor Chip :
1160 * <EX7,8 reserved> <reserved>
1162 * EX10 - Venice only
1163 * EX11 - Venice only
1169 #define POWER8E_CORE_MASK (0x7070ull)
1170 #define POWER8_CORE_MASK (0x7e7eull)
1173 * POWER9 has 24 cores, ids starting at 0x0
1175 #define POWER9_CORE_MASK (0xffffffffffffffull)
1178 #define POWER10_CORE_MASK (0xffffffffffffffull)
1180 static void pnv_chip_power8_instance_init(Object
*obj
)
1182 Pnv8Chip
*chip8
= PNV8_CHIP(obj
);
1183 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(obj
);
1186 object_property_add_link(obj
, "xics", TYPE_XICS_FABRIC
,
1187 (Object
**)&chip8
->xics
,
1188 object_property_allow_set_link
,
1189 OBJ_PROP_LINK_STRONG
);
1191 object_initialize_child(obj
, "psi", &chip8
->psi
, TYPE_PNV8_PSI
);
1193 object_initialize_child(obj
, "lpc", &chip8
->lpc
, TYPE_PNV8_LPC
);
1195 object_initialize_child(obj
, "occ", &chip8
->occ
, TYPE_PNV8_OCC
);
1197 object_initialize_child(obj
, "homer", &chip8
->homer
, TYPE_PNV8_HOMER
);
1199 if (defaults_enabled()) {
1200 chip8
->num_phbs
= pcc
->num_phbs
;
1202 for (i
= 0; i
< chip8
->num_phbs
; i
++) {
1203 Object
*phb
= object_new(TYPE_PNV_PHB
);
1206 * We need the chip to parent the PHB to allow the DT
1207 * to build correctly (via pnv_xscom_dt()).
1209 * TODO: the PHB should be parented by a PEC device that, at
1210 * this moment, is not modelled powernv8/phb3.
1212 object_property_add_child(obj
, "phb[*]", phb
);
1213 chip8
->phbs
[i
] = PNV_PHB(phb
);
1219 static void pnv_chip_icp_realize(Pnv8Chip
*chip8
, Error
**errp
)
1221 PnvChip
*chip
= PNV_CHIP(chip8
);
1222 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(chip
);
1226 name
= g_strdup_printf("icp-%x", chip
->chip_id
);
1227 memory_region_init(&chip8
->icp_mmio
, OBJECT(chip
), name
, PNV_ICP_SIZE
);
1229 memory_region_add_subregion(get_system_memory(), PNV_ICP_BASE(chip
),
1232 /* Map the ICP registers for each thread */
1233 for (i
= 0; i
< chip
->nr_cores
; i
++) {
1234 PnvCore
*pnv_core
= chip
->cores
[i
];
1235 int core_hwid
= CPU_CORE(pnv_core
)->core_id
;
1237 for (j
= 0; j
< CPU_CORE(pnv_core
)->nr_threads
; j
++) {
1238 uint32_t pir
= pcc
->core_pir(chip
, core_hwid
) + j
;
1239 PnvICPState
*icp
= PNV_ICP(xics_icp_get(chip8
->xics
, pir
));
1241 memory_region_add_subregion(&chip8
->icp_mmio
, pir
<< 12,
1247 static void pnv_chip_power8_realize(DeviceState
*dev
, Error
**errp
)
1249 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(dev
);
1250 PnvChip
*chip
= PNV_CHIP(dev
);
1251 Pnv8Chip
*chip8
= PNV8_CHIP(dev
);
1252 Pnv8Psi
*psi8
= &chip8
->psi
;
1253 Error
*local_err
= NULL
;
1256 assert(chip8
->xics
);
1258 /* XSCOM bridge is first */
1259 pnv_xscom_init(chip
, PNV_XSCOM_SIZE
, PNV_XSCOM_BASE(chip
));
1261 pcc
->parent_realize(dev
, &local_err
);
1263 error_propagate(errp
, local_err
);
1267 /* Processor Service Interface (PSI) Host Bridge */
1268 object_property_set_int(OBJECT(&chip8
->psi
), "bar", PNV_PSIHB_BASE(chip
),
1270 object_property_set_link(OBJECT(&chip8
->psi
), ICS_PROP_XICS
,
1271 OBJECT(chip8
->xics
), &error_abort
);
1272 if (!qdev_realize(DEVICE(&chip8
->psi
), NULL
, errp
)) {
1275 pnv_xscom_add_subregion(chip
, PNV_XSCOM_PSIHB_BASE
,
1276 &PNV_PSI(psi8
)->xscom_regs
);
1278 /* Create LPC controller */
1279 qdev_realize(DEVICE(&chip8
->lpc
), NULL
, &error_fatal
);
1280 pnv_xscom_add_subregion(chip
, PNV_XSCOM_LPC_BASE
, &chip8
->lpc
.xscom_regs
);
1282 chip
->fw_mr
= &chip8
->lpc
.isa_fw
;
1283 chip
->dt_isa_nodename
= g_strdup_printf("/xscom@%" PRIx64
"/isa@%x",
1284 (uint64_t) PNV_XSCOM_BASE(chip
),
1285 PNV_XSCOM_LPC_BASE
);
1288 * Interrupt Management Area. This is the memory region holding
1289 * all the Interrupt Control Presenter (ICP) registers
1291 pnv_chip_icp_realize(chip8
, &local_err
);
1293 error_propagate(errp
, local_err
);
1297 /* Create the simplified OCC model */
1298 if (!qdev_realize(DEVICE(&chip8
->occ
), NULL
, errp
)) {
1301 pnv_xscom_add_subregion(chip
, PNV_XSCOM_OCC_BASE
, &chip8
->occ
.xscom_regs
);
1302 qdev_connect_gpio_out(DEVICE(&chip8
->occ
), 0,
1303 qdev_get_gpio_in(DEVICE(&chip8
->psi
), PSIHB_IRQ_OCC
));
1305 /* OCC SRAM model */
1306 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip
),
1307 &chip8
->occ
.sram_regs
);
1310 object_property_set_link(OBJECT(&chip8
->homer
), "chip", OBJECT(chip
),
1312 if (!qdev_realize(DEVICE(&chip8
->homer
), NULL
, errp
)) {
1315 /* Homer Xscom region */
1316 pnv_xscom_add_subregion(chip
, PNV_XSCOM_PBA_BASE
, &chip8
->homer
.pba_regs
);
1318 /* Homer mmio region */
1319 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip
),
1320 &chip8
->homer
.regs
);
1322 /* PHB controllers */
1323 for (i
= 0; i
< chip8
->num_phbs
; i
++) {
1324 PnvPHB
*phb
= chip8
->phbs
[i
];
1326 object_property_set_int(OBJECT(phb
), "index", i
, &error_fatal
);
1327 object_property_set_int(OBJECT(phb
), "chip-id", chip
->chip_id
,
1329 object_property_set_link(OBJECT(phb
), "chip", OBJECT(chip
),
1331 if (!sysbus_realize(SYS_BUS_DEVICE(phb
), errp
)) {
1337 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip
*chip
, uint64_t addr
)
1339 addr
&= (PNV_XSCOM_SIZE
- 1);
1340 return ((addr
>> 4) & ~0xfull
) | ((addr
>> 3) & 0xf);
1343 static void pnv_chip_power8e_class_init(ObjectClass
*klass
, void *data
)
1345 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1346 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
1348 k
->chip_cfam_id
= 0x221ef04980000000ull
; /* P8 Murano DD2.1 */
1349 k
->cores_mask
= POWER8E_CORE_MASK
;
1351 k
->core_pir
= pnv_chip_core_pir_p8
;
1352 k
->intc_create
= pnv_chip_power8_intc_create
;
1353 k
->intc_reset
= pnv_chip_power8_intc_reset
;
1354 k
->intc_destroy
= pnv_chip_power8_intc_destroy
;
1355 k
->intc_print_info
= pnv_chip_power8_intc_print_info
;
1356 k
->isa_create
= pnv_chip_power8_isa_create
;
1357 k
->dt_populate
= pnv_chip_power8_dt_populate
;
1358 k
->pic_print_info
= pnv_chip_power8_pic_print_info
;
1359 k
->xscom_core_base
= pnv_chip_power8_xscom_core_base
;
1360 k
->xscom_pcba
= pnv_chip_power8_xscom_pcba
;
1361 dc
->desc
= "PowerNV Chip POWER8E";
1363 device_class_set_parent_realize(dc
, pnv_chip_power8_realize
,
1364 &k
->parent_realize
);
1367 static void pnv_chip_power8_class_init(ObjectClass
*klass
, void *data
)
1369 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1370 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
1372 k
->chip_cfam_id
= 0x220ea04980000000ull
; /* P8 Venice DD2.0 */
1373 k
->cores_mask
= POWER8_CORE_MASK
;
1375 k
->core_pir
= pnv_chip_core_pir_p8
;
1376 k
->intc_create
= pnv_chip_power8_intc_create
;
1377 k
->intc_reset
= pnv_chip_power8_intc_reset
;
1378 k
->intc_destroy
= pnv_chip_power8_intc_destroy
;
1379 k
->intc_print_info
= pnv_chip_power8_intc_print_info
;
1380 k
->isa_create
= pnv_chip_power8_isa_create
;
1381 k
->dt_populate
= pnv_chip_power8_dt_populate
;
1382 k
->pic_print_info
= pnv_chip_power8_pic_print_info
;
1383 k
->xscom_core_base
= pnv_chip_power8_xscom_core_base
;
1384 k
->xscom_pcba
= pnv_chip_power8_xscom_pcba
;
1385 dc
->desc
= "PowerNV Chip POWER8";
1387 device_class_set_parent_realize(dc
, pnv_chip_power8_realize
,
1388 &k
->parent_realize
);
1391 static void pnv_chip_power8nvl_class_init(ObjectClass
*klass
, void *data
)
1393 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1394 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
1396 k
->chip_cfam_id
= 0x120d304980000000ull
; /* P8 Naples DD1.0 */
1397 k
->cores_mask
= POWER8_CORE_MASK
;
1399 k
->core_pir
= pnv_chip_core_pir_p8
;
1400 k
->intc_create
= pnv_chip_power8_intc_create
;
1401 k
->intc_reset
= pnv_chip_power8_intc_reset
;
1402 k
->intc_destroy
= pnv_chip_power8_intc_destroy
;
1403 k
->intc_print_info
= pnv_chip_power8_intc_print_info
;
1404 k
->isa_create
= pnv_chip_power8nvl_isa_create
;
1405 k
->dt_populate
= pnv_chip_power8_dt_populate
;
1406 k
->pic_print_info
= pnv_chip_power8_pic_print_info
;
1407 k
->xscom_core_base
= pnv_chip_power8_xscom_core_base
;
1408 k
->xscom_pcba
= pnv_chip_power8_xscom_pcba
;
1409 dc
->desc
= "PowerNV Chip POWER8NVL";
1411 device_class_set_parent_realize(dc
, pnv_chip_power8_realize
,
1412 &k
->parent_realize
);
1415 static void pnv_chip_power9_instance_init(Object
*obj
)
1417 PnvChip
*chip
= PNV_CHIP(obj
);
1418 Pnv9Chip
*chip9
= PNV9_CHIP(obj
);
1419 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(obj
);
1422 object_initialize_child(obj
, "xive", &chip9
->xive
, TYPE_PNV_XIVE
);
1423 object_property_add_alias(obj
, "xive-fabric", OBJECT(&chip9
->xive
),
1426 object_initialize_child(obj
, "psi", &chip9
->psi
, TYPE_PNV9_PSI
);
1428 object_initialize_child(obj
, "lpc", &chip9
->lpc
, TYPE_PNV9_LPC
);
1430 object_initialize_child(obj
, "chiptod", &chip9
->chiptod
, TYPE_PNV9_CHIPTOD
);
1432 object_initialize_child(obj
, "occ", &chip9
->occ
, TYPE_PNV9_OCC
);
1434 object_initialize_child(obj
, "sbe", &chip9
->sbe
, TYPE_PNV9_SBE
);
1436 object_initialize_child(obj
, "homer", &chip9
->homer
, TYPE_PNV9_HOMER
);
1438 /* Number of PECs is the chip default */
1439 chip
->num_pecs
= pcc
->num_pecs
;
1441 for (i
= 0; i
< chip
->num_pecs
; i
++) {
1442 object_initialize_child(obj
, "pec[*]", &chip9
->pecs
[i
],
1446 for (i
= 0; i
< pcc
->i2c_num_engines
; i
++) {
1447 object_initialize_child(obj
, "i2c[*]", &chip9
->i2c
[i
], TYPE_PNV_I2C
);
1451 static void pnv_chip_quad_realize_one(PnvChip
*chip
, PnvQuad
*eq
,
1456 int core_id
= CPU_CORE(pnv_core
)->core_id
;
1458 snprintf(eq_name
, sizeof(eq_name
), "eq[%d]", core_id
);
1459 object_initialize_child_with_props(OBJECT(chip
), eq_name
, eq
,
1461 &error_fatal
, NULL
);
1463 object_property_set_int(OBJECT(eq
), "quad-id", core_id
, &error_fatal
);
1464 qdev_realize(DEVICE(eq
), NULL
, &error_fatal
);
1467 static void pnv_chip_quad_realize(Pnv9Chip
*chip9
, Error
**errp
)
1469 PnvChip
*chip
= PNV_CHIP(chip9
);
1472 chip9
->nr_quads
= DIV_ROUND_UP(chip
->nr_cores
, 4);
1473 chip9
->quads
= g_new0(PnvQuad
, chip9
->nr_quads
);
1475 for (i
= 0; i
< chip9
->nr_quads
; i
++) {
1476 PnvQuad
*eq
= &chip9
->quads
[i
];
1478 pnv_chip_quad_realize_one(chip
, eq
, chip
->cores
[i
* 4],
1479 PNV_QUAD_TYPE_NAME("power9"));
1481 pnv_xscom_add_subregion(chip
, PNV9_XSCOM_EQ_BASE(eq
->quad_id
),
1486 static void pnv_chip_power9_pec_realize(PnvChip
*chip
, Error
**errp
)
1488 Pnv9Chip
*chip9
= PNV9_CHIP(chip
);
1491 for (i
= 0; i
< chip
->num_pecs
; i
++) {
1492 PnvPhb4PecState
*pec
= &chip9
->pecs
[i
];
1493 PnvPhb4PecClass
*pecc
= PNV_PHB4_PEC_GET_CLASS(pec
);
1494 uint32_t pec_nest_base
;
1495 uint32_t pec_pci_base
;
1497 object_property_set_int(OBJECT(pec
), "index", i
, &error_fatal
);
1498 object_property_set_int(OBJECT(pec
), "chip-id", chip
->chip_id
,
1500 object_property_set_link(OBJECT(pec
), "chip", OBJECT(chip
),
1502 if (!qdev_realize(DEVICE(pec
), NULL
, errp
)) {
1506 pec_nest_base
= pecc
->xscom_nest_base(pec
);
1507 pec_pci_base
= pecc
->xscom_pci_base(pec
);
1509 pnv_xscom_add_subregion(chip
, pec_nest_base
, &pec
->nest_regs_mr
);
1510 pnv_xscom_add_subregion(chip
, pec_pci_base
, &pec
->pci_regs_mr
);
1514 static void pnv_chip_power9_realize(DeviceState
*dev
, Error
**errp
)
1516 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(dev
);
1517 Pnv9Chip
*chip9
= PNV9_CHIP(dev
);
1518 PnvChip
*chip
= PNV_CHIP(dev
);
1519 Pnv9Psi
*psi9
= &chip9
->psi
;
1520 Error
*local_err
= NULL
;
1523 /* XSCOM bridge is first */
1524 pnv_xscom_init(chip
, PNV9_XSCOM_SIZE
, PNV9_XSCOM_BASE(chip
));
1526 pcc
->parent_realize(dev
, &local_err
);
1528 error_propagate(errp
, local_err
);
1532 pnv_chip_quad_realize(chip9
, &local_err
);
1534 error_propagate(errp
, local_err
);
1538 /* XIVE interrupt controller (POWER9) */
1539 object_property_set_int(OBJECT(&chip9
->xive
), "ic-bar",
1540 PNV9_XIVE_IC_BASE(chip
), &error_fatal
);
1541 object_property_set_int(OBJECT(&chip9
->xive
), "vc-bar",
1542 PNV9_XIVE_VC_BASE(chip
), &error_fatal
);
1543 object_property_set_int(OBJECT(&chip9
->xive
), "pc-bar",
1544 PNV9_XIVE_PC_BASE(chip
), &error_fatal
);
1545 object_property_set_int(OBJECT(&chip9
->xive
), "tm-bar",
1546 PNV9_XIVE_TM_BASE(chip
), &error_fatal
);
1547 object_property_set_link(OBJECT(&chip9
->xive
), "chip", OBJECT(chip
),
1549 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9
->xive
), errp
)) {
1552 pnv_xscom_add_subregion(chip
, PNV9_XSCOM_XIVE_BASE
,
1553 &chip9
->xive
.xscom_regs
);
1555 /* Processor Service Interface (PSI) Host Bridge */
1556 object_property_set_int(OBJECT(&chip9
->psi
), "bar", PNV9_PSIHB_BASE(chip
),
1558 /* This is the only device with 4k ESB pages */
1559 object_property_set_int(OBJECT(&chip9
->psi
), "shift", XIVE_ESB_4K
,
1561 if (!qdev_realize(DEVICE(&chip9
->psi
), NULL
, errp
)) {
1564 pnv_xscom_add_subregion(chip
, PNV9_XSCOM_PSIHB_BASE
,
1565 &PNV_PSI(psi9
)->xscom_regs
);
1568 if (!qdev_realize(DEVICE(&chip9
->lpc
), NULL
, errp
)) {
1571 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip
),
1572 &chip9
->lpc
.xscom_regs
);
1574 chip
->fw_mr
= &chip9
->lpc
.isa_fw
;
1575 chip
->dt_isa_nodename
= g_strdup_printf("/lpcm-opb@%" PRIx64
"/lpc@0",
1576 (uint64_t) PNV9_LPCM_BASE(chip
));
1579 object_property_set_bool(OBJECT(&chip9
->chiptod
), "primary",
1580 chip
->chip_id
== 0, &error_abort
);
1581 object_property_set_bool(OBJECT(&chip9
->chiptod
), "secondary",
1582 chip
->chip_id
== 1, &error_abort
);
1583 object_property_set_link(OBJECT(&chip9
->chiptod
), "chip", OBJECT(chip
),
1585 if (!qdev_realize(DEVICE(&chip9
->chiptod
), NULL
, errp
)) {
1588 pnv_xscom_add_subregion(chip
, PNV9_XSCOM_CHIPTOD_BASE
,
1589 &chip9
->chiptod
.xscom_regs
);
1591 /* Create the simplified OCC model */
1592 if (!qdev_realize(DEVICE(&chip9
->occ
), NULL
, errp
)) {
1595 pnv_xscom_add_subregion(chip
, PNV9_XSCOM_OCC_BASE
, &chip9
->occ
.xscom_regs
);
1596 qdev_connect_gpio_out(DEVICE(&chip9
->occ
), 0, qdev_get_gpio_in(
1597 DEVICE(&chip9
->psi
), PSIHB9_IRQ_OCC
));
1599 /* OCC SRAM model */
1600 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip
),
1601 &chip9
->occ
.sram_regs
);
1604 if (!qdev_realize(DEVICE(&chip9
->sbe
), NULL
, errp
)) {
1607 pnv_xscom_add_subregion(chip
, PNV9_XSCOM_SBE_CTRL_BASE
,
1608 &chip9
->sbe
.xscom_ctrl_regs
);
1609 pnv_xscom_add_subregion(chip
, PNV9_XSCOM_SBE_MBOX_BASE
,
1610 &chip9
->sbe
.xscom_mbox_regs
);
1611 qdev_connect_gpio_out(DEVICE(&chip9
->sbe
), 0, qdev_get_gpio_in(
1612 DEVICE(&chip9
->psi
), PSIHB9_IRQ_PSU
));
1615 object_property_set_link(OBJECT(&chip9
->homer
), "chip", OBJECT(chip
),
1617 if (!qdev_realize(DEVICE(&chip9
->homer
), NULL
, errp
)) {
1620 /* Homer Xscom region */
1621 pnv_xscom_add_subregion(chip
, PNV9_XSCOM_PBA_BASE
, &chip9
->homer
.pba_regs
);
1623 /* Homer mmio region */
1624 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip
),
1625 &chip9
->homer
.regs
);
1628 pnv_chip_power9_pec_realize(chip
, &local_err
);
1630 error_propagate(errp
, local_err
);
1637 for (i
= 0; i
< pcc
->i2c_num_engines
; i
++) {
1638 Object
*obj
= OBJECT(&chip9
->i2c
[i
]);
1640 object_property_set_int(obj
, "engine", i
+ 1, &error_fatal
);
1641 object_property_set_int(obj
, "num-busses",
1642 pcc
->i2c_ports_per_engine
[i
],
1644 object_property_set_link(obj
, "chip", OBJECT(chip
), &error_abort
);
1645 if (!qdev_realize(DEVICE(obj
), NULL
, errp
)) {
1648 pnv_xscom_add_subregion(chip
, PNV9_XSCOM_I2CM_BASE
+
1649 (chip9
->i2c
[i
].engine
- 1) *
1650 PNV9_XSCOM_I2CM_SIZE
,
1651 &chip9
->i2c
[i
].xscom_regs
);
1652 qdev_connect_gpio_out(DEVICE(&chip9
->i2c
[i
]), 0,
1653 qdev_get_gpio_in(DEVICE(&chip9
->psi
),
1654 PSIHB9_IRQ_SBE_I2C
));
1658 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip
*chip
, uint64_t addr
)
1660 addr
&= (PNV9_XSCOM_SIZE
- 1);
1664 static void pnv_chip_power9_class_init(ObjectClass
*klass
, void *data
)
1666 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1667 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
1668 static const int i2c_ports_per_engine
[PNV9_CHIP_MAX_I2C
] = {2, 13, 2, 2};
1670 k
->chip_cfam_id
= 0x220d104900008000ull
; /* P9 Nimbus DD2.0 */
1671 k
->cores_mask
= POWER9_CORE_MASK
;
1672 k
->core_pir
= pnv_chip_core_pir_p9
;
1673 k
->intc_create
= pnv_chip_power9_intc_create
;
1674 k
->intc_reset
= pnv_chip_power9_intc_reset
;
1675 k
->intc_destroy
= pnv_chip_power9_intc_destroy
;
1676 k
->intc_print_info
= pnv_chip_power9_intc_print_info
;
1677 k
->isa_create
= pnv_chip_power9_isa_create
;
1678 k
->dt_populate
= pnv_chip_power9_dt_populate
;
1679 k
->pic_print_info
= pnv_chip_power9_pic_print_info
;
1680 k
->xscom_core_base
= pnv_chip_power9_xscom_core_base
;
1681 k
->xscom_pcba
= pnv_chip_power9_xscom_pcba
;
1682 dc
->desc
= "PowerNV Chip POWER9";
1683 k
->num_pecs
= PNV9_CHIP_MAX_PEC
;
1684 k
->i2c_num_engines
= PNV9_CHIP_MAX_I2C
;
1685 k
->i2c_ports_per_engine
= i2c_ports_per_engine
;
1687 device_class_set_parent_realize(dc
, pnv_chip_power9_realize
,
1688 &k
->parent_realize
);
1691 static void pnv_chip_power10_instance_init(Object
*obj
)
1693 PnvChip
*chip
= PNV_CHIP(obj
);
1694 Pnv10Chip
*chip10
= PNV10_CHIP(obj
);
1695 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(obj
);
1698 object_initialize_child(obj
, "xive", &chip10
->xive
, TYPE_PNV_XIVE2
);
1699 object_property_add_alias(obj
, "xive-fabric", OBJECT(&chip10
->xive
),
1701 object_initialize_child(obj
, "psi", &chip10
->psi
, TYPE_PNV10_PSI
);
1702 object_initialize_child(obj
, "lpc", &chip10
->lpc
, TYPE_PNV10_LPC
);
1703 object_initialize_child(obj
, "chiptod", &chip10
->chiptod
,
1704 TYPE_PNV10_CHIPTOD
);
1705 object_initialize_child(obj
, "occ", &chip10
->occ
, TYPE_PNV10_OCC
);
1706 object_initialize_child(obj
, "sbe", &chip10
->sbe
, TYPE_PNV10_SBE
);
1707 object_initialize_child(obj
, "homer", &chip10
->homer
, TYPE_PNV10_HOMER
);
1708 object_initialize_child(obj
, "n1-chiplet", &chip10
->n1_chiplet
,
1709 TYPE_PNV_N1_CHIPLET
);
1711 chip
->num_pecs
= pcc
->num_pecs
;
1713 for (i
= 0; i
< chip
->num_pecs
; i
++) {
1714 object_initialize_child(obj
, "pec[*]", &chip10
->pecs
[i
],
1718 for (i
= 0; i
< pcc
->i2c_num_engines
; i
++) {
1719 object_initialize_child(obj
, "i2c[*]", &chip10
->i2c
[i
], TYPE_PNV_I2C
);
1723 static void pnv_chip_power10_quad_realize(Pnv10Chip
*chip10
, Error
**errp
)
1725 PnvChip
*chip
= PNV_CHIP(chip10
);
1728 chip10
->nr_quads
= DIV_ROUND_UP(chip
->nr_cores
, 4);
1729 chip10
->quads
= g_new0(PnvQuad
, chip10
->nr_quads
);
1731 for (i
= 0; i
< chip10
->nr_quads
; i
++) {
1732 PnvQuad
*eq
= &chip10
->quads
[i
];
1734 pnv_chip_quad_realize_one(chip
, eq
, chip
->cores
[i
* 4],
1735 PNV_QUAD_TYPE_NAME("power10"));
1737 pnv_xscom_add_subregion(chip
, PNV10_XSCOM_EQ_BASE(eq
->quad_id
),
1740 pnv_xscom_add_subregion(chip
, PNV10_XSCOM_QME_BASE(eq
->quad_id
),
1741 &eq
->xscom_qme_regs
);
1745 static void pnv_chip_power10_phb_realize(PnvChip
*chip
, Error
**errp
)
1747 Pnv10Chip
*chip10
= PNV10_CHIP(chip
);
1750 for (i
= 0; i
< chip
->num_pecs
; i
++) {
1751 PnvPhb4PecState
*pec
= &chip10
->pecs
[i
];
1752 PnvPhb4PecClass
*pecc
= PNV_PHB4_PEC_GET_CLASS(pec
);
1753 uint32_t pec_nest_base
;
1754 uint32_t pec_pci_base
;
1756 object_property_set_int(OBJECT(pec
), "index", i
, &error_fatal
);
1757 object_property_set_int(OBJECT(pec
), "chip-id", chip
->chip_id
,
1759 object_property_set_link(OBJECT(pec
), "chip", OBJECT(chip
),
1761 if (!qdev_realize(DEVICE(pec
), NULL
, errp
)) {
1765 pec_nest_base
= pecc
->xscom_nest_base(pec
);
1766 pec_pci_base
= pecc
->xscom_pci_base(pec
);
1768 pnv_xscom_add_subregion(chip
, pec_nest_base
, &pec
->nest_regs_mr
);
1769 pnv_xscom_add_subregion(chip
, pec_pci_base
, &pec
->pci_regs_mr
);
1773 static void pnv_chip_power10_realize(DeviceState
*dev
, Error
**errp
)
1775 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(dev
);
1776 PnvChip
*chip
= PNV_CHIP(dev
);
1777 Pnv10Chip
*chip10
= PNV10_CHIP(dev
);
1778 Error
*local_err
= NULL
;
1781 /* XSCOM bridge is first */
1782 pnv_xscom_init(chip
, PNV10_XSCOM_SIZE
, PNV10_XSCOM_BASE(chip
));
1784 pcc
->parent_realize(dev
, &local_err
);
1786 error_propagate(errp
, local_err
);
1790 pnv_chip_power10_quad_realize(chip10
, &local_err
);
1792 error_propagate(errp
, local_err
);
1796 /* XIVE2 interrupt controller (POWER10) */
1797 object_property_set_int(OBJECT(&chip10
->xive
), "ic-bar",
1798 PNV10_XIVE2_IC_BASE(chip
), &error_fatal
);
1799 object_property_set_int(OBJECT(&chip10
->xive
), "esb-bar",
1800 PNV10_XIVE2_ESB_BASE(chip
), &error_fatal
);
1801 object_property_set_int(OBJECT(&chip10
->xive
), "end-bar",
1802 PNV10_XIVE2_END_BASE(chip
), &error_fatal
);
1803 object_property_set_int(OBJECT(&chip10
->xive
), "nvpg-bar",
1804 PNV10_XIVE2_NVPG_BASE(chip
), &error_fatal
);
1805 object_property_set_int(OBJECT(&chip10
->xive
), "nvc-bar",
1806 PNV10_XIVE2_NVC_BASE(chip
), &error_fatal
);
1807 object_property_set_int(OBJECT(&chip10
->xive
), "tm-bar",
1808 PNV10_XIVE2_TM_BASE(chip
), &error_fatal
);
1809 object_property_set_link(OBJECT(&chip10
->xive
), "chip", OBJECT(chip
),
1811 if (!sysbus_realize(SYS_BUS_DEVICE(&chip10
->xive
), errp
)) {
1814 pnv_xscom_add_subregion(chip
, PNV10_XSCOM_XIVE2_BASE
,
1815 &chip10
->xive
.xscom_regs
);
1817 /* Processor Service Interface (PSI) Host Bridge */
1818 object_property_set_int(OBJECT(&chip10
->psi
), "bar",
1819 PNV10_PSIHB_BASE(chip
), &error_fatal
);
1820 /* PSI can now be configured to use 64k ESB pages on POWER10 */
1821 object_property_set_int(OBJECT(&chip10
->psi
), "shift", XIVE_ESB_64K
,
1823 if (!qdev_realize(DEVICE(&chip10
->psi
), NULL
, errp
)) {
1826 pnv_xscom_add_subregion(chip
, PNV10_XSCOM_PSIHB_BASE
,
1827 &PNV_PSI(&chip10
->psi
)->xscom_regs
);
1830 if (!qdev_realize(DEVICE(&chip10
->lpc
), NULL
, errp
)) {
1833 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip
),
1834 &chip10
->lpc
.xscom_regs
);
1836 chip
->fw_mr
= &chip10
->lpc
.isa_fw
;
1837 chip
->dt_isa_nodename
= g_strdup_printf("/lpcm-opb@%" PRIx64
"/lpc@0",
1838 (uint64_t) PNV10_LPCM_BASE(chip
));
1841 object_property_set_bool(OBJECT(&chip10
->chiptod
), "primary",
1842 chip
->chip_id
== 0, &error_abort
);
1843 object_property_set_bool(OBJECT(&chip10
->chiptod
), "secondary",
1844 chip
->chip_id
== 1, &error_abort
);
1845 object_property_set_link(OBJECT(&chip10
->chiptod
), "chip", OBJECT(chip
),
1847 if (!qdev_realize(DEVICE(&chip10
->chiptod
), NULL
, errp
)) {
1850 pnv_xscom_add_subregion(chip
, PNV10_XSCOM_CHIPTOD_BASE
,
1851 &chip10
->chiptod
.xscom_regs
);
1853 /* Create the simplified OCC model */
1854 if (!qdev_realize(DEVICE(&chip10
->occ
), NULL
, errp
)) {
1857 pnv_xscom_add_subregion(chip
, PNV10_XSCOM_OCC_BASE
,
1858 &chip10
->occ
.xscom_regs
);
1859 qdev_connect_gpio_out(DEVICE(&chip10
->occ
), 0, qdev_get_gpio_in(
1860 DEVICE(&chip10
->psi
), PSIHB9_IRQ_OCC
));
1862 /* OCC SRAM model */
1863 memory_region_add_subregion(get_system_memory(),
1864 PNV10_OCC_SENSOR_BASE(chip
),
1865 &chip10
->occ
.sram_regs
);
1868 if (!qdev_realize(DEVICE(&chip10
->sbe
), NULL
, errp
)) {
1871 pnv_xscom_add_subregion(chip
, PNV10_XSCOM_SBE_CTRL_BASE
,
1872 &chip10
->sbe
.xscom_ctrl_regs
);
1873 pnv_xscom_add_subregion(chip
, PNV10_XSCOM_SBE_MBOX_BASE
,
1874 &chip10
->sbe
.xscom_mbox_regs
);
1875 qdev_connect_gpio_out(DEVICE(&chip10
->sbe
), 0, qdev_get_gpio_in(
1876 DEVICE(&chip10
->psi
), PSIHB9_IRQ_PSU
));
1879 object_property_set_link(OBJECT(&chip10
->homer
), "chip", OBJECT(chip
),
1881 if (!qdev_realize(DEVICE(&chip10
->homer
), NULL
, errp
)) {
1884 /* Homer Xscom region */
1885 pnv_xscom_add_subregion(chip
, PNV10_XSCOM_PBA_BASE
,
1886 &chip10
->homer
.pba_regs
);
1888 /* Homer mmio region */
1889 memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(chip
),
1890 &chip10
->homer
.regs
);
1893 if (!qdev_realize(DEVICE(&chip10
->n1_chiplet
), NULL
, errp
)) {
1896 pnv_xscom_add_subregion(chip
, PNV10_XSCOM_N1_CHIPLET_CTRL_REGS_BASE
,
1897 &chip10
->n1_chiplet
.nest_pervasive
.xscom_ctrl_regs_mr
);
1899 pnv_xscom_add_subregion(chip
, PNV10_XSCOM_N1_PB_SCOM_EQ_BASE
,
1900 &chip10
->n1_chiplet
.xscom_pb_eq_mr
);
1902 pnv_xscom_add_subregion(chip
, PNV10_XSCOM_N1_PB_SCOM_ES_BASE
,
1903 &chip10
->n1_chiplet
.xscom_pb_es_mr
);
1906 pnv_chip_power10_phb_realize(chip
, &local_err
);
1908 error_propagate(errp
, local_err
);
1916 for (i
= 0; i
< pcc
->i2c_num_engines
; i
++) {
1917 Object
*obj
= OBJECT(&chip10
->i2c
[i
]);
1919 object_property_set_int(obj
, "engine", i
+ 1, &error_fatal
);
1920 object_property_set_int(obj
, "num-busses",
1921 pcc
->i2c_ports_per_engine
[i
],
1923 object_property_set_link(obj
, "chip", OBJECT(chip
), &error_abort
);
1924 if (!qdev_realize(DEVICE(obj
), NULL
, errp
)) {
1927 pnv_xscom_add_subregion(chip
, PNV10_XSCOM_I2CM_BASE
+
1928 (chip10
->i2c
[i
].engine
- 1) *
1929 PNV10_XSCOM_I2CM_SIZE
,
1930 &chip10
->i2c
[i
].xscom_regs
);
1931 qdev_connect_gpio_out(DEVICE(&chip10
->i2c
[i
]), 0,
1932 qdev_get_gpio_in(DEVICE(&chip10
->psi
),
1933 PSIHB9_IRQ_SBE_I2C
));
1938 static void pnv_rainier_i2c_init(PnvMachineState
*pnv
)
1941 for (i
= 0; i
< pnv
->num_chips
; i
++) {
1942 Pnv10Chip
*chip10
= PNV10_CHIP(pnv
->chips
[i
]);
1945 * Add a PCA9552 I2C device for PCIe hotplug control
1946 * to engine 2, bus 1, address 0x63
1948 I2CSlave
*dev
= i2c_slave_create_simple(chip10
->i2c
[2].busses
[1],
1952 * Connect PCA9552 GPIO pins 0-4 (SLOTx_EN) outputs to GPIO pins 5-9
1953 * (SLOTx_PG) inputs in order to fake the pgood state of PCIe slots
1954 * after hypervisor code sets a SLOTx_EN pin high.
1956 qdev_connect_gpio_out(DEVICE(dev
), 0, qdev_get_gpio_in(DEVICE(dev
), 5));
1957 qdev_connect_gpio_out(DEVICE(dev
), 1, qdev_get_gpio_in(DEVICE(dev
), 6));
1958 qdev_connect_gpio_out(DEVICE(dev
), 2, qdev_get_gpio_in(DEVICE(dev
), 7));
1959 qdev_connect_gpio_out(DEVICE(dev
), 3, qdev_get_gpio_in(DEVICE(dev
), 8));
1960 qdev_connect_gpio_out(DEVICE(dev
), 4, qdev_get_gpio_in(DEVICE(dev
), 9));
1963 * Add a PCA9554 I2C device for cable card presence detection
1964 * to engine 2, bus 1, address 0x25
1966 i2c_slave_create_simple(chip10
->i2c
[2].busses
[1], "pca9554", 0x25);
1970 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip
*chip
, uint64_t addr
)
1972 addr
&= (PNV10_XSCOM_SIZE
- 1);
1976 static void pnv_chip_power10_class_init(ObjectClass
*klass
, void *data
)
1978 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1979 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
1980 static const int i2c_ports_per_engine
[PNV10_CHIP_MAX_I2C
] = {14, 14, 2, 16};
1982 k
->chip_cfam_id
= 0x120da04900008000ull
; /* P10 DD1.0 (with NX) */
1983 k
->cores_mask
= POWER10_CORE_MASK
;
1984 k
->core_pir
= pnv_chip_core_pir_p10
;
1985 k
->intc_create
= pnv_chip_power10_intc_create
;
1986 k
->intc_reset
= pnv_chip_power10_intc_reset
;
1987 k
->intc_destroy
= pnv_chip_power10_intc_destroy
;
1988 k
->intc_print_info
= pnv_chip_power10_intc_print_info
;
1989 k
->isa_create
= pnv_chip_power10_isa_create
;
1990 k
->dt_populate
= pnv_chip_power10_dt_populate
;
1991 k
->pic_print_info
= pnv_chip_power10_pic_print_info
;
1992 k
->xscom_core_base
= pnv_chip_power10_xscom_core_base
;
1993 k
->xscom_pcba
= pnv_chip_power10_xscom_pcba
;
1994 dc
->desc
= "PowerNV Chip POWER10";
1995 k
->num_pecs
= PNV10_CHIP_MAX_PEC
;
1996 k
->i2c_num_engines
= PNV10_CHIP_MAX_I2C
;
1997 k
->i2c_ports_per_engine
= i2c_ports_per_engine
;
1999 device_class_set_parent_realize(dc
, pnv_chip_power10_realize
,
2000 &k
->parent_realize
);
2003 static void pnv_chip_core_sanitize(PnvChip
*chip
, Error
**errp
)
2005 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(chip
);
2009 * No custom mask for this chip, let's use the default one from *
2012 if (!chip
->cores_mask
) {
2013 chip
->cores_mask
= pcc
->cores_mask
;
2016 /* filter alien core ids ! some are reserved */
2017 if ((chip
->cores_mask
& pcc
->cores_mask
) != chip
->cores_mask
) {
2018 error_setg(errp
, "warning: invalid core mask for chip Ox%"PRIx64
" !",
2022 chip
->cores_mask
&= pcc
->cores_mask
;
2024 /* now that we have a sane layout, let check the number of cores */
2025 cores_max
= ctpop64(chip
->cores_mask
);
2026 if (chip
->nr_cores
> cores_max
) {
2027 error_setg(errp
, "warning: too many cores for chip ! Limit is %d",
2033 static void pnv_chip_core_realize(PnvChip
*chip
, Error
**errp
)
2035 Error
*error
= NULL
;
2036 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(chip
);
2037 const char *typename
= pnv_chip_core_typename(chip
);
2039 PnvMachineState
*pnv
= PNV_MACHINE(qdev_get_machine());
2041 if (!object_class_by_name(typename
)) {
2042 error_setg(errp
, "Unable to find PowerNV CPU Core '%s'", typename
);
2047 pnv_chip_core_sanitize(chip
, &error
);
2049 error_propagate(errp
, error
);
2053 chip
->cores
= g_new0(PnvCore
*, chip
->nr_cores
);
2055 for (i
= 0, core_hwid
= 0; (core_hwid
< sizeof(chip
->cores_mask
) * 8)
2056 && (i
< chip
->nr_cores
); core_hwid
++) {
2059 uint64_t xscom_core_base
;
2061 if (!(chip
->cores_mask
& (1ull << core_hwid
))) {
2065 pnv_core
= PNV_CORE(object_new(typename
));
2067 snprintf(core_name
, sizeof(core_name
), "core[%d]", core_hwid
);
2068 object_property_add_child(OBJECT(chip
), core_name
, OBJECT(pnv_core
));
2069 chip
->cores
[i
] = pnv_core
;
2070 object_property_set_int(OBJECT(pnv_core
), "nr-threads",
2071 chip
->nr_threads
, &error_fatal
);
2072 object_property_set_int(OBJECT(pnv_core
), CPU_CORE_PROP_CORE_ID
,
2073 core_hwid
, &error_fatal
);
2074 object_property_set_int(OBJECT(pnv_core
), "pir",
2075 pcc
->core_pir(chip
, core_hwid
), &error_fatal
);
2076 object_property_set_int(OBJECT(pnv_core
), "hrmor", pnv
->fw_load_addr
,
2078 object_property_set_link(OBJECT(pnv_core
), "chip", OBJECT(chip
),
2080 qdev_realize(DEVICE(pnv_core
), NULL
, &error_fatal
);
2082 /* Each core has an XSCOM MMIO region */
2083 xscom_core_base
= pcc
->xscom_core_base(chip
, core_hwid
);
2085 pnv_xscom_add_subregion(chip
, xscom_core_base
,
2086 &pnv_core
->xscom_regs
);
2091 static void pnv_chip_realize(DeviceState
*dev
, Error
**errp
)
2093 PnvChip
*chip
= PNV_CHIP(dev
);
2094 Error
*error
= NULL
;
2097 pnv_chip_core_realize(chip
, &error
);
2099 error_propagate(errp
, error
);
2104 static Property pnv_chip_properties
[] = {
2105 DEFINE_PROP_UINT32("chip-id", PnvChip
, chip_id
, 0),
2106 DEFINE_PROP_UINT64("ram-start", PnvChip
, ram_start
, 0),
2107 DEFINE_PROP_UINT64("ram-size", PnvChip
, ram_size
, 0),
2108 DEFINE_PROP_UINT32("nr-cores", PnvChip
, nr_cores
, 1),
2109 DEFINE_PROP_UINT64("cores-mask", PnvChip
, cores_mask
, 0x0),
2110 DEFINE_PROP_UINT32("nr-threads", PnvChip
, nr_threads
, 1),
2111 DEFINE_PROP_END_OF_LIST(),
2114 static void pnv_chip_class_init(ObjectClass
*klass
, void *data
)
2116 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2118 set_bit(DEVICE_CATEGORY_CPU
, dc
->categories
);
2119 dc
->realize
= pnv_chip_realize
;
2120 device_class_set_props(dc
, pnv_chip_properties
);
2121 dc
->desc
= "PowerNV Chip";
2124 PnvCore
*pnv_chip_find_core(PnvChip
*chip
, uint32_t core_id
)
2128 for (i
= 0; i
< chip
->nr_cores
; i
++) {
2129 PnvCore
*pc
= chip
->cores
[i
];
2130 CPUCore
*cc
= CPU_CORE(pc
);
2132 if (cc
->core_id
== core_id
) {
2139 PowerPCCPU
*pnv_chip_find_cpu(PnvChip
*chip
, uint32_t pir
)
2143 for (i
= 0; i
< chip
->nr_cores
; i
++) {
2144 PnvCore
*pc
= chip
->cores
[i
];
2145 CPUCore
*cc
= CPU_CORE(pc
);
2147 for (j
= 0; j
< cc
->nr_threads
; j
++) {
2148 if (ppc_cpu_pir(pc
->threads
[j
]) == pir
) {
2149 return pc
->threads
[j
];
2156 static ICSState
*pnv_ics_get(XICSFabric
*xi
, int irq
)
2158 PnvMachineState
*pnv
= PNV_MACHINE(xi
);
2161 for (i
= 0; i
< pnv
->num_chips
; i
++) {
2162 Pnv8Chip
*chip8
= PNV8_CHIP(pnv
->chips
[i
]);
2164 if (ics_valid_irq(&chip8
->psi
.ics
, irq
)) {
2165 return &chip8
->psi
.ics
;
2168 for (j
= 0; j
< chip8
->num_phbs
; j
++) {
2169 PnvPHB
*phb
= chip8
->phbs
[j
];
2170 PnvPHB3
*phb3
= PNV_PHB3(phb
->backend
);
2172 if (ics_valid_irq(&phb3
->lsis
, irq
)) {
2176 if (ics_valid_irq(ICS(&phb3
->msis
), irq
)) {
2177 return ICS(&phb3
->msis
);
2184 PnvChip
*pnv_get_chip(PnvMachineState
*pnv
, uint32_t chip_id
)
2188 for (i
= 0; i
< pnv
->num_chips
; i
++) {
2189 PnvChip
*chip
= pnv
->chips
[i
];
2190 if (chip
->chip_id
== chip_id
) {
2197 static void pnv_ics_resend(XICSFabric
*xi
)
2199 PnvMachineState
*pnv
= PNV_MACHINE(xi
);
2202 for (i
= 0; i
< pnv
->num_chips
; i
++) {
2203 Pnv8Chip
*chip8
= PNV8_CHIP(pnv
->chips
[i
]);
2205 ics_resend(&chip8
->psi
.ics
);
2207 for (j
= 0; j
< chip8
->num_phbs
; j
++) {
2208 PnvPHB
*phb
= chip8
->phbs
[j
];
2209 PnvPHB3
*phb3
= PNV_PHB3(phb
->backend
);
2211 ics_resend(&phb3
->lsis
);
2212 ics_resend(ICS(&phb3
->msis
));
2217 static ICPState
*pnv_icp_get(XICSFabric
*xi
, int pir
)
2219 PowerPCCPU
*cpu
= ppc_get_vcpu_by_pir(pir
);
2221 return cpu
? ICP(pnv_cpu_state(cpu
)->intc
) : NULL
;
2224 static void pnv_pic_print_info(InterruptStatsProvider
*obj
,
2227 PnvMachineState
*pnv
= PNV_MACHINE(obj
);
2232 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
2234 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */
2235 PNV_CHIP_GET_CLASS(pnv
->chips
[0])->intc_print_info(pnv
->chips
[0], cpu
,
2239 for (i
= 0; i
< pnv
->num_chips
; i
++) {
2240 PNV_CHIP_GET_CLASS(pnv
->chips
[i
])->pic_print_info(pnv
->chips
[i
], mon
);
2244 static int pnv_match_nvt(XiveFabric
*xfb
, uint8_t format
,
2245 uint8_t nvt_blk
, uint32_t nvt_idx
,
2246 bool cam_ignore
, uint8_t priority
,
2247 uint32_t logic_serv
,
2248 XiveTCTXMatch
*match
)
2250 PnvMachineState
*pnv
= PNV_MACHINE(xfb
);
2251 int total_count
= 0;
2254 for (i
= 0; i
< pnv
->num_chips
; i
++) {
2255 Pnv9Chip
*chip9
= PNV9_CHIP(pnv
->chips
[i
]);
2256 XivePresenter
*xptr
= XIVE_PRESENTER(&chip9
->xive
);
2257 XivePresenterClass
*xpc
= XIVE_PRESENTER_GET_CLASS(xptr
);
2260 count
= xpc
->match_nvt(xptr
, format
, nvt_blk
, nvt_idx
, cam_ignore
,
2261 priority
, logic_serv
, match
);
2267 total_count
+= count
;
2273 static int pnv10_xive_match_nvt(XiveFabric
*xfb
, uint8_t format
,
2274 uint8_t nvt_blk
, uint32_t nvt_idx
,
2275 bool cam_ignore
, uint8_t priority
,
2276 uint32_t logic_serv
,
2277 XiveTCTXMatch
*match
)
2279 PnvMachineState
*pnv
= PNV_MACHINE(xfb
);
2280 int total_count
= 0;
2283 for (i
= 0; i
< pnv
->num_chips
; i
++) {
2284 Pnv10Chip
*chip10
= PNV10_CHIP(pnv
->chips
[i
]);
2285 XivePresenter
*xptr
= XIVE_PRESENTER(&chip10
->xive
);
2286 XivePresenterClass
*xpc
= XIVE_PRESENTER_GET_CLASS(xptr
);
2289 count
= xpc
->match_nvt(xptr
, format
, nvt_blk
, nvt_idx
, cam_ignore
,
2290 priority
, logic_serv
, match
);
2296 total_count
+= count
;
2302 static void pnv_machine_power8_class_init(ObjectClass
*oc
, void *data
)
2304 MachineClass
*mc
= MACHINE_CLASS(oc
);
2305 XICSFabricClass
*xic
= XICS_FABRIC_CLASS(oc
);
2306 PnvMachineClass
*pmc
= PNV_MACHINE_CLASS(oc
);
2307 static const char compat
[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv";
2309 static GlobalProperty phb_compat
[] = {
2310 { TYPE_PNV_PHB
, "version", "3" },
2311 { TYPE_PNV_PHB_ROOT_PORT
, "version", "3" },
2314 mc
->desc
= "IBM PowerNV (Non-Virtualized) POWER8";
2315 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power8_v2.0");
2316 compat_props_add(mc
->compat_props
, phb_compat
, G_N_ELEMENTS(phb_compat
));
2318 xic
->icp_get
= pnv_icp_get
;
2319 xic
->ics_get
= pnv_ics_get
;
2320 xic
->ics_resend
= pnv_ics_resend
;
2322 pmc
->compat
= compat
;
2323 pmc
->compat_size
= sizeof(compat
);
2325 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_PNV_PHB
);
2328 static void pnv_machine_power9_class_init(ObjectClass
*oc
, void *data
)
2330 MachineClass
*mc
= MACHINE_CLASS(oc
);
2331 XiveFabricClass
*xfc
= XIVE_FABRIC_CLASS(oc
);
2332 PnvMachineClass
*pmc
= PNV_MACHINE_CLASS(oc
);
2333 static const char compat
[] = "qemu,powernv9\0ibm,powernv";
2335 static GlobalProperty phb_compat
[] = {
2336 { TYPE_PNV_PHB
, "version", "4" },
2337 { TYPE_PNV_PHB_ROOT_PORT
, "version", "4" },
2340 mc
->desc
= "IBM PowerNV (Non-Virtualized) POWER9";
2341 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power9_v2.2");
2342 compat_props_add(mc
->compat_props
, phb_compat
, G_N_ELEMENTS(phb_compat
));
2344 xfc
->match_nvt
= pnv_match_nvt
;
2346 pmc
->compat
= compat
;
2347 pmc
->compat_size
= sizeof(compat
);
2348 pmc
->dt_power_mgt
= pnv_dt_power_mgt
;
2350 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_PNV_PHB
);
2353 static void pnv_machine_p10_common_class_init(ObjectClass
*oc
, void *data
)
2355 MachineClass
*mc
= MACHINE_CLASS(oc
);
2356 PnvMachineClass
*pmc
= PNV_MACHINE_CLASS(oc
);
2357 XiveFabricClass
*xfc
= XIVE_FABRIC_CLASS(oc
);
2358 static const char compat
[] = "qemu,powernv10\0ibm,powernv";
2360 static GlobalProperty phb_compat
[] = {
2361 { TYPE_PNV_PHB
, "version", "5" },
2362 { TYPE_PNV_PHB_ROOT_PORT
, "version", "5" },
2365 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power10_v2.0");
2366 compat_props_add(mc
->compat_props
, phb_compat
, G_N_ELEMENTS(phb_compat
));
2368 mc
->alias
= "powernv";
2370 pmc
->compat
= compat
;
2371 pmc
->compat_size
= sizeof(compat
);
2372 pmc
->dt_power_mgt
= pnv_dt_power_mgt
;
2374 xfc
->match_nvt
= pnv10_xive_match_nvt
;
2376 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_PNV_PHB
);
2379 static void pnv_machine_power10_class_init(ObjectClass
*oc
, void *data
)
2381 MachineClass
*mc
= MACHINE_CLASS(oc
);
2383 pnv_machine_p10_common_class_init(oc
, data
);
2384 mc
->desc
= "IBM PowerNV (Non-Virtualized) POWER10";
2387 static void pnv_machine_p10_rainier_class_init(ObjectClass
*oc
, void *data
)
2389 MachineClass
*mc
= MACHINE_CLASS(oc
);
2390 PnvMachineClass
*pmc
= PNV_MACHINE_CLASS(oc
);
2392 pnv_machine_p10_common_class_init(oc
, data
);
2393 mc
->desc
= "IBM PowerNV (Non-Virtualized) POWER10 Rainier";
2394 pmc
->i2c_init
= pnv_rainier_i2c_init
;
2397 static bool pnv_machine_get_hb(Object
*obj
, Error
**errp
)
2399 PnvMachineState
*pnv
= PNV_MACHINE(obj
);
2401 return !!pnv
->fw_load_addr
;
2404 static void pnv_machine_set_hb(Object
*obj
, bool value
, Error
**errp
)
2406 PnvMachineState
*pnv
= PNV_MACHINE(obj
);
2409 pnv
->fw_load_addr
= 0x8000000;
2413 static void pnv_cpu_do_nmi_on_cpu(CPUState
*cs
, run_on_cpu_data arg
)
2415 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
2416 CPUPPCState
*env
= &cpu
->env
;
2418 cpu_synchronize_state(cs
);
2419 ppc_cpu_do_system_reset(cs
);
2420 if (env
->spr
[SPR_SRR1
] & SRR1_WAKESTATE
) {
2422 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the
2423 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100
2426 if (!(env
->spr
[SPR_SRR1
] & SRR1_WAKERESET
)) {
2427 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason");
2428 env
->spr
[SPR_SRR1
] |= SRR1_WAKERESET
;
2432 * For non-powersave system resets, SRR1[42:45] are defined to be
2433 * implementation-dependent. The POWER9 User Manual specifies that
2434 * an external (SCOM driven, which may come from a BMC nmi command or
2435 * another CPU requesting a NMI IPI) system reset exception should be
2436 * 0b0010 (PPC_BIT(44)).
2438 env
->spr
[SPR_SRR1
] |= SRR1_WAKESCOM
;
2442 static void pnv_nmi(NMIState
*n
, int cpu_index
, Error
**errp
)
2447 async_run_on_cpu(cs
, pnv_cpu_do_nmi_on_cpu
, RUN_ON_CPU_NULL
);
2451 static void pnv_machine_class_init(ObjectClass
*oc
, void *data
)
2453 MachineClass
*mc
= MACHINE_CLASS(oc
);
2454 InterruptStatsProviderClass
*ispc
= INTERRUPT_STATS_PROVIDER_CLASS(oc
);
2455 NMIClass
*nc
= NMI_CLASS(oc
);
2457 mc
->desc
= "IBM PowerNV (Non-Virtualized)";
2458 mc
->init
= pnv_init
;
2459 mc
->reset
= pnv_reset
;
2460 mc
->max_cpus
= MAX_CPUS
;
2461 /* Pnv provides a AHCI device for storage */
2462 mc
->block_default_type
= IF_IDE
;
2463 mc
->no_parallel
= 1;
2464 mc
->default_boot_order
= NULL
;
2466 * RAM defaults to less than 2048 for 32-bit hosts, and large
2467 * enough to fit the maximum initrd size at it's load address
2469 mc
->default_ram_size
= 1 * GiB
;
2470 mc
->default_ram_id
= "pnv.ram";
2471 ispc
->print_info
= pnv_pic_print_info
;
2472 nc
->nmi_monitor_handler
= pnv_nmi
;
2474 object_class_property_add_bool(oc
, "hb-mode",
2475 pnv_machine_get_hb
, pnv_machine_set_hb
);
2476 object_class_property_set_description(oc
, "hb-mode",
2477 "Use a hostboot like boot loader");
2480 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \
2483 .class_init = class_initfn, \
2484 .parent = TYPE_PNV8_CHIP, \
2487 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \
2490 .class_init = class_initfn, \
2491 .parent = TYPE_PNV9_CHIP, \
2494 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \
2497 .class_init = class_initfn, \
2498 .parent = TYPE_PNV10_CHIP, \
2501 static const TypeInfo types
[] = {
2503 .name
= MACHINE_TYPE_NAME("powernv10-rainier"),
2504 .parent
= MACHINE_TYPE_NAME("powernv10"),
2505 .class_init
= pnv_machine_p10_rainier_class_init
,
2508 .name
= MACHINE_TYPE_NAME("powernv10"),
2509 .parent
= TYPE_PNV_MACHINE
,
2510 .class_init
= pnv_machine_power10_class_init
,
2511 .interfaces
= (InterfaceInfo
[]) {
2512 { TYPE_XIVE_FABRIC
},
2517 .name
= MACHINE_TYPE_NAME("powernv9"),
2518 .parent
= TYPE_PNV_MACHINE
,
2519 .class_init
= pnv_machine_power9_class_init
,
2520 .interfaces
= (InterfaceInfo
[]) {
2521 { TYPE_XIVE_FABRIC
},
2526 .name
= MACHINE_TYPE_NAME("powernv8"),
2527 .parent
= TYPE_PNV_MACHINE
,
2528 .class_init
= pnv_machine_power8_class_init
,
2529 .interfaces
= (InterfaceInfo
[]) {
2530 { TYPE_XICS_FABRIC
},
2535 .name
= TYPE_PNV_MACHINE
,
2536 .parent
= TYPE_MACHINE
,
2538 .instance_size
= sizeof(PnvMachineState
),
2539 .class_init
= pnv_machine_class_init
,
2540 .class_size
= sizeof(PnvMachineClass
),
2541 .interfaces
= (InterfaceInfo
[]) {
2542 { TYPE_INTERRUPT_STATS_PROVIDER
},
2548 .name
= TYPE_PNV_CHIP
,
2549 .parent
= TYPE_SYS_BUS_DEVICE
,
2550 .class_init
= pnv_chip_class_init
,
2551 .instance_size
= sizeof(PnvChip
),
2552 .class_size
= sizeof(PnvChipClass
),
2557 * P10 chip and variants
2560 .name
= TYPE_PNV10_CHIP
,
2561 .parent
= TYPE_PNV_CHIP
,
2562 .instance_init
= pnv_chip_power10_instance_init
,
2563 .instance_size
= sizeof(Pnv10Chip
),
2565 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10
, pnv_chip_power10_class_init
),
2568 * P9 chip and variants
2571 .name
= TYPE_PNV9_CHIP
,
2572 .parent
= TYPE_PNV_CHIP
,
2573 .instance_init
= pnv_chip_power9_instance_init
,
2574 .instance_size
= sizeof(Pnv9Chip
),
2576 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9
, pnv_chip_power9_class_init
),
2579 * P8 chip and variants
2582 .name
= TYPE_PNV8_CHIP
,
2583 .parent
= TYPE_PNV_CHIP
,
2584 .instance_init
= pnv_chip_power8_instance_init
,
2585 .instance_size
= sizeof(Pnv8Chip
),
2587 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8
, pnv_chip_power8_class_init
),
2588 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E
, pnv_chip_power8e_class_init
),
2589 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL
,
2590 pnv_chip_power8nvl_class_init
),