target-i386/fpu_helper.c

   1 /*
   2  *  x86 FPU, MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4/PNI helpers
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <math.h>
  21 #include "cpu.h"
  22 #include "exec/helper-proto.h"
  23 #include "qemu/aes.h"
  24 #include "qemu/host-utils.h"
  25 #include "exec/cpu_ldst.h"
  26
  27 #define FPU_RC_MASK         0xc00
  28 #define FPU_RC_NEAR         0x000
  29 #define FPU_RC_DOWN         0x400
  30 #define FPU_RC_UP           0x800
  31 #define FPU_RC_CHOP         0xc00
  32
  33 #define MAXTAN 9223372036854775808.0
  34
  35 /* the following deal with x86 long double-precision numbers */
  36 #define MAXEXPD 0x7fff
  37 #define EXPBIAS 16383
  38 #define EXPD(fp)        (fp.l.upper & 0x7fff)
  39 #define SIGND(fp)       ((fp.l.upper) & 0x8000)
  40 #define MANTD(fp)       (fp.l.lower)
  41 #define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7fff)) | EXPBIAS
  42
  43 #define FPUS_IE (1 << 0)
  44 #define FPUS_DE (1 << 1)
  45 #define FPUS_ZE (1 << 2)
  46 #define FPUS_OE (1 << 3)
  47 #define FPUS_UE (1 << 4)
  48 #define FPUS_PE (1 << 5)
  49 #define FPUS_SF (1 << 6)
  50 #define FPUS_SE (1 << 7)
  51 #define FPUS_B  (1 << 15)
  52
  53 #define FPUC_EM 0x3f
  54
  55 #define floatx80_lg2 make_floatx80(0x3ffd, 0x9a209a84fbcff799LL)
  56 #define floatx80_l2e make_floatx80(0x3fff, 0xb8aa3b295c17f0bcLL)
  57 #define floatx80_l2t make_floatx80(0x4000, 0xd49a784bcd1b8afeLL)
  58
  59 static inline void fpush(CPUX86State *env)
  60 {
  61     env->fpstt = (env->fpstt - 1) & 7;
  62     env->fptags[env->fpstt] = 0; /* validate stack entry */
  63 }
  64
  65 static inline void fpop(CPUX86State *env)
  66 {
  67     env->fptags[env->fpstt] = 1; /* invalidate stack entry */
  68     env->fpstt = (env->fpstt + 1) & 7;
  69 }
  70
  71 static inline floatx80 helper_fldt(CPUX86State *env, target_ulong ptr)
  72 {
  73     CPU_LDoubleU temp;
  74
  75     temp.l.lower = cpu_ldq_data(env, ptr);
  76     temp.l.upper = cpu_lduw_data(env, ptr + 8);
  77     return temp.d;
  78 }
  79
  80 static inline void helper_fstt(CPUX86State *env, floatx80 f, target_ulong ptr)
  81 {
  82     CPU_LDoubleU temp;
  83
  84     temp.d = f;
  85     cpu_stq_data(env, ptr, temp.l.lower);
  86     cpu_stw_data(env, ptr + 8, temp.l.upper);
  87 }
  88
  89 /* x87 FPU helpers */
  90
  91 static inline double floatx80_to_double(CPUX86State *env, floatx80 a)
  92 {
  93     union {
  94         float64 f64;
  95         double d;
  96     } u;
  97
  98     u.f64 = floatx80_to_float64(a, &env->fp_status);
  99     return u.d;
 100 }
 101
 102 static inline floatx80 double_to_floatx80(CPUX86State *env, double a)
 103 {
 104     union {
 105         float64 f64;
 106         double d;
 107     } u;
 108
 109     u.d = a;
 110     return float64_to_floatx80(u.f64, &env->fp_status);
 111 }
 112
 113 static void fpu_set_exception(CPUX86State *env, int mask)
 114 {
 115     env->fpus |= mask;
 116     if (env->fpus & (~env->fpuc & FPUC_EM)) {
 117         env->fpus |= FPUS_SE | FPUS_B;
 118     }
 119 }
 120
 121 static inline floatx80 helper_fdiv(CPUX86State *env, floatx80 a, floatx80 b)
 122 {
 123     if (floatx80_is_zero(b)) {
 124         fpu_set_exception(env, FPUS_ZE);
 125     }
 126     return floatx80_div(a, b, &env->fp_status);
 127 }
 128
 129 static void fpu_raise_exception(CPUX86State *env)
 130 {
 131     if (env->cr[0] & CR0_NE_MASK) {
 132         raise_exception(env, EXCP10_COPR);
 133     }
 134 #if !defined(CONFIG_USER_ONLY)
 135     else {
 136         cpu_set_ferr(env);
 137     }
 138 #endif
 139 }
 140
 141 void helper_flds_FT0(CPUX86State *env, uint32_t val)
 142 {
 143     union {
 144         float32 f;
 145         uint32_t i;
 146     } u;
 147
 148     u.i = val;
 149     FT0 = float32_to_floatx80(u.f, &env->fp_status);
 150 }
 151
 152 void helper_fldl_FT0(CPUX86State *env, uint64_t val)
 153 {
 154     union {
 155         float64 f;
 156         uint64_t i;
 157     } u;
 158
 159     u.i = val;
 160     FT0 = float64_to_floatx80(u.f, &env->fp_status);
 161 }
 162
 163 void helper_fildl_FT0(CPUX86State *env, int32_t val)
 164 {
 165     FT0 = int32_to_floatx80(val, &env->fp_status);
 166 }
 167
 168 void helper_flds_ST0(CPUX86State *env, uint32_t val)
 169 {
 170     int new_fpstt;
 171     union {
 172         float32 f;
 173         uint32_t i;
 174     } u;
 175
 176     new_fpstt = (env->fpstt - 1) & 7;
 177     u.i = val;
 178     env->fpregs[new_fpstt].d = float32_to_floatx80(u.f, &env->fp_status);
 179     env->fpstt = new_fpstt;
 180     env->fptags[new_fpstt] = 0; /* validate stack entry */
 181 }
 182
 183 void helper_fldl_ST0(CPUX86State *env, uint64_t val)
 184 {
 185     int new_fpstt;
 186     union {
 187         float64 f;
 188         uint64_t i;
 189     } u;
 190
 191     new_fpstt = (env->fpstt - 1) & 7;
 192     u.i = val;
 193     env->fpregs[new_fpstt].d = float64_to_floatx80(u.f, &env->fp_status);
 194     env->fpstt = new_fpstt;
 195     env->fptags[new_fpstt] = 0; /* validate stack entry */
 196 }
 197
 198 void helper_fildl_ST0(CPUX86State *env, int32_t val)
 199 {
 200     int new_fpstt;
 201
 202     new_fpstt = (env->fpstt - 1) & 7;
 203     env->fpregs[new_fpstt].d = int32_to_floatx80(val, &env->fp_status);
 204     env->fpstt = new_fpstt;
 205     env->fptags[new_fpstt] = 0; /* validate stack entry */
 206 }
 207
 208 void helper_fildll_ST0(CPUX86State *env, int64_t val)
 209 {
 210     int new_fpstt;
 211
 212     new_fpstt = (env->fpstt - 1) & 7;
 213     env->fpregs[new_fpstt].d = int64_to_floatx80(val, &env->fp_status);
 214     env->fpstt = new_fpstt;
 215     env->fptags[new_fpstt] = 0; /* validate stack entry */
 216 }
 217
 218 uint32_t helper_fsts_ST0(CPUX86State *env)
 219 {
 220     union {
 221         float32 f;
 222         uint32_t i;
 223     } u;
 224
 225     u.f = floatx80_to_float32(ST0, &env->fp_status);
 226     return u.i;
 227 }
 228
 229 uint64_t helper_fstl_ST0(CPUX86State *env)
 230 {
 231     union {
 232         float64 f;
 233         uint64_t i;
 234     } u;
 235
 236     u.f = floatx80_to_float64(ST0, &env->fp_status);
 237     return u.i;
 238 }
 239
 240 int32_t helper_fist_ST0(CPUX86State *env)
 241 {
 242     int32_t val;
 243
 244     val = floatx80_to_int32(ST0, &env->fp_status);
 245     if (val != (int16_t)val) {
 246         val = -32768;
 247     }
 248     return val;
 249 }
 250
 251 int32_t helper_fistl_ST0(CPUX86State *env)
 252 {
 253     int32_t val;
 254
 255     val = floatx80_to_int32(ST0, &env->fp_status);
 256     return val;
 257 }
 258
 259 int64_t helper_fistll_ST0(CPUX86State *env)
 260 {
 261     int64_t val;
 262
 263     val = floatx80_to_int64(ST0, &env->fp_status);
 264     return val;
 265 }
 266
 267 int32_t helper_fistt_ST0(CPUX86State *env)
 268 {
 269     int32_t val;
 270
 271     val = floatx80_to_int32_round_to_zero(ST0, &env->fp_status);
 272     if (val != (int16_t)val) {
 273         val = -32768;
 274     }
 275     return val;
 276 }
 277
 278 int32_t helper_fisttl_ST0(CPUX86State *env)
 279 {
 280     int32_t val;
 281
 282     val = floatx80_to_int32_round_to_zero(ST0, &env->fp_status);
 283     return val;
 284 }
 285
 286 int64_t helper_fisttll_ST0(CPUX86State *env)
 287 {
 288     int64_t val;
 289
 290     val = floatx80_to_int64_round_to_zero(ST0, &env->fp_status);
 291     return val;
 292 }
 293
 294 void helper_fldt_ST0(CPUX86State *env, target_ulong ptr)
 295 {
 296     int new_fpstt;
 297
 298     new_fpstt = (env->fpstt - 1) & 7;
 299     env->fpregs[new_fpstt].d = helper_fldt(env, ptr);
 300     env->fpstt = new_fpstt;
 301     env->fptags[new_fpstt] = 0; /* validate stack entry */
 302 }
 303
 304 void helper_fstt_ST0(CPUX86State *env, target_ulong ptr)
 305 {
 306     helper_fstt(env, ST0, ptr);
 307 }
 308
 309 void helper_fpush(CPUX86State *env)
 310 {
 311     fpush(env);
 312 }
 313
 314 void helper_fpop(CPUX86State *env)
 315 {
 316     fpop(env);
 317 }
 318
 319 void helper_fdecstp(CPUX86State *env)
 320 {
 321     env->fpstt = (env->fpstt - 1) & 7;
 322     env->fpus &= ~0x4700;
 323 }
 324
 325 void helper_fincstp(CPUX86State *env)
 326 {
 327     env->fpstt = (env->fpstt + 1) & 7;
 328     env->fpus &= ~0x4700;
 329 }
 330
 331 /* FPU move */
 332
 333 void helper_ffree_STN(CPUX86State *env, int st_index)
 334 {
 335     env->fptags[(env->fpstt + st_index) & 7] = 1;
 336 }
 337
 338 void helper_fmov_ST0_FT0(CPUX86State *env)
 339 {
 340     ST0 = FT0;
 341 }
 342
 343 void helper_fmov_FT0_STN(CPUX86State *env, int st_index)
 344 {
 345     FT0 = ST(st_index);
 346 }
 347
 348 void helper_fmov_ST0_STN(CPUX86State *env, int st_index)
 349 {
 350     ST0 = ST(st_index);
 351 }
 352
 353 void helper_fmov_STN_ST0(CPUX86State *env, int st_index)
 354 {
 355     ST(st_index) = ST0;
 356 }
 357
 358 void helper_fxchg_ST0_STN(CPUX86State *env, int st_index)
 359 {
 360     floatx80 tmp;
 361
 362     tmp = ST(st_index);
 363     ST(st_index) = ST0;
 364     ST0 = tmp;
 365 }
 366
 367 /* FPU operations */
 368
 369 static const int fcom_ccval[4] = {0x0100, 0x4000, 0x0000, 0x4500};
 370
 371 void helper_fcom_ST0_FT0(CPUX86State *env)
 372 {
 373     int ret;
 374
 375     ret = floatx80_compare(ST0, FT0, &env->fp_status);
 376     env->fpus = (env->fpus & ~0x4500) | fcom_ccval[ret + 1];
 377 }
 378
 379 void helper_fucom_ST0_FT0(CPUX86State *env)
 380 {
 381     int ret;
 382
 383     ret = floatx80_compare_quiet(ST0, FT0, &env->fp_status);
 384     env->fpus = (env->fpus & ~0x4500) | fcom_ccval[ret + 1];
 385 }
 386
 387 static const int fcomi_ccval[4] = {CC_C, CC_Z, 0, CC_Z | CC_P | CC_C};
 388
 389 void helper_fcomi_ST0_FT0(CPUX86State *env)
 390 {
 391     int eflags;
 392     int ret;
 393
 394     ret = floatx80_compare(ST0, FT0, &env->fp_status);
 395     eflags = cpu_cc_compute_all(env, CC_OP);
 396     eflags = (eflags & ~(CC_Z | CC_P | CC_C)) | fcomi_ccval[ret + 1];
 397     CC_SRC = eflags;
 398 }
 399
 400 void helper_fucomi_ST0_FT0(CPUX86State *env)
 401 {
 402     int eflags;
 403     int ret;
 404
 405     ret = floatx80_compare_quiet(ST0, FT0, &env->fp_status);
 406     eflags = cpu_cc_compute_all(env, CC_OP);
 407     eflags = (eflags & ~(CC_Z | CC_P | CC_C)) | fcomi_ccval[ret + 1];
 408     CC_SRC = eflags;
 409 }
 410
 411 void helper_fadd_ST0_FT0(CPUX86State *env)
 412 {
 413     ST0 = floatx80_add(ST0, FT0, &env->fp_status);
 414 }
 415
 416 void helper_fmul_ST0_FT0(CPUX86State *env)
 417 {
 418     ST0 = floatx80_mul(ST0, FT0, &env->fp_status);
 419 }
 420
 421 void helper_fsub_ST0_FT0(CPUX86State *env)
 422 {
 423     ST0 = floatx80_sub(ST0, FT0, &env->fp_status);
 424 }
 425
 426 void helper_fsubr_ST0_FT0(CPUX86State *env)
 427 {
 428     ST0 = floatx80_sub(FT0, ST0, &env->fp_status);
 429 }
 430
 431 void helper_fdiv_ST0_FT0(CPUX86State *env)
 432 {
 433     ST0 = helper_fdiv(env, ST0, FT0);
 434 }
 435
 436 void helper_fdivr_ST0_FT0(CPUX86State *env)
 437 {
 438     ST0 = helper_fdiv(env, FT0, ST0);
 439 }
 440
 441 /* fp operations between STN and ST0 */
 442
 443 void helper_fadd_STN_ST0(CPUX86State *env, int st_index)
 444 {
 445     ST(st_index) = floatx80_add(ST(st_index), ST0, &env->fp_status);
 446 }
 447
 448 void helper_fmul_STN_ST0(CPUX86State *env, int st_index)
 449 {
 450     ST(st_index) = floatx80_mul(ST(st_index), ST0, &env->fp_status);
 451 }
 452
 453 void helper_fsub_STN_ST0(CPUX86State *env, int st_index)
 454 {
 455     ST(st_index) = floatx80_sub(ST(st_index), ST0, &env->fp_status);
 456 }
 457
 458 void helper_fsubr_STN_ST0(CPUX86State *env, int st_index)
 459 {
 460     ST(st_index) = floatx80_sub(ST0, ST(st_index), &env->fp_status);
 461 }
 462
 463 void helper_fdiv_STN_ST0(CPUX86State *env, int st_index)
 464 {
 465     floatx80 *p;
 466
 467     p = &ST(st_index);
 468     *p = helper_fdiv(env, *p, ST0);
 469 }
 470
 471 void helper_fdivr_STN_ST0(CPUX86State *env, int st_index)
 472 {
 473     floatx80 *p;
 474
 475     p = &ST(st_index);
 476     *p = helper_fdiv(env, ST0, *p);
 477 }
 478
 479 /* misc FPU operations */
 480 void helper_fchs_ST0(CPUX86State *env)
 481 {
 482     ST0 = floatx80_chs(ST0);
 483 }
 484
 485 void helper_fabs_ST0(CPUX86State *env)
 486 {
 487     ST0 = floatx80_abs(ST0);
 488 }
 489
 490 void helper_fld1_ST0(CPUX86State *env)
 491 {
 492     ST0 = floatx80_one;
 493 }
 494
 495 void helper_fldl2t_ST0(CPUX86State *env)
 496 {
 497     ST0 = floatx80_l2t;
 498 }
 499
 500 void helper_fldl2e_ST0(CPUX86State *env)
 501 {
 502     ST0 = floatx80_l2e;
 503 }
 504
 505 void helper_fldpi_ST0(CPUX86State *env)
 506 {
 507     ST0 = floatx80_pi;
 508 }
 509
 510 void helper_fldlg2_ST0(CPUX86State *env)
 511 {
 512     ST0 = floatx80_lg2;
 513 }
 514
 515 void helper_fldln2_ST0(CPUX86State *env)
 516 {
 517     ST0 = floatx80_ln2;
 518 }
 519
 520 void helper_fldz_ST0(CPUX86State *env)
 521 {
 522     ST0 = floatx80_zero;
 523 }
 524
 525 void helper_fldz_FT0(CPUX86State *env)
 526 {
 527     FT0 = floatx80_zero;
 528 }
 529
 530 uint32_t helper_fnstsw(CPUX86State *env)
 531 {
 532     return (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
 533 }
 534
 535 uint32_t helper_fnstcw(CPUX86State *env)
 536 {
 537     return env->fpuc;
 538 }
 539
 540 void update_fp_status(CPUX86State *env)
 541 {
 542     int rnd_type;
 543
 544     /* set rounding mode */
 545     switch (env->fpuc & FPU_RC_MASK) {
 546     default:
 547     case FPU_RC_NEAR:
 548         rnd_type = float_round_nearest_even;
 549         break;
 550     case FPU_RC_DOWN:
 551         rnd_type = float_round_down;
 552         break;
 553     case FPU_RC_UP:
 554         rnd_type = float_round_up;
 555         break;
 556     case FPU_RC_CHOP:
 557         rnd_type = float_round_to_zero;
 558         break;
 559     }
 560     set_float_rounding_mode(rnd_type, &env->fp_status);
 561     switch ((env->fpuc >> 8) & 3) {
 562     case 0:
 563         rnd_type = 32;
 564         break;
 565     case 2:
 566         rnd_type = 64;
 567         break;
 568     case 3:
 569     default:
 570         rnd_type = 80;
 571         break;
 572     }
 573     set_floatx80_rounding_precision(rnd_type, &env->fp_status);
 574 }
 575
 576 void helper_fldcw(CPUX86State *env, uint32_t val)
 577 {
 578     cpu_set_fpuc(env, val);
 579 }
 580
 581 void helper_fclex(CPUX86State *env)
 582 {
 583     env->fpus &= 0x7f00;
 584 }
 585
 586 void helper_fwait(CPUX86State *env)
 587 {
 588     if (env->fpus & FPUS_SE) {
 589         fpu_raise_exception(env);
 590     }
 591 }
 592
 593 void helper_fninit(CPUX86State *env)
 594 {
 595     env->fpus = 0;
 596     env->fpstt = 0;
 597     cpu_set_fpuc(env, 0x37f);
 598     env->fptags[0] = 1;
 599     env->fptags[1] = 1;
 600     env->fptags[2] = 1;
 601     env->fptags[3] = 1;
 602     env->fptags[4] = 1;
 603     env->fptags[5] = 1;
 604     env->fptags[6] = 1;
 605     env->fptags[7] = 1;
 606 }
 607
 608 /* BCD ops */
 609
 610 void helper_fbld_ST0(CPUX86State *env, target_ulong ptr)
 611 {
 612     floatx80 tmp;
 613     uint64_t val;
 614     unsigned int v;
 615     int i;
 616
 617     val = 0;
 618     for (i = 8; i >= 0; i--) {
 619         v = cpu_ldub_data(env, ptr + i);
 620         val = (val * 100) + ((v >> 4) * 10) + (v & 0xf);
 621     }
 622     tmp = int64_to_floatx80(val, &env->fp_status);
 623     if (cpu_ldub_data(env, ptr + 9) & 0x80) {
 624         floatx80_chs(tmp);
 625     }
 626     fpush(env);
 627     ST0 = tmp;
 628 }
 629
 630 void helper_fbst_ST0(CPUX86State *env, target_ulong ptr)
 631 {
 632     int v;
 633     target_ulong mem_ref, mem_end;
 634     int64_t val;
 635
 636     val = floatx80_to_int64(ST0, &env->fp_status);
 637     mem_ref = ptr;
 638     mem_end = mem_ref + 9;
 639     if (val < 0) {
 640         cpu_stb_data(env, mem_end, 0x80);
 641         val = -val;
 642     } else {
 643         cpu_stb_data(env, mem_end, 0x00);
 644     }
 645     while (mem_ref < mem_end) {
 646         if (val == 0) {
 647             break;
 648         }
 649         v = val % 100;
 650         val = val / 100;
 651         v = ((v / 10) << 4) | (v % 10);
 652         cpu_stb_data(env, mem_ref++, v);
 653     }
 654     while (mem_ref < mem_end) {
 655         cpu_stb_data(env, mem_ref++, 0);
 656     }
 657 }
 658
 659 void helper_f2xm1(CPUX86State *env)
 660 {
 661     double val = floatx80_to_double(env, ST0);
 662
 663     val = pow(2.0, val) - 1.0;
 664     ST0 = double_to_floatx80(env, val);
 665 }
 666
 667 void helper_fyl2x(CPUX86State *env)
 668 {
 669     double fptemp = floatx80_to_double(env, ST0);
 670
 671     if (fptemp > 0.0) {
 672         fptemp = log(fptemp) / log(2.0); /* log2(ST) */
 673         fptemp *= floatx80_to_double(env, ST1);
 674         ST1 = double_to_floatx80(env, fptemp);
 675         fpop(env);
 676     } else {
 677         env->fpus &= ~0x4700;
 678         env->fpus |= 0x400;
 679     }
 680 }
 681
 682 void helper_fptan(CPUX86State *env)
 683 {
 684     double fptemp = floatx80_to_double(env, ST0);
 685
 686     if ((fptemp > MAXTAN) || (fptemp < -MAXTAN)) {
 687         env->fpus |= 0x400;
 688     } else {
 689         fptemp = tan(fptemp);
 690         ST0 = double_to_floatx80(env, fptemp);
 691         fpush(env);
 692         ST0 = floatx80_one;
 693         env->fpus &= ~0x400; /* C2 <-- 0 */
 694         /* the above code is for |arg| < 2**52 only */
 695     }
 696 }
 697
 698 void helper_fpatan(CPUX86State *env)
 699 {
 700     double fptemp, fpsrcop;
 701
 702     fpsrcop = floatx80_to_double(env, ST1);
 703     fptemp = floatx80_to_double(env, ST0);
 704     ST1 = double_to_floatx80(env, atan2(fpsrcop, fptemp));
 705     fpop(env);
 706 }
 707
 708 void helper_fxtract(CPUX86State *env)
 709 {
 710     CPU_LDoubleU temp;
 711
 712     temp.d = ST0;
 713
 714     if (floatx80_is_zero(ST0)) {
 715         /* Easy way to generate -inf and raising division by 0 exception */
 716         ST0 = floatx80_div(floatx80_chs(floatx80_one), floatx80_zero,
 717                            &env->fp_status);
 718         fpush(env);
 719         ST0 = temp.d;
 720     } else {
 721         int expdif;
 722
 723         expdif = EXPD(temp) - EXPBIAS;
 724         /* DP exponent bias */
 725         ST0 = int32_to_floatx80(expdif, &env->fp_status);
 726         fpush(env);
 727         BIASEXPONENT(temp);
 728         ST0 = temp.d;
 729     }
 730 }
 731
 732 void helper_fprem1(CPUX86State *env)
 733 {
 734     double st0, st1, dblq, fpsrcop, fptemp;
 735     CPU_LDoubleU fpsrcop1, fptemp1;
 736     int expdif;
 737     signed long long int q;
 738
 739     st0 = floatx80_to_double(env, ST0);
 740     st1 = floatx80_to_double(env, ST1);
 741
 742     if (isinf(st0) || isnan(st0) || isnan(st1) || (st1 == 0.0)) {
 743         ST0 = double_to_floatx80(env, 0.0 / 0.0); /* NaN */
 744         env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
 745         return;
 746     }
 747
 748     fpsrcop = st0;
 749     fptemp = st1;
 750     fpsrcop1.d = ST0;
 751     fptemp1.d = ST1;
 752     expdif = EXPD(fpsrcop1) - EXPD(fptemp1);
 753
 754     if (expdif < 0) {
 755         /* optimisation? taken from the AMD docs */
 756         env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
 757         /* ST0 is unchanged */
 758         return;
 759     }
 760
 761     if (expdif < 53) {
 762         dblq = fpsrcop / fptemp;
 763         /* round dblq towards nearest integer */
 764         dblq = rint(dblq);
 765         st0 = fpsrcop - fptemp * dblq;
 766
 767         /* convert dblq to q by truncating towards zero */
 768         if (dblq < 0.0) {
 769             q = (signed long long int)(-dblq);
 770         } else {
 771             q = (signed long long int)dblq;
 772         }
 773
 774         env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
 775         /* (C0,C3,C1) <-- (q2,q1,q0) */
 776         env->fpus |= (q & 0x4) << (8 - 2);  /* (C0) <-- q2 */
 777         env->fpus |= (q & 0x2) << (14 - 1); /* (C3) <-- q1 */
 778         env->fpus |= (q & 0x1) << (9 - 0);  /* (C1) <-- q0 */
 779     } else {
 780         env->fpus |= 0x400;  /* C2 <-- 1 */
 781         fptemp = pow(2.0, expdif - 50);
 782         fpsrcop = (st0 / st1) / fptemp;
 783         /* fpsrcop = integer obtained by chopping */
 784         fpsrcop = (fpsrcop < 0.0) ?
 785                   -(floor(fabs(fpsrcop))) : floor(fpsrcop);
 786         st0 -= (st1 * fpsrcop * fptemp);
 787     }
 788     ST0 = double_to_floatx80(env, st0);
 789 }
 790
 791 void helper_fprem(CPUX86State *env)
 792 {
 793     double st0, st1, dblq, fpsrcop, fptemp;
 794     CPU_LDoubleU fpsrcop1, fptemp1;
 795     int expdif;
 796     signed long long int q;
 797
 798     st0 = floatx80_to_double(env, ST0);
 799     st1 = floatx80_to_double(env, ST1);
 800
 801     if (isinf(st0) || isnan(st0) || isnan(st1) || (st1 == 0.0)) {
 802         ST0 = double_to_floatx80(env, 0.0 / 0.0); /* NaN */
 803         env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
 804         return;
 805     }
 806
 807     fpsrcop = st0;
 808     fptemp = st1;
 809     fpsrcop1.d = ST0;
 810     fptemp1.d = ST1;
 811     expdif = EXPD(fpsrcop1) - EXPD(fptemp1);
 812
 813     if (expdif < 0) {
 814         /* optimisation? taken from the AMD docs */
 815         env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
 816         /* ST0 is unchanged */
 817         return;
 818     }
 819
 820     if (expdif < 53) {
 821         dblq = fpsrcop / fptemp; /* ST0 / ST1 */
 822         /* round dblq towards zero */
 823         dblq = (dblq < 0.0) ? ceil(dblq) : floor(dblq);
 824         st0 = fpsrcop - fptemp * dblq; /* fpsrcop is ST0 */
 825
 826         /* convert dblq to q by truncating towards zero */
 827         if (dblq < 0.0) {
 828             q = (signed long long int)(-dblq);
 829         } else {
 830             q = (signed long long int)dblq;
 831         }
 832
 833         env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
 834         /* (C0,C3,C1) <-- (q2,q1,q0) */
 835         env->fpus |= (q & 0x4) << (8 - 2);  /* (C0) <-- q2 */
 836         env->fpus |= (q & 0x2) << (14 - 1); /* (C3) <-- q1 */
 837         env->fpus |= (q & 0x1) << (9 - 0);  /* (C1) <-- q0 */
 838     } else {
 839         int N = 32 + (expdif % 32); /* as per AMD docs */
 840
 841         env->fpus |= 0x400;  /* C2 <-- 1 */
 842         fptemp = pow(2.0, (double)(expdif - N));
 843         fpsrcop = (st0 / st1) / fptemp;
 844         /* fpsrcop = integer obtained by chopping */
 845         fpsrcop = (fpsrcop < 0.0) ?
 846                   -(floor(fabs(fpsrcop))) : floor(fpsrcop);
 847         st0 -= (st1 * fpsrcop * fptemp);
 848     }
 849     ST0 = double_to_floatx80(env, st0);
 850 }
 851
 852 void helper_fyl2xp1(CPUX86State *env)
 853 {
 854     double fptemp = floatx80_to_double(env, ST0);
 855
 856     if ((fptemp + 1.0) > 0.0) {
 857         fptemp = log(fptemp + 1.0) / log(2.0); /* log2(ST + 1.0) */
 858         fptemp *= floatx80_to_double(env, ST1);
 859         ST1 = double_to_floatx80(env, fptemp);
 860         fpop(env);
 861     } else {
 862         env->fpus &= ~0x4700;
 863         env->fpus |= 0x400;
 864     }
 865 }
 866
 867 void helper_fsqrt(CPUX86State *env)
 868 {
 869     if (floatx80_is_neg(ST0)) {
 870         env->fpus &= ~0x4700;  /* (C3,C2,C1,C0) <-- 0000 */
 871         env->fpus |= 0x400;
 872     }
 873     ST0 = floatx80_sqrt(ST0, &env->fp_status);
 874 }
 875
 876 void helper_fsincos(CPUX86State *env)
 877 {
 878     double fptemp = floatx80_to_double(env, ST0);
 879
 880     if ((fptemp > MAXTAN) || (fptemp < -MAXTAN)) {
 881         env->fpus |= 0x400;
 882     } else {
 883         ST0 = double_to_floatx80(env, sin(fptemp));
 884         fpush(env);
 885         ST0 = double_to_floatx80(env, cos(fptemp));
 886         env->fpus &= ~0x400;  /* C2 <-- 0 */
 887         /* the above code is for |arg| < 2**63 only */
 888     }
 889 }
 890
 891 void helper_frndint(CPUX86State *env)
 892 {
 893     ST0 = floatx80_round_to_int(ST0, &env->fp_status);
 894 }
 895
 896 void helper_fscale(CPUX86State *env)
 897 {
 898     if (floatx80_is_any_nan(ST1)) {
 899         ST0 = ST1;
 900     } else {
 901         int n = floatx80_to_int32_round_to_zero(ST1, &env->fp_status);
 902         ST0 = floatx80_scalbn(ST0, n, &env->fp_status);
 903     }
 904 }
 905
 906 void helper_fsin(CPUX86State *env)
 907 {
 908     double fptemp = floatx80_to_double(env, ST0);
 909
 910     if ((fptemp > MAXTAN) || (fptemp < -MAXTAN)) {
 911         env->fpus |= 0x400;
 912     } else {
 913         ST0 = double_to_floatx80(env, sin(fptemp));
 914         env->fpus &= ~0x400;  /* C2 <-- 0 */
 915         /* the above code is for |arg| < 2**53 only */
 916     }
 917 }
 918
 919 void helper_fcos(CPUX86State *env)
 920 {
 921     double fptemp = floatx80_to_double(env, ST0);
 922
 923     if ((fptemp > MAXTAN) || (fptemp < -MAXTAN)) {
 924         env->fpus |= 0x400;
 925     } else {
 926         ST0 = double_to_floatx80(env, cos(fptemp));
 927         env->fpus &= ~0x400;  /* C2 <-- 0 */
 928         /* the above code is for |arg| < 2**63 only */
 929     }
 930 }
 931
 932 void helper_fxam_ST0(CPUX86State *env)
 933 {
 934     CPU_LDoubleU temp;
 935     int expdif;
 936
 937     temp.d = ST0;
 938
 939     env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
 940     if (SIGND(temp)) {
 941         env->fpus |= 0x200; /* C1 <-- 1 */
 942     }
 943
 944     /* XXX: test fptags too */
 945     expdif = EXPD(temp);
 946     if (expdif == MAXEXPD) {
 947         if (MANTD(temp) == 0x8000000000000000ULL) {
 948             env->fpus |= 0x500; /* Infinity */
 949         } else {
 950             env->fpus |= 0x100; /* NaN */
 951         }
 952     } else if (expdif == 0) {
 953         if (MANTD(temp) == 0) {
 954             env->fpus |=  0x4000; /* Zero */
 955         } else {
 956             env->fpus |= 0x4400; /* Denormal */
 957         }
 958     } else {
 959         env->fpus |= 0x400;
 960     }
 961 }
 962
 963 void helper_fstenv(CPUX86State *env, target_ulong ptr, int data32)
 964 {
 965     int fpus, fptag, exp, i;
 966     uint64_t mant;
 967     CPU_LDoubleU tmp;
 968
 969     fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
 970     fptag = 0;
 971     for (i = 7; i >= 0; i--) {
 972         fptag <<= 2;
 973         if (env->fptags[i]) {
 974             fptag |= 3;
 975         } else {
 976             tmp.d = env->fpregs[i].d;
 977             exp = EXPD(tmp);
 978             mant = MANTD(tmp);
 979             if (exp == 0 && mant == 0) {
 980                 /* zero */
 981                 fptag |= 1;
 982             } else if (exp == 0 || exp == MAXEXPD
 983                        || (mant & (1LL << 63)) == 0) {
 984                 /* NaNs, infinity, denormal */
 985                 fptag |= 2;
 986             }
 987         }
 988     }
 989     if (data32) {
 990         /* 32 bit */
 991         cpu_stl_data(env, ptr, env->fpuc);
 992         cpu_stl_data(env, ptr + 4, fpus);
 993         cpu_stl_data(env, ptr + 8, fptag);
 994         cpu_stl_data(env, ptr + 12, 0); /* fpip */
 995         cpu_stl_data(env, ptr + 16, 0); /* fpcs */
 996         cpu_stl_data(env, ptr + 20, 0); /* fpoo */
 997         cpu_stl_data(env, ptr + 24, 0); /* fpos */
 998     } else {
 999         /* 16 bit */
1000         cpu_stw_data(env, ptr, env->fpuc);
1001         cpu_stw_data(env, ptr + 2, fpus);
1002         cpu_stw_data(env, ptr + 4, fptag);
1003         cpu_stw_data(env, ptr + 6, 0);
1004         cpu_stw_data(env, ptr + 8, 0);
1005         cpu_stw_data(env, ptr + 10, 0);
1006         cpu_stw_data(env, ptr + 12, 0);
1007     }
1008 }
1009
1010 void helper_fldenv(CPUX86State *env, target_ulong ptr, int data32)
1011 {
1012     int i, fpus, fptag;
1013
1014     if (data32) {
1015         cpu_set_fpuc(env, cpu_lduw_data(env, ptr));
1016         fpus = cpu_lduw_data(env, ptr + 4);
1017         fptag = cpu_lduw_data(env, ptr + 8);
1018     } else {
1019         cpu_set_fpuc(env, cpu_lduw_data(env, ptr));
1020         fpus = cpu_lduw_data(env, ptr + 2);
1021         fptag = cpu_lduw_data(env, ptr + 4);
1022     }
1023     env->fpstt = (fpus >> 11) & 7;
1024     env->fpus = fpus & ~0x3800;
1025     for (i = 0; i < 8; i++) {
1026         env->fptags[i] = ((fptag & 3) == 3);
1027         fptag >>= 2;
1028     }
1029 }
1030
1031 void helper_fsave(CPUX86State *env, target_ulong ptr, int data32)
1032 {
1033     floatx80 tmp;
1034     int i;
1035
1036     helper_fstenv(env, ptr, data32);
1037
1038     ptr += (14 << data32);
1039     for (i = 0; i < 8; i++) {
1040         tmp = ST(i);
1041         helper_fstt(env, tmp, ptr);
1042         ptr += 10;
1043     }
1044
1045     /* fninit */
1046     env->fpus = 0;
1047     env->fpstt = 0;
1048     cpu_set_fpuc(env, 0x37f);
1049     env->fptags[0] = 1;
1050     env->fptags[1] = 1;
1051     env->fptags[2] = 1;
1052     env->fptags[3] = 1;
1053     env->fptags[4] = 1;
1054     env->fptags[5] = 1;
1055     env->fptags[6] = 1;
1056     env->fptags[7] = 1;
1057 }
1058
1059 void helper_frstor(CPUX86State *env, target_ulong ptr, int data32)
1060 {
1061     floatx80 tmp;
1062     int i;
1063
1064     helper_fldenv(env, ptr, data32);
1065     ptr += (14 << data32);
1066
1067     for (i = 0; i < 8; i++) {
1068         tmp = helper_fldt(env, ptr);
1069         ST(i) = tmp;
1070         ptr += 10;
1071     }
1072 }
1073
1074 #if defined(CONFIG_USER_ONLY)
1075 void cpu_x86_fsave(CPUX86State *env, target_ulong ptr, int data32)
1076 {
1077     helper_fsave(env, ptr, data32);
1078 }
1079
1080 void cpu_x86_frstor(CPUX86State *env, target_ulong ptr, int data32)
1081 {
1082     helper_frstor(env, ptr, data32);
1083 }
1084 #endif
1085
1086 void helper_fxsave(CPUX86State *env, target_ulong ptr, int data64)
1087 {
1088     int fpus, fptag, i, nb_xmm_regs;
1089     floatx80 tmp;
1090     target_ulong addr;
1091
1092     /* The operand must be 16 byte aligned */
1093     if (ptr & 0xf) {
1094         raise_exception(env, EXCP0D_GPF);
1095     }
1096
1097     fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
1098     fptag = 0;
1099     for (i = 0; i < 8; i++) {
1100         fptag |= (env->fptags[i] << i);
1101     }
1102     cpu_stw_data(env, ptr, env->fpuc);
1103     cpu_stw_data(env, ptr + 2, fpus);
1104     cpu_stw_data(env, ptr + 4, fptag ^ 0xff);
1105 #ifdef TARGET_X86_64
1106     if (data64) {
1107         cpu_stq_data(env, ptr + 0x08, 0); /* rip */
1108         cpu_stq_data(env, ptr + 0x10, 0); /* rdp */
1109     } else
1110 #endif
1111     {
1112         cpu_stl_data(env, ptr + 0x08, 0); /* eip */
1113         cpu_stl_data(env, ptr + 0x0c, 0); /* sel  */
1114         cpu_stl_data(env, ptr + 0x10, 0); /* dp */
1115         cpu_stl_data(env, ptr + 0x14, 0); /* sel  */
1116     }
1117
1118     addr = ptr + 0x20;
1119     for (i = 0; i < 8; i++) {
1120         tmp = ST(i);
1121         helper_fstt(env, tmp, addr);
1122         addr += 16;
1123     }
1124
1125     if (env->cr[4] & CR4_OSFXSR_MASK) {
1126         /* XXX: finish it */
1127         cpu_stl_data(env, ptr + 0x18, env->mxcsr); /* mxcsr */
1128         cpu_stl_data(env, ptr + 0x1c, 0x0000ffff); /* mxcsr_mask */
1129         if (env->hflags & HF_CS64_MASK) {
1130             nb_xmm_regs = 16;
1131         } else {
1132             nb_xmm_regs = 8;
1133         }
1134         addr = ptr + 0xa0;
1135         /* Fast FXSAVE leaves out the XMM registers */
1136         if (!(env->efer & MSR_EFER_FFXSR)
1137             || (env->hflags & HF_CPL_MASK)
1138             || !(env->hflags & HF_LMA_MASK)) {
1139             for (i = 0; i < nb_xmm_regs; i++) {
1140                 cpu_stq_data(env, addr, env->xmm_regs[i].XMM_Q(0));
1141                 cpu_stq_data(env, addr + 8, env->xmm_regs[i].XMM_Q(1));
1142                 addr += 16;
1143             }
1144         }
1145     }
1146 }
1147
1148 void helper_fxrstor(CPUX86State *env, target_ulong ptr, int data64)
1149 {
1150     int i, fpus, fptag, nb_xmm_regs;
1151     floatx80 tmp;
1152     target_ulong addr;
1153
1154     /* The operand must be 16 byte aligned */
1155     if (ptr & 0xf) {
1156         raise_exception(env, EXCP0D_GPF);
1157     }
1158
1159     cpu_set_fpuc(env, cpu_lduw_data(env, ptr));
1160     fpus = cpu_lduw_data(env, ptr + 2);
1161     fptag = cpu_lduw_data(env, ptr + 4);
1162     env->fpstt = (fpus >> 11) & 7;
1163     env->fpus = fpus & ~0x3800;
1164     fptag ^= 0xff;
1165     for (i = 0; i < 8; i++) {
1166         env->fptags[i] = ((fptag >> i) & 1);
1167     }
1168
1169     addr = ptr + 0x20;
1170     for (i = 0; i < 8; i++) {
1171         tmp = helper_fldt(env, addr);
1172         ST(i) = tmp;
1173         addr += 16;
1174     }
1175
1176     if (env->cr[4] & CR4_OSFXSR_MASK) {
1177         /* XXX: finish it */
1178         cpu_set_mxcsr(env, cpu_ldl_data(env, ptr + 0x18));
1179         /* cpu_ldl_data(env, ptr + 0x1c); */
1180         if (env->hflags & HF_CS64_MASK) {
1181             nb_xmm_regs = 16;
1182         } else {
1183             nb_xmm_regs = 8;
1184         }
1185         addr = ptr + 0xa0;
1186         /* Fast FXRESTORE leaves out the XMM registers */
1187         if (!(env->efer & MSR_EFER_FFXSR)
1188             || (env->hflags & HF_CPL_MASK)
1189             || !(env->hflags & HF_LMA_MASK)) {
1190             for (i = 0; i < nb_xmm_regs; i++) {
1191                 env->xmm_regs[i].XMM_Q(0) = cpu_ldq_data(env, addr);
1192                 env->xmm_regs[i].XMM_Q(1) = cpu_ldq_data(env, addr + 8);
1193                 addr += 16;
1194             }
1195         }
1196     }
1197 }
1198
1199 void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, floatx80 f)
1200 {
1201     CPU_LDoubleU temp;
1202
1203     temp.d = f;
1204     *pmant = temp.l.lower;
1205     *pexp = temp.l.upper;
1206 }
1207
1208 floatx80 cpu_set_fp80(uint64_t mant, uint16_t upper)
1209 {
1210     CPU_LDoubleU temp;
1211
1212     temp.l.upper = upper;
1213     temp.l.lower = mant;
1214     return temp.d;
1215 }
1216
1217 /* MMX/SSE */
1218 /* XXX: optimize by storing fptt and fptags in the static cpu state */
1219
1220 #define SSE_DAZ             0x0040
1221 #define SSE_RC_MASK         0x6000
1222 #define SSE_RC_NEAR         0x0000
1223 #define SSE_RC_DOWN         0x2000
1224 #define SSE_RC_UP           0x4000
1225 #define SSE_RC_CHOP         0x6000
1226 #define SSE_FZ              0x8000
1227
1228 void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr)
1229 {
1230     int rnd_type;
1231
1232     env->mxcsr = mxcsr;
1233
1234     /* set rounding mode */
1235     switch (mxcsr & SSE_RC_MASK) {
1236     default:
1237     case SSE_RC_NEAR:
1238         rnd_type = float_round_nearest_even;
1239         break;
1240     case SSE_RC_DOWN:
1241         rnd_type = float_round_down;
1242         break;
1243     case SSE_RC_UP:
1244         rnd_type = float_round_up;
1245         break;
1246     case SSE_RC_CHOP:
1247         rnd_type = float_round_to_zero;
1248         break;
1249     }
1250     set_float_rounding_mode(rnd_type, &env->sse_status);
1251
1252     /* set denormals are zero */
1253     set_flush_inputs_to_zero((mxcsr & SSE_DAZ) ? 1 : 0, &env->sse_status);
1254
1255     /* set flush to zero */
1256     set_flush_to_zero((mxcsr & SSE_FZ) ? 1 : 0, &env->fp_status);
1257 }
1258
1259 void cpu_set_fpuc(CPUX86State *env, uint16_t val)
1260 {
1261     env->fpuc = val;
1262     update_fp_status(env);
1263 }
1264
1265 void helper_ldmxcsr(CPUX86State *env, uint32_t val)
1266 {
1267     cpu_set_mxcsr(env, val);
1268 }
1269
1270 void helper_enter_mmx(CPUX86State *env)
1271 {
1272     env->fpstt = 0;
1273     *(uint32_t *)(env->fptags) = 0;
1274     *(uint32_t *)(env->fptags + 4) = 0;
1275 }
1276
1277 void helper_emms(CPUX86State *env)
1278 {
1279     /* set to empty state */
1280     *(uint32_t *)(env->fptags) = 0x01010101;
1281     *(uint32_t *)(env->fptags + 4) = 0x01010101;
1282 }
1283
1284 /* XXX: suppress */
1285 void helper_movq(CPUX86State *env, void *d, void *s)
1286 {
1287     *(uint64_t *)d = *(uint64_t *)s;
1288 }
1289
1290 #define SHIFT 0
1291 #include "ops_sse.h"
1292
1293 #define SHIFT 1
1294 #include "ops_sse.h"