2 * ARM Integrator CP System emulation.
4 * Copyright (c) 2005-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL
10 #include "qemu/osdep.h"
11 #include "qapi/error.h"
12 #include "qemu-common.h"
14 #include "hw/sysbus.h"
15 #include "hw/devices.h"
16 #include "hw/boards.h"
17 #include "hw/arm/arm.h"
18 #include "hw/misc/arm_integrator_debug.h"
20 #include "exec/address-spaces.h"
21 #include "sysemu/sysemu.h"
22 #include "qemu/error-report.h"
23 #include "hw/char/pl011.h"
25 #define TYPE_INTEGRATOR_CM "integrator_core"
26 #define INTEGRATOR_CM(obj) \
27 OBJECT_CHECK(IntegratorCMState, (obj), TYPE_INTEGRATOR_CM)
29 typedef struct IntegratorCMState
{
31 SysBusDevice parent_obj
;
45 uint32_t cm_refcnt_offset
;
51 static uint8_t integrator_spd
[128] = {
52 128, 8, 4, 11, 9, 1, 64, 0, 2, 0xa0, 0xa0, 0, 0, 8, 0, 1,
53 0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40
56 static const VMStateDescription vmstate_integratorcm
= {
57 .name
= "integratorcm",
59 .minimum_version_id
= 1,
60 .fields
= (VMStateField
[]) {
61 VMSTATE_UINT32(cm_osc
, IntegratorCMState
),
62 VMSTATE_UINT32(cm_ctrl
, IntegratorCMState
),
63 VMSTATE_UINT32(cm_lock
, IntegratorCMState
),
64 VMSTATE_UINT32(cm_auxosc
, IntegratorCMState
),
65 VMSTATE_UINT32(cm_sdram
, IntegratorCMState
),
66 VMSTATE_UINT32(cm_init
, IntegratorCMState
),
67 VMSTATE_UINT32(cm_flags
, IntegratorCMState
),
68 VMSTATE_UINT32(cm_nvflags
, IntegratorCMState
),
69 VMSTATE_UINT32(int_level
, IntegratorCMState
),
70 VMSTATE_UINT32(irq_enabled
, IntegratorCMState
),
71 VMSTATE_UINT32(fiq_enabled
, IntegratorCMState
),
76 static uint64_t integratorcm_read(void *opaque
, hwaddr offset
,
79 IntegratorCMState
*s
= opaque
;
80 if (offset
>= 0x100 && offset
< 0x200) {
84 return integrator_spd
[offset
>> 2];
86 switch (offset
>> 2) {
98 if (s
->cm_lock
== 0xa05f) {
103 case 6: /* CM_LMBUSCNT */
104 /* ??? High frequency timer. */
105 hw_error("integratorcm_read: CM_LMBUSCNT");
106 case 7: /* CM_AUXOSC */
108 case 8: /* CM_SDRAM */
110 case 9: /* CM_INIT */
112 case 10: /* CM_REFCNT */
113 /* This register, CM_REFCNT, provides a 32-bit count value.
114 * The count increments at the fixed reference clock frequency of 24MHz
115 * and can be used as a real-time counter.
117 return (uint32_t)muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
), 24,
118 1000) - s
->cm_refcnt_offset
;
119 case 12: /* CM_FLAGS */
121 case 14: /* CM_NVFLAGS */
122 return s
->cm_nvflags
;
123 case 16: /* CM_IRQ_STAT */
124 return s
->int_level
& s
->irq_enabled
;
125 case 17: /* CM_IRQ_RSTAT */
127 case 18: /* CM_IRQ_ENSET */
128 return s
->irq_enabled
;
129 case 20: /* CM_SOFT_INTSET */
130 return s
->int_level
& 1;
131 case 24: /* CM_FIQ_STAT */
132 return s
->int_level
& s
->fiq_enabled
;
133 case 25: /* CM_FIQ_RSTAT */
135 case 26: /* CM_FIQ_ENSET */
136 return s
->fiq_enabled
;
137 case 32: /* CM_VOLTAGE_CTL0 */
138 case 33: /* CM_VOLTAGE_CTL1 */
139 case 34: /* CM_VOLTAGE_CTL2 */
140 case 35: /* CM_VOLTAGE_CTL3 */
141 /* ??? Voltage control unimplemented. */
144 hw_error("integratorcm_read: Unimplemented offset 0x%x\n",
150 static void integratorcm_do_remap(IntegratorCMState
*s
)
152 /* Sync memory region state with CM_CTRL REMAP bit:
153 * bit 0 => flash at address 0; bit 1 => RAM
155 memory_region_set_enabled(&s
->flash
, !(s
->cm_ctrl
& 4));
158 static void integratorcm_set_ctrl(IntegratorCMState
*s
, uint32_t value
)
161 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
163 if ((s
->cm_ctrl
^ value
) & 1) {
164 /* (value & 1) != 0 means the green "MISC LED" is lit.
165 * We don't have any nice place to display LEDs. printf is a bad
166 * idea because Linux uses the LED as a heartbeat and the output
167 * will swamp anything else on the terminal.
170 /* Note that the RESET bit [3] always reads as zero */
171 s
->cm_ctrl
= (s
->cm_ctrl
& ~5) | (value
& 5);
172 integratorcm_do_remap(s
);
175 static void integratorcm_update(IntegratorCMState
*s
)
177 /* ??? The CPU irq/fiq is raised when either the core module or base PIC
179 if (s
->int_level
& (s
->irq_enabled
| s
->fiq_enabled
))
180 hw_error("Core module interrupt\n");
183 static void integratorcm_write(void *opaque
, hwaddr offset
,
184 uint64_t value
, unsigned size
)
186 IntegratorCMState
*s
= opaque
;
187 switch (offset
>> 2) {
189 if (s
->cm_lock
== 0xa05f)
192 case 3: /* CM_CTRL */
193 integratorcm_set_ctrl(s
, value
);
195 case 5: /* CM_LOCK */
196 s
->cm_lock
= value
& 0xffff;
198 case 7: /* CM_AUXOSC */
199 if (s
->cm_lock
== 0xa05f)
200 s
->cm_auxosc
= value
;
202 case 8: /* CM_SDRAM */
205 case 9: /* CM_INIT */
206 /* ??? This can change the memory bus frequency. */
209 case 12: /* CM_FLAGSS */
210 s
->cm_flags
|= value
;
212 case 13: /* CM_FLAGSC */
213 s
->cm_flags
&= ~value
;
215 case 14: /* CM_NVFLAGSS */
216 s
->cm_nvflags
|= value
;
218 case 15: /* CM_NVFLAGSS */
219 s
->cm_nvflags
&= ~value
;
221 case 18: /* CM_IRQ_ENSET */
222 s
->irq_enabled
|= value
;
223 integratorcm_update(s
);
225 case 19: /* CM_IRQ_ENCLR */
226 s
->irq_enabled
&= ~value
;
227 integratorcm_update(s
);
229 case 20: /* CM_SOFT_INTSET */
230 s
->int_level
|= (value
& 1);
231 integratorcm_update(s
);
233 case 21: /* CM_SOFT_INTCLR */
234 s
->int_level
&= ~(value
& 1);
235 integratorcm_update(s
);
237 case 26: /* CM_FIQ_ENSET */
238 s
->fiq_enabled
|= value
;
239 integratorcm_update(s
);
241 case 27: /* CM_FIQ_ENCLR */
242 s
->fiq_enabled
&= ~value
;
243 integratorcm_update(s
);
245 case 32: /* CM_VOLTAGE_CTL0 */
246 case 33: /* CM_VOLTAGE_CTL1 */
247 case 34: /* CM_VOLTAGE_CTL2 */
248 case 35: /* CM_VOLTAGE_CTL3 */
249 /* ??? Voltage control unimplemented. */
252 hw_error("integratorcm_write: Unimplemented offset 0x%x\n",
258 /* Integrator/CM control registers. */
260 static const MemoryRegionOps integratorcm_ops
= {
261 .read
= integratorcm_read
,
262 .write
= integratorcm_write
,
263 .endianness
= DEVICE_NATIVE_ENDIAN
,
266 static void integratorcm_init(Object
*obj
)
268 IntegratorCMState
*s
= INTEGRATOR_CM(obj
);
269 SysBusDevice
*dev
= SYS_BUS_DEVICE(obj
);
271 s
->cm_osc
= 0x01000048;
272 /* ??? What should the high bits of this value be? */
273 s
->cm_auxosc
= 0x0007feff;
274 s
->cm_sdram
= 0x00011122;
275 memcpy(integrator_spd
+ 73, "QEMU-MEMORY", 11);
276 s
->cm_init
= 0x00000112;
277 s
->cm_refcnt_offset
= muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
), 24,
279 memory_region_init_ram(&s
->flash
, obj
, "integrator.flash", 0x100000,
282 memory_region_init_io(&s
->iomem
, obj
, &integratorcm_ops
, s
,
283 "integratorcm", 0x00800000);
284 sysbus_init_mmio(dev
, &s
->iomem
);
286 integratorcm_do_remap(s
);
287 /* ??? Save/restore. */
290 static void integratorcm_realize(DeviceState
*d
, Error
**errp
)
292 IntegratorCMState
*s
= INTEGRATOR_CM(d
);
294 if (s
->memsz
>= 256) {
295 integrator_spd
[31] = 64;
297 } else if (s
->memsz
>= 128) {
298 integrator_spd
[31] = 32;
300 } else if (s
->memsz
>= 64) {
301 integrator_spd
[31] = 16;
303 } else if (s
->memsz
>= 32) {
304 integrator_spd
[31] = 4;
307 integrator_spd
[31] = 2;
311 /* Integrator/CP hardware emulation. */
312 /* Primary interrupt controller. */
314 #define TYPE_INTEGRATOR_PIC "integrator_pic"
315 #define INTEGRATOR_PIC(obj) \
316 OBJECT_CHECK(icp_pic_state, (obj), TYPE_INTEGRATOR_PIC)
318 typedef struct icp_pic_state
{
320 SysBusDevice parent_obj
;
325 uint32_t irq_enabled
;
326 uint32_t fiq_enabled
;
331 static const VMStateDescription vmstate_icp_pic
= {
334 .minimum_version_id
= 1,
335 .fields
= (VMStateField
[]) {
336 VMSTATE_UINT32(level
, icp_pic_state
),
337 VMSTATE_UINT32(irq_enabled
, icp_pic_state
),
338 VMSTATE_UINT32(fiq_enabled
, icp_pic_state
),
339 VMSTATE_END_OF_LIST()
343 static void icp_pic_update(icp_pic_state
*s
)
347 flags
= (s
->level
& s
->irq_enabled
);
348 qemu_set_irq(s
->parent_irq
, flags
!= 0);
349 flags
= (s
->level
& s
->fiq_enabled
);
350 qemu_set_irq(s
->parent_fiq
, flags
!= 0);
353 static void icp_pic_set_irq(void *opaque
, int irq
, int level
)
355 icp_pic_state
*s
= (icp_pic_state
*)opaque
;
357 s
->level
|= 1 << irq
;
359 s
->level
&= ~(1 << irq
);
363 static uint64_t icp_pic_read(void *opaque
, hwaddr offset
,
366 icp_pic_state
*s
= (icp_pic_state
*)opaque
;
368 switch (offset
>> 2) {
369 case 0: /* IRQ_STATUS */
370 return s
->level
& s
->irq_enabled
;
371 case 1: /* IRQ_RAWSTAT */
373 case 2: /* IRQ_ENABLESET */
374 return s
->irq_enabled
;
375 case 4: /* INT_SOFTSET */
377 case 8: /* FRQ_STATUS */
378 return s
->level
& s
->fiq_enabled
;
379 case 9: /* FRQ_RAWSTAT */
381 case 10: /* FRQ_ENABLESET */
382 return s
->fiq_enabled
;
383 case 3: /* IRQ_ENABLECLR */
384 case 5: /* INT_SOFTCLR */
385 case 11: /* FRQ_ENABLECLR */
387 printf ("icp_pic_read: Bad register offset 0x%x\n", (int)offset
);
392 static void icp_pic_write(void *opaque
, hwaddr offset
,
393 uint64_t value
, unsigned size
)
395 icp_pic_state
*s
= (icp_pic_state
*)opaque
;
397 switch (offset
>> 2) {
398 case 2: /* IRQ_ENABLESET */
399 s
->irq_enabled
|= value
;
401 case 3: /* IRQ_ENABLECLR */
402 s
->irq_enabled
&= ~value
;
404 case 4: /* INT_SOFTSET */
406 icp_pic_set_irq(s
, 0, 1);
408 case 5: /* INT_SOFTCLR */
410 icp_pic_set_irq(s
, 0, 0);
412 case 10: /* FRQ_ENABLESET */
413 s
->fiq_enabled
|= value
;
415 case 11: /* FRQ_ENABLECLR */
416 s
->fiq_enabled
&= ~value
;
418 case 0: /* IRQ_STATUS */
419 case 1: /* IRQ_RAWSTAT */
420 case 8: /* FRQ_STATUS */
421 case 9: /* FRQ_RAWSTAT */
423 printf ("icp_pic_write: Bad register offset 0x%x\n", (int)offset
);
429 static const MemoryRegionOps icp_pic_ops
= {
430 .read
= icp_pic_read
,
431 .write
= icp_pic_write
,
432 .endianness
= DEVICE_NATIVE_ENDIAN
,
435 static void icp_pic_init(Object
*obj
)
437 DeviceState
*dev
= DEVICE(obj
);
438 icp_pic_state
*s
= INTEGRATOR_PIC(obj
);
439 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
441 qdev_init_gpio_in(dev
, icp_pic_set_irq
, 32);
442 sysbus_init_irq(sbd
, &s
->parent_irq
);
443 sysbus_init_irq(sbd
, &s
->parent_fiq
);
444 memory_region_init_io(&s
->iomem
, obj
, &icp_pic_ops
, s
,
445 "icp-pic", 0x00800000);
446 sysbus_init_mmio(sbd
, &s
->iomem
);
449 /* CP control registers. */
451 #define TYPE_ICP_CONTROL_REGS "icp-ctrl-regs"
452 #define ICP_CONTROL_REGS(obj) \
453 OBJECT_CHECK(ICPCtrlRegsState, (obj), TYPE_ICP_CONTROL_REGS)
455 typedef struct ICPCtrlRegsState
{
457 SysBusDevice parent_obj
;
463 uint32_t intreg_state
;
466 #define ICP_GPIO_MMC_WPROT "mmc-wprot"
467 #define ICP_GPIO_MMC_CARDIN "mmc-cardin"
469 #define ICP_INTREG_WPROT (1 << 0)
470 #define ICP_INTREG_CARDIN (1 << 3)
472 static const VMStateDescription vmstate_icp_control
= {
473 .name
= "icp_control",
475 .minimum_version_id
= 1,
476 .fields
= (VMStateField
[]) {
477 VMSTATE_UINT32(intreg_state
, ICPCtrlRegsState
),
478 VMSTATE_END_OF_LIST()
482 static uint64_t icp_control_read(void *opaque
, hwaddr offset
,
485 ICPCtrlRegsState
*s
= opaque
;
487 switch (offset
>> 2) {
488 case 0: /* CP_IDFIELD */
490 case 1: /* CP_FLASHPROG */
492 case 2: /* CP_INTREG */
493 return s
->intreg_state
;
494 case 3: /* CP_DECODE */
497 hw_error("icp_control_read: Bad offset %x\n", (int)offset
);
502 static void icp_control_write(void *opaque
, hwaddr offset
,
503 uint64_t value
, unsigned size
)
505 ICPCtrlRegsState
*s
= opaque
;
507 switch (offset
>> 2) {
508 case 2: /* CP_INTREG */
509 s
->intreg_state
&= ~(value
& ICP_INTREG_CARDIN
);
510 qemu_set_irq(s
->mmc_irq
, !!(s
->intreg_state
& ICP_INTREG_CARDIN
));
512 case 1: /* CP_FLASHPROG */
513 case 3: /* CP_DECODE */
514 /* Nothing interesting implemented yet. */
517 hw_error("icp_control_write: Bad offset %x\n", (int)offset
);
521 static const MemoryRegionOps icp_control_ops
= {
522 .read
= icp_control_read
,
523 .write
= icp_control_write
,
524 .endianness
= DEVICE_NATIVE_ENDIAN
,
527 static void icp_control_mmc_wprot(void *opaque
, int line
, int level
)
529 ICPCtrlRegsState
*s
= opaque
;
531 s
->intreg_state
&= ~ICP_INTREG_WPROT
;
533 s
->intreg_state
|= ICP_INTREG_WPROT
;
537 static void icp_control_mmc_cardin(void *opaque
, int line
, int level
)
539 ICPCtrlRegsState
*s
= opaque
;
541 /* line is released by writing to CP_INTREG */
543 s
->intreg_state
|= ICP_INTREG_CARDIN
;
544 qemu_set_irq(s
->mmc_irq
, 1);
548 static void icp_control_init(Object
*obj
)
550 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
551 ICPCtrlRegsState
*s
= ICP_CONTROL_REGS(obj
);
552 DeviceState
*dev
= DEVICE(obj
);
554 memory_region_init_io(&s
->iomem
, OBJECT(s
), &icp_control_ops
, s
,
555 "icp_ctrl_regs", 0x00800000);
556 sysbus_init_mmio(sbd
, &s
->iomem
);
558 qdev_init_gpio_in_named(dev
, icp_control_mmc_wprot
, ICP_GPIO_MMC_WPROT
, 1);
559 qdev_init_gpio_in_named(dev
, icp_control_mmc_cardin
,
560 ICP_GPIO_MMC_CARDIN
, 1);
561 sysbus_init_irq(sbd
, &s
->mmc_irq
);
567 static struct arm_boot_info integrator_binfo
= {
572 static void integratorcp_init(MachineState
*machine
)
574 ram_addr_t ram_size
= machine
->ram_size
;
575 const char *kernel_filename
= machine
->kernel_filename
;
576 const char *kernel_cmdline
= machine
->kernel_cmdline
;
577 const char *initrd_filename
= machine
->initrd_filename
;
580 MemoryRegion
*address_space_mem
= get_system_memory();
581 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
582 MemoryRegion
*ram_alias
= g_new(MemoryRegion
, 1);
584 DeviceState
*dev
, *sic
, *icp
;
587 cpuobj
= object_new(machine
->cpu_type
);
589 /* By default ARM1176 CPUs have EL3 enabled. This board does not
590 * currently support EL3 so the CPU EL3 property is disabled before
593 if (object_property_find(cpuobj
, "has_el3", NULL
)) {
594 object_property_set_bool(cpuobj
, false, "has_el3", &error_fatal
);
597 object_property_set_bool(cpuobj
, true, "realized", &error_fatal
);
599 cpu
= ARM_CPU(cpuobj
);
601 memory_region_allocate_system_memory(ram
, NULL
, "integrator.ram",
603 /* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */
604 /* ??? RAM should repeat to fill physical memory space. */
605 /* SDRAM at address zero*/
606 memory_region_add_subregion(address_space_mem
, 0, ram
);
607 /* And again at address 0x80000000 */
608 memory_region_init_alias(ram_alias
, NULL
, "ram.alias", ram
, 0, ram_size
);
609 memory_region_add_subregion(address_space_mem
, 0x80000000, ram_alias
);
611 dev
= qdev_create(NULL
, TYPE_INTEGRATOR_CM
);
612 qdev_prop_set_uint32(dev
, "memsz", ram_size
>> 20);
613 qdev_init_nofail(dev
);
614 sysbus_mmio_map((SysBusDevice
*)dev
, 0, 0x10000000);
616 dev
= sysbus_create_varargs(TYPE_INTEGRATOR_PIC
, 0x14000000,
617 qdev_get_gpio_in(DEVICE(cpu
), ARM_CPU_IRQ
),
618 qdev_get_gpio_in(DEVICE(cpu
), ARM_CPU_FIQ
),
620 for (i
= 0; i
< 32; i
++) {
621 pic
[i
] = qdev_get_gpio_in(dev
, i
);
623 sic
= sysbus_create_simple(TYPE_INTEGRATOR_PIC
, 0xca000000, pic
[26]);
624 sysbus_create_varargs("integrator_pit", 0x13000000,
625 pic
[5], pic
[6], pic
[7], NULL
);
626 sysbus_create_simple("pl031", 0x15000000, pic
[8]);
627 pl011_create(0x16000000, pic
[1], serial_hds
[0]);
628 pl011_create(0x17000000, pic
[2], serial_hds
[1]);
629 icp
= sysbus_create_simple(TYPE_ICP_CONTROL_REGS
, 0xcb000000,
630 qdev_get_gpio_in(sic
, 3));
631 sysbus_create_simple("pl050_keyboard", 0x18000000, pic
[3]);
632 sysbus_create_simple("pl050_mouse", 0x19000000, pic
[4]);
633 sysbus_create_simple(TYPE_INTEGRATOR_DEBUG
, 0x1a000000, 0);
635 dev
= sysbus_create_varargs("pl181", 0x1c000000, pic
[23], pic
[24], NULL
);
636 qdev_connect_gpio_out(dev
, 0,
637 qdev_get_gpio_in_named(icp
, ICP_GPIO_MMC_WPROT
, 0));
638 qdev_connect_gpio_out(dev
, 1,
639 qdev_get_gpio_in_named(icp
, ICP_GPIO_MMC_CARDIN
, 0));
641 if (nd_table
[0].used
)
642 smc91c111_init(&nd_table
[0], 0xc8000000, pic
[27]);
644 sysbus_create_simple("pl110", 0xc0000000, pic
[22]);
646 integrator_binfo
.ram_size
= ram_size
;
647 integrator_binfo
.kernel_filename
= kernel_filename
;
648 integrator_binfo
.kernel_cmdline
= kernel_cmdline
;
649 integrator_binfo
.initrd_filename
= initrd_filename
;
650 arm_load_kernel(cpu
, &integrator_binfo
);
653 static void integratorcp_machine_init(MachineClass
*mc
)
655 mc
->desc
= "ARM Integrator/CP (ARM926EJ-S)";
656 mc
->init
= integratorcp_init
;
657 mc
->ignore_memory_transaction_failures
= true;
658 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("arm926");
661 DEFINE_MACHINE("integratorcp", integratorcp_machine_init
)
663 static Property core_properties
[] = {
664 DEFINE_PROP_UINT32("memsz", IntegratorCMState
, memsz
, 0),
665 DEFINE_PROP_END_OF_LIST(),
668 static void core_class_init(ObjectClass
*klass
, void *data
)
670 DeviceClass
*dc
= DEVICE_CLASS(klass
);
672 dc
->props
= core_properties
;
673 dc
->realize
= integratorcm_realize
;
674 dc
->vmsd
= &vmstate_integratorcm
;
677 static void icp_pic_class_init(ObjectClass
*klass
, void *data
)
679 DeviceClass
*dc
= DEVICE_CLASS(klass
);
681 dc
->vmsd
= &vmstate_icp_pic
;
684 static void icp_control_class_init(ObjectClass
*klass
, void *data
)
686 DeviceClass
*dc
= DEVICE_CLASS(klass
);
688 dc
->vmsd
= &vmstate_icp_control
;
691 static const TypeInfo core_info
= {
692 .name
= TYPE_INTEGRATOR_CM
,
693 .parent
= TYPE_SYS_BUS_DEVICE
,
694 .instance_size
= sizeof(IntegratorCMState
),
695 .instance_init
= integratorcm_init
,
696 .class_init
= core_class_init
,
699 static const TypeInfo icp_pic_info
= {
700 .name
= TYPE_INTEGRATOR_PIC
,
701 .parent
= TYPE_SYS_BUS_DEVICE
,
702 .instance_size
= sizeof(icp_pic_state
),
703 .instance_init
= icp_pic_init
,
704 .class_init
= icp_pic_class_init
,
707 static const TypeInfo icp_ctrl_regs_info
= {
708 .name
= TYPE_ICP_CONTROL_REGS
,
709 .parent
= TYPE_SYS_BUS_DEVICE
,
710 .instance_size
= sizeof(ICPCtrlRegsState
),
711 .instance_init
= icp_control_init
,
712 .class_init
= icp_control_class_init
,
715 static void integratorcp_register_types(void)
717 type_register_static(&icp_pic_info
);
718 type_register_static(&core_info
);
719 type_register_static(&icp_ctrl_regs_info
);
722 type_init(integratorcp_register_types
)