2 * ARM mach-virt emulation
4 * Copyright (c) 2013 Linaro Limited
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
18 * Emulate a virtual board which works by passing Linux all the information
19 * it needs about what devices are present via the device tree.
20 * There are some restrictions about what we can do here:
21 * + we can only present devices whose Linux drivers will work based
22 * purely on the device tree with no platform data at all
23 * + we want to present a very stripped-down minimalist platform,
24 * both because this reduces the security attack surface from the guest
25 * and also because it reduces our exposure to being broken when
26 * the kernel updates its device tree bindings and requires further
27 * information in a device binding that we aren't providing.
28 * This is essentially the same approach kvmtool uses.
31 #include "qemu/osdep.h"
32 #include "qemu-common.h"
33 #include "qemu/datadir.h"
34 #include "qemu/units.h"
35 #include "qemu/option.h"
36 #include "monitor/qdev.h"
37 #include "qapi/error.h"
38 #include "hw/sysbus.h"
39 #include "hw/arm/boot.h"
40 #include "hw/arm/primecell.h"
41 #include "hw/arm/virt.h"
42 #include "hw/block/flash.h"
43 #include "hw/vfio/vfio-calxeda-xgmac.h"
44 #include "hw/vfio/vfio-amd-xgbe.h"
45 #include "hw/display/ramfb.h"
47 #include "sysemu/device_tree.h"
48 #include "sysemu/numa.h"
49 #include "sysemu/runstate.h"
50 #include "sysemu/tpm.h"
51 #include "sysemu/kvm.h"
52 #include "hw/loader.h"
53 #include "qapi/error.h"
54 #include "qemu/bitops.h"
55 #include "qemu/error-report.h"
56 #include "qemu/module.h"
57 #include "hw/pci-host/gpex.h"
58 #include "hw/virtio/virtio-pci.h"
59 #include "hw/arm/sysbus-fdt.h"
60 #include "hw/platform-bus.h"
61 #include "hw/qdev-properties.h"
62 #include "hw/arm/fdt.h"
63 #include "hw/intc/arm_gic.h"
64 #include "hw/intc/arm_gicv3_common.h"
67 #include "hw/firmware/smbios.h"
68 #include "qapi/visitor.h"
69 #include "qapi/qapi-visit-common.h"
70 #include "standard-headers/linux/input.h"
71 #include "hw/arm/smmuv3.h"
72 #include "hw/acpi/acpi.h"
73 #include "target/arm/internals.h"
74 #include "hw/mem/pc-dimm.h"
75 #include "hw/mem/nvdimm.h"
76 #include "hw/acpi/generic_event_device.h"
77 #include "hw/virtio/virtio-iommu.h"
78 #include "hw/char/pl011.h"
79 #include "qemu/guest-random.h"
81 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
82 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
85 MachineClass *mc = MACHINE_CLASS(oc); \
86 virt_machine_##major##_##minor##_options(mc); \
87 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \
92 static const TypeInfo machvirt_##major##_##minor##_info = { \
93 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
94 .parent = TYPE_VIRT_MACHINE, \
95 .class_init = virt_##major##_##minor##_class_init, \
97 static void machvirt_machine_##major##_##minor##_init(void) \
99 type_register_static(&machvirt_##major##_##minor##_info); \
101 type_init(machvirt_machine_##major##_##minor##_init);
103 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
104 DEFINE_VIRT_MACHINE_LATEST(major, minor, true)
105 #define DEFINE_VIRT_MACHINE(major, minor) \
106 DEFINE_VIRT_MACHINE_LATEST(major, minor, false)
109 /* Number of external interrupt lines to configure the GIC with */
112 #define PLATFORM_BUS_NUM_IRQS 64
114 /* Legacy RAM limit in GB (< version 4.0) */
115 #define LEGACY_RAMLIMIT_GB 255
116 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB)
118 /* Addresses and sizes of our components.
119 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
120 * 128MB..256MB is used for miscellaneous device I/O.
121 * 256MB..1GB is reserved for possible future PCI support (ie where the
122 * PCI memory window will go if we add a PCI host controller).
123 * 1GB and up is RAM (which may happily spill over into the
124 * high memory region beyond 4GB).
125 * This represents a compromise between how much RAM can be given to
126 * a 32 bit VM and leaving space for expansion and in particular for PCI.
127 * Note that devices should generally be placed at multiples of 0x10000,
128 * to accommodate guests using 64K pages.
130 static const MemMapEntry base_memmap
[] = {
131 /* Space up to 0x8000000 is reserved for a boot ROM */
132 [VIRT_FLASH
] = { 0, 0x08000000 },
133 [VIRT_CPUPERIPHS
] = { 0x08000000, 0x00020000 },
134 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
135 [VIRT_GIC_DIST
] = { 0x08000000, 0x00010000 },
136 [VIRT_GIC_CPU
] = { 0x08010000, 0x00010000 },
137 [VIRT_GIC_V2M
] = { 0x08020000, 0x00001000 },
138 [VIRT_GIC_HYP
] = { 0x08030000, 0x00010000 },
139 [VIRT_GIC_VCPU
] = { 0x08040000, 0x00010000 },
140 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
141 [VIRT_GIC_ITS
] = { 0x08080000, 0x00020000 },
142 /* This redistributor space allows up to 2*64kB*123 CPUs */
143 [VIRT_GIC_REDIST
] = { 0x080A0000, 0x00F60000 },
144 [VIRT_UART
] = { 0x09000000, 0x00001000 },
145 [VIRT_RTC
] = { 0x09010000, 0x00001000 },
146 [VIRT_FW_CFG
] = { 0x09020000, 0x00000018 },
147 [VIRT_GPIO
] = { 0x09030000, 0x00001000 },
148 [VIRT_SECURE_UART
] = { 0x09040000, 0x00001000 },
149 [VIRT_SMMU
] = { 0x09050000, 0x00020000 },
150 [VIRT_PCDIMM_ACPI
] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN
},
151 [VIRT_ACPI_GED
] = { 0x09080000, ACPI_GED_EVT_SEL_LEN
},
152 [VIRT_NVDIMM_ACPI
] = { 0x09090000, NVDIMM_ACPI_IO_LEN
},
153 [VIRT_PVTIME
] = { 0x090a0000, 0x00010000 },
154 [VIRT_SECURE_GPIO
] = { 0x090b0000, 0x00001000 },
155 [VIRT_MMIO
] = { 0x0a000000, 0x00000200 },
156 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
157 [VIRT_PLATFORM_BUS
] = { 0x0c000000, 0x02000000 },
158 [VIRT_SECURE_MEM
] = { 0x0e000000, 0x01000000 },
159 [VIRT_PCIE_MMIO
] = { 0x10000000, 0x2eff0000 },
160 [VIRT_PCIE_PIO
] = { 0x3eff0000, 0x00010000 },
161 [VIRT_PCIE_ECAM
] = { 0x3f000000, 0x01000000 },
162 /* Actual RAM size depends on initial RAM and device memory settings */
163 [VIRT_MEM
] = { GiB
, LEGACY_RAMLIMIT_BYTES
},
167 * Highmem IO Regions: This memory map is floating, located after the RAM.
168 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the
169 * top of the RAM, so that its base get the same alignment as the size,
170 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is
171 * less than 256GiB of RAM, the floating area starts at the 256GiB mark.
172 * Note the extended_memmap is sized so that it eventually also includes the
173 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
174 * index of base_memmap).
176 static MemMapEntry extended_memmap
[] = {
177 /* Additional 64 MB redist region (can contain up to 512 redistributors) */
178 [VIRT_HIGH_GIC_REDIST2
] = { 0x0, 64 * MiB
},
179 [VIRT_HIGH_PCIE_ECAM
] = { 0x0, 256 * MiB
},
180 /* Second PCIe window */
181 [VIRT_HIGH_PCIE_MMIO
] = { 0x0, 512 * GiB
},
184 static const int a15irqmap
[] = {
187 [VIRT_PCIE
] = 3, /* ... to 6 */
189 [VIRT_SECURE_UART
] = 8,
191 [VIRT_MMIO
] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
192 [VIRT_GIC_V2M
] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
193 [VIRT_SMMU
] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */
194 [VIRT_PLATFORM_BUS
] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
197 static const char *valid_cpus
[] = {
198 ARM_CPU_TYPE_NAME("cortex-a7"),
199 ARM_CPU_TYPE_NAME("cortex-a15"),
200 ARM_CPU_TYPE_NAME("cortex-a53"),
201 ARM_CPU_TYPE_NAME("cortex-a57"),
202 ARM_CPU_TYPE_NAME("cortex-a72"),
203 ARM_CPU_TYPE_NAME("a64fx"),
204 ARM_CPU_TYPE_NAME("host"),
205 ARM_CPU_TYPE_NAME("max"),
208 static bool cpu_type_valid(const char *cpu
)
212 for (i
= 0; i
< ARRAY_SIZE(valid_cpus
); i
++) {
213 if (strcmp(cpu
, valid_cpus
[i
]) == 0) {
220 static void create_kaslr_seed(MachineState
*ms
, const char *node
)
224 if (qemu_guest_getrandom(&seed
, sizeof(seed
), NULL
)) {
227 qemu_fdt_setprop_u64(ms
->fdt
, node
, "kaslr-seed", seed
);
230 static void create_fdt(VirtMachineState
*vms
)
232 MachineState
*ms
= MACHINE(vms
);
233 int nb_numa_nodes
= ms
->numa_state
->num_nodes
;
234 void *fdt
= create_device_tree(&vms
->fdt_size
);
237 error_report("create_device_tree() failed");
244 qemu_fdt_setprop_string(fdt
, "/", "compatible", "linux,dummy-virt");
245 qemu_fdt_setprop_cell(fdt
, "/", "#address-cells", 0x2);
246 qemu_fdt_setprop_cell(fdt
, "/", "#size-cells", 0x2);
248 /* /chosen must exist for load_dtb to fill in necessary properties later */
249 qemu_fdt_add_subnode(fdt
, "/chosen");
250 create_kaslr_seed(ms
, "/chosen");
253 qemu_fdt_add_subnode(fdt
, "/secure-chosen");
254 create_kaslr_seed(ms
, "/secure-chosen");
257 /* Clock node, for the benefit of the UART. The kernel device tree
258 * binding documentation claims the PL011 node clock properties are
259 * optional but in practice if you omit them the kernel refuses to
260 * probe for the device.
262 vms
->clock_phandle
= qemu_fdt_alloc_phandle(fdt
);
263 qemu_fdt_add_subnode(fdt
, "/apb-pclk");
264 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "compatible", "fixed-clock");
265 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "#clock-cells", 0x0);
266 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "clock-frequency", 24000000);
267 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "clock-output-names",
269 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "phandle", vms
->clock_phandle
);
271 if (nb_numa_nodes
> 0 && ms
->numa_state
->have_numa_distance
) {
272 int size
= nb_numa_nodes
* nb_numa_nodes
* 3 * sizeof(uint32_t);
273 uint32_t *matrix
= g_malloc0(size
);
276 for (i
= 0; i
< nb_numa_nodes
; i
++) {
277 for (j
= 0; j
< nb_numa_nodes
; j
++) {
278 idx
= (i
* nb_numa_nodes
+ j
) * 3;
279 matrix
[idx
+ 0] = cpu_to_be32(i
);
280 matrix
[idx
+ 1] = cpu_to_be32(j
);
282 cpu_to_be32(ms
->numa_state
->nodes
[i
].distance
[j
]);
286 qemu_fdt_add_subnode(fdt
, "/distance-map");
287 qemu_fdt_setprop_string(fdt
, "/distance-map", "compatible",
288 "numa-distance-map-v1");
289 qemu_fdt_setprop(fdt
, "/distance-map", "distance-matrix",
295 static void fdt_add_timer_nodes(const VirtMachineState
*vms
)
297 /* On real hardware these interrupts are level-triggered.
298 * On KVM they were edge-triggered before host kernel version 4.4,
299 * and level-triggered afterwards.
300 * On emulated QEMU they are level-triggered.
302 * Getting the DTB info about them wrong is awkward for some
304 * pre-4.8 ignore the DT and leave the interrupt configured
305 * with whatever the GIC reset value (or the bootloader) left it at
306 * 4.8 before rc6 honour the incorrect data by programming it back
307 * into the GIC, causing problems
308 * 4.8rc6 and later ignore the DT and always write "level triggered"
311 * For backwards-compatibility, virt-2.8 and earlier will continue
312 * to say these are edge-triggered, but later machines will report
313 * the correct information.
316 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
317 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
318 MachineState
*ms
= MACHINE(vms
);
320 if (vmc
->claim_edge_triggered_timers
) {
321 irqflags
= GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
;
324 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
325 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
326 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
327 (1 << MACHINE(vms
)->smp
.cpus
) - 1);
330 qemu_fdt_add_subnode(ms
->fdt
, "/timer");
332 armcpu
= ARM_CPU(qemu_get_cpu(0));
333 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
334 const char compat
[] = "arm,armv8-timer\0arm,armv7-timer";
335 qemu_fdt_setprop(ms
->fdt
, "/timer", "compatible",
336 compat
, sizeof(compat
));
338 qemu_fdt_setprop_string(ms
->fdt
, "/timer", "compatible",
341 qemu_fdt_setprop(ms
->fdt
, "/timer", "always-on", NULL
, 0);
342 qemu_fdt_setprop_cells(ms
->fdt
, "/timer", "interrupts",
343 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_S_EL1_IRQ
, irqflags
,
344 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL1_IRQ
, irqflags
,
345 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_VIRT_IRQ
, irqflags
,
346 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL2_IRQ
, irqflags
);
349 static void fdt_add_cpu_nodes(const VirtMachineState
*vms
)
353 const MachineState
*ms
= MACHINE(vms
);
354 int smp_cpus
= ms
->smp
.cpus
;
357 * From Documentation/devicetree/bindings/arm/cpus.txt
358 * On ARM v8 64-bit systems value should be set to 2,
359 * that corresponds to the MPIDR_EL1 register size.
360 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
361 * in the system, #address-cells can be set to 1, since
362 * MPIDR_EL1[63:32] bits are not used for CPUs
365 * Here we actually don't know whether our system is 32- or 64-bit one.
366 * The simplest way to go is to examine affinity IDs of all our CPUs. If
367 * at least one of them has Aff3 populated, we set #address-cells to 2.
369 for (cpu
= 0; cpu
< smp_cpus
; cpu
++) {
370 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
372 if (armcpu
->mp_affinity
& ARM_AFF3_MASK
) {
378 qemu_fdt_add_subnode(ms
->fdt
, "/cpus");
379 qemu_fdt_setprop_cell(ms
->fdt
, "/cpus", "#address-cells", addr_cells
);
380 qemu_fdt_setprop_cell(ms
->fdt
, "/cpus", "#size-cells", 0x0);
382 for (cpu
= smp_cpus
- 1; cpu
>= 0; cpu
--) {
383 char *nodename
= g_strdup_printf("/cpus/cpu@%d", cpu
);
384 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
385 CPUState
*cs
= CPU(armcpu
);
387 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
388 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "device_type", "cpu");
389 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
390 armcpu
->dtb_compatible
);
392 if (vms
->psci_conduit
!= QEMU_PSCI_CONDUIT_DISABLED
&& smp_cpus
> 1) {
393 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
394 "enable-method", "psci");
397 if (addr_cells
== 2) {
398 qemu_fdt_setprop_u64(ms
->fdt
, nodename
, "reg",
399 armcpu
->mp_affinity
);
401 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "reg",
402 armcpu
->mp_affinity
);
405 if (ms
->possible_cpus
->cpus
[cs
->cpu_index
].props
.has_node_id
) {
406 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "numa-node-id",
407 ms
->possible_cpus
->cpus
[cs
->cpu_index
].props
.node_id
);
414 static void fdt_add_its_gic_node(VirtMachineState
*vms
)
417 MachineState
*ms
= MACHINE(vms
);
419 vms
->msi_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
420 nodename
= g_strdup_printf("/intc/its@%" PRIx64
,
421 vms
->memmap
[VIRT_GIC_ITS
].base
);
422 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
423 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
425 qemu_fdt_setprop(ms
->fdt
, nodename
, "msi-controller", NULL
, 0);
426 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
427 2, vms
->memmap
[VIRT_GIC_ITS
].base
,
428 2, vms
->memmap
[VIRT_GIC_ITS
].size
);
429 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", vms
->msi_phandle
);
433 static void fdt_add_v2m_gic_node(VirtMachineState
*vms
)
435 MachineState
*ms
= MACHINE(vms
);
438 nodename
= g_strdup_printf("/intc/v2m@%" PRIx64
,
439 vms
->memmap
[VIRT_GIC_V2M
].base
);
440 vms
->msi_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
441 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
442 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
443 "arm,gic-v2m-frame");
444 qemu_fdt_setprop(ms
->fdt
, nodename
, "msi-controller", NULL
, 0);
445 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
446 2, vms
->memmap
[VIRT_GIC_V2M
].base
,
447 2, vms
->memmap
[VIRT_GIC_V2M
].size
);
448 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", vms
->msi_phandle
);
452 static void fdt_add_gic_node(VirtMachineState
*vms
)
454 MachineState
*ms
= MACHINE(vms
);
457 vms
->gic_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
458 qemu_fdt_setprop_cell(ms
->fdt
, "/", "interrupt-parent", vms
->gic_phandle
);
460 nodename
= g_strdup_printf("/intc@%" PRIx64
,
461 vms
->memmap
[VIRT_GIC_DIST
].base
);
462 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
463 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#interrupt-cells", 3);
464 qemu_fdt_setprop(ms
->fdt
, nodename
, "interrupt-controller", NULL
, 0);
465 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#address-cells", 0x2);
466 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#size-cells", 0x2);
467 qemu_fdt_setprop(ms
->fdt
, nodename
, "ranges", NULL
, 0);
468 if (vms
->gic_version
== VIRT_GIC_VERSION_3
) {
469 int nb_redist_regions
= virt_gicv3_redist_region_count(vms
);
471 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
474 qemu_fdt_setprop_cell(ms
->fdt
, nodename
,
475 "#redistributor-regions", nb_redist_regions
);
477 if (nb_redist_regions
== 1) {
478 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
479 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
480 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
481 2, vms
->memmap
[VIRT_GIC_REDIST
].base
,
482 2, vms
->memmap
[VIRT_GIC_REDIST
].size
);
484 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
485 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
486 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
487 2, vms
->memmap
[VIRT_GIC_REDIST
].base
,
488 2, vms
->memmap
[VIRT_GIC_REDIST
].size
,
489 2, vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].base
,
490 2, vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].size
);
494 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
495 GIC_FDT_IRQ_TYPE_PPI
, ARCH_GIC_MAINT_IRQ
,
496 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
499 /* 'cortex-a15-gic' means 'GIC v2' */
500 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
501 "arm,cortex-a15-gic");
503 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
504 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
505 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
506 2, vms
->memmap
[VIRT_GIC_CPU
].base
,
507 2, vms
->memmap
[VIRT_GIC_CPU
].size
);
509 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
510 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
511 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
512 2, vms
->memmap
[VIRT_GIC_CPU
].base
,
513 2, vms
->memmap
[VIRT_GIC_CPU
].size
,
514 2, vms
->memmap
[VIRT_GIC_HYP
].base
,
515 2, vms
->memmap
[VIRT_GIC_HYP
].size
,
516 2, vms
->memmap
[VIRT_GIC_VCPU
].base
,
517 2, vms
->memmap
[VIRT_GIC_VCPU
].size
);
518 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
519 GIC_FDT_IRQ_TYPE_PPI
, ARCH_GIC_MAINT_IRQ
,
520 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
524 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", vms
->gic_phandle
);
528 static void fdt_add_pmu_nodes(const VirtMachineState
*vms
)
530 ARMCPU
*armcpu
= ARM_CPU(first_cpu
);
531 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
532 MachineState
*ms
= MACHINE(vms
);
534 if (!arm_feature(&armcpu
->env
, ARM_FEATURE_PMU
)) {
535 assert(!object_property_get_bool(OBJECT(armcpu
), "pmu", NULL
));
539 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
540 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
541 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
542 (1 << MACHINE(vms
)->smp
.cpus
) - 1);
545 qemu_fdt_add_subnode(ms
->fdt
, "/pmu");
546 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
547 const char compat
[] = "arm,armv8-pmuv3";
548 qemu_fdt_setprop(ms
->fdt
, "/pmu", "compatible",
549 compat
, sizeof(compat
));
550 qemu_fdt_setprop_cells(ms
->fdt
, "/pmu", "interrupts",
551 GIC_FDT_IRQ_TYPE_PPI
, VIRTUAL_PMU_IRQ
, irqflags
);
555 static inline DeviceState
*create_acpi_ged(VirtMachineState
*vms
)
558 MachineState
*ms
= MACHINE(vms
);
559 int irq
= vms
->irqmap
[VIRT_ACPI_GED
];
560 uint32_t event
= ACPI_GED_PWR_DOWN_EVT
;
563 event
|= ACPI_GED_MEM_HOTPLUG_EVT
;
566 if (ms
->nvdimms_state
->is_enabled
) {
567 event
|= ACPI_GED_NVDIMM_HOTPLUG_EVT
;
570 dev
= qdev_new(TYPE_ACPI_GED
);
571 qdev_prop_set_uint32(dev
, "ged-event", event
);
573 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_ACPI_GED
].base
);
574 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 1, vms
->memmap
[VIRT_PCDIMM_ACPI
].base
);
575 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0, qdev_get_gpio_in(vms
->gic
, irq
));
577 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
582 static void create_its(VirtMachineState
*vms
)
584 const char *itsclass
= its_class_name();
587 if (!strcmp(itsclass
, "arm-gicv3-its")) {
594 /* Do nothing if not supported */
598 dev
= qdev_new(itsclass
);
600 object_property_set_link(OBJECT(dev
), "parent-gicv3", OBJECT(vms
->gic
),
602 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
603 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_GIC_ITS
].base
);
605 fdt_add_its_gic_node(vms
);
606 vms
->msi_controller
= VIRT_MSI_CTRL_ITS
;
609 static void create_v2m(VirtMachineState
*vms
)
612 int irq
= vms
->irqmap
[VIRT_GIC_V2M
];
615 dev
= qdev_new("arm-gicv2m");
616 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_GIC_V2M
].base
);
617 qdev_prop_set_uint32(dev
, "base-spi", irq
);
618 qdev_prop_set_uint32(dev
, "num-spi", NUM_GICV2M_SPIS
);
619 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
621 for (i
= 0; i
< NUM_GICV2M_SPIS
; i
++) {
622 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
623 qdev_get_gpio_in(vms
->gic
, irq
+ i
));
626 fdt_add_v2m_gic_node(vms
);
627 vms
->msi_controller
= VIRT_MSI_CTRL_GICV2M
;
630 static void create_gic(VirtMachineState
*vms
, MemoryRegion
*mem
)
632 MachineState
*ms
= MACHINE(vms
);
633 /* We create a standalone GIC */
634 SysBusDevice
*gicbusdev
;
636 int type
= vms
->gic_version
, i
;
637 unsigned int smp_cpus
= ms
->smp
.cpus
;
638 uint32_t nb_redist_regions
= 0;
640 gictype
= (type
== 3) ? gicv3_class_name() : gic_class_name();
642 vms
->gic
= qdev_new(gictype
);
643 qdev_prop_set_uint32(vms
->gic
, "revision", type
);
644 qdev_prop_set_uint32(vms
->gic
, "num-cpu", smp_cpus
);
645 /* Note that the num-irq property counts both internal and external
646 * interrupts; there are always 32 of the former (mandated by GIC spec).
648 qdev_prop_set_uint32(vms
->gic
, "num-irq", NUM_IRQS
+ 32);
649 if (!kvm_irqchip_in_kernel()) {
650 qdev_prop_set_bit(vms
->gic
, "has-security-extensions", vms
->secure
);
654 uint32_t redist0_capacity
=
655 vms
->memmap
[VIRT_GIC_REDIST
].size
/ GICV3_REDIST_SIZE
;
656 uint32_t redist0_count
= MIN(smp_cpus
, redist0_capacity
);
658 nb_redist_regions
= virt_gicv3_redist_region_count(vms
);
660 qdev_prop_set_uint32(vms
->gic
, "len-redist-region-count",
662 qdev_prop_set_uint32(vms
->gic
, "redist-region-count[0]", redist0_count
);
664 if (!kvm_irqchip_in_kernel()) {
666 object_property_set_link(OBJECT(vms
->gic
), "sysmem",
667 OBJECT(mem
), &error_fatal
);
668 qdev_prop_set_bit(vms
->gic
, "has-lpi", true);
672 if (nb_redist_regions
== 2) {
673 uint32_t redist1_capacity
=
674 vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].size
/ GICV3_REDIST_SIZE
;
676 qdev_prop_set_uint32(vms
->gic
, "redist-region-count[1]",
677 MIN(smp_cpus
- redist0_count
, redist1_capacity
));
680 if (!kvm_irqchip_in_kernel()) {
681 qdev_prop_set_bit(vms
->gic
, "has-virtualization-extensions",
685 gicbusdev
= SYS_BUS_DEVICE(vms
->gic
);
686 sysbus_realize_and_unref(gicbusdev
, &error_fatal
);
687 sysbus_mmio_map(gicbusdev
, 0, vms
->memmap
[VIRT_GIC_DIST
].base
);
689 sysbus_mmio_map(gicbusdev
, 1, vms
->memmap
[VIRT_GIC_REDIST
].base
);
690 if (nb_redist_regions
== 2) {
691 sysbus_mmio_map(gicbusdev
, 2,
692 vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].base
);
695 sysbus_mmio_map(gicbusdev
, 1, vms
->memmap
[VIRT_GIC_CPU
].base
);
697 sysbus_mmio_map(gicbusdev
, 2, vms
->memmap
[VIRT_GIC_HYP
].base
);
698 sysbus_mmio_map(gicbusdev
, 3, vms
->memmap
[VIRT_GIC_VCPU
].base
);
702 /* Wire the outputs from each CPU's generic timer and the GICv3
703 * maintenance interrupt signal to the appropriate GIC PPI inputs,
704 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
706 for (i
= 0; i
< smp_cpus
; i
++) {
707 DeviceState
*cpudev
= DEVICE(qemu_get_cpu(i
));
708 int ppibase
= NUM_IRQS
+ i
* GIC_INTERNAL
+ GIC_NR_SGIS
;
710 /* Mapping from the output timer irq lines from the CPU to the
711 * GIC PPI inputs we use for the virt board.
713 const int timer_irq
[] = {
714 [GTIMER_PHYS
] = ARCH_TIMER_NS_EL1_IRQ
,
715 [GTIMER_VIRT
] = ARCH_TIMER_VIRT_IRQ
,
716 [GTIMER_HYP
] = ARCH_TIMER_NS_EL2_IRQ
,
717 [GTIMER_SEC
] = ARCH_TIMER_S_EL1_IRQ
,
720 for (irq
= 0; irq
< ARRAY_SIZE(timer_irq
); irq
++) {
721 qdev_connect_gpio_out(cpudev
, irq
,
722 qdev_get_gpio_in(vms
->gic
,
723 ppibase
+ timer_irq
[irq
]));
727 qemu_irq irq
= qdev_get_gpio_in(vms
->gic
,
728 ppibase
+ ARCH_GIC_MAINT_IRQ
);
729 qdev_connect_gpio_out_named(cpudev
, "gicv3-maintenance-interrupt",
731 } else if (vms
->virt
) {
732 qemu_irq irq
= qdev_get_gpio_in(vms
->gic
,
733 ppibase
+ ARCH_GIC_MAINT_IRQ
);
734 sysbus_connect_irq(gicbusdev
, i
+ 4 * smp_cpus
, irq
);
737 qdev_connect_gpio_out_named(cpudev
, "pmu-interrupt", 0,
738 qdev_get_gpio_in(vms
->gic
, ppibase
741 sysbus_connect_irq(gicbusdev
, i
, qdev_get_gpio_in(cpudev
, ARM_CPU_IRQ
));
742 sysbus_connect_irq(gicbusdev
, i
+ smp_cpus
,
743 qdev_get_gpio_in(cpudev
, ARM_CPU_FIQ
));
744 sysbus_connect_irq(gicbusdev
, i
+ 2 * smp_cpus
,
745 qdev_get_gpio_in(cpudev
, ARM_CPU_VIRQ
));
746 sysbus_connect_irq(gicbusdev
, i
+ 3 * smp_cpus
,
747 qdev_get_gpio_in(cpudev
, ARM_CPU_VFIQ
));
750 fdt_add_gic_node(vms
);
752 if (type
== 3 && vms
->its
) {
754 } else if (type
== 2) {
759 static void create_uart(const VirtMachineState
*vms
, int uart
,
760 MemoryRegion
*mem
, Chardev
*chr
)
763 hwaddr base
= vms
->memmap
[uart
].base
;
764 hwaddr size
= vms
->memmap
[uart
].size
;
765 int irq
= vms
->irqmap
[uart
];
766 const char compat
[] = "arm,pl011\0arm,primecell";
767 const char clocknames
[] = "uartclk\0apb_pclk";
768 DeviceState
*dev
= qdev_new(TYPE_PL011
);
769 SysBusDevice
*s
= SYS_BUS_DEVICE(dev
);
770 MachineState
*ms
= MACHINE(vms
);
772 qdev_prop_set_chr(dev
, "chardev", chr
);
773 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
774 memory_region_add_subregion(mem
, base
,
775 sysbus_mmio_get_region(s
, 0));
776 sysbus_connect_irq(s
, 0, qdev_get_gpio_in(vms
->gic
, irq
));
778 nodename
= g_strdup_printf("/pl011@%" PRIx64
, base
);
779 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
780 /* Note that we can't use setprop_string because of the embedded NUL */
781 qemu_fdt_setprop(ms
->fdt
, nodename
, "compatible",
782 compat
, sizeof(compat
));
783 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
785 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
786 GIC_FDT_IRQ_TYPE_SPI
, irq
,
787 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
788 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "clocks",
789 vms
->clock_phandle
, vms
->clock_phandle
);
790 qemu_fdt_setprop(ms
->fdt
, nodename
, "clock-names",
791 clocknames
, sizeof(clocknames
));
793 if (uart
== VIRT_UART
) {
794 qemu_fdt_setprop_string(ms
->fdt
, "/chosen", "stdout-path", nodename
);
796 /* Mark as not usable by the normal world */
797 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
798 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
800 qemu_fdt_setprop_string(ms
->fdt
, "/secure-chosen", "stdout-path",
807 static void create_rtc(const VirtMachineState
*vms
)
810 hwaddr base
= vms
->memmap
[VIRT_RTC
].base
;
811 hwaddr size
= vms
->memmap
[VIRT_RTC
].size
;
812 int irq
= vms
->irqmap
[VIRT_RTC
];
813 const char compat
[] = "arm,pl031\0arm,primecell";
814 MachineState
*ms
= MACHINE(vms
);
816 sysbus_create_simple("pl031", base
, qdev_get_gpio_in(vms
->gic
, irq
));
818 nodename
= g_strdup_printf("/pl031@%" PRIx64
, base
);
819 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
820 qemu_fdt_setprop(ms
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
821 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
823 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
824 GIC_FDT_IRQ_TYPE_SPI
, irq
,
825 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
826 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "clocks", vms
->clock_phandle
);
827 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "clock-names", "apb_pclk");
831 static DeviceState
*gpio_key_dev
;
832 static void virt_powerdown_req(Notifier
*n
, void *opaque
)
834 VirtMachineState
*s
= container_of(n
, VirtMachineState
, powerdown_notifier
);
837 acpi_send_event(s
->acpi_dev
, ACPI_POWER_DOWN_STATUS
);
839 /* use gpio Pin 3 for power button event */
840 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev
, 0), 1);
844 static void create_gpio_keys(char *fdt
, DeviceState
*pl061_dev
,
847 gpio_key_dev
= sysbus_create_simple("gpio-key", -1,
848 qdev_get_gpio_in(pl061_dev
, 3));
850 qemu_fdt_add_subnode(fdt
, "/gpio-keys");
851 qemu_fdt_setprop_string(fdt
, "/gpio-keys", "compatible", "gpio-keys");
852 qemu_fdt_setprop_cell(fdt
, "/gpio-keys", "#size-cells", 0);
853 qemu_fdt_setprop_cell(fdt
, "/gpio-keys", "#address-cells", 1);
855 qemu_fdt_add_subnode(fdt
, "/gpio-keys/poweroff");
856 qemu_fdt_setprop_string(fdt
, "/gpio-keys/poweroff",
857 "label", "GPIO Key Poweroff");
858 qemu_fdt_setprop_cell(fdt
, "/gpio-keys/poweroff", "linux,code",
860 qemu_fdt_setprop_cells(fdt
, "/gpio-keys/poweroff",
861 "gpios", phandle
, 3, 0);
864 #define SECURE_GPIO_POWEROFF 0
865 #define SECURE_GPIO_RESET 1
867 static void create_secure_gpio_pwr(char *fdt
, DeviceState
*pl061_dev
,
870 DeviceState
*gpio_pwr_dev
;
873 gpio_pwr_dev
= sysbus_create_simple("gpio-pwr", -1, NULL
);
875 /* connect secure pl061 to gpio-pwr */
876 qdev_connect_gpio_out(pl061_dev
, SECURE_GPIO_RESET
,
877 qdev_get_gpio_in_named(gpio_pwr_dev
, "reset", 0));
878 qdev_connect_gpio_out(pl061_dev
, SECURE_GPIO_POWEROFF
,
879 qdev_get_gpio_in_named(gpio_pwr_dev
, "shutdown", 0));
881 qemu_fdt_add_subnode(fdt
, "/gpio-poweroff");
882 qemu_fdt_setprop_string(fdt
, "/gpio-poweroff", "compatible",
884 qemu_fdt_setprop_cells(fdt
, "/gpio-poweroff",
885 "gpios", phandle
, SECURE_GPIO_POWEROFF
, 0);
886 qemu_fdt_setprop_string(fdt
, "/gpio-poweroff", "status", "disabled");
887 qemu_fdt_setprop_string(fdt
, "/gpio-poweroff", "secure-status",
890 qemu_fdt_add_subnode(fdt
, "/gpio-restart");
891 qemu_fdt_setprop_string(fdt
, "/gpio-restart", "compatible",
893 qemu_fdt_setprop_cells(fdt
, "/gpio-restart",
894 "gpios", phandle
, SECURE_GPIO_RESET
, 0);
895 qemu_fdt_setprop_string(fdt
, "/gpio-restart", "status", "disabled");
896 qemu_fdt_setprop_string(fdt
, "/gpio-restart", "secure-status",
900 static void create_gpio_devices(const VirtMachineState
*vms
, int gpio
,
904 DeviceState
*pl061_dev
;
905 hwaddr base
= vms
->memmap
[gpio
].base
;
906 hwaddr size
= vms
->memmap
[gpio
].size
;
907 int irq
= vms
->irqmap
[gpio
];
908 const char compat
[] = "arm,pl061\0arm,primecell";
910 MachineState
*ms
= MACHINE(vms
);
912 pl061_dev
= qdev_new("pl061");
913 /* Pull lines down to 0 if not driven by the PL061 */
914 qdev_prop_set_uint32(pl061_dev
, "pullups", 0);
915 qdev_prop_set_uint32(pl061_dev
, "pulldowns", 0xff);
916 s
= SYS_BUS_DEVICE(pl061_dev
);
917 sysbus_realize_and_unref(s
, &error_fatal
);
918 memory_region_add_subregion(mem
, base
, sysbus_mmio_get_region(s
, 0));
919 sysbus_connect_irq(s
, 0, qdev_get_gpio_in(vms
->gic
, irq
));
921 uint32_t phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
922 nodename
= g_strdup_printf("/pl061@%" PRIx64
, base
);
923 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
924 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
926 qemu_fdt_setprop(ms
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
927 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#gpio-cells", 2);
928 qemu_fdt_setprop(ms
->fdt
, nodename
, "gpio-controller", NULL
, 0);
929 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
930 GIC_FDT_IRQ_TYPE_SPI
, irq
,
931 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
932 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "clocks", vms
->clock_phandle
);
933 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "clock-names", "apb_pclk");
934 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", phandle
);
936 if (gpio
!= VIRT_GPIO
) {
937 /* Mark as not usable by the normal world */
938 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
939 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
943 /* Child gpio devices */
944 if (gpio
== VIRT_GPIO
) {
945 create_gpio_keys(ms
->fdt
, pl061_dev
, phandle
);
947 create_secure_gpio_pwr(ms
->fdt
, pl061_dev
, phandle
);
951 static void create_virtio_devices(const VirtMachineState
*vms
)
954 hwaddr size
= vms
->memmap
[VIRT_MMIO
].size
;
955 MachineState
*ms
= MACHINE(vms
);
957 /* We create the transports in forwards order. Since qbus_realize()
958 * prepends (not appends) new child buses, the incrementing loop below will
959 * create a list of virtio-mmio buses with decreasing base addresses.
961 * When a -device option is processed from the command line,
962 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
963 * order. The upshot is that -device options in increasing command line
964 * order are mapped to virtio-mmio buses with decreasing base addresses.
966 * When this code was originally written, that arrangement ensured that the
967 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
968 * the first -device on the command line. (The end-to-end order is a
969 * function of this loop, qbus_realize(), qbus_find_recursive(), and the
970 * guest kernel's name-to-address assignment strategy.)
972 * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
973 * the message, if not necessarily the code, of commit 70161ff336.
974 * Therefore the loop now establishes the inverse of the original intent.
976 * Unfortunately, we can't counteract the kernel change by reversing the
977 * loop; it would break existing command lines.
979 * In any case, the kernel makes no guarantee about the stability of
980 * enumeration order of virtio devices (as demonstrated by it changing
981 * between kernel versions). For reliable and stable identification
982 * of disks users must use UUIDs or similar mechanisms.
984 for (i
= 0; i
< NUM_VIRTIO_TRANSPORTS
; i
++) {
985 int irq
= vms
->irqmap
[VIRT_MMIO
] + i
;
986 hwaddr base
= vms
->memmap
[VIRT_MMIO
].base
+ i
* size
;
988 sysbus_create_simple("virtio-mmio", base
,
989 qdev_get_gpio_in(vms
->gic
, irq
));
992 /* We add dtb nodes in reverse order so that they appear in the finished
993 * device tree lowest address first.
995 * Note that this mapping is independent of the loop above. The previous
996 * loop influences virtio device to virtio transport assignment, whereas
997 * this loop controls how virtio transports are laid out in the dtb.
999 for (i
= NUM_VIRTIO_TRANSPORTS
- 1; i
>= 0; i
--) {
1001 int irq
= vms
->irqmap
[VIRT_MMIO
] + i
;
1002 hwaddr base
= vms
->memmap
[VIRT_MMIO
].base
+ i
* size
;
1004 nodename
= g_strdup_printf("/virtio_mmio@%" PRIx64
, base
);
1005 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1006 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
1007 "compatible", "virtio,mmio");
1008 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1010 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
1011 GIC_FDT_IRQ_TYPE_SPI
, irq
,
1012 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
1013 qemu_fdt_setprop(ms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1018 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
1020 static PFlashCFI01
*virt_flash_create1(VirtMachineState
*vms
,
1022 const char *alias_prop_name
)
1025 * Create a single flash device. We use the same parameters as
1026 * the flash devices on the Versatile Express board.
1028 DeviceState
*dev
= qdev_new(TYPE_PFLASH_CFI01
);
1030 qdev_prop_set_uint64(dev
, "sector-length", VIRT_FLASH_SECTOR_SIZE
);
1031 qdev_prop_set_uint8(dev
, "width", 4);
1032 qdev_prop_set_uint8(dev
, "device-width", 2);
1033 qdev_prop_set_bit(dev
, "big-endian", false);
1034 qdev_prop_set_uint16(dev
, "id0", 0x89);
1035 qdev_prop_set_uint16(dev
, "id1", 0x18);
1036 qdev_prop_set_uint16(dev
, "id2", 0x00);
1037 qdev_prop_set_uint16(dev
, "id3", 0x00);
1038 qdev_prop_set_string(dev
, "name", name
);
1039 object_property_add_child(OBJECT(vms
), name
, OBJECT(dev
));
1040 object_property_add_alias(OBJECT(vms
), alias_prop_name
,
1041 OBJECT(dev
), "drive");
1042 return PFLASH_CFI01(dev
);
1045 static void virt_flash_create(VirtMachineState
*vms
)
1047 vms
->flash
[0] = virt_flash_create1(vms
, "virt.flash0", "pflash0");
1048 vms
->flash
[1] = virt_flash_create1(vms
, "virt.flash1", "pflash1");
1051 static void virt_flash_map1(PFlashCFI01
*flash
,
1052 hwaddr base
, hwaddr size
,
1053 MemoryRegion
*sysmem
)
1055 DeviceState
*dev
= DEVICE(flash
);
1057 assert(QEMU_IS_ALIGNED(size
, VIRT_FLASH_SECTOR_SIZE
));
1058 assert(size
/ VIRT_FLASH_SECTOR_SIZE
<= UINT32_MAX
);
1059 qdev_prop_set_uint32(dev
, "num-blocks", size
/ VIRT_FLASH_SECTOR_SIZE
);
1060 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1062 memory_region_add_subregion(sysmem
, base
,
1063 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
),
1067 static void virt_flash_map(VirtMachineState
*vms
,
1068 MemoryRegion
*sysmem
,
1069 MemoryRegion
*secure_sysmem
)
1072 * Map two flash devices to fill the VIRT_FLASH space in the memmap.
1073 * sysmem is the system memory space. secure_sysmem is the secure view
1074 * of the system, and the first flash device should be made visible only
1075 * there. The second flash device is visible to both secure and nonsecure.
1076 * If sysmem == secure_sysmem this means there is no separate Secure
1077 * address space and both flash devices are generally visible.
1079 hwaddr flashsize
= vms
->memmap
[VIRT_FLASH
].size
/ 2;
1080 hwaddr flashbase
= vms
->memmap
[VIRT_FLASH
].base
;
1082 virt_flash_map1(vms
->flash
[0], flashbase
, flashsize
,
1084 virt_flash_map1(vms
->flash
[1], flashbase
+ flashsize
, flashsize
,
1088 static void virt_flash_fdt(VirtMachineState
*vms
,
1089 MemoryRegion
*sysmem
,
1090 MemoryRegion
*secure_sysmem
)
1092 hwaddr flashsize
= vms
->memmap
[VIRT_FLASH
].size
/ 2;
1093 hwaddr flashbase
= vms
->memmap
[VIRT_FLASH
].base
;
1094 MachineState
*ms
= MACHINE(vms
);
1097 if (sysmem
== secure_sysmem
) {
1098 /* Report both flash devices as a single node in the DT */
1099 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
1100 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1101 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible", "cfi-flash");
1102 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1103 2, flashbase
, 2, flashsize
,
1104 2, flashbase
+ flashsize
, 2, flashsize
);
1105 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "bank-width", 4);
1109 * Report the devices as separate nodes so we can mark one as
1110 * only visible to the secure world.
1112 nodename
= g_strdup_printf("/secflash@%" PRIx64
, flashbase
);
1113 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1114 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible", "cfi-flash");
1115 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1116 2, flashbase
, 2, flashsize
);
1117 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "bank-width", 4);
1118 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
1119 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
1122 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
1123 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1124 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible", "cfi-flash");
1125 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1126 2, flashbase
+ flashsize
, 2, flashsize
);
1127 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "bank-width", 4);
1132 static bool virt_firmware_init(VirtMachineState
*vms
,
1133 MemoryRegion
*sysmem
,
1134 MemoryRegion
*secure_sysmem
)
1137 const char *bios_name
;
1138 BlockBackend
*pflash_blk0
;
1140 /* Map legacy -drive if=pflash to machine properties */
1141 for (i
= 0; i
< ARRAY_SIZE(vms
->flash
); i
++) {
1142 pflash_cfi01_legacy_drive(vms
->flash
[i
],
1143 drive_get(IF_PFLASH
, 0, i
));
1146 virt_flash_map(vms
, sysmem
, secure_sysmem
);
1148 pflash_blk0
= pflash_cfi01_get_blk(vms
->flash
[0]);
1150 bios_name
= MACHINE(vms
)->firmware
;
1157 error_report("The contents of the first flash device may be "
1158 "specified with -bios or with -drive if=pflash... "
1159 "but you cannot use both options at once");
1163 /* Fall back to -bios */
1165 fname
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
1167 error_report("Could not find ROM image '%s'", bios_name
);
1170 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(vms
->flash
[0]), 0);
1171 image_size
= load_image_mr(fname
, mr
);
1173 if (image_size
< 0) {
1174 error_report("Could not load ROM image '%s'", bios_name
);
1179 return pflash_blk0
|| bios_name
;
1182 static FWCfgState
*create_fw_cfg(const VirtMachineState
*vms
, AddressSpace
*as
)
1184 MachineState
*ms
= MACHINE(vms
);
1185 hwaddr base
= vms
->memmap
[VIRT_FW_CFG
].base
;
1186 hwaddr size
= vms
->memmap
[VIRT_FW_CFG
].size
;
1190 fw_cfg
= fw_cfg_init_mem_wide(base
+ 8, base
, 8, base
+ 16, as
);
1191 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, (uint16_t)ms
->smp
.cpus
);
1193 nodename
= g_strdup_printf("/fw-cfg@%" PRIx64
, base
);
1194 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1195 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
1196 "compatible", "qemu,fw-cfg-mmio");
1197 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1199 qemu_fdt_setprop(ms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1204 static void create_pcie_irq_map(const MachineState
*ms
,
1205 uint32_t gic_phandle
,
1206 int first_irq
, const char *nodename
)
1209 uint32_t full_irq_map
[4 * 4 * 10] = { 0 };
1210 uint32_t *irq_map
= full_irq_map
;
1212 for (devfn
= 0; devfn
<= 0x18; devfn
+= 0x8) {
1213 for (pin
= 0; pin
< 4; pin
++) {
1214 int irq_type
= GIC_FDT_IRQ_TYPE_SPI
;
1215 int irq_nr
= first_irq
+ ((pin
+ PCI_SLOT(devfn
)) % PCI_NUM_PINS
);
1216 int irq_level
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
1220 devfn
<< 8, 0, 0, /* devfn */
1221 pin
+ 1, /* PCI pin */
1222 gic_phandle
, 0, 0, irq_type
, irq_nr
, irq_level
}; /* GIC irq */
1224 /* Convert map to big endian */
1225 for (i
= 0; i
< 10; i
++) {
1226 irq_map
[i
] = cpu_to_be32(map
[i
]);
1232 qemu_fdt_setprop(ms
->fdt
, nodename
, "interrupt-map",
1233 full_irq_map
, sizeof(full_irq_map
));
1235 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupt-map-mask",
1236 cpu_to_be16(PCI_DEVFN(3, 0)), /* Slot 3 */
1241 static void create_smmu(const VirtMachineState
*vms
,
1245 const char compat
[] = "arm,smmu-v3";
1246 int irq
= vms
->irqmap
[VIRT_SMMU
];
1248 hwaddr base
= vms
->memmap
[VIRT_SMMU
].base
;
1249 hwaddr size
= vms
->memmap
[VIRT_SMMU
].size
;
1250 const char irq_names
[] = "eventq\0priq\0cmdq-sync\0gerror";
1252 MachineState
*ms
= MACHINE(vms
);
1254 if (vms
->iommu
!= VIRT_IOMMU_SMMUV3
|| !vms
->iommu_phandle
) {
1258 dev
= qdev_new("arm-smmuv3");
1260 object_property_set_link(OBJECT(dev
), "primary-bus", OBJECT(bus
),
1262 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1263 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, base
);
1264 for (i
= 0; i
< NUM_SMMU_IRQS
; i
++) {
1265 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
1266 qdev_get_gpio_in(vms
->gic
, irq
+ i
));
1269 node
= g_strdup_printf("/smmuv3@%" PRIx64
, base
);
1270 qemu_fdt_add_subnode(ms
->fdt
, node
);
1271 qemu_fdt_setprop(ms
->fdt
, node
, "compatible", compat
, sizeof(compat
));
1272 qemu_fdt_setprop_sized_cells(ms
->fdt
, node
, "reg", 2, base
, 2, size
);
1274 qemu_fdt_setprop_cells(ms
->fdt
, node
, "interrupts",
1275 GIC_FDT_IRQ_TYPE_SPI
, irq
, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1276 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1277 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1278 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
1280 qemu_fdt_setprop(ms
->fdt
, node
, "interrupt-names", irq_names
,
1283 qemu_fdt_setprop_cell(ms
->fdt
, node
, "clocks", vms
->clock_phandle
);
1284 qemu_fdt_setprop_string(ms
->fdt
, node
, "clock-names", "apb_pclk");
1285 qemu_fdt_setprop(ms
->fdt
, node
, "dma-coherent", NULL
, 0);
1287 qemu_fdt_setprop_cell(ms
->fdt
, node
, "#iommu-cells", 1);
1289 qemu_fdt_setprop_cell(ms
->fdt
, node
, "phandle", vms
->iommu_phandle
);
1293 static void create_virtio_iommu_dt_bindings(VirtMachineState
*vms
)
1295 const char compat
[] = "virtio,pci-iommu";
1296 uint16_t bdf
= vms
->virtio_iommu_bdf
;
1297 MachineState
*ms
= MACHINE(vms
);
1300 vms
->iommu_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
1302 node
= g_strdup_printf("%s/virtio_iommu@%d", vms
->pciehb_nodename
, bdf
);
1303 qemu_fdt_add_subnode(ms
->fdt
, node
);
1304 qemu_fdt_setprop(ms
->fdt
, node
, "compatible", compat
, sizeof(compat
));
1305 qemu_fdt_setprop_sized_cells(ms
->fdt
, node
, "reg",
1306 1, bdf
<< 8, 1, 0, 1, 0,
1309 qemu_fdt_setprop_cell(ms
->fdt
, node
, "#iommu-cells", 1);
1310 qemu_fdt_setprop_cell(ms
->fdt
, node
, "phandle", vms
->iommu_phandle
);
1313 qemu_fdt_setprop_cells(ms
->fdt
, vms
->pciehb_nodename
, "iommu-map",
1314 0x0, vms
->iommu_phandle
, 0x0, bdf
,
1315 bdf
+ 1, vms
->iommu_phandle
, bdf
+ 1, 0xffff - bdf
);
1318 static void create_pcie(VirtMachineState
*vms
)
1320 hwaddr base_mmio
= vms
->memmap
[VIRT_PCIE_MMIO
].base
;
1321 hwaddr size_mmio
= vms
->memmap
[VIRT_PCIE_MMIO
].size
;
1322 hwaddr base_mmio_high
= vms
->memmap
[VIRT_HIGH_PCIE_MMIO
].base
;
1323 hwaddr size_mmio_high
= vms
->memmap
[VIRT_HIGH_PCIE_MMIO
].size
;
1324 hwaddr base_pio
= vms
->memmap
[VIRT_PCIE_PIO
].base
;
1325 hwaddr size_pio
= vms
->memmap
[VIRT_PCIE_PIO
].size
;
1326 hwaddr base_ecam
, size_ecam
;
1327 hwaddr base
= base_mmio
;
1329 int irq
= vms
->irqmap
[VIRT_PCIE
];
1330 MemoryRegion
*mmio_alias
;
1331 MemoryRegion
*mmio_reg
;
1332 MemoryRegion
*ecam_alias
;
1333 MemoryRegion
*ecam_reg
;
1338 MachineState
*ms
= MACHINE(vms
);
1340 dev
= qdev_new(TYPE_GPEX_HOST
);
1341 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1343 ecam_id
= VIRT_ECAM_ID(vms
->highmem_ecam
);
1344 base_ecam
= vms
->memmap
[ecam_id
].base
;
1345 size_ecam
= vms
->memmap
[ecam_id
].size
;
1346 nr_pcie_buses
= size_ecam
/ PCIE_MMCFG_SIZE_MIN
;
1347 /* Map only the first size_ecam bytes of ECAM space */
1348 ecam_alias
= g_new0(MemoryRegion
, 1);
1349 ecam_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0);
1350 memory_region_init_alias(ecam_alias
, OBJECT(dev
), "pcie-ecam",
1351 ecam_reg
, 0, size_ecam
);
1352 memory_region_add_subregion(get_system_memory(), base_ecam
, ecam_alias
);
1354 /* Map the MMIO window into system address space so as to expose
1355 * the section of PCI MMIO space which starts at the same base address
1356 * (ie 1:1 mapping for that part of PCI MMIO space visible through
1359 mmio_alias
= g_new0(MemoryRegion
, 1);
1360 mmio_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 1);
1361 memory_region_init_alias(mmio_alias
, OBJECT(dev
), "pcie-mmio",
1362 mmio_reg
, base_mmio
, size_mmio
);
1363 memory_region_add_subregion(get_system_memory(), base_mmio
, mmio_alias
);
1366 /* Map high MMIO space */
1367 MemoryRegion
*high_mmio_alias
= g_new0(MemoryRegion
, 1);
1369 memory_region_init_alias(high_mmio_alias
, OBJECT(dev
), "pcie-mmio-high",
1370 mmio_reg
, base_mmio_high
, size_mmio_high
);
1371 memory_region_add_subregion(get_system_memory(), base_mmio_high
,
1375 /* Map IO port space */
1376 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 2, base_pio
);
1378 for (i
= 0; i
< GPEX_NUM_IRQS
; i
++) {
1379 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
1380 qdev_get_gpio_in(vms
->gic
, irq
+ i
));
1381 gpex_set_irq_num(GPEX_HOST(dev
), i
, irq
+ i
);
1384 pci
= PCI_HOST_BRIDGE(dev
);
1385 pci
->bypass_iommu
= vms
->default_bus_bypass_iommu
;
1386 vms
->bus
= pci
->bus
;
1388 for (i
= 0; i
< nb_nics
; i
++) {
1389 NICInfo
*nd
= &nd_table
[i
];
1392 nd
->model
= g_strdup("virtio");
1395 pci_nic_init_nofail(nd
, pci
->bus
, nd
->model
, NULL
);
1399 nodename
= vms
->pciehb_nodename
= g_strdup_printf("/pcie@%" PRIx64
, base
);
1400 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1401 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
1402 "compatible", "pci-host-ecam-generic");
1403 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "device_type", "pci");
1404 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#address-cells", 3);
1405 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#size-cells", 2);
1406 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "linux,pci-domain", 0);
1407 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "bus-range", 0,
1409 qemu_fdt_setprop(ms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1411 if (vms
->msi_phandle
) {
1412 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "msi-parent",
1416 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1417 2, base_ecam
, 2, size_ecam
);
1420 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "ranges",
1421 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1422 2, base_pio
, 2, size_pio
,
1423 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1424 2, base_mmio
, 2, size_mmio
,
1425 1, FDT_PCI_RANGE_MMIO_64BIT
,
1427 2, base_mmio_high
, 2, size_mmio_high
);
1429 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "ranges",
1430 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1431 2, base_pio
, 2, size_pio
,
1432 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1433 2, base_mmio
, 2, size_mmio
);
1436 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#interrupt-cells", 1);
1437 create_pcie_irq_map(ms
, vms
->gic_phandle
, irq
, nodename
);
1440 vms
->iommu_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
1442 switch (vms
->iommu
) {
1443 case VIRT_IOMMU_SMMUV3
:
1444 create_smmu(vms
, vms
->bus
);
1445 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "iommu-map",
1446 0x0, vms
->iommu_phandle
, 0x0, 0x10000);
1449 g_assert_not_reached();
1454 static void create_platform_bus(VirtMachineState
*vms
)
1459 MemoryRegion
*sysmem
= get_system_memory();
1461 dev
= qdev_new(TYPE_PLATFORM_BUS_DEVICE
);
1462 dev
->id
= TYPE_PLATFORM_BUS_DEVICE
;
1463 qdev_prop_set_uint32(dev
, "num_irqs", PLATFORM_BUS_NUM_IRQS
);
1464 qdev_prop_set_uint32(dev
, "mmio_size", vms
->memmap
[VIRT_PLATFORM_BUS
].size
);
1465 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1466 vms
->platform_bus_dev
= dev
;
1468 s
= SYS_BUS_DEVICE(dev
);
1469 for (i
= 0; i
< PLATFORM_BUS_NUM_IRQS
; i
++) {
1470 int irq
= vms
->irqmap
[VIRT_PLATFORM_BUS
] + i
;
1471 sysbus_connect_irq(s
, i
, qdev_get_gpio_in(vms
->gic
, irq
));
1474 memory_region_add_subregion(sysmem
,
1475 vms
->memmap
[VIRT_PLATFORM_BUS
].base
,
1476 sysbus_mmio_get_region(s
, 0));
1479 static void create_tag_ram(MemoryRegion
*tag_sysmem
,
1480 hwaddr base
, hwaddr size
,
1483 MemoryRegion
*tagram
= g_new(MemoryRegion
, 1);
1485 memory_region_init_ram(tagram
, NULL
, name
, size
/ 32, &error_fatal
);
1486 memory_region_add_subregion(tag_sysmem
, base
/ 32, tagram
);
1489 static void create_secure_ram(VirtMachineState
*vms
,
1490 MemoryRegion
*secure_sysmem
,
1491 MemoryRegion
*secure_tag_sysmem
)
1493 MemoryRegion
*secram
= g_new(MemoryRegion
, 1);
1495 hwaddr base
= vms
->memmap
[VIRT_SECURE_MEM
].base
;
1496 hwaddr size
= vms
->memmap
[VIRT_SECURE_MEM
].size
;
1497 MachineState
*ms
= MACHINE(vms
);
1499 memory_region_init_ram(secram
, NULL
, "virt.secure-ram", size
,
1501 memory_region_add_subregion(secure_sysmem
, base
, secram
);
1503 nodename
= g_strdup_printf("/secram@%" PRIx64
, base
);
1504 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1505 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "device_type", "memory");
1506 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg", 2, base
, 2, size
);
1507 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
1508 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
1510 if (secure_tag_sysmem
) {
1511 create_tag_ram(secure_tag_sysmem
, base
, size
, "mach-virt.secure-tag");
1517 static void *machvirt_dtb(const struct arm_boot_info
*binfo
, int *fdt_size
)
1519 const VirtMachineState
*board
= container_of(binfo
, VirtMachineState
,
1521 MachineState
*ms
= MACHINE(board
);
1524 *fdt_size
= board
->fdt_size
;
1528 static void virt_build_smbios(VirtMachineState
*vms
)
1530 MachineClass
*mc
= MACHINE_GET_CLASS(vms
);
1531 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
1532 uint8_t *smbios_tables
, *smbios_anchor
;
1533 size_t smbios_tables_len
, smbios_anchor_len
;
1534 const char *product
= "QEMU Virtual Machine";
1536 if (kvm_enabled()) {
1537 product
= "KVM Virtual Machine";
1540 smbios_set_defaults("QEMU", product
,
1541 vmc
->smbios_old_sys_ver
? "1.0" : mc
->name
, false,
1542 true, SMBIOS_ENTRY_POINT_30
);
1544 smbios_get_tables(MACHINE(vms
), NULL
, 0,
1545 &smbios_tables
, &smbios_tables_len
,
1546 &smbios_anchor
, &smbios_anchor_len
,
1549 if (smbios_anchor
) {
1550 fw_cfg_add_file(vms
->fw_cfg
, "etc/smbios/smbios-tables",
1551 smbios_tables
, smbios_tables_len
);
1552 fw_cfg_add_file(vms
->fw_cfg
, "etc/smbios/smbios-anchor",
1553 smbios_anchor
, smbios_anchor_len
);
1558 void virt_machine_done(Notifier
*notifier
, void *data
)
1560 VirtMachineState
*vms
= container_of(notifier
, VirtMachineState
,
1562 MachineState
*ms
= MACHINE(vms
);
1563 ARMCPU
*cpu
= ARM_CPU(first_cpu
);
1564 struct arm_boot_info
*info
= &vms
->bootinfo
;
1565 AddressSpace
*as
= arm_boot_address_space(cpu
, info
);
1568 * If the user provided a dtb, we assume the dynamic sysbus nodes
1569 * already are integrated there. This corresponds to a use case where
1570 * the dynamic sysbus nodes are complex and their generation is not yet
1571 * supported. In that case the user can take charge of the guest dt
1572 * while qemu takes charge of the qom stuff.
1574 if (info
->dtb_filename
== NULL
) {
1575 platform_bus_add_all_fdt_nodes(ms
->fdt
, "/intc",
1576 vms
->memmap
[VIRT_PLATFORM_BUS
].base
,
1577 vms
->memmap
[VIRT_PLATFORM_BUS
].size
,
1578 vms
->irqmap
[VIRT_PLATFORM_BUS
]);
1580 if (arm_load_dtb(info
->dtb_start
, info
, info
->dtb_limit
, as
, ms
) < 0) {
1584 fw_cfg_add_extra_pci_roots(vms
->bus
, vms
->fw_cfg
);
1586 virt_acpi_setup(vms
);
1587 virt_build_smbios(vms
);
1590 static uint64_t virt_cpu_mp_affinity(VirtMachineState
*vms
, int idx
)
1592 uint8_t clustersz
= ARM_DEFAULT_CPUS_PER_CLUSTER
;
1593 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
1595 if (!vmc
->disallow_affinity_adjustment
) {
1596 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the
1597 * GIC's target-list limitations. 32-bit KVM hosts currently
1598 * always create clusters of 4 CPUs, but that is expected to
1599 * change when they gain support for gicv3. When KVM is enabled
1600 * it will override the changes we make here, therefore our
1601 * purposes are to make TCG consistent (with 64-bit KVM hosts)
1602 * and to improve SGI efficiency.
1604 if (vms
->gic_version
== VIRT_GIC_VERSION_3
) {
1605 clustersz
= GICV3_TARGETLIST_BITS
;
1607 clustersz
= GIC_TARGETLIST_BITS
;
1610 return arm_cpu_mp_affinity(idx
, clustersz
);
1613 static void virt_set_memmap(VirtMachineState
*vms
)
1615 MachineState
*ms
= MACHINE(vms
);
1616 hwaddr base
, device_memory_base
, device_memory_size
;
1619 vms
->memmap
= extended_memmap
;
1621 for (i
= 0; i
< ARRAY_SIZE(base_memmap
); i
++) {
1622 vms
->memmap
[i
] = base_memmap
[i
];
1625 if (ms
->ram_slots
> ACPI_MAX_RAM_SLOTS
) {
1626 error_report("unsupported number of memory slots: %"PRIu64
,
1632 * We compute the base of the high IO region depending on the
1633 * amount of initial and device memory. The device memory start/size
1634 * is aligned on 1GiB. We never put the high IO region below 256GiB
1635 * so that if maxram_size is < 255GiB we keep the legacy memory map.
1636 * The device region size assumes 1GiB page max alignment per slot.
1638 device_memory_base
=
1639 ROUND_UP(vms
->memmap
[VIRT_MEM
].base
+ ms
->ram_size
, GiB
);
1640 device_memory_size
= ms
->maxram_size
- ms
->ram_size
+ ms
->ram_slots
* GiB
;
1642 /* Base address of the high IO region */
1643 base
= device_memory_base
+ ROUND_UP(device_memory_size
, GiB
);
1644 if (base
< device_memory_base
) {
1645 error_report("maxmem/slots too huge");
1648 if (base
< vms
->memmap
[VIRT_MEM
].base
+ LEGACY_RAMLIMIT_BYTES
) {
1649 base
= vms
->memmap
[VIRT_MEM
].base
+ LEGACY_RAMLIMIT_BYTES
;
1652 for (i
= VIRT_LOWMEMMAP_LAST
; i
< ARRAY_SIZE(extended_memmap
); i
++) {
1653 hwaddr size
= extended_memmap
[i
].size
;
1655 base
= ROUND_UP(base
, size
);
1656 vms
->memmap
[i
].base
= base
;
1657 vms
->memmap
[i
].size
= size
;
1660 vms
->highest_gpa
= base
- 1;
1661 if (device_memory_size
> 0) {
1662 ms
->device_memory
= g_malloc0(sizeof(*ms
->device_memory
));
1663 ms
->device_memory
->base
= device_memory_base
;
1664 memory_region_init(&ms
->device_memory
->mr
, OBJECT(vms
),
1665 "device-memory", device_memory_size
);
1670 * finalize_gic_version - Determines the final gic_version
1671 * according to the gic-version property
1673 * Default GIC type is v2
1675 static void finalize_gic_version(VirtMachineState
*vms
)
1677 unsigned int max_cpus
= MACHINE(vms
)->smp
.max_cpus
;
1679 if (kvm_enabled()) {
1682 if (!kvm_irqchip_in_kernel()) {
1683 switch (vms
->gic_version
) {
1684 case VIRT_GIC_VERSION_HOST
:
1686 "gic-version=host not relevant with kernel-irqchip=off "
1687 "as only userspace GICv2 is supported. Using v2 ...");
1689 case VIRT_GIC_VERSION_MAX
:
1690 case VIRT_GIC_VERSION_NOSEL
:
1691 vms
->gic_version
= VIRT_GIC_VERSION_2
;
1693 case VIRT_GIC_VERSION_2
:
1695 case VIRT_GIC_VERSION_3
:
1697 "gic-version=3 is not supported with kernel-irqchip=off");
1702 probe_bitmap
= kvm_arm_vgic_probe();
1703 if (!probe_bitmap
) {
1704 error_report("Unable to determine GIC version supported by host");
1708 switch (vms
->gic_version
) {
1709 case VIRT_GIC_VERSION_HOST
:
1710 case VIRT_GIC_VERSION_MAX
:
1711 if (probe_bitmap
& KVM_ARM_VGIC_V3
) {
1712 vms
->gic_version
= VIRT_GIC_VERSION_3
;
1714 vms
->gic_version
= VIRT_GIC_VERSION_2
;
1717 case VIRT_GIC_VERSION_NOSEL
:
1718 if ((probe_bitmap
& KVM_ARM_VGIC_V2
) && max_cpus
<= GIC_NCPU
) {
1719 vms
->gic_version
= VIRT_GIC_VERSION_2
;
1720 } else if (probe_bitmap
& KVM_ARM_VGIC_V3
) {
1722 * in case the host does not support v2 in-kernel emulation or
1723 * the end-user requested more than 8 VCPUs we now default
1724 * to v3. In any case defaulting to v2 would be broken.
1726 vms
->gic_version
= VIRT_GIC_VERSION_3
;
1727 } else if (max_cpus
> GIC_NCPU
) {
1728 error_report("host only supports in-kernel GICv2 emulation "
1729 "but more than 8 vcpus are requested");
1733 case VIRT_GIC_VERSION_2
:
1734 case VIRT_GIC_VERSION_3
:
1738 /* Check chosen version is effectively supported by the host */
1739 if (vms
->gic_version
== VIRT_GIC_VERSION_2
&&
1740 !(probe_bitmap
& KVM_ARM_VGIC_V2
)) {
1741 error_report("host does not support in-kernel GICv2 emulation");
1743 } else if (vms
->gic_version
== VIRT_GIC_VERSION_3
&&
1744 !(probe_bitmap
& KVM_ARM_VGIC_V3
)) {
1745 error_report("host does not support in-kernel GICv3 emulation");
1752 switch (vms
->gic_version
) {
1753 case VIRT_GIC_VERSION_NOSEL
:
1754 vms
->gic_version
= VIRT_GIC_VERSION_2
;
1756 case VIRT_GIC_VERSION_MAX
:
1757 vms
->gic_version
= VIRT_GIC_VERSION_3
;
1759 case VIRT_GIC_VERSION_HOST
:
1760 error_report("gic-version=host requires KVM");
1762 case VIRT_GIC_VERSION_2
:
1763 case VIRT_GIC_VERSION_3
:
1769 * virt_cpu_post_init() must be called after the CPUs have
1770 * been realized and the GIC has been created.
1772 static void virt_cpu_post_init(VirtMachineState
*vms
, MemoryRegion
*sysmem
)
1774 int max_cpus
= MACHINE(vms
)->smp
.max_cpus
;
1775 bool aarch64
, pmu
, steal_time
;
1778 aarch64
= object_property_get_bool(OBJECT(first_cpu
), "aarch64", NULL
);
1779 pmu
= object_property_get_bool(OBJECT(first_cpu
), "pmu", NULL
);
1780 steal_time
= object_property_get_bool(OBJECT(first_cpu
),
1781 "kvm-steal-time", NULL
);
1783 if (kvm_enabled()) {
1784 hwaddr pvtime_reg_base
= vms
->memmap
[VIRT_PVTIME
].base
;
1785 hwaddr pvtime_reg_size
= vms
->memmap
[VIRT_PVTIME
].size
;
1788 MemoryRegion
*pvtime
= g_new(MemoryRegion
, 1);
1789 hwaddr pvtime_size
= max_cpus
* PVTIME_SIZE_PER_CPU
;
1791 /* The memory region size must be a multiple of host page size. */
1792 pvtime_size
= REAL_HOST_PAGE_ALIGN(pvtime_size
);
1794 if (pvtime_size
> pvtime_reg_size
) {
1795 error_report("pvtime requires a %" HWADDR_PRId
1796 " byte memory region for %d CPUs,"
1797 " but only %" HWADDR_PRId
" has been reserved",
1798 pvtime_size
, max_cpus
, pvtime_reg_size
);
1802 memory_region_init_ram(pvtime
, NULL
, "pvtime", pvtime_size
, NULL
);
1803 memory_region_add_subregion(sysmem
, pvtime_reg_base
, pvtime
);
1808 assert(arm_feature(&ARM_CPU(cpu
)->env
, ARM_FEATURE_PMU
));
1809 if (kvm_irqchip_in_kernel()) {
1810 kvm_arm_pmu_set_irq(cpu
, PPI(VIRTUAL_PMU_IRQ
));
1812 kvm_arm_pmu_init(cpu
);
1815 kvm_arm_pvtime_init(cpu
, pvtime_reg_base
+
1816 cpu
->cpu_index
* PVTIME_SIZE_PER_CPU
);
1820 if (aarch64
&& vms
->highmem
) {
1821 int requested_pa_size
= 64 - clz64(vms
->highest_gpa
);
1822 int pamax
= arm_pamax(ARM_CPU(first_cpu
));
1824 if (pamax
< requested_pa_size
) {
1825 error_report("VCPU supports less PA bits (%d) than "
1826 "requested by the memory map (%d)",
1827 pamax
, requested_pa_size
);
1834 static void machvirt_init(MachineState
*machine
)
1836 VirtMachineState
*vms
= VIRT_MACHINE(machine
);
1837 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(machine
);
1838 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
1839 const CPUArchIdList
*possible_cpus
;
1840 MemoryRegion
*sysmem
= get_system_memory();
1841 MemoryRegion
*secure_sysmem
= NULL
;
1842 MemoryRegion
*tag_sysmem
= NULL
;
1843 MemoryRegion
*secure_tag_sysmem
= NULL
;
1844 int n
, virt_max_cpus
;
1845 bool firmware_loaded
;
1846 bool aarch64
= true;
1847 bool has_ged
= !vmc
->no_ged
;
1848 unsigned int smp_cpus
= machine
->smp
.cpus
;
1849 unsigned int max_cpus
= machine
->smp
.max_cpus
;
1852 * In accelerated mode, the memory map is computed earlier in kvm_type()
1853 * to create a VM with the right number of IPA bits.
1856 virt_set_memmap(vms
);
1859 /* We can probe only here because during property set
1860 * KVM is not available yet
1862 finalize_gic_version(vms
);
1864 if (!cpu_type_valid(machine
->cpu_type
)) {
1865 error_report("mach-virt: CPU type %s not supported", machine
->cpu_type
);
1871 * The Secure view of the world is the same as the NonSecure,
1872 * but with a few extra devices. Create it as a container region
1873 * containing the system memory at low priority; any secure-only
1874 * devices go in at higher priority and take precedence.
1876 secure_sysmem
= g_new(MemoryRegion
, 1);
1877 memory_region_init(secure_sysmem
, OBJECT(machine
), "secure-memory",
1879 memory_region_add_subregion_overlap(secure_sysmem
, 0, sysmem
, -1);
1882 firmware_loaded
= virt_firmware_init(vms
, sysmem
,
1883 secure_sysmem
?: sysmem
);
1885 /* If we have an EL3 boot ROM then the assumption is that it will
1886 * implement PSCI itself, so disable QEMU's internal implementation
1887 * so it doesn't get in the way. Instead of starting secondary
1888 * CPUs in PSCI powerdown state we will start them all running and
1889 * let the boot ROM sort them out.
1890 * The usual case is that we do use QEMU's PSCI implementation;
1891 * if the guest has EL2 then we will use SMC as the conduit,
1892 * and otherwise we will use HVC (for backwards compatibility and
1893 * because if we're using KVM then we must use HVC).
1895 if (vms
->secure
&& firmware_loaded
) {
1896 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_DISABLED
;
1897 } else if (vms
->virt
) {
1898 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_SMC
;
1900 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_HVC
;
1903 /* The maximum number of CPUs depends on the GIC version, or on how
1904 * many redistributors we can fit into the memory map.
1906 if (vms
->gic_version
== VIRT_GIC_VERSION_3
) {
1908 vms
->memmap
[VIRT_GIC_REDIST
].size
/ GICV3_REDIST_SIZE
;
1910 vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].size
/ GICV3_REDIST_SIZE
;
1912 virt_max_cpus
= GIC_NCPU
;
1915 if (max_cpus
> virt_max_cpus
) {
1916 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
1917 "supported by machine 'mach-virt' (%d)",
1918 max_cpus
, virt_max_cpus
);
1922 if (vms
->virt
&& kvm_enabled()) {
1923 error_report("mach-virt: KVM does not support providing "
1924 "Virtualization extensions to the guest CPU");
1928 if (vms
->mte
&& kvm_enabled()) {
1929 error_report("mach-virt: KVM does not support providing "
1930 "MTE to the guest CPU");
1936 possible_cpus
= mc
->possible_cpu_arch_ids(machine
);
1937 assert(possible_cpus
->len
== max_cpus
);
1938 for (n
= 0; n
< possible_cpus
->len
; n
++) {
1942 if (n
>= smp_cpus
) {
1946 cpuobj
= object_new(possible_cpus
->cpus
[n
].type
);
1947 object_property_set_int(cpuobj
, "mp-affinity",
1948 possible_cpus
->cpus
[n
].arch_id
, NULL
);
1953 numa_cpu_pre_plug(&possible_cpus
->cpus
[cs
->cpu_index
], DEVICE(cpuobj
),
1956 aarch64
&= object_property_get_bool(cpuobj
, "aarch64", NULL
);
1959 object_property_set_bool(cpuobj
, "has_el3", false, NULL
);
1962 if (!vms
->virt
&& object_property_find(cpuobj
, "has_el2")) {
1963 object_property_set_bool(cpuobj
, "has_el2", false, NULL
);
1966 if (vms
->psci_conduit
!= QEMU_PSCI_CONDUIT_DISABLED
) {
1967 object_property_set_int(cpuobj
, "psci-conduit", vms
->psci_conduit
,
1970 /* Secondary CPUs start in PSCI powered-down state */
1972 object_property_set_bool(cpuobj
, "start-powered-off", true,
1977 if (vmc
->kvm_no_adjvtime
&&
1978 object_property_find(cpuobj
, "kvm-no-adjvtime")) {
1979 object_property_set_bool(cpuobj
, "kvm-no-adjvtime", true, NULL
);
1982 if (vmc
->no_kvm_steal_time
&&
1983 object_property_find(cpuobj
, "kvm-steal-time")) {
1984 object_property_set_bool(cpuobj
, "kvm-steal-time", false, NULL
);
1987 if (vmc
->no_pmu
&& object_property_find(cpuobj
, "pmu")) {
1988 object_property_set_bool(cpuobj
, "pmu", false, NULL
);
1991 if (object_property_find(cpuobj
, "reset-cbar")) {
1992 object_property_set_int(cpuobj
, "reset-cbar",
1993 vms
->memmap
[VIRT_CPUPERIPHS
].base
,
1997 object_property_set_link(cpuobj
, "memory", OBJECT(sysmem
),
2000 object_property_set_link(cpuobj
, "secure-memory",
2001 OBJECT(secure_sysmem
), &error_abort
);
2005 /* Create the memory region only once, but link to all cpus. */
2008 * The property exists only if MemTag is supported.
2009 * If it is, we must allocate the ram to back that up.
2011 if (!object_property_find(cpuobj
, "tag-memory")) {
2012 error_report("MTE requested, but not supported "
2013 "by the guest CPU");
2017 tag_sysmem
= g_new(MemoryRegion
, 1);
2018 memory_region_init(tag_sysmem
, OBJECT(machine
),
2019 "tag-memory", UINT64_MAX
/ 32);
2022 secure_tag_sysmem
= g_new(MemoryRegion
, 1);
2023 memory_region_init(secure_tag_sysmem
, OBJECT(machine
),
2024 "secure-tag-memory", UINT64_MAX
/ 32);
2026 /* As with ram, secure-tag takes precedence over tag. */
2027 memory_region_add_subregion_overlap(secure_tag_sysmem
, 0,
2032 object_property_set_link(cpuobj
, "tag-memory", OBJECT(tag_sysmem
),
2035 object_property_set_link(cpuobj
, "secure-tag-memory",
2036 OBJECT(secure_tag_sysmem
),
2041 qdev_realize(DEVICE(cpuobj
), NULL
, &error_fatal
);
2042 object_unref(cpuobj
);
2044 fdt_add_timer_nodes(vms
);
2045 fdt_add_cpu_nodes(vms
);
2047 memory_region_add_subregion(sysmem
, vms
->memmap
[VIRT_MEM
].base
,
2049 if (machine
->device_memory
) {
2050 memory_region_add_subregion(sysmem
, machine
->device_memory
->base
,
2051 &machine
->device_memory
->mr
);
2054 virt_flash_fdt(vms
, sysmem
, secure_sysmem
?: sysmem
);
2056 create_gic(vms
, sysmem
);
2058 virt_cpu_post_init(vms
, sysmem
);
2060 fdt_add_pmu_nodes(vms
);
2062 create_uart(vms
, VIRT_UART
, sysmem
, serial_hd(0));
2065 create_secure_ram(vms
, secure_sysmem
, secure_tag_sysmem
);
2066 create_uart(vms
, VIRT_SECURE_UART
, secure_sysmem
, serial_hd(1));
2070 create_tag_ram(tag_sysmem
, vms
->memmap
[VIRT_MEM
].base
,
2071 machine
->ram_size
, "mach-virt.tag");
2074 vms
->highmem_ecam
&= vms
->highmem
&& (!firmware_loaded
|| aarch64
);
2080 if (has_ged
&& aarch64
&& firmware_loaded
&& virt_is_acpi_enabled(vms
)) {
2081 vms
->acpi_dev
= create_acpi_ged(vms
);
2083 create_gpio_devices(vms
, VIRT_GPIO
, sysmem
);
2086 if (vms
->secure
&& !vmc
->no_secure_gpio
) {
2087 create_gpio_devices(vms
, VIRT_SECURE_GPIO
, secure_sysmem
);
2090 /* connect powerdown request */
2091 vms
->powerdown_notifier
.notify
= virt_powerdown_req
;
2092 qemu_register_powerdown_notifier(&vms
->powerdown_notifier
);
2094 /* Create mmio transports, so the user can create virtio backends
2095 * (which will be automatically plugged in to the transports). If
2096 * no backend is created the transport will just sit harmlessly idle.
2098 create_virtio_devices(vms
);
2100 vms
->fw_cfg
= create_fw_cfg(vms
, &address_space_memory
);
2101 rom_set_fw(vms
->fw_cfg
);
2103 create_platform_bus(vms
);
2105 if (machine
->nvdimms_state
->is_enabled
) {
2106 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio
= {
2107 .space_id
= AML_AS_SYSTEM_MEMORY
,
2108 .address
= vms
->memmap
[VIRT_NVDIMM_ACPI
].base
,
2109 .bit_width
= NVDIMM_ACPI_IO_LEN
<< 3
2112 nvdimm_init_acpi_state(machine
->nvdimms_state
, sysmem
,
2113 arm_virt_nvdimm_acpi_dsmio
,
2114 vms
->fw_cfg
, OBJECT(vms
));
2117 vms
->bootinfo
.ram_size
= machine
->ram_size
;
2118 vms
->bootinfo
.nb_cpus
= smp_cpus
;
2119 vms
->bootinfo
.board_id
= -1;
2120 vms
->bootinfo
.loader_start
= vms
->memmap
[VIRT_MEM
].base
;
2121 vms
->bootinfo
.get_dtb
= machvirt_dtb
;
2122 vms
->bootinfo
.skip_dtb_autoload
= true;
2123 vms
->bootinfo
.firmware_loaded
= firmware_loaded
;
2124 arm_load_kernel(ARM_CPU(first_cpu
), machine
, &vms
->bootinfo
);
2126 vms
->machine_done
.notify
= virt_machine_done
;
2127 qemu_add_machine_init_done_notifier(&vms
->machine_done
);
2130 static bool virt_get_secure(Object
*obj
, Error
**errp
)
2132 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2137 static void virt_set_secure(Object
*obj
, bool value
, Error
**errp
)
2139 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2141 vms
->secure
= value
;
2144 static bool virt_get_virt(Object
*obj
, Error
**errp
)
2146 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2151 static void virt_set_virt(Object
*obj
, bool value
, Error
**errp
)
2153 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2158 static bool virt_get_highmem(Object
*obj
, Error
**errp
)
2160 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2162 return vms
->highmem
;
2165 static void virt_set_highmem(Object
*obj
, bool value
, Error
**errp
)
2167 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2169 vms
->highmem
= value
;
2172 static bool virt_get_its(Object
*obj
, Error
**errp
)
2174 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2179 static void virt_set_its(Object
*obj
, bool value
, Error
**errp
)
2181 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2186 static char *virt_get_oem_id(Object
*obj
, Error
**errp
)
2188 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2190 return g_strdup(vms
->oem_id
);
2193 static void virt_set_oem_id(Object
*obj
, const char *value
, Error
**errp
)
2195 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2196 size_t len
= strlen(value
);
2200 "User specified oem-id value is bigger than 6 bytes in size");
2204 strncpy(vms
->oem_id
, value
, 6);
2207 static char *virt_get_oem_table_id(Object
*obj
, Error
**errp
)
2209 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2211 return g_strdup(vms
->oem_table_id
);
2214 static void virt_set_oem_table_id(Object
*obj
, const char *value
,
2217 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2218 size_t len
= strlen(value
);
2222 "User specified oem-table-id value is bigger than 8 bytes in size");
2225 strncpy(vms
->oem_table_id
, value
, 8);
2229 bool virt_is_acpi_enabled(VirtMachineState
*vms
)
2231 if (vms
->acpi
== ON_OFF_AUTO_OFF
) {
2237 static void virt_get_acpi(Object
*obj
, Visitor
*v
, const char *name
,
2238 void *opaque
, Error
**errp
)
2240 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2241 OnOffAuto acpi
= vms
->acpi
;
2243 visit_type_OnOffAuto(v
, name
, &acpi
, errp
);
2246 static void virt_set_acpi(Object
*obj
, Visitor
*v
, const char *name
,
2247 void *opaque
, Error
**errp
)
2249 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2251 visit_type_OnOffAuto(v
, name
, &vms
->acpi
, errp
);
2254 static bool virt_get_ras(Object
*obj
, Error
**errp
)
2256 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2261 static void virt_set_ras(Object
*obj
, bool value
, Error
**errp
)
2263 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2268 static bool virt_get_mte(Object
*obj
, Error
**errp
)
2270 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2275 static void virt_set_mte(Object
*obj
, bool value
, Error
**errp
)
2277 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2282 static char *virt_get_gic_version(Object
*obj
, Error
**errp
)
2284 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2285 const char *val
= vms
->gic_version
== VIRT_GIC_VERSION_3
? "3" : "2";
2287 return g_strdup(val
);
2290 static void virt_set_gic_version(Object
*obj
, const char *value
, Error
**errp
)
2292 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2294 if (!strcmp(value
, "3")) {
2295 vms
->gic_version
= VIRT_GIC_VERSION_3
;
2296 } else if (!strcmp(value
, "2")) {
2297 vms
->gic_version
= VIRT_GIC_VERSION_2
;
2298 } else if (!strcmp(value
, "host")) {
2299 vms
->gic_version
= VIRT_GIC_VERSION_HOST
; /* Will probe later */
2300 } else if (!strcmp(value
, "max")) {
2301 vms
->gic_version
= VIRT_GIC_VERSION_MAX
; /* Will probe later */
2303 error_setg(errp
, "Invalid gic-version value");
2304 error_append_hint(errp
, "Valid values are 3, 2, host, max.\n");
2308 static char *virt_get_iommu(Object
*obj
, Error
**errp
)
2310 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2312 switch (vms
->iommu
) {
2313 case VIRT_IOMMU_NONE
:
2314 return g_strdup("none");
2315 case VIRT_IOMMU_SMMUV3
:
2316 return g_strdup("smmuv3");
2318 g_assert_not_reached();
2322 static void virt_set_iommu(Object
*obj
, const char *value
, Error
**errp
)
2324 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2326 if (!strcmp(value
, "smmuv3")) {
2327 vms
->iommu
= VIRT_IOMMU_SMMUV3
;
2328 } else if (!strcmp(value
, "none")) {
2329 vms
->iommu
= VIRT_IOMMU_NONE
;
2331 error_setg(errp
, "Invalid iommu value");
2332 error_append_hint(errp
, "Valid values are none, smmuv3.\n");
2336 static bool virt_get_default_bus_bypass_iommu(Object
*obj
, Error
**errp
)
2338 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2340 return vms
->default_bus_bypass_iommu
;
2343 static void virt_set_default_bus_bypass_iommu(Object
*obj
, bool value
,
2346 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2348 vms
->default_bus_bypass_iommu
= value
;
2351 static CpuInstanceProperties
2352 virt_cpu_index_to_props(MachineState
*ms
, unsigned cpu_index
)
2354 MachineClass
*mc
= MACHINE_GET_CLASS(ms
);
2355 const CPUArchIdList
*possible_cpus
= mc
->possible_cpu_arch_ids(ms
);
2357 assert(cpu_index
< possible_cpus
->len
);
2358 return possible_cpus
->cpus
[cpu_index
].props
;
2361 static int64_t virt_get_default_cpu_node_id(const MachineState
*ms
, int idx
)
2363 return idx
% ms
->numa_state
->num_nodes
;
2366 static const CPUArchIdList
*virt_possible_cpu_arch_ids(MachineState
*ms
)
2369 unsigned int max_cpus
= ms
->smp
.max_cpus
;
2370 VirtMachineState
*vms
= VIRT_MACHINE(ms
);
2372 if (ms
->possible_cpus
) {
2373 assert(ms
->possible_cpus
->len
== max_cpus
);
2374 return ms
->possible_cpus
;
2377 ms
->possible_cpus
= g_malloc0(sizeof(CPUArchIdList
) +
2378 sizeof(CPUArchId
) * max_cpus
);
2379 ms
->possible_cpus
->len
= max_cpus
;
2380 for (n
= 0; n
< ms
->possible_cpus
->len
; n
++) {
2381 ms
->possible_cpus
->cpus
[n
].type
= ms
->cpu_type
;
2382 ms
->possible_cpus
->cpus
[n
].arch_id
=
2383 virt_cpu_mp_affinity(vms
, n
);
2384 ms
->possible_cpus
->cpus
[n
].props
.has_thread_id
= true;
2385 ms
->possible_cpus
->cpus
[n
].props
.thread_id
= n
;
2387 return ms
->possible_cpus
;
2390 static void virt_memory_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
2393 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2394 const MachineState
*ms
= MACHINE(hotplug_dev
);
2395 const bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
2397 if (!vms
->acpi_dev
) {
2399 "memory hotplug is not enabled: missing acpi-ged device");
2404 error_setg(errp
, "memory hotplug is not enabled: MTE is enabled");
2408 if (is_nvdimm
&& !ms
->nvdimms_state
->is_enabled
) {
2409 error_setg(errp
, "nvdimm is not enabled: add 'nvdimm=on' to '-M'");
2413 pc_dimm_pre_plug(PC_DIMM(dev
), MACHINE(hotplug_dev
), NULL
, errp
);
2416 static void virt_memory_plug(HotplugHandler
*hotplug_dev
,
2417 DeviceState
*dev
, Error
**errp
)
2419 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2420 MachineState
*ms
= MACHINE(hotplug_dev
);
2421 bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
2423 pc_dimm_plug(PC_DIMM(dev
), MACHINE(vms
));
2426 nvdimm_plug(ms
->nvdimms_state
);
2429 hotplug_handler_plug(HOTPLUG_HANDLER(vms
->acpi_dev
),
2433 static void virt_machine_device_pre_plug_cb(HotplugHandler
*hotplug_dev
,
2434 DeviceState
*dev
, Error
**errp
)
2436 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2438 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2439 virt_memory_pre_plug(hotplug_dev
, dev
, errp
);
2440 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
)) {
2441 hwaddr db_start
= 0, db_end
= 0;
2442 char *resv_prop_str
;
2444 switch (vms
->msi_controller
) {
2445 case VIRT_MSI_CTRL_NONE
:
2447 case VIRT_MSI_CTRL_ITS
:
2448 /* GITS_TRANSLATER page */
2449 db_start
= base_memmap
[VIRT_GIC_ITS
].base
+ 0x10000;
2450 db_end
= base_memmap
[VIRT_GIC_ITS
].base
+
2451 base_memmap
[VIRT_GIC_ITS
].size
- 1;
2453 case VIRT_MSI_CTRL_GICV2M
:
2454 /* MSI_SETSPI_NS page */
2455 db_start
= base_memmap
[VIRT_GIC_V2M
].base
;
2456 db_end
= db_start
+ base_memmap
[VIRT_GIC_V2M
].size
- 1;
2459 resv_prop_str
= g_strdup_printf("0x%"PRIx64
":0x%"PRIx64
":%u",
2461 VIRTIO_IOMMU_RESV_MEM_T_MSI
);
2463 qdev_prop_set_uint32(dev
, "len-reserved-regions", 1);
2464 qdev_prop_set_string(dev
, "reserved-regions[0]", resv_prop_str
);
2465 g_free(resv_prop_str
);
2469 static void virt_machine_device_plug_cb(HotplugHandler
*hotplug_dev
,
2470 DeviceState
*dev
, Error
**errp
)
2472 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2474 if (vms
->platform_bus_dev
) {
2475 MachineClass
*mc
= MACHINE_GET_CLASS(vms
);
2477 if (device_is_dynamic_sysbus(mc
, dev
)) {
2478 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms
->platform_bus_dev
),
2479 SYS_BUS_DEVICE(dev
));
2482 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2483 virt_memory_plug(hotplug_dev
, dev
, errp
);
2485 if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
)) {
2486 PCIDevice
*pdev
= PCI_DEVICE(dev
);
2488 vms
->iommu
= VIRT_IOMMU_VIRTIO
;
2489 vms
->virtio_iommu_bdf
= pci_get_bdf(pdev
);
2490 create_virtio_iommu_dt_bindings(vms
);
2494 static void virt_dimm_unplug_request(HotplugHandler
*hotplug_dev
,
2495 DeviceState
*dev
, Error
**errp
)
2497 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2498 Error
*local_err
= NULL
;
2500 if (!vms
->acpi_dev
) {
2501 error_setg(&local_err
,
2502 "memory hotplug is not enabled: missing acpi-ged device");
2506 if (object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
)) {
2507 error_setg(&local_err
,
2508 "nvdimm device hot unplug is not supported yet.");
2512 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms
->acpi_dev
), dev
,
2515 error_propagate(errp
, local_err
);
2518 static void virt_dimm_unplug(HotplugHandler
*hotplug_dev
,
2519 DeviceState
*dev
, Error
**errp
)
2521 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2522 Error
*local_err
= NULL
;
2524 hotplug_handler_unplug(HOTPLUG_HANDLER(vms
->acpi_dev
), dev
, &local_err
);
2529 pc_dimm_unplug(PC_DIMM(dev
), MACHINE(vms
));
2530 qdev_unrealize(dev
);
2533 error_propagate(errp
, local_err
);
2536 static void virt_machine_device_unplug_request_cb(HotplugHandler
*hotplug_dev
,
2537 DeviceState
*dev
, Error
**errp
)
2539 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2540 virt_dimm_unplug_request(hotplug_dev
, dev
, errp
);
2542 error_setg(errp
, "device unplug request for unsupported device"
2543 " type: %s", object_get_typename(OBJECT(dev
)));
2547 static void virt_machine_device_unplug_cb(HotplugHandler
*hotplug_dev
,
2548 DeviceState
*dev
, Error
**errp
)
2550 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2551 virt_dimm_unplug(hotplug_dev
, dev
, errp
);
2553 error_setg(errp
, "virt: device unplug for unsupported device"
2554 " type: %s", object_get_typename(OBJECT(dev
)));
2558 static HotplugHandler
*virt_machine_get_hotplug_handler(MachineState
*machine
,
2561 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2563 if (device_is_dynamic_sysbus(mc
, dev
) ||
2564 (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
))) {
2565 return HOTPLUG_HANDLER(machine
);
2567 if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
)) {
2568 VirtMachineState
*vms
= VIRT_MACHINE(machine
);
2570 if (!vms
->bootinfo
.firmware_loaded
|| !virt_is_acpi_enabled(vms
)) {
2571 return HOTPLUG_HANDLER(machine
);
2578 * for arm64 kvm_type [7-0] encodes the requested number of bits
2579 * in the IPA address space
2581 static int virt_kvm_type(MachineState
*ms
, const char *type_str
)
2583 VirtMachineState
*vms
= VIRT_MACHINE(ms
);
2584 int max_vm_pa_size
, requested_pa_size
;
2587 max_vm_pa_size
= kvm_arm_get_max_vm_ipa_size(ms
, &fixed_ipa
);
2589 /* we freeze the memory map to compute the highest gpa */
2590 virt_set_memmap(vms
);
2592 requested_pa_size
= 64 - clz64(vms
->highest_gpa
);
2595 * KVM requires the IPA size to be at least 32 bits.
2597 if (requested_pa_size
< 32) {
2598 requested_pa_size
= 32;
2601 if (requested_pa_size
> max_vm_pa_size
) {
2602 error_report("-m and ,maxmem option values "
2603 "require an IPA range (%d bits) larger than "
2604 "the one supported by the host (%d bits)",
2605 requested_pa_size
, max_vm_pa_size
);
2609 * We return the requested PA log size, unless KVM only supports
2610 * the implicit legacy 40b IPA setting, in which case the kvm_type
2613 return fixed_ipa
? 0 : requested_pa_size
;
2616 static void virt_machine_class_init(ObjectClass
*oc
, void *data
)
2618 MachineClass
*mc
= MACHINE_CLASS(oc
);
2619 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
2621 mc
->init
= machvirt_init
;
2622 /* Start with max_cpus set to 512, which is the maximum supported by KVM.
2623 * The value may be reduced later when we have more information about the
2624 * configuration of the particular instance.
2627 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_CALXEDA_XGMAC
);
2628 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_AMD_XGBE
);
2629 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_RAMFB_DEVICE
);
2630 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_PLATFORM
);
2632 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_TPM_TIS_SYSBUS
);
2634 mc
->block_default_type
= IF_VIRTIO
;
2636 mc
->pci_allow_0_address
= true;
2637 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */
2638 mc
->minimum_page_bits
= 12;
2639 mc
->possible_cpu_arch_ids
= virt_possible_cpu_arch_ids
;
2640 mc
->cpu_index_to_instance_props
= virt_cpu_index_to_props
;
2641 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-a15");
2642 mc
->get_default_cpu_node_id
= virt_get_default_cpu_node_id
;
2643 mc
->kvm_type
= virt_kvm_type
;
2644 assert(!mc
->get_hotplug_handler
);
2645 mc
->get_hotplug_handler
= virt_machine_get_hotplug_handler
;
2646 hc
->pre_plug
= virt_machine_device_pre_plug_cb
;
2647 hc
->plug
= virt_machine_device_plug_cb
;
2648 hc
->unplug_request
= virt_machine_device_unplug_request_cb
;
2649 hc
->unplug
= virt_machine_device_unplug_cb
;
2650 mc
->nvdimm_supported
= true;
2651 mc
->auto_enable_numa_with_memhp
= true;
2652 mc
->auto_enable_numa_with_memdev
= true;
2653 mc
->default_ram_id
= "mach-virt.ram";
2655 object_class_property_add(oc
, "acpi", "OnOffAuto",
2656 virt_get_acpi
, virt_set_acpi
,
2658 object_class_property_set_description(oc
, "acpi",
2660 object_class_property_add_bool(oc
, "secure", virt_get_secure
,
2662 object_class_property_set_description(oc
, "secure",
2663 "Set on/off to enable/disable the ARM "
2664 "Security Extensions (TrustZone)");
2666 object_class_property_add_bool(oc
, "virtualization", virt_get_virt
,
2668 object_class_property_set_description(oc
, "virtualization",
2669 "Set on/off to enable/disable emulating a "
2670 "guest CPU which implements the ARM "
2671 "Virtualization Extensions");
2673 object_class_property_add_bool(oc
, "highmem", virt_get_highmem
,
2675 object_class_property_set_description(oc
, "highmem",
2676 "Set on/off to enable/disable using "
2677 "physical address space above 32 bits");
2679 object_class_property_add_str(oc
, "gic-version", virt_get_gic_version
,
2680 virt_set_gic_version
);
2681 object_class_property_set_description(oc
, "gic-version",
2683 "Valid values are 2, 3, host and max");
2685 object_class_property_add_str(oc
, "iommu", virt_get_iommu
, virt_set_iommu
);
2686 object_class_property_set_description(oc
, "iommu",
2687 "Set the IOMMU type. "
2688 "Valid values are none and smmuv3");
2690 object_class_property_add_bool(oc
, "default_bus_bypass_iommu",
2691 virt_get_default_bus_bypass_iommu
,
2692 virt_set_default_bus_bypass_iommu
);
2693 object_class_property_set_description(oc
, "default_bus_bypass_iommu",
2694 "Set on/off to enable/disable "
2695 "bypass_iommu for default root bus");
2697 object_class_property_add_bool(oc
, "ras", virt_get_ras
,
2699 object_class_property_set_description(oc
, "ras",
2700 "Set on/off to enable/disable reporting host memory errors "
2701 "to a KVM guest using ACPI and guest external abort exceptions");
2703 object_class_property_add_bool(oc
, "mte", virt_get_mte
, virt_set_mte
);
2704 object_class_property_set_description(oc
, "mte",
2705 "Set on/off to enable/disable emulating a "
2706 "guest CPU which implements the ARM "
2707 "Memory Tagging Extension");
2709 object_class_property_add_bool(oc
, "its", virt_get_its
,
2711 object_class_property_set_description(oc
, "its",
2712 "Set on/off to enable/disable "
2713 "ITS instantiation");
2715 object_class_property_add_str(oc
, "x-oem-id",
2718 object_class_property_set_description(oc
, "x-oem-id",
2719 "Override the default value of field OEMID "
2720 "in ACPI table header."
2721 "The string may be up to 6 bytes in size");
2724 object_class_property_add_str(oc
, "x-oem-table-id",
2725 virt_get_oem_table_id
,
2726 virt_set_oem_table_id
);
2727 object_class_property_set_description(oc
, "x-oem-table-id",
2728 "Override the default value of field OEM Table ID "
2729 "in ACPI table header."
2730 "The string may be up to 8 bytes in size");
2734 static void virt_instance_init(Object
*obj
)
2736 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2737 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
2739 /* EL3 is disabled by default on virt: this makes us consistent
2740 * between KVM and TCG for this board, and it also allows us to
2741 * boot UEFI blobs which assume no TrustZone support.
2743 vms
->secure
= false;
2745 /* EL2 is also disabled by default, for similar reasons */
2748 /* High memory is enabled by default */
2749 vms
->highmem
= true;
2750 vms
->gic_version
= VIRT_GIC_VERSION_NOSEL
;
2752 vms
->highmem_ecam
= !vmc
->no_highmem_ecam
;
2757 /* Default allows ITS instantiation */
2760 if (vmc
->no_tcg_its
) {
2761 vms
->tcg_its
= false;
2763 vms
->tcg_its
= true;
2767 /* Default disallows iommu instantiation */
2768 vms
->iommu
= VIRT_IOMMU_NONE
;
2770 /* The default root bus is attached to iommu by default */
2771 vms
->default_bus_bypass_iommu
= false;
2773 /* Default disallows RAS instantiation */
2776 /* MTE is disabled by default. */
2779 vms
->irqmap
= a15irqmap
;
2781 virt_flash_create(vms
);
2783 vms
->oem_id
= g_strndup(ACPI_BUILD_APPNAME6
, 6);
2784 vms
->oem_table_id
= g_strndup(ACPI_BUILD_APPNAME8
, 8);
2787 static const TypeInfo virt_machine_info
= {
2788 .name
= TYPE_VIRT_MACHINE
,
2789 .parent
= TYPE_MACHINE
,
2791 .instance_size
= sizeof(VirtMachineState
),
2792 .class_size
= sizeof(VirtMachineClass
),
2793 .class_init
= virt_machine_class_init
,
2794 .instance_init
= virt_instance_init
,
2795 .interfaces
= (InterfaceInfo
[]) {
2796 { TYPE_HOTPLUG_HANDLER
},
2801 static void machvirt_machine_init(void)
2803 type_register_static(&virt_machine_info
);
2805 type_init(machvirt_machine_init
);
2807 static void virt_machine_6_2_options(MachineClass
*mc
)
2810 DEFINE_VIRT_MACHINE_AS_LATEST(6, 2)
2812 static void virt_machine_6_1_options(MachineClass
*mc
)
2814 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2816 virt_machine_6_2_options(mc
);
2817 compat_props_add(mc
->compat_props
, hw_compat_6_1
, hw_compat_6_1_len
);
2818 mc
->smp_props
.prefer_sockets
= true;
2820 /* qemu ITS was introduced with 6.2 */
2821 vmc
->no_tcg_its
= true;
2823 DEFINE_VIRT_MACHINE(6, 1)
2825 static void virt_machine_6_0_options(MachineClass
*mc
)
2827 virt_machine_6_1_options(mc
);
2828 compat_props_add(mc
->compat_props
, hw_compat_6_0
, hw_compat_6_0_len
);
2830 DEFINE_VIRT_MACHINE(6, 0)
2832 static void virt_machine_5_2_options(MachineClass
*mc
)
2834 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2836 virt_machine_6_0_options(mc
);
2837 compat_props_add(mc
->compat_props
, hw_compat_5_2
, hw_compat_5_2_len
);
2838 vmc
->no_secure_gpio
= true;
2840 DEFINE_VIRT_MACHINE(5, 2)
2842 static void virt_machine_5_1_options(MachineClass
*mc
)
2844 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2846 virt_machine_5_2_options(mc
);
2847 compat_props_add(mc
->compat_props
, hw_compat_5_1
, hw_compat_5_1_len
);
2848 vmc
->no_kvm_steal_time
= true;
2850 DEFINE_VIRT_MACHINE(5, 1)
2852 static void virt_machine_5_0_options(MachineClass
*mc
)
2854 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2856 virt_machine_5_1_options(mc
);
2857 compat_props_add(mc
->compat_props
, hw_compat_5_0
, hw_compat_5_0_len
);
2858 mc
->numa_mem_supported
= true;
2859 vmc
->acpi_expose_flash
= true;
2860 mc
->auto_enable_numa_with_memdev
= false;
2862 DEFINE_VIRT_MACHINE(5, 0)
2864 static void virt_machine_4_2_options(MachineClass
*mc
)
2866 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2868 virt_machine_5_0_options(mc
);
2869 compat_props_add(mc
->compat_props
, hw_compat_4_2
, hw_compat_4_2_len
);
2870 vmc
->kvm_no_adjvtime
= true;
2872 DEFINE_VIRT_MACHINE(4, 2)
2874 static void virt_machine_4_1_options(MachineClass
*mc
)
2876 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2878 virt_machine_4_2_options(mc
);
2879 compat_props_add(mc
->compat_props
, hw_compat_4_1
, hw_compat_4_1_len
);
2881 mc
->auto_enable_numa_with_memhp
= false;
2883 DEFINE_VIRT_MACHINE(4, 1)
2885 static void virt_machine_4_0_options(MachineClass
*mc
)
2887 virt_machine_4_1_options(mc
);
2888 compat_props_add(mc
->compat_props
, hw_compat_4_0
, hw_compat_4_0_len
);
2890 DEFINE_VIRT_MACHINE(4, 0)
2892 static void virt_machine_3_1_options(MachineClass
*mc
)
2894 virt_machine_4_0_options(mc
);
2895 compat_props_add(mc
->compat_props
, hw_compat_3_1
, hw_compat_3_1_len
);
2897 DEFINE_VIRT_MACHINE(3, 1)
2899 static void virt_machine_3_0_options(MachineClass
*mc
)
2901 virt_machine_3_1_options(mc
);
2902 compat_props_add(mc
->compat_props
, hw_compat_3_0
, hw_compat_3_0_len
);
2904 DEFINE_VIRT_MACHINE(3, 0)
2906 static void virt_machine_2_12_options(MachineClass
*mc
)
2908 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2910 virt_machine_3_0_options(mc
);
2911 compat_props_add(mc
->compat_props
, hw_compat_2_12
, hw_compat_2_12_len
);
2912 vmc
->no_highmem_ecam
= true;
2915 DEFINE_VIRT_MACHINE(2, 12)
2917 static void virt_machine_2_11_options(MachineClass
*mc
)
2919 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2921 virt_machine_2_12_options(mc
);
2922 compat_props_add(mc
->compat_props
, hw_compat_2_11
, hw_compat_2_11_len
);
2923 vmc
->smbios_old_sys_ver
= true;
2925 DEFINE_VIRT_MACHINE(2, 11)
2927 static void virt_machine_2_10_options(MachineClass
*mc
)
2929 virt_machine_2_11_options(mc
);
2930 compat_props_add(mc
->compat_props
, hw_compat_2_10
, hw_compat_2_10_len
);
2931 /* before 2.11 we never faulted accesses to bad addresses */
2932 mc
->ignore_memory_transaction_failures
= true;
2934 DEFINE_VIRT_MACHINE(2, 10)
2936 static void virt_machine_2_9_options(MachineClass
*mc
)
2938 virt_machine_2_10_options(mc
);
2939 compat_props_add(mc
->compat_props
, hw_compat_2_9
, hw_compat_2_9_len
);
2941 DEFINE_VIRT_MACHINE(2, 9)
2943 static void virt_machine_2_8_options(MachineClass
*mc
)
2945 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2947 virt_machine_2_9_options(mc
);
2948 compat_props_add(mc
->compat_props
, hw_compat_2_8
, hw_compat_2_8_len
);
2949 /* For 2.8 and earlier we falsely claimed in the DT that
2950 * our timers were edge-triggered, not level-triggered.
2952 vmc
->claim_edge_triggered_timers
= true;
2954 DEFINE_VIRT_MACHINE(2, 8)
2956 static void virt_machine_2_7_options(MachineClass
*mc
)
2958 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2960 virt_machine_2_8_options(mc
);
2961 compat_props_add(mc
->compat_props
, hw_compat_2_7
, hw_compat_2_7_len
);
2962 /* ITS was introduced with 2.8 */
2964 /* Stick with 1K pages for migration compatibility */
2965 mc
->minimum_page_bits
= 0;
2967 DEFINE_VIRT_MACHINE(2, 7)
2969 static void virt_machine_2_6_options(MachineClass
*mc
)
2971 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2973 virt_machine_2_7_options(mc
);
2974 compat_props_add(mc
->compat_props
, hw_compat_2_6
, hw_compat_2_6_len
);
2975 vmc
->disallow_affinity_adjustment
= true;
2976 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */
2979 DEFINE_VIRT_MACHINE(2, 6)