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m25p80: Introduce COLLECTING_VAR_LEN_DATA state.
[qemu/ar7.git] / hw / block / m25p80.c
blob0af2ee4dc655e7828d9394c90a364bcdfc7f8d6c
1 /*
2 * ST M25P80 emulator. Emulate all SPI flash devices based on the m25p80 command
3 * set. Known devices table current as of Jun/2012 and taken from linux.
4 * See drivers/mtd/devices/m25p80.c.
5 *
6 * Copyright (C) 2011 Edgar E. Iglesias <edgar.iglesias@gmail.com>
7 * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
8 * Copyright (C) 2012 PetaLogix
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 or
13 * (at your option) a later version of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 */
23
24 #include "qemu/osdep.h"
25 #include "hw/hw.h"
26 #include "sysemu/block-backend.h"
27 #include "sysemu/blockdev.h"
28 #include "hw/ssi/ssi.h"
29 #include "qemu/bitops.h"
30 #include "qemu/log.h"
31
32 #ifndef M25P80_ERR_DEBUG
33 #define M25P80_ERR_DEBUG 0
34 #endif
35
36 #define DB_PRINT_L(level, ...) do { \
37 if (M25P80_ERR_DEBUG > (level)) { \
38 fprintf(stderr, ": %s: ", __func__); \
39 fprintf(stderr, ## __VA_ARGS__); \
40 } \
41 } while (0);
42
43 /* Fields for FlashPartInfo->flags */
44
45 /* erase capabilities */
46 #define ER_4K 1
47 #define ER_32K 2
48 /* set to allow the page program command to write 0s back to 1. Useful for
49 * modelling EEPROM with SPI flash command set
50 */
51 #define EEPROM 0x100
52
53 /* 16 MiB max in 3 byte address mode */
54 #define MAX_3BYTES_SIZE 0x1000000
55
56 #define SPI_NOR_MAX_ID_LEN 6
57
58 typedef struct FlashPartInfo {
59 const char *part_name;
60 /*
61 * This array stores the ID bytes.
62 * The first three bytes are the JEDIC ID.
63 * JEDEC ID zero means "no ID" (mostly older chips).
64 */
65 uint8_t id[SPI_NOR_MAX_ID_LEN];
66 uint8_t id_len;
67 /* there is confusion between manufacturers as to what a sector is. In this
68 * device model, a "sector" is the size that is erased by the ERASE_SECTOR
69 * command (opcode 0xd8).
70 */
71 uint32_t sector_size;
72 uint32_t n_sectors;
73 uint32_t page_size;
74 uint16_t flags;
75 } FlashPartInfo;
76
77 /* adapted from linux */
78 /* Used when the "_ext_id" is two bytes at most */
79 #define INFO(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\
80 .part_name = _part_name,\
81 .id = {\
82 ((_jedec_id) >> 16) & 0xff,\
83 ((_jedec_id) >> 8) & 0xff,\
84 (_jedec_id) & 0xff,\
85 ((_ext_id) >> 8) & 0xff,\
86 (_ext_id) & 0xff,\
87 },\
88 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\
89 .sector_size = (_sector_size),\
90 .n_sectors = (_n_sectors),\
91 .page_size = 256,\
92 .flags = (_flags),
93
94 #define INFO6(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\
95 .part_name = _part_name,\
96 .id = {\
97 ((_jedec_id) >> 16) & 0xff,\
98 ((_jedec_id) >> 8) & 0xff,\
99 (_jedec_id) & 0xff,\
100 ((_ext_id) >> 16) & 0xff,\
101 ((_ext_id) >> 8) & 0xff,\
102 (_ext_id) & 0xff,\
103 },\
104 .id_len = 6,\
105 .sector_size = (_sector_size),\
106 .n_sectors = (_n_sectors),\
107 .page_size = 256,\
108 .flags = (_flags),\
109
110 #define JEDEC_NUMONYX 0x20
111 #define JEDEC_WINBOND 0xEF
112 #define JEDEC_SPANSION 0x01
113
114 /* Numonyx (Micron) Configuration register macros */
115 #define VCFG_DUMMY 0x1
116 #define VCFG_WRAP_SEQUENTIAL 0x2
117 #define NVCFG_XIP_MODE_DISABLED (7 << 9)
118 #define NVCFG_XIP_MODE_MASK (7 << 9)
119 #define VCFG_XIP_MODE_ENABLED (1 << 3)
120 #define CFG_DUMMY_CLK_LEN 4
121 #define NVCFG_DUMMY_CLK_POS 12
122 #define VCFG_DUMMY_CLK_POS 4
123 #define EVCFG_OUT_DRIVER_STRENGHT_DEF 7
124 #define EVCFG_VPP_ACCELERATOR (1 << 3)
125 #define EVCFG_RESET_HOLD_ENABLED (1 << 4)
126 #define NVCFG_DUAL_IO_MASK (1 << 2)
127 #define EVCFG_DUAL_IO_ENABLED (1 << 6)
128 #define NVCFG_QUAD_IO_MASK (1 << 3)
129 #define EVCFG_QUAD_IO_ENABLED (1 << 7)
130 #define NVCFG_4BYTE_ADDR_MASK (1 << 0)
131 #define NVCFG_LOWER_SEGMENT_MASK (1 << 1)
132
133 /* Numonyx (Micron) Flag Status Register macros */
134 #define FSR_4BYTE_ADDR_MODE_ENABLED 0x1
135 #define FSR_FLASH_READY (1 << 7)
136
137 static const FlashPartInfo known_devices[] = {
138 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
139 { INFO("at25fs010", 0x1f6601, 0, 32 << 10, 4, ER_4K) },
140 { INFO("at25fs040", 0x1f6604, 0, 64 << 10, 8, ER_4K) },
141
142 { INFO("at25df041a", 0x1f4401, 0, 64 << 10, 8, ER_4K) },
143 { INFO("at25df321a", 0x1f4701, 0, 64 << 10, 64, ER_4K) },
144 { INFO("at25df641", 0x1f4800, 0, 64 << 10, 128, ER_4K) },
145
146 { INFO("at26f004", 0x1f0400, 0, 64 << 10, 8, ER_4K) },
147 { INFO("at26df081a", 0x1f4501, 0, 64 << 10, 16, ER_4K) },
148 { INFO("at26df161a", 0x1f4601, 0, 64 << 10, 32, ER_4K) },
149 { INFO("at26df321", 0x1f4700, 0, 64 << 10, 64, ER_4K) },
150
151 { INFO("at45db081d", 0x1f2500, 0, 64 << 10, 16, ER_4K) },
152
153 /* Atmel EEPROMS - it is assumed, that don't care bit in command
154 * is set to 0. Block protection is not supported.
155 */
156 { INFO("at25128a-nonjedec", 0x0, 0, 1, 131072, EEPROM) },
157 { INFO("at25256a-nonjedec", 0x0, 0, 1, 262144, EEPROM) },
158
159 /* EON -- en25xxx */
160 { INFO("en25f32", 0x1c3116, 0, 64 << 10, 64, ER_4K) },
161 { INFO("en25p32", 0x1c2016, 0, 64 << 10, 64, 0) },
162 { INFO("en25q32b", 0x1c3016, 0, 64 << 10, 64, 0) },
163 { INFO("en25p64", 0x1c2017, 0, 64 << 10, 128, 0) },
164 { INFO("en25q64", 0x1c3017, 0, 64 << 10, 128, ER_4K) },
165
166 /* GigaDevice */
167 { INFO("gd25q32", 0xc84016, 0, 64 << 10, 64, ER_4K) },
168 { INFO("gd25q64", 0xc84017, 0, 64 << 10, 128, ER_4K) },
169
170 /* Intel/Numonyx -- xxxs33b */
171 { INFO("160s33b", 0x898911, 0, 64 << 10, 32, 0) },
172 { INFO("320s33b", 0x898912, 0, 64 << 10, 64, 0) },
173 { INFO("640s33b", 0x898913, 0, 64 << 10, 128, 0) },
174 { INFO("n25q064", 0x20ba17, 0, 64 << 10, 128, 0) },
175
176 /* Macronix */
177 { INFO("mx25l2005a", 0xc22012, 0, 64 << 10, 4, ER_4K) },
178 { INFO("mx25l4005a", 0xc22013, 0, 64 << 10, 8, ER_4K) },
179 { INFO("mx25l8005", 0xc22014, 0, 64 << 10, 16, 0) },
180 { INFO("mx25l1606e", 0xc22015, 0, 64 << 10, 32, ER_4K) },
181 { INFO("mx25l3205d", 0xc22016, 0, 64 << 10, 64, 0) },
182 { INFO("mx25l6405d", 0xc22017, 0, 64 << 10, 128, 0) },
183 { INFO("mx25l12805d", 0xc22018, 0, 64 << 10, 256, 0) },
184 { INFO("mx25l12855e", 0xc22618, 0, 64 << 10, 256, 0) },
185 { INFO("mx25l25635e", 0xc22019, 0, 64 << 10, 512, 0) },
186 { INFO("mx25l25655e", 0xc22619, 0, 64 << 10, 512, 0) },
187
188 /* Micron */
189 { INFO("n25q032a11", 0x20bb16, 0, 64 << 10, 64, ER_4K) },
190 { INFO("n25q032a13", 0x20ba16, 0, 64 << 10, 64, ER_4K) },
191 { INFO("n25q064a11", 0x20bb17, 0, 64 << 10, 128, ER_4K) },
192 { INFO("n25q064a13", 0x20ba17, 0, 64 << 10, 128, ER_4K) },
193 { INFO("n25q128a11", 0x20bb18, 0, 64 << 10, 256, ER_4K) },
194 { INFO("n25q128a13", 0x20ba18, 0, 64 << 10, 256, ER_4K) },
195 { INFO("n25q256a11", 0x20bb19, 0, 64 << 10, 512, ER_4K) },
196 { INFO("n25q256a13", 0x20ba19, 0, 64 << 10, 512, ER_4K) },
197
198 /* Spansion -- single (large) sector size only, at least
199 * for the chips listed here (without boot sectors).
200 */
201 { INFO("s25sl032p", 0x010215, 0x4d00, 64 << 10, 64, ER_4K) },
202 { INFO("s25sl064p", 0x010216, 0x4d00, 64 << 10, 128, ER_4K) },
203 { INFO("s25fl256s0", 0x010219, 0x4d00, 256 << 10, 128, 0) },
204 { INFO("s25fl256s1", 0x010219, 0x4d01, 64 << 10, 512, 0) },
205 { INFO("s25fl512s", 0x010220, 0x4d00, 256 << 10, 256, 0) },
206 { INFO("s70fl01gs", 0x010221, 0x4d00, 256 << 10, 256, 0) },
207 { INFO("s25sl12800", 0x012018, 0x0300, 256 << 10, 64, 0) },
208 { INFO("s25sl12801", 0x012018, 0x0301, 64 << 10, 256, 0) },
209 { INFO("s25fl129p0", 0x012018, 0x4d00, 256 << 10, 64, 0) },
210 { INFO("s25fl129p1", 0x012018, 0x4d01, 64 << 10, 256, 0) },
211 { INFO("s25sl004a", 0x010212, 0, 64 << 10, 8, 0) },
212 { INFO("s25sl008a", 0x010213, 0, 64 << 10, 16, 0) },
213 { INFO("s25sl016a", 0x010214, 0, 64 << 10, 32, 0) },
214 { INFO("s25sl032a", 0x010215, 0, 64 << 10, 64, 0) },
215 { INFO("s25sl064a", 0x010216, 0, 64 << 10, 128, 0) },
216 { INFO("s25fl016k", 0xef4015, 0, 64 << 10, 32, ER_4K | ER_32K) },
217 { INFO("s25fl064k", 0xef4017, 0, 64 << 10, 128, ER_4K | ER_32K) },
218
219 /* SST -- large erase sizes are "overlays", "sectors" are 4<< 10 */
220 { INFO("sst25vf040b", 0xbf258d, 0, 64 << 10, 8, ER_4K) },
221 { INFO("sst25vf080b", 0xbf258e, 0, 64 << 10, 16, ER_4K) },
222 { INFO("sst25vf016b", 0xbf2541, 0, 64 << 10, 32, ER_4K) },
223 { INFO("sst25vf032b", 0xbf254a, 0, 64 << 10, 64, ER_4K) },
224 { INFO("sst25wf512", 0xbf2501, 0, 64 << 10, 1, ER_4K) },
225 { INFO("sst25wf010", 0xbf2502, 0, 64 << 10, 2, ER_4K) },
226 { INFO("sst25wf020", 0xbf2503, 0, 64 << 10, 4, ER_4K) },
227 { INFO("sst25wf040", 0xbf2504, 0, 64 << 10, 8, ER_4K) },
228 { INFO("sst25wf080", 0xbf2505, 0, 64 << 10, 16, ER_4K) },
229
230 /* ST Microelectronics -- newer production may have feature updates */
231 { INFO("m25p05", 0x202010, 0, 32 << 10, 2, 0) },
232 { INFO("m25p10", 0x202011, 0, 32 << 10, 4, 0) },
233 { INFO("m25p20", 0x202012, 0, 64 << 10, 4, 0) },
234 { INFO("m25p40", 0x202013, 0, 64 << 10, 8, 0) },
235 { INFO("m25p80", 0x202014, 0, 64 << 10, 16, 0) },
236 { INFO("m25p16", 0x202015, 0, 64 << 10, 32, 0) },
237 { INFO("m25p32", 0x202016, 0, 64 << 10, 64, 0) },
238 { INFO("m25p64", 0x202017, 0, 64 << 10, 128, 0) },
239 { INFO("m25p128", 0x202018, 0, 256 << 10, 64, 0) },
240 { INFO("n25q032", 0x20ba16, 0, 64 << 10, 64, 0) },
241
242 { INFO("m45pe10", 0x204011, 0, 64 << 10, 2, 0) },
243 { INFO("m45pe80", 0x204014, 0, 64 << 10, 16, 0) },
244 { INFO("m45pe16", 0x204015, 0, 64 << 10, 32, 0) },
245
246 { INFO("m25pe20", 0x208012, 0, 64 << 10, 4, 0) },
247 { INFO("m25pe80", 0x208014, 0, 64 << 10, 16, 0) },
248 { INFO("m25pe16", 0x208015, 0, 64 << 10, 32, ER_4K) },
249
250 { INFO("m25px32", 0x207116, 0, 64 << 10, 64, ER_4K) },
251 { INFO("m25px32-s0", 0x207316, 0, 64 << 10, 64, ER_4K) },
252 { INFO("m25px32-s1", 0x206316, 0, 64 << 10, 64, ER_4K) },
253 { INFO("m25px64", 0x207117, 0, 64 << 10, 128, 0) },
254
255 /* Winbond -- w25x "blocks" are 64k, "sectors" are 4KiB */
256 { INFO("w25x10", 0xef3011, 0, 64 << 10, 2, ER_4K) },
257 { INFO("w25x20", 0xef3012, 0, 64 << 10, 4, ER_4K) },
258 { INFO("w25x40", 0xef3013, 0, 64 << 10, 8, ER_4K) },
259 { INFO("w25x80", 0xef3014, 0, 64 << 10, 16, ER_4K) },
260 { INFO("w25x16", 0xef3015, 0, 64 << 10, 32, ER_4K) },
261 { INFO("w25x32", 0xef3016, 0, 64 << 10, 64, ER_4K) },
262 { INFO("w25q32", 0xef4016, 0, 64 << 10, 64, ER_4K) },
263 { INFO("w25q32dw", 0xef6016, 0, 64 << 10, 64, ER_4K) },
264 { INFO("w25x64", 0xef3017, 0, 64 << 10, 128, ER_4K) },
265 { INFO("w25q64", 0xef4017, 0, 64 << 10, 128, ER_4K) },
266 { INFO("w25q80", 0xef5014, 0, 64 << 10, 16, ER_4K) },
267 { INFO("w25q80bl", 0xef4014, 0, 64 << 10, 16, ER_4K) },
268 { INFO("w25q256", 0xef4019, 0, 64 << 10, 512, ER_4K) },
269
270 { INFO("n25q128", 0x20ba18, 0, 64 << 10, 256, 0) },
271 { INFO("n25q256a", 0x20ba19, 0, 64 << 10, 512, ER_4K) },
272 { INFO("n25q512a", 0x20ba20, 0, 64 << 10, 1024, ER_4K) },
273 };
274
275 typedef enum {
276 NOP = 0,
277 WRSR = 0x1,
278 WRDI = 0x4,
279 RDSR = 0x5,
280 WREN = 0x6,
281 JEDEC_READ = 0x9f,
282 BULK_ERASE = 0xc7,
283 READ_FSR = 0x70,
284
285 READ = 0x03,
286 READ4 = 0x13,
287 FAST_READ = 0x0b,
288 FAST_READ4 = 0x0c,
289 DOR = 0x3b,
290 DOR4 = 0x3c,
291 QOR = 0x6b,
292 QOR4 = 0x6c,
293 DIOR = 0xbb,
294 DIOR4 = 0xbc,
295 QIOR = 0xeb,
296 QIOR4 = 0xec,
297
298 PP = 0x02,
299 PP4 = 0x12,
300 DPP = 0xa2,
301 QPP = 0x32,
302
303 ERASE_4K = 0x20,
304 ERASE4_4K = 0x21,
305 ERASE_32K = 0x52,
306 ERASE_SECTOR = 0xd8,
307 ERASE4_SECTOR = 0xdc,
308
309 EN_4BYTE_ADDR = 0xB7,
310 EX_4BYTE_ADDR = 0xE9,
311
312 EXTEND_ADDR_READ = 0xC8,
313 EXTEND_ADDR_WRITE = 0xC5,
314
315 RESET_ENABLE = 0x66,
316 RESET_MEMORY = 0x99,
317
318 RNVCR = 0xB5,
319 WNVCR = 0xB1,
320
321 RVCR = 0x85,
322 WVCR = 0x81,
323
324 REVCR = 0x65,
325 WEVCR = 0x61,
326 } FlashCMD;
327
328 typedef enum {
329 STATE_IDLE,
330 STATE_PAGE_PROGRAM,
331 STATE_READ,
332 STATE_COLLECTING_DATA,
333 STATE_COLLECTING_VAR_LEN_DATA,
334 STATE_READING_DATA,
335 } CMDState;
336
337 typedef enum {
338 MAN_SPANSION,
339 MAN_MACRONIX,
340 MAN_NUMONYX,
341 MAN_WINBOND,
342 MAN_GENERIC,
343 } Manufacturer;
344
345 typedef struct Flash {
346 SSISlave parent_obj;
347
348 BlockBackend *blk;
349
350 uint8_t *storage;
351 uint32_t size;
352 int page_size;
353
354 uint8_t state;
355 uint8_t data[16];
356 uint32_t len;
357 uint32_t pos;
358 uint8_t needed_bytes;
359 uint8_t cmd_in_progress;
360 uint64_t cur_addr;
361 uint32_t nonvolatile_cfg;
362 uint32_t volatile_cfg;
363 uint32_t enh_volatile_cfg;
364 bool write_enable;
365 bool four_bytes_address_mode;
366 bool reset_enable;
367 uint8_t ear;
368
369 int64_t dirty_page;
370
371 const FlashPartInfo *pi;
372
373 } Flash;
374
375 typedef struct M25P80Class {
376 SSISlaveClass parent_class;
377 FlashPartInfo *pi;
378 } M25P80Class;
379
380 #define TYPE_M25P80 "m25p80-generic"
381 #define M25P80(obj) \
382 OBJECT_CHECK(Flash, (obj), TYPE_M25P80)
383 #define M25P80_CLASS(klass) \
384 OBJECT_CLASS_CHECK(M25P80Class, (klass), TYPE_M25P80)
385 #define M25P80_GET_CLASS(obj) \
386 OBJECT_GET_CLASS(M25P80Class, (obj), TYPE_M25P80)
387
388 static inline Manufacturer get_man(Flash *s)
389 {
390 switch (s->pi->id[0]) {
391 case 0x20:
392 return MAN_NUMONYX;
393 case 0xEF:
394 return MAN_WINBOND;
395 case 0x01:
396 return MAN_SPANSION;
397 case 0xC2:
398 return MAN_MACRONIX;
399 default:
400 return MAN_GENERIC;
401 }
402 }
403
404 static void blk_sync_complete(void *opaque, int ret)
405 {
406 /* do nothing. Masters do not directly interact with the backing store,
407 * only the working copy so no mutexing required.
408 */
409 }
410
411 static void flash_sync_page(Flash *s, int page)
412 {
413 QEMUIOVector iov;
414
415 if (!s->blk || blk_is_read_only(s->blk)) {
416 return;
417 }
418
419 qemu_iovec_init(&iov, 1);
420 qemu_iovec_add(&iov, s->storage + page * s->pi->page_size,
421 s->pi->page_size);
422 blk_aio_pwritev(s->blk, page * s->pi->page_size, &iov, 0,
423 blk_sync_complete, NULL);
424 }
425
426 static inline void flash_sync_area(Flash *s, int64_t off, int64_t len)
427 {
428 QEMUIOVector iov;
429
430 if (!s->blk || blk_is_read_only(s->blk)) {
431 return;
432 }
433
434 assert(!(len % BDRV_SECTOR_SIZE));
435 qemu_iovec_init(&iov, 1);
436 qemu_iovec_add(&iov, s->storage + off, len);
437 blk_aio_pwritev(s->blk, off, &iov, 0, blk_sync_complete, NULL);
438 }
439
440 static void flash_erase(Flash *s, int offset, FlashCMD cmd)
441 {
442 uint32_t len;
443 uint8_t capa_to_assert = 0;
444
445 switch (cmd) {
446 case ERASE_4K:
447 case ERASE4_4K:
448 len = 4 << 10;
449 capa_to_assert = ER_4K;
450 break;
451 case ERASE_32K:
452 len = 32 << 10;
453 capa_to_assert = ER_32K;
454 break;
455 case ERASE_SECTOR:
456 case ERASE4_SECTOR:
457 len = s->pi->sector_size;
458 break;
459 case BULK_ERASE:
460 len = s->size;
461 break;
462 default:
463 abort();
464 }
465
466 DB_PRINT_L(0, "offset = %#x, len = %d\n", offset, len);
467 if ((s->pi->flags & capa_to_assert) != capa_to_assert) {
468 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %d erase size not supported by"
469 " device\n", len);
470 }
471
472 if (!s->write_enable) {
473 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: erase with write protect!\n");
474 return;
475 }
476 memset(s->storage + offset, 0xff, len);
477 flash_sync_area(s, offset, len);
478 }
479
480 static inline void flash_sync_dirty(Flash *s, int64_t newpage)
481 {
482 if (s->dirty_page >= 0 && s->dirty_page != newpage) {
483 flash_sync_page(s, s->dirty_page);
484 s->dirty_page = newpage;
485 }
486 }
487
488 static inline
489 void flash_write8(Flash *s, uint64_t addr, uint8_t data)
490 {
491 int64_t page = addr / s->pi->page_size;
492 uint8_t prev = s->storage[s->cur_addr];
493
494 if (!s->write_enable) {
495 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write protect!\n");
496 }
497
498 if ((prev ^ data) & data) {
499 DB_PRINT_L(1, "programming zero to one! addr=%" PRIx64 " %" PRIx8
500 " -> %" PRIx8 "\n", addr, prev, data);
501 }
502
503 if (s->pi->flags & EEPROM) {
504 s->storage[s->cur_addr] = data;
505 } else {
506 s->storage[s->cur_addr] &= data;
507 }
508
509 flash_sync_dirty(s, page);
510 s->dirty_page = page;
511 }
512
513 static inline int get_addr_length(Flash *s)
514 {
515 /* check if eeprom is in use */
516 if (s->pi->flags == EEPROM) {
517 return 2;
518 }
519
520 switch (s->cmd_in_progress) {
521 case PP4:
522 case READ4:
523 case QIOR4:
524 case ERASE4_4K:
525 case ERASE4_SECTOR:
526 case FAST_READ4:
527 case DOR4:
528 case QOR4:
529 case DIOR4:
530 return 4;
531 default:
532 return s->four_bytes_address_mode ? 4 : 3;
533 }
534 }
535
536 static void complete_collecting_data(Flash *s)
537 {
538 int i;
539
540 s->cur_addr = 0;
541
542 for (i = 0; i < get_addr_length(s); ++i) {
543 s->cur_addr <<= 8;
544 s->cur_addr |= s->data[i];
545 }
546
547 if (get_addr_length(s) == 3) {
548 s->cur_addr += s->ear * MAX_3BYTES_SIZE;
549 }
550
551 s->state = STATE_IDLE;
552
553 switch (s->cmd_in_progress) {
554 case DPP:
555 case QPP:
556 case PP:
557 case PP4:
558 s->state = STATE_PAGE_PROGRAM;
559 break;
560 case READ:
561 case READ4:
562 case FAST_READ:
563 case FAST_READ4:
564 case DOR:
565 case DOR4:
566 case QOR:
567 case QOR4:
568 case DIOR:
569 case DIOR4:
570 case QIOR:
571 case QIOR4:
572 s->state = STATE_READ;
573 break;
574 case ERASE_4K:
575 case ERASE4_4K:
576 case ERASE_32K:
577 case ERASE_SECTOR:
578 case ERASE4_SECTOR:
579 flash_erase(s, s->cur_addr, s->cmd_in_progress);
580 break;
581 case WRSR:
582 if (s->write_enable) {
583 s->write_enable = false;
584 }
585 break;
586 case EXTEND_ADDR_WRITE:
587 s->ear = s->data[0];
588 break;
589 case WNVCR:
590 s->nonvolatile_cfg = s->data[0] | (s->data[1] << 8);
591 break;
592 case WVCR:
593 s->volatile_cfg = s->data[0];
594 break;
595 case WEVCR:
596 s->enh_volatile_cfg = s->data[0];
597 break;
598 default:
599 break;
600 }
601 }
602
603 static void reset_memory(Flash *s)
604 {
605 s->cmd_in_progress = NOP;
606 s->cur_addr = 0;
607 s->ear = 0;
608 s->four_bytes_address_mode = false;
609 s->len = 0;
610 s->needed_bytes = 0;
611 s->pos = 0;
612 s->state = STATE_IDLE;
613 s->write_enable = false;
614 s->reset_enable = false;
615
616 switch (get_man(s)) {
617 case MAN_NUMONYX:
618 s->volatile_cfg = 0;
619 s->volatile_cfg |= VCFG_DUMMY;
620 s->volatile_cfg |= VCFG_WRAP_SEQUENTIAL;
621 if ((s->nonvolatile_cfg & NVCFG_XIP_MODE_MASK)
622 != NVCFG_XIP_MODE_DISABLED) {
623 s->volatile_cfg |= VCFG_XIP_MODE_ENABLED;
624 }
625 s->volatile_cfg |= deposit32(s->volatile_cfg,
626 VCFG_DUMMY_CLK_POS,
627 CFG_DUMMY_CLK_LEN,
628 extract32(s->nonvolatile_cfg,
629 NVCFG_DUMMY_CLK_POS,
630 CFG_DUMMY_CLK_LEN)
631 );
632
633 s->enh_volatile_cfg = 0;
634 s->enh_volatile_cfg |= EVCFG_OUT_DRIVER_STRENGHT_DEF;
635 s->enh_volatile_cfg |= EVCFG_VPP_ACCELERATOR;
636 s->enh_volatile_cfg |= EVCFG_RESET_HOLD_ENABLED;
637 if (s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK) {
638 s->enh_volatile_cfg |= EVCFG_DUAL_IO_ENABLED;
639 }
640 if (s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK) {
641 s->enh_volatile_cfg |= EVCFG_QUAD_IO_ENABLED;
642 }
643 if (!(s->nonvolatile_cfg & NVCFG_4BYTE_ADDR_MASK)) {
644 s->four_bytes_address_mode = true;
645 }
646 if (!(s->nonvolatile_cfg & NVCFG_LOWER_SEGMENT_MASK)) {
647 s->ear = s->size / MAX_3BYTES_SIZE - 1;
648 }
649 break;
650 default:
651 break;
652 }
653
654 DB_PRINT_L(0, "Reset done.\n");
655 }
656
657 static void decode_new_cmd(Flash *s, uint32_t value)
658 {
659 s->cmd_in_progress = value;
660 int i;
661 DB_PRINT_L(0, "decoded new command:%x\n", value);
662
663 if (value != RESET_MEMORY) {
664 s->reset_enable = false;
665 }
666
667 switch (value) {
668
669 case ERASE_4K:
670 case ERASE4_4K:
671 case ERASE_32K:
672 case ERASE_SECTOR:
673 case ERASE4_SECTOR:
674 case READ:
675 case READ4:
676 case DPP:
677 case QPP:
678 case PP:
679 case PP4:
680 s->needed_bytes = get_addr_length(s);
681 s->pos = 0;
682 s->len = 0;
683 s->state = STATE_COLLECTING_DATA;
684 break;
685
686 case FAST_READ:
687 case FAST_READ4:
688 case DOR:
689 case DOR4:
690 case QOR:
691 case QOR4:
692 s->needed_bytes = get_addr_length(s);
693 switch (get_man(s)) {
694 case MAN_NUMONYX:
695 s->needed_bytes += extract32(s->volatile_cfg, 4, 4);
696 break;
697 default:
698 break;
699 }
700 s->pos = 0;
701 s->len = 0;
702 s->state = STATE_COLLECTING_DATA;
703 break;
704
705 case DIOR:
706 case DIOR4:
707 switch (get_man(s)) {
708 case MAN_WINBOND:
709 case MAN_SPANSION:
710 s->needed_bytes = 4;
711 break;
712 default:
713 s->needed_bytes = get_addr_length(s);
714 /* Dummy cycles modeled with bytes writes instead of bits */
715 s->needed_bytes += extract32(s->volatile_cfg, 4, 4);
716 }
717 s->pos = 0;
718 s->len = 0;
719 s->state = STATE_COLLECTING_DATA;
720 break;
721
722 case QIOR:
723 case QIOR4:
724 switch (get_man(s)) {
725 case MAN_WINBOND:
726 case MAN_SPANSION:
727 s->needed_bytes = 6;
728 break;
729 default:
730 s->needed_bytes = get_addr_length(s);
731 /* Dummy cycles modeled with bytes writes instead of bits */
732 s->needed_bytes += extract32(s->volatile_cfg, 4, 4);
733 }
734 s->pos = 0;
735 s->len = 0;
736 s->state = STATE_COLLECTING_DATA;
737 break;
738
739 case WRSR:
740 if (s->write_enable) {
741 s->needed_bytes = 1;
742 s->pos = 0;
743 s->len = 0;
744 s->state = STATE_COLLECTING_DATA;
745 }
746 break;
747
748 case WRDI:
749 s->write_enable = false;
750 break;
751 case WREN:
752 s->write_enable = true;
753 break;
754
755 case RDSR:
756 s->data[0] = (!!s->write_enable) << 1;
757 s->pos = 0;
758 s->len = 1;
759 s->state = STATE_READING_DATA;
760 break;
761
762 case READ_FSR:
763 s->data[0] = FSR_FLASH_READY;
764 if (s->four_bytes_address_mode) {
765 s->data[0] |= FSR_4BYTE_ADDR_MODE_ENABLED;
766 }
767 s->pos = 0;
768 s->len = 1;
769 s->state = STATE_READING_DATA;
770 break;
771
772 case JEDEC_READ:
773 DB_PRINT_L(0, "populated jedec code\n");
774 for (i = 0; i < s->pi->id_len; i++) {
775 s->data[i] = s->pi->id[i];
776 }
777
778 s->len = s->pi->id_len;
779 s->pos = 0;
780 s->state = STATE_READING_DATA;
781 break;
782
783 case BULK_ERASE:
784 if (s->write_enable) {
785 DB_PRINT_L(0, "chip erase\n");
786 flash_erase(s, 0, BULK_ERASE);
787 } else {
788 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: chip erase with write "
789 "protect!\n");
790 }
791 break;
792 case NOP:
793 break;
794 case EN_4BYTE_ADDR:
795 s->four_bytes_address_mode = true;
796 break;
797 case EX_4BYTE_ADDR:
798 s->four_bytes_address_mode = false;
799 break;
800 case EXTEND_ADDR_READ:
801 s->data[0] = s->ear;
802 s->pos = 0;
803 s->len = 1;
804 s->state = STATE_READING_DATA;
805 break;
806 case EXTEND_ADDR_WRITE:
807 if (s->write_enable) {
808 s->needed_bytes = 1;
809 s->pos = 0;
810 s->len = 0;
811 s->state = STATE_COLLECTING_DATA;
812 }
813 break;
814 case RNVCR:
815 s->data[0] = s->nonvolatile_cfg & 0xFF;
816 s->data[1] = (s->nonvolatile_cfg >> 8) & 0xFF;
817 s->pos = 0;
818 s->len = 2;
819 s->state = STATE_READING_DATA;
820 break;
821 case WNVCR:
822 if (s->write_enable) {
823 s->needed_bytes = 2;
824 s->pos = 0;
825 s->len = 0;
826 s->state = STATE_COLLECTING_DATA;
827 }
828 break;
829 case RVCR:
830 s->data[0] = s->volatile_cfg & 0xFF;
831 s->pos = 0;
832 s->len = 1;
833 s->state = STATE_READING_DATA;
834 break;
835 case WVCR:
836 if (s->write_enable) {
837 s->needed_bytes = 1;
838 s->pos = 0;
839 s->len = 0;
840 s->state = STATE_COLLECTING_DATA;
841 }
842 break;
843 case REVCR:
844 s->data[0] = s->enh_volatile_cfg & 0xFF;
845 s->pos = 0;
846 s->len = 1;
847 s->state = STATE_READING_DATA;
848 break;
849 case WEVCR:
850 if (s->write_enable) {
851 s->needed_bytes = 1;
852 s->pos = 0;
853 s->len = 0;
854 s->state = STATE_COLLECTING_DATA;
855 }
856 break;
857 case RESET_ENABLE:
858 s->reset_enable = true;
859 break;
860 case RESET_MEMORY:
861 if (s->reset_enable) {
862 reset_memory(s);
863 }
864 break;
865 default:
866 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value);
867 break;
868 }
869 }
870
871 static int m25p80_cs(SSISlave *ss, bool select)
872 {
873 Flash *s = M25P80(ss);
874
875 if (select) {
876 if (s->state == STATE_COLLECTING_VAR_LEN_DATA) {
877 complete_collecting_data(s);
878 }
879 s->len = 0;
880 s->pos = 0;
881 s->state = STATE_IDLE;
882 flash_sync_dirty(s, -1);
883 }
884
885 DB_PRINT_L(0, "%sselect\n", select ? "de" : "");
886
887 return 0;
888 }
889
890 static uint32_t m25p80_transfer8(SSISlave *ss, uint32_t tx)
891 {
892 Flash *s = M25P80(ss);
893 uint32_t r = 0;
894
895 switch (s->state) {
896
897 case STATE_PAGE_PROGRAM:
898 DB_PRINT_L(1, "page program cur_addr=%#" PRIx64 " data=%" PRIx8 "\n",
899 s->cur_addr, (uint8_t)tx);
900 flash_write8(s, s->cur_addr, (uint8_t)tx);
901 s->cur_addr++;
902 break;
903
904 case STATE_READ:
905 r = s->storage[s->cur_addr];
906 DB_PRINT_L(1, "READ 0x%" PRIx64 "=%" PRIx8 "\n", s->cur_addr,
907 (uint8_t)r);
908 s->cur_addr = (s->cur_addr + 1) % s->size;
909 break;
910
911 case STATE_COLLECTING_DATA:
912 case STATE_COLLECTING_VAR_LEN_DATA:
913 s->data[s->len] = (uint8_t)tx;
914 s->len++;
915
916 if (s->len == s->needed_bytes) {
917 complete_collecting_data(s);
918 }
919 break;
920
921 case STATE_READING_DATA:
922 r = s->data[s->pos];
923 s->pos++;
924 if (s->pos == s->len) {
925 s->pos = 0;
926 s->state = STATE_IDLE;
927 }
928 break;
929
930 default:
931 case STATE_IDLE:
932 decode_new_cmd(s, (uint8_t)tx);
933 break;
934 }
935
936 return r;
937 }
938
939 static int m25p80_init(SSISlave *ss)
940 {
941 DriveInfo *dinfo;
942 Flash *s = M25P80(ss);
943 M25P80Class *mc = M25P80_GET_CLASS(s);
944
945 s->pi = mc->pi;
946
947 s->size = s->pi->sector_size * s->pi->n_sectors;
948 s->dirty_page = -1;
949
950 /* FIXME use a qdev drive property instead of drive_get_next() */
951 dinfo = drive_get_next(IF_MTD);
952
953 if (dinfo) {
954 DB_PRINT_L(0, "Binding to IF_MTD drive\n");
955 s->blk = blk_by_legacy_dinfo(dinfo);
956 blk_attach_dev_nofail(s->blk, s);
957
958 s->storage = blk_blockalign(s->blk, s->size);
959
960 /* FIXME: Move to late init */
961 if (blk_pread(s->blk, 0, s->storage, s->size) != s->size) {
962 fprintf(stderr, "Failed to initialize SPI flash!\n");
963 return 1;
964 }
965 } else {
966 DB_PRINT_L(0, "No BDRV - binding to RAM\n");
967 s->storage = blk_blockalign(NULL, s->size);
968 memset(s->storage, 0xFF, s->size);
969 }
970
971 return 0;
972 }
973
974 static void m25p80_reset(DeviceState *d)
975 {
976 Flash *s = M25P80(d);
977
978 reset_memory(s);
979 }
980
981 static void m25p80_pre_save(void *opaque)
982 {
983 flash_sync_dirty((Flash *)opaque, -1);
984 }
985
986 static Property m25p80_properties[] = {
987 DEFINE_PROP_UINT32("nonvolatile-cfg", Flash, nonvolatile_cfg, 0x8FFF),
988 DEFINE_PROP_END_OF_LIST(),
989 };
990
991 static const VMStateDescription vmstate_m25p80 = {
992 .name = "xilinx_spi",
993 .version_id = 2,
994 .minimum_version_id = 1,
995 .pre_save = m25p80_pre_save,
996 .fields = (VMStateField[]) {
997 VMSTATE_UINT8(state, Flash),
998 VMSTATE_UINT8_ARRAY(data, Flash, 16),
999 VMSTATE_UINT32(len, Flash),
1000 VMSTATE_UINT32(pos, Flash),
1001 VMSTATE_UINT8(needed_bytes, Flash),
1002 VMSTATE_UINT8(cmd_in_progress, Flash),
1003 VMSTATE_UINT64(cur_addr, Flash),
1004 VMSTATE_BOOL(write_enable, Flash),
1005 VMSTATE_BOOL_V(reset_enable, Flash, 2),
1006 VMSTATE_UINT8_V(ear, Flash, 2),
1007 VMSTATE_BOOL_V(four_bytes_address_mode, Flash, 2),
1008 VMSTATE_UINT32_V(nonvolatile_cfg, Flash, 2),
1009 VMSTATE_UINT32_V(volatile_cfg, Flash, 2),
1010 VMSTATE_UINT32_V(enh_volatile_cfg, Flash, 2),
1011 VMSTATE_END_OF_LIST()
1012 }
1013 };
1014
1015 static void m25p80_class_init(ObjectClass *klass, void *data)
1016 {
1017 DeviceClass *dc = DEVICE_CLASS(klass);
1018 SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
1019 M25P80Class *mc = M25P80_CLASS(klass);
1020
1021 k->init = m25p80_init;
1022 k->transfer = m25p80_transfer8;
1023 k->set_cs = m25p80_cs;
1024 k->cs_polarity = SSI_CS_LOW;
1025 dc->vmsd = &vmstate_m25p80;
1026 dc->props = m25p80_properties;
1027 dc->reset = m25p80_reset;
1028 mc->pi = data;
1029 }
1030
1031 static const TypeInfo m25p80_info = {
1032 .name = TYPE_M25P80,
1033 .parent = TYPE_SSI_SLAVE,
1034 .instance_size = sizeof(Flash),
1035 .class_size = sizeof(M25P80Class),
1036 .abstract = true,
1037 };
1038
1039 static void m25p80_register_types(void)
1040 {
1041 int i;
1042
1043 type_register_static(&m25p80_info);
1044 for (i = 0; i < ARRAY_SIZE(known_devices); ++i) {
1045 TypeInfo ti = {
1046 .name = known_devices[i].part_name,
1047 .parent = TYPE_M25P80,
1048 .class_init = m25p80_class_init,
1049 .class_data = (void *)&known_devices[i],
1050 };
1051 type_register(&ti);
1052 }
1053 }
1054
1055 type_init(m25p80_register_types)
AR7 emulation for QEMU