target/arm/cpu-qom.h

   1 /*
   2  * QEMU ARM CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20 #ifndef QEMU_ARM_CPU_QOM_H
  21 #define QEMU_ARM_CPU_QOM_H
  22
  23 #include "hw/core/cpu.h"
  24
  25 struct arm_boot_info;
  26
  27 #define TYPE_ARM_CPU "arm-cpu"
  28
  29 #define ARM_CPU_CLASS(klass) \
  30     OBJECT_CLASS_CHECK(ARMCPUClass, (klass), TYPE_ARM_CPU)
  31 #define ARM_CPU(obj) \
  32     OBJECT_CHECK(ARMCPU, (obj), TYPE_ARM_CPU)
  33 #define ARM_CPU_GET_CLASS(obj) \
  34     OBJECT_GET_CLASS(ARMCPUClass, (obj), TYPE_ARM_CPU)
  35
  36 #define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU
  37
  38 typedef struct ARMCPUInfo {
  39     const char *name;
  40     void (*initfn)(Object *obj);
  41     void (*class_init)(ObjectClass *oc, void *data);
  42 } ARMCPUInfo;
  43
  44 void arm_cpu_register(const ARMCPUInfo *info);
  45 void aarch64_cpu_register(const ARMCPUInfo *info);
  46
  47 /**
  48  * ARMCPUClass:
  49  * @parent_realize: The parent class' realize handler.
  50  * @parent_reset: The parent class' reset handler.
  51  *
  52  * An ARM CPU model.
  53  */
  54 typedef struct ARMCPUClass {
  55     /*< private >*/
  56     CPUClass parent_class;
  57     /*< public >*/
  58
  59     const ARMCPUInfo *info;
  60     DeviceRealize parent_realize;
  61     DeviceReset parent_reset;
  62 } ARMCPUClass;
  63
  64 typedef struct ARMCPU ARMCPU;
  65
  66 #define TYPE_AARCH64_CPU "aarch64-cpu"
  67 #define AARCH64_CPU_CLASS(klass) \
  68     OBJECT_CLASS_CHECK(AArch64CPUClass, (klass), TYPE_AARCH64_CPU)
  69 #define AARCH64_CPU_GET_CLASS(obj) \
  70     OBJECT_GET_CLASS(AArch64CPUClass, (obj), TYPE_AArch64_CPU)
  71
  72 typedef struct AArch64CPUClass {
  73     /*< private >*/
  74     ARMCPUClass parent_class;
  75     /*< public >*/
  76 } AArch64CPUClass;
  77
  78 void register_cp_regs_for_features(ARMCPU *cpu);
  79 void init_cpreg_list(ARMCPU *cpu);
  80
  81 /* Callback functions for the generic timer's timers. */
  82 void arm_gt_ptimer_cb(void *opaque);
  83 void arm_gt_vtimer_cb(void *opaque);
  84 void arm_gt_htimer_cb(void *opaque);
  85 void arm_gt_stimer_cb(void *opaque);
  86 void arm_gt_hvtimer_cb(void *opaque);
  87
  88 #define ARM_AFF0_SHIFT 0
  89 #define ARM_AFF0_MASK  (0xFFULL << ARM_AFF0_SHIFT)
  90 #define ARM_AFF1_SHIFT 8
  91 #define ARM_AFF1_MASK  (0xFFULL << ARM_AFF1_SHIFT)
  92 #define ARM_AFF2_SHIFT 16
  93 #define ARM_AFF2_MASK  (0xFFULL << ARM_AFF2_SHIFT)
  94 #define ARM_AFF3_SHIFT 32
  95 #define ARM_AFF3_MASK  (0xFFULL << ARM_AFF3_SHIFT)
  96 #define ARM_DEFAULT_CPUS_PER_CLUSTER 8
  97
  98 #define ARM32_AFFINITY_MASK (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK)
  99 #define ARM64_AFFINITY_MASK \
 100     (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK)
 101 #define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK)
 102
 103 #endif