| blob | 41be574e89d6b493107c1b94ee4156e1916f4ca6 |
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
5 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net>
6 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
27 #ifdef HOST_WORDS_BIGENDIAN
28 # define MIPS_BE 1
29 #else
30 # define MIPS_BE 0
31 #endif
33 #if TCG_TARGET_REG_BITS == 32
34 # define LO_OFF (MIPS_BE * 4)
35 # define HI_OFF (4 - LO_OFF)
36 #else
37 /* To assert at compile-time that these values are never used
38 for TCG_TARGET_REG_BITS == 64. */
39 int link_error(void);
40 # define LO_OFF link_error()
41 # define HI_OFF link_error()
42 #endif
44 #ifdef CONFIG_DEBUG_TCG
45 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
46 "zero",
47 "at",
48 "v0",
49 "v1",
50 "a0",
51 "a1",
52 "a2",
53 "a3",
54 "t0",
55 "t1",
56 "t2",
57 "t3",
58 "t4",
59 "t5",
60 "t6",
61 "t7",
62 "s0",
63 "s1",
64 "s2",
65 "s3",
66 "s4",
67 "s5",
68 "s6",
69 "s7",
70 "t8",
71 "t9",
72 "k0",
73 "k1",
74 "gp",
75 "sp",
76 "s8",
77 "ra",
78 };
79 #endif
81 #define TCG_TMP0 TCG_REG_AT
82 #define TCG_TMP1 TCG_REG_T9
83 #define TCG_TMP2 TCG_REG_T8
84 #define TCG_TMP3 TCG_REG_T7
86 #ifndef CONFIG_SOFTMMU
87 #define TCG_GUEST_BASE_REG TCG_REG_S1
88 #endif
90 /* check if we really need so many registers :P */
91 static const int tcg_target_reg_alloc_order[] = {
92 /* Call saved registers. */
93 TCG_REG_S0,
94 TCG_REG_S1,
95 TCG_REG_S2,
96 TCG_REG_S3,
97 TCG_REG_S4,
98 TCG_REG_S5,
99 TCG_REG_S6,
100 TCG_REG_S7,
101 TCG_REG_S8,
103 /* Call clobbered registers. */
104 TCG_REG_T4,
105 TCG_REG_T5,
106 TCG_REG_T6,
107 TCG_REG_T7,
108 TCG_REG_T8,
109 TCG_REG_T9,
110 TCG_REG_V1,
111 TCG_REG_V0,
113 /* Argument registers, opposite order of allocation. */
114 TCG_REG_T3,
115 TCG_REG_T2,
116 TCG_REG_T1,
117 TCG_REG_T0,
118 TCG_REG_A3,
119 TCG_REG_A2,
120 TCG_REG_A1,
121 TCG_REG_A0,
122 };
124 static const TCGReg tcg_target_call_iarg_regs[] = {
125 TCG_REG_A0,
126 TCG_REG_A1,
127 TCG_REG_A2,
128 TCG_REG_A3,
129 #if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64
130 TCG_REG_T0,
131 TCG_REG_T1,
132 TCG_REG_T2,
133 TCG_REG_T3,
134 #endif
135 };
137 static const TCGReg tcg_target_call_oarg_regs[2] = {
138 TCG_REG_V0,
139 TCG_REG_V1
140 };
142 static tcg_insn_unit *tb_ret_addr;
143 static tcg_insn_unit *bswap32_addr;
144 static tcg_insn_unit *bswap32u_addr;
145 static tcg_insn_unit *bswap64_addr;
147 static inline uint32_t reloc_pc16_val(tcg_insn_unit *pc, tcg_insn_unit *target)
148 {
149 /* Let the compiler perform the right-shift as part of the arithmetic. */
150 ptrdiff_t disp = target - (pc + 1);
151 tcg_debug_assert(disp == (int16_t)disp);
152 return disp & 0xffff;
153 }
155 static inline void reloc_pc16(tcg_insn_unit *pc, tcg_insn_unit *target)
156 {
157 *pc = deposit32(*pc, 0, 16, reloc_pc16_val(pc, target));
158 }
160 static inline uint32_t reloc_26_val(tcg_insn_unit *pc, tcg_insn_unit *target)
161 {
162 tcg_debug_assert((((uintptr_t)pc ^ (uintptr_t)target) & 0xf0000000) == 0);
163 return ((uintptr_t)target >> 2) & 0x3ffffff;
164 }
166 static inline void reloc_26(tcg_insn_unit *pc, tcg_insn_unit *target)
167 {
168 *pc = deposit32(*pc, 0, 26, reloc_26_val(pc, target));
169 }
171 static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
172 intptr_t value, intptr_t addend)
173 {
174 tcg_debug_assert(type == R_MIPS_PC16);
175 tcg_debug_assert(addend == 0);
176 reloc_pc16(code_ptr, (tcg_insn_unit *)value);
177 return true;
178 }
180 #define TCG_CT_CONST_ZERO 0x100
181 #define TCG_CT_CONST_U16 0x200 /* Unsigned 16-bit: 0 - 0xffff. */
182 #define TCG_CT_CONST_S16 0x400 /* Signed 16-bit: -32768 - 32767 */
183 #define TCG_CT_CONST_P2M1 0x800 /* Power of 2 minus 1. */
184 #define TCG_CT_CONST_N16 0x1000 /* "Negatable" 16-bit: -32767 - 32767 */
185 #define TCG_CT_CONST_WSZ 0x2000 /* word size */
187 static inline bool is_p2m1(tcg_target_long val)
188 {
189 return val && ((val + 1) & val) == 0;
190 }
192 /* parse target specific constraints */
193 static const char *target_parse_constraint(TCGArgConstraint *ct,
194 const char *ct_str, TCGType type)
195 {
196 switch(*ct_str++) {
197 case 'r':
198 ct->regs = 0xffffffff;
199 break;
200 case 'L': /* qemu_ld input arg constraint */
201 ct->regs = 0xffffffff;
202 tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
203 #if defined(CONFIG_SOFTMMU)
204 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
205 tcg_regset_reset_reg(ct->regs, TCG_REG_A2);
206 }
207 #endif
208 break;
209 case 'S': /* qemu_st constraint */
210 ct->regs = 0xffffffff;
211 tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
212 #if defined(CONFIG_SOFTMMU)
213 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
214 tcg_regset_reset_reg(ct->regs, TCG_REG_A2);
215 tcg_regset_reset_reg(ct->regs, TCG_REG_A3);
216 } else {
217 tcg_regset_reset_reg(ct->regs, TCG_REG_A1);
218 }
219 #endif
220 break;
221 case 'I':
222 ct->ct |= TCG_CT_CONST_U16;
223 break;
224 case 'J':
225 ct->ct |= TCG_CT_CONST_S16;
226 break;
227 case 'K':
228 ct->ct |= TCG_CT_CONST_P2M1;
229 break;
230 case 'N':
231 ct->ct |= TCG_CT_CONST_N16;
232 break;
233 case 'W':
234 ct->ct |= TCG_CT_CONST_WSZ;
235 break;
236 case 'Z':
237 /* We are cheating a bit here, using the fact that the register
238 ZERO is also the register number 0. Hence there is no need
239 to check for const_args in each instruction. */
240 ct->ct |= TCG_CT_CONST_ZERO;
241 break;
242 default:
243 return NULL;
244 }
245 return ct_str;
246 }
248 /* test if a constant matches the constraint */
249 static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
250 const TCGArgConstraint *arg_ct)
251 {
252 int ct;
253 ct = arg_ct->ct;
254 if (ct & TCG_CT_CONST) {
255 return 1;
256 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
257 return 1;
258 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) {
259 return 1;
260 } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) {
261 return 1;
262 } else if ((ct & TCG_CT_CONST_N16) && val >= -32767 && val <= 32767) {
263 return 1;
264 } else if ((ct & TCG_CT_CONST_P2M1)
265 && use_mips32r2_instructions && is_p2m1(val)) {
266 return 1;
267 } else if ((ct & TCG_CT_CONST_WSZ)
268 && val == (type == TCG_TYPE_I32 ? 32 : 64)) {
269 return 1;
270 }
271 return 0;
272 }
274 /* instruction opcodes */
275 typedef enum {
276 OPC_J = 002 << 26,
277 OPC_JAL = 003 << 26,
278 OPC_BEQ = 004 << 26,
279 OPC_BNE = 005 << 26,
280 OPC_BLEZ = 006 << 26,
281 OPC_BGTZ = 007 << 26,
282 OPC_ADDIU = 011 << 26,
283 OPC_SLTI = 012 << 26,
284 OPC_SLTIU = 013 << 26,
285 OPC_ANDI = 014 << 26,
286 OPC_ORI = 015 << 26,
287 OPC_XORI = 016 << 26,
288 OPC_LUI = 017 << 26,
289 OPC_DADDIU = 031 << 26,
290 OPC_LB = 040 << 26,
291 OPC_LH = 041 << 26,
292 OPC_LW = 043 << 26,
293 OPC_LBU = 044 << 26,
294 OPC_LHU = 045 << 26,
295 OPC_LWU = 047 << 26,
296 OPC_SB = 050 << 26,
297 OPC_SH = 051 << 26,
298 OPC_SW = 053 << 26,
299 OPC_LD = 067 << 26,
300 OPC_SD = 077 << 26,
302 OPC_SPECIAL = 000 << 26,
303 OPC_SLL = OPC_SPECIAL | 000,
304 OPC_SRL = OPC_SPECIAL | 002,
305 OPC_ROTR = OPC_SPECIAL | 002 | (1 << 21),
306 OPC_SRA = OPC_SPECIAL | 003,
307 OPC_SLLV = OPC_SPECIAL | 004,
308 OPC_SRLV = OPC_SPECIAL | 006,
309 OPC_ROTRV = OPC_SPECIAL | 006 | 0100,
310 OPC_SRAV = OPC_SPECIAL | 007,
311 OPC_JR_R5 = OPC_SPECIAL | 010,
312 OPC_JALR = OPC_SPECIAL | 011,
313 OPC_MOVZ = OPC_SPECIAL | 012,
314 OPC_MOVN = OPC_SPECIAL | 013,
315 OPC_SYNC = OPC_SPECIAL | 017,
316 OPC_MFHI = OPC_SPECIAL | 020,
317 OPC_MFLO = OPC_SPECIAL | 022,
318 OPC_DSLLV = OPC_SPECIAL | 024,
319 OPC_DSRLV = OPC_SPECIAL | 026,
320 OPC_DROTRV = OPC_SPECIAL | 026 | 0100,
321 OPC_DSRAV = OPC_SPECIAL | 027,
322 OPC_MULT = OPC_SPECIAL | 030,
323 OPC_MUL_R6 = OPC_SPECIAL | 030 | 0200,
324 OPC_MUH = OPC_SPECIAL | 030 | 0300,
325 OPC_MULTU = OPC_SPECIAL | 031,
326 OPC_MULU = OPC_SPECIAL | 031 | 0200,
327 OPC_MUHU = OPC_SPECIAL | 031 | 0300,
328 OPC_DIV = OPC_SPECIAL | 032,
329 OPC_DIV_R6 = OPC_SPECIAL | 032 | 0200,
330 OPC_MOD = OPC_SPECIAL | 032 | 0300,
331 OPC_DIVU = OPC_SPECIAL | 033,
332 OPC_DIVU_R6 = OPC_SPECIAL | 033 | 0200,
333 OPC_MODU = OPC_SPECIAL | 033 | 0300,
334 OPC_DMULT = OPC_SPECIAL | 034,
335 OPC_DMUL = OPC_SPECIAL | 034 | 0200,
336 OPC_DMUH = OPC_SPECIAL | 034 | 0300,
337 OPC_DMULTU = OPC_SPECIAL | 035,
338 OPC_DMULU = OPC_SPECIAL | 035 | 0200,
339 OPC_DMUHU = OPC_SPECIAL | 035 | 0300,
340 OPC_DDIV = OPC_SPECIAL | 036,
341 OPC_DDIV_R6 = OPC_SPECIAL | 036 | 0200,
342 OPC_DMOD = OPC_SPECIAL | 036 | 0300,
343 OPC_DDIVU = OPC_SPECIAL | 037,
344 OPC_DDIVU_R6 = OPC_SPECIAL | 037 | 0200,
345 OPC_DMODU = OPC_SPECIAL | 037 | 0300,
346 OPC_ADDU = OPC_SPECIAL | 041,
347 OPC_SUBU = OPC_SPECIAL | 043,
348 OPC_AND = OPC_SPECIAL | 044,
349 OPC_OR = OPC_SPECIAL | 045,
350 OPC_XOR = OPC_SPECIAL | 046,
351 OPC_NOR = OPC_SPECIAL | 047,
352 OPC_SLT = OPC_SPECIAL | 052,
353 OPC_SLTU = OPC_SPECIAL | 053,
354 OPC_DADDU = OPC_SPECIAL | 055,
355 OPC_DSUBU = OPC_SPECIAL | 057,
356 OPC_SELEQZ = OPC_SPECIAL | 065,
357 OPC_SELNEZ = OPC_SPECIAL | 067,
358 OPC_DSLL = OPC_SPECIAL | 070,
359 OPC_DSRL = OPC_SPECIAL | 072,
360 OPC_DROTR = OPC_SPECIAL | 072 | (1 << 21),
361 OPC_DSRA = OPC_SPECIAL | 073,
362 OPC_DSLL32 = OPC_SPECIAL | 074,
363 OPC_DSRL32 = OPC_SPECIAL | 076,
364 OPC_DROTR32 = OPC_SPECIAL | 076 | (1 << 21),
365 OPC_DSRA32 = OPC_SPECIAL | 077,
366 OPC_CLZ_R6 = OPC_SPECIAL | 0120,
367 OPC_DCLZ_R6 = OPC_SPECIAL | 0122,
369 OPC_REGIMM = 001 << 26,
370 OPC_BLTZ = OPC_REGIMM | (000 << 16),
371 OPC_BGEZ = OPC_REGIMM | (001 << 16),
373 OPC_SPECIAL2 = 034 << 26,
374 OPC_MUL_R5 = OPC_SPECIAL2 | 002,
375 OPC_CLZ = OPC_SPECIAL2 | 040,
376 OPC_DCLZ = OPC_SPECIAL2 | 044,
378 OPC_SPECIAL3 = 037 << 26,
379 OPC_EXT = OPC_SPECIAL3 | 000,
380 OPC_DEXTM = OPC_SPECIAL3 | 001,
381 OPC_DEXTU = OPC_SPECIAL3 | 002,
382 OPC_DEXT = OPC_SPECIAL3 | 003,
383 OPC_INS = OPC_SPECIAL3 | 004,
384 OPC_DINSM = OPC_SPECIAL3 | 005,
385 OPC_DINSU = OPC_SPECIAL3 | 006,
386 OPC_DINS = OPC_SPECIAL3 | 007,
387 OPC_WSBH = OPC_SPECIAL3 | 00240,
388 OPC_DSBH = OPC_SPECIAL3 | 00244,
389 OPC_DSHD = OPC_SPECIAL3 | 00544,
390 OPC_SEB = OPC_SPECIAL3 | 02040,
391 OPC_SEH = OPC_SPECIAL3 | 03040,
393 /* MIPS r6 doesn't have JR, JALR should be used instead */
394 OPC_JR = use_mips32r6_instructions ? OPC_JALR : OPC_JR_R5,
396 /*
397 * MIPS r6 replaces MUL with an alternative encoding which is
398 * backwards-compatible at the assembly level.
399 */
400 OPC_MUL = use_mips32r6_instructions ? OPC_MUL_R6 : OPC_MUL_R5,
402 /* MIPS r6 introduced names for weaker variants of SYNC. These are
403 backward compatible to previous architecture revisions. */
404 OPC_SYNC_WMB = OPC_SYNC | 0x04 << 6,
405 OPC_SYNC_MB = OPC_SYNC | 0x10 << 6,
406 OPC_SYNC_ACQUIRE = OPC_SYNC | 0x11 << 6,
407 OPC_SYNC_RELEASE = OPC_SYNC | 0x12 << 6,
408 OPC_SYNC_RMB = OPC_SYNC | 0x13 << 6,
410 /* Aliases for convenience. */
411 ALIAS_PADD = sizeof(void *) == 4 ? OPC_ADDU : OPC_DADDU,
412 ALIAS_PADDI = sizeof(void *) == 4 ? OPC_ADDIU : OPC_DADDIU,
413 ALIAS_TSRL = TARGET_LONG_BITS == 32 || TCG_TARGET_REG_BITS == 32
414 ? OPC_SRL : OPC_DSRL,
415 } MIPSInsn;
417 /*
418 * Type reg
419 */
420 static inline void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc,
421 TCGReg rd, TCGReg rs, TCGReg rt)
422 {
423 int32_t inst;
425 inst = opc;
426 inst |= (rs & 0x1F) << 21;
427 inst |= (rt & 0x1F) << 16;
428 inst |= (rd & 0x1F) << 11;
429 tcg_out32(s, inst);
430 }
432 /*
433 * Type immediate
434 */
435 static inline void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc,
436 TCGReg rt, TCGReg rs, TCGArg imm)
437 {
438 int32_t inst;
440 inst = opc;
441 inst |= (rs & 0x1F) << 21;
442 inst |= (rt & 0x1F) << 16;
443 inst |= (imm & 0xffff);
444 tcg_out32(s, inst);
445 }
447 /*
448 * Type bitfield
449 */
450 static inline void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt,
451 TCGReg rs, int msb, int lsb)
452 {
453 int32_t inst;
455 inst = opc;
456 inst |= (rs & 0x1F) << 21;
457 inst |= (rt & 0x1F) << 16;
458 inst |= (msb & 0x1F) << 11;
459 inst |= (lsb & 0x1F) << 6;
460 tcg_out32(s, inst);
461 }
463 static inline void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm,
464 MIPSInsn oph, TCGReg rt, TCGReg rs,
465 int msb, int lsb)
466 {
467 if (lsb >= 32) {
468 opc = oph;
469 msb -= 32;
470 lsb -= 32;
471 } else if (msb >= 32) {
472 opc = opm;
473 msb -= 32;
474 }
475 tcg_out_opc_bf(s, opc, rt, rs, msb, lsb);
476 }
478 /*
479 * Type branch
480 */
481 static inline void tcg_out_opc_br(TCGContext *s, MIPSInsn opc,
482 TCGReg rt, TCGReg rs)
483 {
484 tcg_out_opc_imm(s, opc, rt, rs, 0);
485 }
487 /*
488 * Type sa
489 */
490 static inline void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc,
491 TCGReg rd, TCGReg rt, TCGArg sa)
492 {
493 int32_t inst;
495 inst = opc;
496 inst |= (rt & 0x1F) << 16;
497 inst |= (rd & 0x1F) << 11;
498 inst |= (sa & 0x1F) << 6;
499 tcg_out32(s, inst);
501 }
503 static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2,
504 TCGReg rd, TCGReg rt, TCGArg sa)
505 {
506 int32_t inst;
508 inst = (sa & 32 ? opc2 : opc1);
509 inst |= (rt & 0x1F) << 16;
510 inst |= (rd & 0x1F) << 11;
511 inst |= (sa & 0x1F) << 6;
512 tcg_out32(s, inst);
513 }
515 /*
516 * Type jump.
517 * Returns true if the branch was in range and the insn was emitted.
518 */
519 static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, void *target)
520 {
521 uintptr_t dest = (uintptr_t)target;
522 uintptr_t from = (uintptr_t)s->code_ptr + 4;
523 int32_t inst;
525 /* The pc-region branch happens within the 256MB region of
526 the delay slot (thus the +4). */
527 if ((from ^ dest) & -(1 << 28)) {
528 return false;
529 }
530 tcg_debug_assert((dest & 3) == 0);
532 inst = opc;
533 inst |= (dest >> 2) & 0x3ffffff;
534 tcg_out32(s, inst);
535 return true;
536 }
538 static inline void tcg_out_nop(TCGContext *s)
539 {
540 tcg_out32(s, 0);
541 }
543 static inline void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
544 {
545 tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa);
546 }
548 static inline void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
549 {
550 tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa);
551 }
553 static inline void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
554 {
555 tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa);
556 }
558 static inline bool tcg_out_mov(TCGContext *s, TCGType type,
559 TCGReg ret, TCGReg arg)
560 {
561 /* Simple reg-reg move, optimising out the 'do nothing' case */
562 if (ret != arg) {
563 tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO);
564 }
565 return true;
566 }
568 static void tcg_out_movi(TCGContext *s, TCGType type,
569 TCGReg ret, tcg_target_long arg)
570 {
571 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
572 arg = (int32_t)arg;
573 }
574 if (arg == (int16_t)arg) {
575 tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg);
576 return;
577 }
578 if (arg == (uint16_t)arg) {
579 tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg);
580 return;
581 }
582 if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) {
583 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16);
584 } else {
585 tcg_out_movi(s, TCG_TYPE_I32, ret, arg >> 31 >> 1);
586 if (arg & 0xffff0000ull) {
587 tcg_out_dsll(s, ret, ret, 16);
588 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg >> 16);
589 tcg_out_dsll(s, ret, ret, 16);
590 } else {
591 tcg_out_dsll(s, ret, ret, 32);
592 }
593 }
594 if (arg & 0xffff) {
595 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff);
596 }
597 }
599 static inline void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg)
600 {
601 if (use_mips32r2_instructions) {
602 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
603 } else {
604 /* ret and arg can't be register at */
605 if (ret == TCG_TMP0 || arg == TCG_TMP0) {
606 tcg_abort();
607 }
609 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8);
610 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8);
611 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00);
612 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0);
613 }
614 }
616 static inline void tcg_out_bswap16s(TCGContext *s, TCGReg ret, TCGReg arg)
617 {
618 if (use_mips32r2_instructions) {
619 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
620 tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret);
621 } else {
622 /* ret and arg can't be register at */
623 if (ret == TCG_TMP0 || arg == TCG_TMP0) {
624 tcg_abort();
625 }
627 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8);
628 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24);
629 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16);
630 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0);
631 }
632 }
634 static void tcg_out_bswap_subr(TCGContext *s, tcg_insn_unit *sub)
635 {
636 bool ok = tcg_out_opc_jmp(s, OPC_JAL, sub);
637 tcg_debug_assert(ok);
638 }
640 static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg)
641 {
642 if (use_mips32r2_instructions) {
643 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
644 tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16);
645 } else {
646 tcg_out_bswap_subr(s, bswap32_addr);
647 /* delay slot -- never omit the insn, like tcg_out_mov might. */
648 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
649 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
650 }
651 }
653 static void tcg_out_bswap32u(TCGContext *s, TCGReg ret, TCGReg arg)
654 {
655 if (use_mips32r2_instructions) {
656 tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg);
657 tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret);
658 tcg_out_dsrl(s, ret, ret, 32);
659 } else {
660 tcg_out_bswap_subr(s, bswap32u_addr);
661 /* delay slot -- never omit the insn, like tcg_out_mov might. */
662 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
663 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
664 }
665 }
667 static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg)
668 {
669 if (use_mips32r2_instructions) {
670 tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg);
671 tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret);
672 } else {
673 tcg_out_bswap_subr(s, bswap64_addr);
674 /* delay slot -- never omit the insn, like tcg_out_mov might. */
675 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
676 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
677 }
678 }
680 static inline void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg)
681 {
682 if (use_mips32r2_instructions) {
683 tcg_out_opc_reg(s, OPC_SEB, ret, 0, arg);
684 } else {
685 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24);
686 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 24);
687 }
688 }
690 static inline void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg)
691 {
692 if (use_mips32r2_instructions) {
693 tcg_out_opc_reg(s, OPC_SEH, ret, 0, arg);
694 } else {
695 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 16);
696 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16);
697 }
698 }
700 static inline void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
701 {
702 if (use_mips32r2_instructions) {
703 tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0);
704 } else {
705 tcg_out_dsll(s, ret, arg, 32);
706 tcg_out_dsrl(s, ret, ret, 32);
707 }
708 }
710 static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data,
711 TCGReg addr, intptr_t ofs)
712 {
713 int16_t lo = ofs;
714 if (ofs != lo) {
715 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo);
716 if (addr != TCG_REG_ZERO) {
717 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_TMP0, addr);
718 }
719 addr = TCG_TMP0;
720 }
721 tcg_out_opc_imm(s, opc, data, addr, lo);
722 }
724 static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
725 TCGReg arg1, intptr_t arg2)
726 {
727 MIPSInsn opc = OPC_LD;
728 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) {
729 opc = OPC_LW;
730 }
731 tcg_out_ldst(s, opc, arg, arg1, arg2);
732 }
734 static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
735 TCGReg arg1, intptr_t arg2)
736 {
737 MIPSInsn opc = OPC_SD;
738 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) {
739 opc = OPC_SW;
740 }
741 tcg_out_ldst(s, opc, arg, arg1, arg2);
742 }
744 static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
745 TCGReg base, intptr_t ofs)
746 {
747 if (val == 0) {
748 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs);
749 return true;
750 }
751 return false;
752 }
754 static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al,
755 TCGReg ah, TCGArg bl, TCGArg bh, bool cbl,
756 bool cbh, bool is_sub)
757 {
758 TCGReg th = TCG_TMP1;
760 /* If we have a negative constant such that negating it would
761 make the high part zero, we can (usually) eliminate one insn. */
762 if (cbl && cbh && bh == -1 && bl != 0) {
763 bl = -bl;
764 bh = 0;
765 is_sub = !is_sub;
766 }
768 /* By operating on the high part first, we get to use the final
769 carry operation to move back from the temporary. */
770 if (!cbh) {
771 tcg_out_opc_reg(s, (is_sub ? OPC_SUBU : OPC_ADDU), th, ah, bh);
772 } else if (bh != 0 || ah == rl) {
773 tcg_out_opc_imm(s, OPC_ADDIU, th, ah, (is_sub ? -bh : bh));
774 } else {
775 th = ah;
776 }
778 /* Note that tcg optimization should eliminate the bl == 0 case. */
779 if (is_sub) {
780 if (cbl) {
781 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, al, bl);
782 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, -bl);
783 } else {
784 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, al, bl);
785 tcg_out_opc_reg(s, OPC_SUBU, rl, al, bl);
786 }
787 tcg_out_opc_reg(s, OPC_SUBU, rh, th, TCG_TMP0);
788 } else {
789 if (cbl) {
790 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, bl);
791 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, rl, bl);
792 } else if (rl == al && rl == bl) {
793 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, TCG_TARGET_REG_BITS - 1);
794 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl);
795 } else {
796 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl);
797 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, rl, (rl == bl ? al : bl));
798 }
799 tcg_out_opc_reg(s, OPC_ADDU, rh, th, TCG_TMP0);
800 }
801 }
803 /* Bit 0 set if inversion required; bit 1 set if swapping required. */
804 #define MIPS_CMP_INV 1
805 #define MIPS_CMP_SWAP 2
807 static const uint8_t mips_cmp_map[16] = {
808 [TCG_COND_LT] = 0,
809 [TCG_COND_LTU] = 0,
810 [TCG_COND_GE] = MIPS_CMP_INV,
811 [TCG_COND_GEU] = MIPS_CMP_INV,
812 [TCG_COND_LE] = MIPS_CMP_INV | MIPS_CMP_SWAP,
813 [TCG_COND_LEU] = MIPS_CMP_INV | MIPS_CMP_SWAP,
814 [TCG_COND_GT] = MIPS_CMP_SWAP,
815 [TCG_COND_GTU] = MIPS_CMP_SWAP,
816 };
818 static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret,
819 TCGReg arg1, TCGReg arg2)
820 {
821 MIPSInsn s_opc = OPC_SLTU;
822 int cmp_map;
824 switch (cond) {
825 case TCG_COND_EQ:
826 if (arg2 != 0) {
827 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2);
828 arg1 = ret;
829 }
830 tcg_out_opc_imm(s, OPC_SLTIU, ret, arg1, 1);
831 break;
833 case TCG_COND_NE:
834 if (arg2 != 0) {
835 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2);
836 arg1 = ret;
837 }
838 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, arg1);
839 break;
841 case TCG_COND_LT:
842 case TCG_COND_GE:
843 case TCG_COND_LE:
844 case TCG_COND_GT:
845 s_opc = OPC_SLT;
846 /* FALLTHRU */
848 case TCG_COND_LTU:
849 case TCG_COND_GEU:
850 case TCG_COND_LEU:
851 case TCG_COND_GTU:
852 cmp_map = mips_cmp_map[cond];
853 if (cmp_map & MIPS_CMP_SWAP) {
854 TCGReg t = arg1;
855 arg1 = arg2;
856 arg2 = t;
857 }
858 tcg_out_opc_reg(s, s_opc, ret, arg1, arg2);
859 if (cmp_map & MIPS_CMP_INV) {
860 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
861 }
862 break;
864 default:
865 tcg_abort();
866 break;
867 }
868 }
870 static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1,
871 TCGReg arg2, TCGLabel *l)
872 {
873 static const MIPSInsn b_zero[16] = {
874 [TCG_COND_LT] = OPC_BLTZ,
875 [TCG_COND_GT] = OPC_BGTZ,
876 [TCG_COND_LE] = OPC_BLEZ,
877 [TCG_COND_GE] = OPC_BGEZ,
878 };
880 MIPSInsn s_opc = OPC_SLTU;
881 MIPSInsn b_opc;
882 int cmp_map;
884 switch (cond) {
885 case TCG_COND_EQ:
886 b_opc = OPC_BEQ;
887 break;
888 case TCG_COND_NE:
889 b_opc = OPC_BNE;
890 break;
892 case TCG_COND_LT:
893 case TCG_COND_GT:
894 case TCG_COND_LE:
895 case TCG_COND_GE:
896 if (arg2 == 0) {
897 b_opc = b_zero[cond];
898 arg2 = arg1;
899 arg1 = 0;
900 break;
901 }
902 s_opc = OPC_SLT;
903 /* FALLTHRU */
905 case TCG_COND_LTU:
906 case TCG_COND_GTU:
907 case TCG_COND_LEU:
908 case TCG_COND_GEU:
909 cmp_map = mips_cmp_map[cond];
910 if (cmp_map & MIPS_CMP_SWAP) {
911 TCGReg t = arg1;
912 arg1 = arg2;
913 arg2 = t;
914 }
915 tcg_out_opc_reg(s, s_opc, TCG_TMP0, arg1, arg2);
916 b_opc = (cmp_map & MIPS_CMP_INV ? OPC_BEQ : OPC_BNE);
917 arg1 = TCG_TMP0;
918 arg2 = TCG_REG_ZERO;
919 break;
921 default:
922 tcg_abort();
923 break;
924 }
926 tcg_out_opc_br(s, b_opc, arg1, arg2);
927 if (l->has_value) {
928 reloc_pc16(s->code_ptr - 1, l->u.value_ptr);
929 } else {
930 tcg_out_reloc(s, s->code_ptr - 1, R_MIPS_PC16, l, 0);
931 }
932 tcg_out_nop(s);
933 }
935 static TCGReg tcg_out_reduce_eq2(TCGContext *s, TCGReg tmp0, TCGReg tmp1,
936 TCGReg al, TCGReg ah,
937 TCGReg bl, TCGReg bh)
938 {
939 /* Merge highpart comparison into AH. */
940 if (bh != 0) {
941 if (ah != 0) {
942 tcg_out_opc_reg(s, OPC_XOR, tmp0, ah, bh);
943 ah = tmp0;
944 } else {
945 ah = bh;
946 }
947 }
948 /* Merge lowpart comparison into AL. */
949 if (bl != 0) {
950 if (al != 0) {
951 tcg_out_opc_reg(s, OPC_XOR, tmp1, al, bl);
952 al = tmp1;
953 } else {
954 al = bl;
955 }
956 }
957 /* Merge high and low part comparisons into AL. */
958 if (ah != 0) {
959 if (al != 0) {
960 tcg_out_opc_reg(s, OPC_OR, tmp0, ah, al);
961 al = tmp0;
962 } else {
963 al = ah;
964 }
965 }
966 return al;
967 }
969 static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret,
970 TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh)
971 {
972 TCGReg tmp0 = TCG_TMP0;
973 TCGReg tmp1 = ret;
975 tcg_debug_assert(ret != TCG_TMP0);
976 if (ret == ah || ret == bh) {
977 tcg_debug_assert(ret != TCG_TMP1);
978 tmp1 = TCG_TMP1;
979 }
981 switch (cond) {
982 case TCG_COND_EQ:
983 case TCG_COND_NE:
984 tmp1 = tcg_out_reduce_eq2(s, tmp0, tmp1, al, ah, bl, bh);
985 tcg_out_setcond(s, cond, ret, tmp1, TCG_REG_ZERO);
986 break;
988 default:
989 tcg_out_setcond(s, TCG_COND_EQ, tmp0, ah, bh);
990 tcg_out_setcond(s, tcg_unsigned_cond(cond), tmp1, al, bl);
991 tcg_out_opc_reg(s, OPC_AND, tmp1, tmp1, tmp0);
992 tcg_out_setcond(s, tcg_high_cond(cond), tmp0, ah, bh);
993 tcg_out_opc_reg(s, OPC_OR, ret, tmp1, tmp0);
994 break;
995 }
996 }
998 static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah,
999 TCGReg bl, TCGReg bh, TCGLabel *l)
1000 {
1001 TCGCond b_cond = TCG_COND_NE;
1002 TCGReg tmp = TCG_TMP1;
1004 /* With branches, we emit between 4 and 9 insns with 2 or 3 branches.
1005 With setcond, we emit between 3 and 10 insns and only 1 branch,
1006 which ought to get better branch prediction. */
1007 switch (cond) {
1008 case TCG_COND_EQ:
1009 case TCG_COND_NE:
1010 b_cond = cond;
1011 tmp = tcg_out_reduce_eq2(s, TCG_TMP0, TCG_TMP1, al, ah, bl, bh);
1012 break;
1014 default:
1015 /* Minimize code size by preferring a compare not requiring INV. */
1016 if (mips_cmp_map[cond] & MIPS_CMP_INV) {
1017 cond = tcg_invert_cond(cond);
1018 b_cond = TCG_COND_EQ;
1019 }
1020 tcg_out_setcond2(s, cond, tmp, al, ah, bl, bh);
1021 break;
1022 }
1024 tcg_out_brcond(s, b_cond, tmp, TCG_REG_ZERO, l);
1025 }
1027 static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret,
1028 TCGReg c1, TCGReg c2, TCGReg v1, TCGReg v2)
1029 {
1030 bool eqz = false;
1032 /* If one of the values is zero, put it last to match SEL*Z instructions */
1033 if (use_mips32r6_instructions && v1 == 0) {
1034 v1 = v2;
1035 v2 = 0;
1036 cond = tcg_invert_cond(cond);
1037 }
1039 switch (cond) {
1040 case TCG_COND_EQ:
1041 eqz = true;
1042 /* FALLTHRU */
1043 case TCG_COND_NE:
1044 if (c2 != 0) {
1045 tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, c1, c2);
1046 c1 = TCG_TMP0;
1047 }
1048 break;
1050 default:
1051 /* Minimize code size by preferring a compare not requiring INV. */
1052 if (mips_cmp_map[cond] & MIPS_CMP_INV) {
1053 cond = tcg_invert_cond(cond);
1054 eqz = true;
1055 }
1056 tcg_out_setcond(s, cond, TCG_TMP0, c1, c2);
1057 c1 = TCG_TMP0;
1058 break;
1059 }
1061 if (use_mips32r6_instructions) {
1062 MIPSInsn m_opc_t = eqz ? OPC_SELEQZ : OPC_SELNEZ;
1063 MIPSInsn m_opc_f = eqz ? OPC_SELNEZ : OPC_SELEQZ;
1065 if (v2 != 0) {
1066 tcg_out_opc_reg(s, m_opc_f, TCG_TMP1, v2, c1);
1067 }
1068 tcg_out_opc_reg(s, m_opc_t, ret, v1, c1);
1069 if (v2 != 0) {
1070 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP1);
1071 }
1072 } else {
1073 MIPSInsn m_opc = eqz ? OPC_MOVZ : OPC_MOVN;
1075 tcg_out_opc_reg(s, m_opc, ret, v1, c1);
1077 /* This should be guaranteed via constraints */
1078 tcg_debug_assert(v2 == ret);
1079 }
1080 }
1082 static void tcg_out_call_int(TCGContext *s, tcg_insn_unit *arg, bool tail)
1083 {
1084 /* Note that the ABI requires the called function's address to be
1085 loaded into T9, even if a direct branch is in range. */
1086 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg);
1088 /* But do try a direct branch, allowing the cpu better insn prefetch. */
1089 if (tail) {
1090 if (!tcg_out_opc_jmp(s, OPC_J, arg)) {
1091 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_T9, 0);
1092 }
1093 } else {
1094 if (!tcg_out_opc_jmp(s, OPC_JAL, arg)) {
1095 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0);
1096 }
1097 }
1098 }
1100 static void tcg_out_call(TCGContext *s, tcg_insn_unit *arg)
1101 {
1102 tcg_out_call_int(s, arg, false);
1103 tcg_out_nop(s);
1104 }
1106 #if defined(CONFIG_SOFTMMU)
1107 #include "../tcg-ldst.c.inc"
1109 static void * const qemu_ld_helpers[16] = {
1110 [MO_UB] = helper_ret_ldub_mmu,
1111 [MO_SB] = helper_ret_ldsb_mmu,
1112 [MO_LEUW] = helper_le_lduw_mmu,
1113 [MO_LESW] = helper_le_ldsw_mmu,
1114 [MO_LEUL] = helper_le_ldul_mmu,
1115 [MO_LEQ] = helper_le_ldq_mmu,
1116 [MO_BEUW] = helper_be_lduw_mmu,
1117 [MO_BESW] = helper_be_ldsw_mmu,
1118 [MO_BEUL] = helper_be_ldul_mmu,
1119 [MO_BEQ] = helper_be_ldq_mmu,
1120 #if TCG_TARGET_REG_BITS == 64
1121 [MO_LESL] = helper_le_ldsl_mmu,
1122 [MO_BESL] = helper_be_ldsl_mmu,
1123 #endif
1124 };
1126 static void * const qemu_st_helpers[16] = {
1127 [MO_UB] = helper_ret_stb_mmu,
1128 [MO_LEUW] = helper_le_stw_mmu,
1129 [MO_LEUL] = helper_le_stl_mmu,
1130 [MO_LEQ] = helper_le_stq_mmu,
1131 [MO_BEUW] = helper_be_stw_mmu,
1132 [MO_BEUL] = helper_be_stl_mmu,
1133 [MO_BEQ] = helper_be_stq_mmu,
1134 };
1136 /* Helper routines for marshalling helper function arguments into
1137 * the correct registers and stack.
1138 * I is where we want to put this argument, and is updated and returned
1139 * for the next call. ARG is the argument itself.
1140 *
1141 * We provide routines for arguments which are: immediate, 32 bit
1142 * value in register, 16 and 8 bit values in register (which must be zero
1143 * extended before use) and 64 bit value in a lo:hi register pair.
1144 */
1146 static int tcg_out_call_iarg_reg(TCGContext *s, int i, TCGReg arg)
1147 {
1148 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
1149 tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[i], arg);
1150 } else {
1151 /* For N32 and N64, the initial offset is different. But there
1152 we also have 8 argument register so we don't run out here. */
1153 tcg_debug_assert(TCG_TARGET_REG_BITS == 32);
1154 tcg_out_st(s, TCG_TYPE_REG, arg, TCG_REG_SP, 4 * i);
1155 }
1156 return i + 1;
1157 }
1159 static int tcg_out_call_iarg_reg8(TCGContext *s, int i, TCGReg arg)
1160 {
1161 TCGReg tmp = TCG_TMP0;
1162 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
1163 tmp = tcg_target_call_iarg_regs[i];
1164 }
1165 tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xff);
1166 return tcg_out_call_iarg_reg(s, i, tmp);
1167 }
1169 static int tcg_out_call_iarg_reg16(TCGContext *s, int i, TCGReg arg)
1170 {
1171 TCGReg tmp = TCG_TMP0;
1172 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
1173 tmp = tcg_target_call_iarg_regs[i];
1174 }
1175 tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xffff);
1176 return tcg_out_call_iarg_reg(s, i, tmp);
1177 }
1179 static int tcg_out_call_iarg_imm(TCGContext *s, int i, TCGArg arg)
1180 {
1181 TCGReg tmp = TCG_TMP0;
1182 if (arg == 0) {
1183 tmp = TCG_REG_ZERO;
1184 } else {
1185 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
1186 tmp = tcg_target_call_iarg_regs[i];
1187 }
1188 tcg_out_movi(s, TCG_TYPE_REG, tmp, arg);
1189 }
1190 return tcg_out_call_iarg_reg(s, i, tmp);
1191 }
1193 static int tcg_out_call_iarg_reg2(TCGContext *s, int i, TCGReg al, TCGReg ah)
1194 {
1195 tcg_debug_assert(TCG_TARGET_REG_BITS == 32);
1196 i = (i + 1) & ~1;
1197 i = tcg_out_call_iarg_reg(s, i, (MIPS_BE ? ah : al));
1198 i = tcg_out_call_iarg_reg(s, i, (MIPS_BE ? al : ah));
1199 return i;
1200 }
1202 /* We expect to use a 16-bit negative offset from ENV. */
1203 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
1204 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768);
1206 /*
1207 * Perform the tlb comparison operation.
1208 * The complete host address is placed in BASE.
1209 * Clobbers TMP0, TMP1, TMP2, TMP3.
1210 */
1211 static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl,
1212 TCGReg addrh, TCGMemOpIdx oi,
1213 tcg_insn_unit *label_ptr[2], bool is_load)
1214 {
1215 MemOp opc = get_memop(oi);
1216 unsigned s_bits = opc & MO_SIZE;
1217 unsigned a_bits = get_alignment_bits(opc);
1218 int mem_index = get_mmuidx(oi);
1219 int fast_off = TLB_MASK_TABLE_OFS(mem_index);
1220 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
1221 int table_off = fast_off + offsetof(CPUTLBDescFast, table);
1222 int add_off = offsetof(CPUTLBEntry, addend);
1223 int cmp_off = (is_load ? offsetof(CPUTLBEntry, addr_read)
1224 : offsetof(CPUTLBEntry, addr_write));
1225 target_ulong mask;
1227 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
1228 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off);
1229 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off);
1231 /* Extract the TLB index from the address into TMP3. */
1232 tcg_out_opc_sa(s, ALIAS_TSRL, TCG_TMP3, addrl,
1233 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
1234 tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0);
1236 /* Add the tlb_table pointer, creating the CPUTLBEntry address in TMP3. */
1237 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1);
1239 /* We don't currently support unaligned accesses.
1240 We could do so with mips32r6. */
1241 if (a_bits < s_bits) {
1242 a_bits = s_bits;
1243 }
1245 /* Mask the page bits, keeping the alignment bits to compare against. */
1246 mask = (target_ulong)TARGET_PAGE_MASK | ((1 << a_bits) - 1);
1248 /* Load the (low-half) tlb comparator. */
1249 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1250 tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, cmp_off + LO_OFF);
1251 tcg_out_movi(s, TCG_TYPE_I32, TCG_TMP1, mask);
1252 } else {
1253 tcg_out_ldst(s, (TARGET_LONG_BITS == 64 ? OPC_LD
1254 : TCG_TARGET_REG_BITS == 64 ? OPC_LWU : OPC_LW),
1255 TCG_TMP0, TCG_TMP3, cmp_off);
1256 tcg_out_movi(s, TCG_TYPE_TL, TCG_TMP1, mask);
1257 /* No second compare is required here;
1258 load the tlb addend for the fast path. */
1259 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off);
1260 }
1261 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrl);
1263 /* Zero extend a 32-bit guest address for a 64-bit host. */
1264 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1265 tcg_out_ext32u(s, base, addrl);
1266 addrl = base;
1267 }
1269 label_ptr[0] = s->code_ptr;
1270 tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0);
1272 /* Load and test the high half tlb comparator. */
1273 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1274 /* delay slot */
1275 tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF);
1277 /* Load the tlb addend for the fast path. */
1278 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off);
1280 label_ptr[1] = s->code_ptr;
1281 tcg_out_opc_br(s, OPC_BNE, addrh, TCG_TMP0);
1282 }
1284 /* delay slot */
1285 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP2, addrl);
1286 }
1288 static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi,
1289 TCGType ext,
1290 TCGReg datalo, TCGReg datahi,
1291 TCGReg addrlo, TCGReg addrhi,
1292 void *raddr, tcg_insn_unit *label_ptr[2])
1293 {
1294 TCGLabelQemuLdst *label = new_ldst_label(s);
1296 label->is_ld = is_ld;
1297 label->oi = oi;
1298 label->type = ext;
1299 label->datalo_reg = datalo;
1300 label->datahi_reg = datahi;
1301 label->addrlo_reg = addrlo;
1302 label->addrhi_reg = addrhi;
1303 label->raddr = raddr;
1304 label->label_ptr[0] = label_ptr[0];
1305 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1306 label->label_ptr[1] = label_ptr[1];
1307 }
1308 }
1310 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
1311 {
1312 TCGMemOpIdx oi = l->oi;
1313 MemOp opc = get_memop(oi);
1314 TCGReg v0;
1315 int i;
1317 /* resolve label address */
1318 reloc_pc16(l->label_ptr[0], s->code_ptr);
1319 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1320 reloc_pc16(l->label_ptr[1], s->code_ptr);
1321 }
1323 i = 1;
1324 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1325 i = tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg);
1326 } else {
1327 i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg);
1328 }
1329 i = tcg_out_call_iarg_imm(s, i, oi);
1330 i = tcg_out_call_iarg_imm(s, i, (intptr_t)l->raddr);
1331 tcg_out_call_int(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)], false);
1332 /* delay slot */
1333 tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0);
1335 v0 = l->datalo_reg;
1336 if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) {
1337 /* We eliminated V0 from the possible output registers, so it
1338 cannot be clobbered here. So we must move V1 first. */
1339 if (MIPS_BE) {
1340 tcg_out_mov(s, TCG_TYPE_I32, v0, TCG_REG_V1);
1341 v0 = l->datahi_reg;
1342 } else {
1343 tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_V1);
1344 }
1345 }
1347 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO);
1348 reloc_pc16(s->code_ptr - 1, l->raddr);
1350 /* delay slot */
1351 if (TCG_TARGET_REG_BITS == 64 && l->type == TCG_TYPE_I32) {
1352 /* we always sign-extend 32-bit loads */
1353 tcg_out_opc_sa(s, OPC_SLL, v0, TCG_REG_V0, 0);
1354 } else {
1355 tcg_out_opc_reg(s, OPC_OR, v0, TCG_REG_V0, TCG_REG_ZERO);
1356 }
1357 return true;
1358 }
1360 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
1361 {
1362 TCGMemOpIdx oi = l->oi;
1363 MemOp opc = get_memop(oi);
1364 MemOp s_bits = opc & MO_SIZE;
1365 int i;
1367 /* resolve label address */
1368 reloc_pc16(l->label_ptr[0], s->code_ptr);
1369 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1370 reloc_pc16(l->label_ptr[1], s->code_ptr);
1371 }
1373 i = 1;
1374 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1375 i = tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg);
1376 } else {
1377 i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg);
1378 }
1379 switch (s_bits) {
1380 case MO_8:
1381 i = tcg_out_call_iarg_reg8(s, i, l->datalo_reg);
1382 break;
1383 case MO_16:
1384 i = tcg_out_call_iarg_reg16(s, i, l->datalo_reg);
1385 break;
1386 case MO_32:
1387 i = tcg_out_call_iarg_reg(s, i, l->datalo_reg);
1388 break;
1389 case MO_64:
1390 if (TCG_TARGET_REG_BITS == 32) {
1391 i = tcg_out_call_iarg_reg2(s, i, l->datalo_reg, l->datahi_reg);
1392 } else {
1393 i = tcg_out_call_iarg_reg(s, i, l->datalo_reg);
1394 }
1395 break;
1396 default:
1397 tcg_abort();
1398 }
1399 i = tcg_out_call_iarg_imm(s, i, oi);
1401 /* Tail call to the store helper. Thus force the return address
1402 computation to take place in the return address register. */
1403 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (intptr_t)l->raddr);
1404 i = tcg_out_call_iarg_reg(s, i, TCG_REG_RA);
1405 tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)], true);
1406 /* delay slot */
1407 tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0);
1408 return true;
1409 }
1410 #endif
1412 static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
1413 TCGReg base, MemOp opc, bool is_64)
1414 {
1415 switch (opc & (MO_SSIZE | MO_BSWAP)) {
1416 case MO_UB:
1417 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0);
1418 break;
1419 case MO_SB:
1420 tcg_out_opc_imm(s, OPC_LB, lo, base, 0);
1421 break;
1422 case MO_UW | MO_BSWAP:
1423 tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0);
1424 tcg_out_bswap16(s, lo, TCG_TMP1);
1425 break;
1426 case MO_UW:
1427 tcg_out_opc_imm(s, OPC_LHU, lo, base, 0);
1428 break;
1429 case MO_SW | MO_BSWAP:
1430 tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0);
1431 tcg_out_bswap16s(s, lo, TCG_TMP1);
1432 break;
1433 case MO_SW:
1434 tcg_out_opc_imm(s, OPC_LH, lo, base, 0);
1435 break;
1436 case MO_UL | MO_BSWAP:
1437 if (TCG_TARGET_REG_BITS == 64 && is_64) {
1438 if (use_mips32r2_instructions) {
1439 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0);
1440 tcg_out_bswap32u(s, lo, lo);
1441 } else {
1442 tcg_out_bswap_subr(s, bswap32u_addr);
1443 /* delay slot */
1444 tcg_out_opc_imm(s, OPC_LWU, TCG_TMP0, base, 0);
1445 tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3);
1446 }
1447 break;
1448 }
1449 /* FALLTHRU */
1450 case MO_SL | MO_BSWAP:
1451 if (use_mips32r2_instructions) {
1452 tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
1453 tcg_out_bswap32(s, lo, lo);
1454 } else {
1455 tcg_out_bswap_subr(s, bswap32_addr);
1456 /* delay slot */
1457 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0);
1458 tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_TMP3);
1459 }
1460 break;
1461 case MO_UL:
1462 if (TCG_TARGET_REG_BITS == 64 && is_64) {
1463 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0);
1464 break;
1465 }
1466 /* FALLTHRU */
1467 case MO_SL:
1468 tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
1469 break;
1470 case MO_Q | MO_BSWAP:
1471 if (TCG_TARGET_REG_BITS == 64) {
1472 if (use_mips32r2_instructions) {
1473 tcg_out_opc_imm(s, OPC_LD, lo, base, 0);
1474 tcg_out_bswap64(s, lo, lo);
1475 } else {
1476 tcg_out_bswap_subr(s, bswap64_addr);
1477 /* delay slot */
1478 tcg_out_opc_imm(s, OPC_LD, TCG_TMP0, base, 0);
1479 tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3);
1480 }
1481 } else if (use_mips32r2_instructions) {
1482 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0);
1483 tcg_out_opc_imm(s, OPC_LW, TCG_TMP1, base, 4);
1484 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, TCG_TMP0);
1485 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, TCG_TMP1);
1486 tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? lo : hi, TCG_TMP0, 16);
1487 tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? hi : lo, TCG_TMP1, 16);
1488 } else {
1489 tcg_out_bswap_subr(s, bswap32_addr);
1490 /* delay slot */
1491 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0);
1492 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 4);
1493 tcg_out_bswap_subr(s, bswap32_addr);
1494 /* delay slot */
1495 tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? lo : hi, TCG_TMP3);
1496 tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? hi : lo, TCG_TMP3);
1497 }
1498 break;
1499 case MO_Q:
1500 /* Prefer to load from offset 0 first, but allow for overlap. */
1501 if (TCG_TARGET_REG_BITS == 64) {
1502 tcg_out_opc_imm(s, OPC_LD, lo, base, 0);
1503 } else if (MIPS_BE ? hi != base : lo == base) {
1504 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF);
1505 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF);
1506 } else {
1507 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF);
1508 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF);
1509 }
1510 break;
1511 default:
1512 tcg_abort();
1513 }
1514 }
1516 static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
1517 {
1518 TCGReg addr_regl, addr_regh __attribute__((unused));
1519 TCGReg data_regl, data_regh;
1520 TCGMemOpIdx oi;
1521 MemOp opc;
1522 #if defined(CONFIG_SOFTMMU)
1523 tcg_insn_unit *label_ptr[2];
1524 #endif
1525 TCGReg base = TCG_REG_A0;
1527 data_regl = *args++;
1528 data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
1529 addr_regl = *args++;
1530 addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
1531 oi = *args++;
1532 opc = get_memop(oi);
1534 #if defined(CONFIG_SOFTMMU)
1535 tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 1);
1536 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
1537 add_qemu_ldst_label(s, 1, oi,
1538 (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
1539 data_regl, data_regh, addr_regl, addr_regh,
1540 s->code_ptr, label_ptr);
1541 #else
1542 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1543 tcg_out_ext32u(s, base, addr_regl);
1544 addr_regl = base;
1545 }
1546 if (guest_base == 0 && data_regl != addr_regl) {
1547 base = addr_regl;
1548 } else if (guest_base == (int16_t)guest_base) {
1549 tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base);
1550 } else {
1551 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl);
1552 }
1553 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
1554 #endif
1555 }
1557 static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,
1558 TCGReg base, MemOp opc)
1559 {
1560 /* Don't clutter the code below with checks to avoid bswapping ZERO. */
1561 if ((lo | hi) == 0) {
1562 opc &= ~MO_BSWAP;
1563 }
1565 switch (opc & (MO_SIZE | MO_BSWAP)) {
1566 case MO_8:
1567 tcg_out_opc_imm(s, OPC_SB, lo, base, 0);
1568 break;
1570 case MO_16 | MO_BSWAP:
1571 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, lo, 0xffff);
1572 tcg_out_bswap16(s, TCG_TMP1, TCG_TMP1);
1573 lo = TCG_TMP1;
1574 /* FALLTHRU */
1575 case MO_16:
1576 tcg_out_opc_imm(s, OPC_SH, lo, base, 0);
1577 break;
1579 case MO_32 | MO_BSWAP:
1580 tcg_out_bswap32(s, TCG_TMP3, lo);
1581 lo = TCG_TMP3;
1582 /* FALLTHRU */
1583 case MO_32:
1584 tcg_out_opc_imm(s, OPC_SW, lo, base, 0);
1585 break;
1587 case MO_64 | MO_BSWAP:
1588 if (TCG_TARGET_REG_BITS == 64) {
1589 tcg_out_bswap64(s, TCG_TMP3, lo);
1590 tcg_out_opc_imm(s, OPC_SD, TCG_TMP3, base, 0);
1591 } else if (use_mips32r2_instructions) {
1592 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, MIPS_BE ? lo : hi);
1593 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, MIPS_BE ? hi : lo);
1594 tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP0, TCG_TMP0, 16);
1595 tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP1, TCG_TMP1, 16);
1596 tcg_out_opc_imm(s, OPC_SW, TCG_TMP0, base, 0);
1597 tcg_out_opc_imm(s, OPC_SW, TCG_TMP1, base, 4);
1598 } else {
1599 tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? lo : hi);
1600 tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 0);
1601 tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? hi : lo);
1602 tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 4);
1603 }
1604 break;
1605 case MO_64:
1606 if (TCG_TARGET_REG_BITS == 64) {
1607 tcg_out_opc_imm(s, OPC_SD, lo, base, 0);
1608 } else {
1609 tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? hi : lo, base, 0);
1610 tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? lo : hi, base, 4);
1611 }
1612 break;
1614 default:
1615 tcg_abort();
1616 }
1617 }
1619 static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
1620 {
1621 TCGReg addr_regl, addr_regh __attribute__((unused));
1622 TCGReg data_regl, data_regh;
1623 TCGMemOpIdx oi;
1624 MemOp opc;
1625 #if defined(CONFIG_SOFTMMU)
1626 tcg_insn_unit *label_ptr[2];
1627 #endif
1628 TCGReg base = TCG_REG_A0;
1630 data_regl = *args++;
1631 data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
1632 addr_regl = *args++;
1633 addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
1634 oi = *args++;
1635 opc = get_memop(oi);
1637 #if defined(CONFIG_SOFTMMU)
1638 tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 0);
1639 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
1640 add_qemu_ldst_label(s, 0, oi,
1641 (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
1642 data_regl, data_regh, addr_regl, addr_regh,
1643 s->code_ptr, label_ptr);
1644 #else
1645 base = TCG_REG_A0;
1646 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1647 tcg_out_ext32u(s, base, addr_regl);
1648 addr_regl = base;
1649 }
1650 if (guest_base == 0) {
1651 base = addr_regl;
1652 } else if (guest_base == (int16_t)guest_base) {
1653 tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base);
1654 } else {
1655 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl);
1656 }
1657 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
1658 #endif
1659 }
1661 static void tcg_out_mb(TCGContext *s, TCGArg a0)
1662 {
1663 static const MIPSInsn sync[] = {
1664 /* Note that SYNC_MB is a slightly weaker than SYNC 0,
1665 as the former is an ordering barrier and the latter
1666 is a completion barrier. */
1667 [0 ... TCG_MO_ALL] = OPC_SYNC_MB,
1668 [TCG_MO_LD_LD] = OPC_SYNC_RMB,
1669 [TCG_MO_ST_ST] = OPC_SYNC_WMB,
1670 [TCG_MO_LD_ST] = OPC_SYNC_RELEASE,
1671 [TCG_MO_LD_ST | TCG_MO_ST_ST] = OPC_SYNC_RELEASE,
1672 [TCG_MO_LD_ST | TCG_MO_LD_LD] = OPC_SYNC_ACQUIRE,
1673 };
1674 tcg_out32(s, sync[a0 & TCG_MO_ALL]);
1675 }
1677 static void tcg_out_clz(TCGContext *s, MIPSInsn opcv2, MIPSInsn opcv6,
1678 int width, TCGReg a0, TCGReg a1, TCGArg a2)
1679 {
1680 if (use_mips32r6_instructions) {
1681 if (a2 == width) {
1682 tcg_out_opc_reg(s, opcv6, a0, a1, 0);
1683 } else {
1684 tcg_out_opc_reg(s, opcv6, TCG_TMP0, a1, 0);
1685 tcg_out_movcond(s, TCG_COND_EQ, a0, a1, 0, a2, TCG_TMP0);
1686 }
1687 } else {
1688 if (a2 == width) {
1689 tcg_out_opc_reg(s, opcv2, a0, a1, a1);
1690 } else if (a0 == a2) {
1691 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1);
1692 tcg_out_opc_reg(s, OPC_MOVN, a0, TCG_TMP0, a1);
1693 } else if (a0 != a1) {
1694 tcg_out_opc_reg(s, opcv2, a0, a1, a1);
1695 tcg_out_opc_reg(s, OPC_MOVZ, a0, a2, a1);
1696 } else {
1697 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1);
1698 tcg_out_opc_reg(s, OPC_MOVZ, TCG_TMP0, a2, a1);
1699 tcg_out_mov(s, TCG_TYPE_REG, a0, TCG_TMP0);
1700 }
1701 }
1702 }
1704 static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
1705 const TCGArg *args, const int *const_args)
1706 {
1707 MIPSInsn i1, i2;
1708 TCGArg a0, a1, a2;
1709 int c2;
1711 a0 = args[0];
1712 a1 = args[1];
1713 a2 = args[2];
1714 c2 = const_args[2];
1716 switch (opc) {
1717 case INDEX_op_exit_tb:
1718 {
1719 TCGReg b0 = TCG_REG_ZERO;
1721 a0 = (intptr_t)a0;
1722 if (a0 & ~0xffff) {
1723 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_V0, a0 & ~0xffff);
1724 b0 = TCG_REG_V0;
1725 }
1726 if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) {
1727 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0,
1728 (uintptr_t)tb_ret_addr);
1729 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0);
1730 }
1731 tcg_out_opc_imm(s, OPC_ORI, TCG_REG_V0, b0, a0 & 0xffff);
1732 }
1733 break;
1734 case INDEX_op_goto_tb:
1735 if (s->tb_jmp_insn_offset) {
1736 /* direct jump method */
1737 s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s);
1738 /* Avoid clobbering the address during retranslation. */
1739 tcg_out32(s, OPC_J | (*(uint32_t *)s->code_ptr & 0x3ffffff));
1740 } else {
1741 /* indirect jump method */
1742 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO,
1743 (uintptr_t)(s->tb_jmp_target_addr + a0));
1744 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0);
1745 }
1746 tcg_out_nop(s);
1747 set_jmp_reset_offset(s, a0);
1748 break;
1749 case INDEX_op_goto_ptr:
1750 /* jmp to the given host address (could be epilogue) */
1751 tcg_out_opc_reg(s, OPC_JR, 0, a0, 0);
1752 tcg_out_nop(s);
1753 break;
1754 case INDEX_op_br:
1755 tcg_out_brcond(s, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO,
1756 arg_label(a0));
1757 break;
1759 case INDEX_op_ld8u_i32:
1760 case INDEX_op_ld8u_i64:
1761 i1 = OPC_LBU;
1762 goto do_ldst;
1763 case INDEX_op_ld8s_i32:
1764 case INDEX_op_ld8s_i64:
1765 i1 = OPC_LB;
1766 goto do_ldst;
1767 case INDEX_op_ld16u_i32:
1768 case INDEX_op_ld16u_i64:
1769 i1 = OPC_LHU;
1770 goto do_ldst;
1771 case INDEX_op_ld16s_i32:
1772 case INDEX_op_ld16s_i64:
1773 i1 = OPC_LH;
1774 goto do_ldst;
1775 case INDEX_op_ld_i32:
1776 case INDEX_op_ld32s_i64:
1777 i1 = OPC_LW;
1778 goto do_ldst;
1779 case INDEX_op_ld32u_i64:
1780 i1 = OPC_LWU;
1781 goto do_ldst;
1782 case INDEX_op_ld_i64:
1783 i1 = OPC_LD;
1784 goto do_ldst;
1785 case INDEX_op_st8_i32:
1786 case INDEX_op_st8_i64:
1787 i1 = OPC_SB;
1788 goto do_ldst;
1789 case INDEX_op_st16_i32:
1790 case INDEX_op_st16_i64:
1791 i1 = OPC_SH;
1792 goto do_ldst;
1793 case INDEX_op_st_i32:
1794 case INDEX_op_st32_i64:
1795 i1 = OPC_SW;
1796 goto do_ldst;
1797 case INDEX_op_st_i64:
1798 i1 = OPC_SD;
1799 do_ldst:
1800 tcg_out_ldst(s, i1, a0, a1, a2);
1801 break;
1803 case INDEX_op_add_i32:
1804 i1 = OPC_ADDU, i2 = OPC_ADDIU;
1805 goto do_binary;
1806 case INDEX_op_add_i64:
1807 i1 = OPC_DADDU, i2 = OPC_DADDIU;
1808 goto do_binary;
1809 case INDEX_op_or_i32:
1810 case INDEX_op_or_i64:
1811 i1 = OPC_OR, i2 = OPC_ORI;
1812 goto do_binary;
1813 case INDEX_op_xor_i32:
1814 case INDEX_op_xor_i64:
1815 i1 = OPC_XOR, i2 = OPC_XORI;
1816 do_binary:
1817 if (c2) {
1818 tcg_out_opc_imm(s, i2, a0, a1, a2);
1819 break;
1820 }
1821 do_binaryv:
1822 tcg_out_opc_reg(s, i1, a0, a1, a2);
1823 break;
1825 case INDEX_op_sub_i32:
1826 i1 = OPC_SUBU, i2 = OPC_ADDIU;
1827 goto do_subtract;
1828 case INDEX_op_sub_i64:
1829 i1 = OPC_DSUBU, i2 = OPC_DADDIU;
1830 do_subtract:
1831 if (c2) {
1832 tcg_out_opc_imm(s, i2, a0, a1, -a2);
1833 break;
1834 }
1835 goto do_binaryv;
1836 case INDEX_op_and_i32:
1837 if (c2 && a2 != (uint16_t)a2) {
1838 int msb = ctz32(~a2) - 1;
1839 tcg_debug_assert(use_mips32r2_instructions);
1840 tcg_debug_assert(is_p2m1(a2));
1841 tcg_out_opc_bf(s, OPC_EXT, a0, a1, msb, 0);
1842 break;
1843 }
1844 i1 = OPC_AND, i2 = OPC_ANDI;
1845 goto do_binary;
1846 case INDEX_op_and_i64:
1847 if (c2 && a2 != (uint16_t)a2) {
1848 int msb = ctz64(~a2) - 1;
1849 tcg_debug_assert(use_mips32r2_instructions);
1850 tcg_debug_assert(is_p2m1(a2));
1851 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, msb, 0);
1852 break;
1853 }
1854 i1 = OPC_AND, i2 = OPC_ANDI;
1855 goto do_binary;
1856 case INDEX_op_nor_i32:
1857 case INDEX_op_nor_i64:
1858 i1 = OPC_NOR;
1859 goto do_binaryv;
1861 case INDEX_op_mul_i32:
1862 if (use_mips32_instructions) {
1863 tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2);
1864 break;
1865 }
1866 i1 = OPC_MULT, i2 = OPC_MFLO;
1867 goto do_hilo1;
1868 case INDEX_op_mulsh_i32:
1869 if (use_mips32r6_instructions) {
1870 tcg_out_opc_reg(s, OPC_MUH, a0, a1, a2);
1871 break;
1872 }
1873 i1 = OPC_MULT, i2 = OPC_MFHI;
1874 goto do_hilo1;
1875 case INDEX_op_muluh_i32:
1876 if (use_mips32r6_instructions) {
1877 tcg_out_opc_reg(s, OPC_MUHU, a0, a1, a2);
1878 break;
1879 }
1880 i1 = OPC_MULTU, i2 = OPC_MFHI;
1881 goto do_hilo1;
1882 case INDEX_op_div_i32:
1883 if (use_mips32r6_instructions) {
1884 tcg_out_opc_reg(s, OPC_DIV_R6, a0, a1, a2);
1885 break;
1886 }
1887 i1 = OPC_DIV, i2 = OPC_MFLO;
1888 goto do_hilo1;
1889 case INDEX_op_divu_i32:
1890 if (use_mips32r6_instructions) {
1891 tcg_out_opc_reg(s, OPC_DIVU_R6, a0, a1, a2);
1892 break;
1893 }
1894 i1 = OPC_DIVU, i2 = OPC_MFLO;
1895 goto do_hilo1;
1896 case INDEX_op_rem_i32:
1897 if (use_mips32r6_instructions) {
1898 tcg_out_opc_reg(s, OPC_MOD, a0, a1, a2);
1899 break;
1900 }
1901 i1 = OPC_DIV, i2 = OPC_MFHI;
1902 goto do_hilo1;
1903 case INDEX_op_remu_i32:
1904 if (use_mips32r6_instructions) {
1905 tcg_out_opc_reg(s, OPC_MODU, a0, a1, a2);
1906 break;
1907 }
1908 i1 = OPC_DIVU, i2 = OPC_MFHI;
1909 goto do_hilo1;
1910 case INDEX_op_mul_i64:
1911 if (use_mips32r6_instructions) {
1912 tcg_out_opc_reg(s, OPC_DMUL, a0, a1, a2);
1913 break;
1914 }
1915 i1 = OPC_DMULT, i2 = OPC_MFLO;
1916 goto do_hilo1;
1917 case INDEX_op_mulsh_i64:
1918 if (use_mips32r6_instructions) {
1919 tcg_out_opc_reg(s, OPC_DMUH, a0, a1, a2);
1920 break;
1921 }
1922 i1 = OPC_DMULT, i2 = OPC_MFHI;
1923 goto do_hilo1;
1924 case INDEX_op_muluh_i64:
1925 if (use_mips32r6_instructions) {
1926 tcg_out_opc_reg(s, OPC_DMUHU, a0, a1, a2);
1927 break;
1928 }
1929 i1 = OPC_DMULTU, i2 = OPC_MFHI;
1930 goto do_hilo1;
1931 case INDEX_op_div_i64:
1932 if (use_mips32r6_instructions) {
1933 tcg_out_opc_reg(s, OPC_DDIV_R6, a0, a1, a2);
1934 break;
1935 }
1936 i1 = OPC_DDIV, i2 = OPC_MFLO;
1937 goto do_hilo1;
1938 case INDEX_op_divu_i64:
1939 if (use_mips32r6_instructions) {
1940 tcg_out_opc_reg(s, OPC_DDIVU_R6, a0, a1, a2);
1941 break;
1942 }
1943 i1 = OPC_DDIVU, i2 = OPC_MFLO;
1944 goto do_hilo1;
1945 case INDEX_op_rem_i64:
1946 if (use_mips32r6_instructions) {
1947 tcg_out_opc_reg(s, OPC_DMOD, a0, a1, a2);
1948 break;
1949 }
1950 i1 = OPC_DDIV, i2 = OPC_MFHI;
1951 goto do_hilo1;
1952 case INDEX_op_remu_i64:
1953 if (use_mips32r6_instructions) {
1954 tcg_out_opc_reg(s, OPC_DMODU, a0, a1, a2);
1955 break;
1956 }
1957 i1 = OPC_DDIVU, i2 = OPC_MFHI;
1958 do_hilo1:
1959 tcg_out_opc_reg(s, i1, 0, a1, a2);
1960 tcg_out_opc_reg(s, i2, a0, 0, 0);
1961 break;
1963 case INDEX_op_muls2_i32:
1964 i1 = OPC_MULT;
1965 goto do_hilo2;
1966 case INDEX_op_mulu2_i32:
1967 i1 = OPC_MULTU;
1968 goto do_hilo2;
1969 case INDEX_op_muls2_i64:
1970 i1 = OPC_DMULT;
1971 goto do_hilo2;
1972 case INDEX_op_mulu2_i64:
1973 i1 = OPC_DMULTU;
1974 do_hilo2:
1975 tcg_out_opc_reg(s, i1, 0, a2, args[3]);
1976 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0);
1977 tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0);
1978 break;
1980 case INDEX_op_not_i32:
1981 case INDEX_op_not_i64:
1982 i1 = OPC_NOR;
1983 goto do_unary;
1984 case INDEX_op_bswap16_i32:
1985 case INDEX_op_bswap16_i64:
1986 i1 = OPC_WSBH;
1987 goto do_unary;
1988 case INDEX_op_ext8s_i32:
1989 case INDEX_op_ext8s_i64:
1990 i1 = OPC_SEB;
1991 goto do_unary;
1992 case INDEX_op_ext16s_i32:
1993 case INDEX_op_ext16s_i64:
1994 i1 = OPC_SEH;
1995 do_unary:
1996 tcg_out_opc_reg(s, i1, a0, TCG_REG_ZERO, a1);
1997 break;
1999 case INDEX_op_bswap32_i32:
2000 tcg_out_bswap32(s, a0, a1);
2001 break;
2002 case INDEX_op_bswap32_i64:
2003 tcg_out_bswap32u(s, a0, a1);
2004 break;
2005 case INDEX_op_bswap64_i64:
2006 tcg_out_bswap64(s, a0, a1);
2007 break;
2008 case INDEX_op_extrh_i64_i32:
2009 tcg_out_dsra(s, a0, a1, 32);
2010 break;
2011 case INDEX_op_ext32s_i64:
2012 case INDEX_op_ext_i32_i64:
2013 case INDEX_op_extrl_i64_i32:
2014 tcg_out_opc_sa(s, OPC_SLL, a0, a1, 0);
2015 break;
2016 case INDEX_op_ext32u_i64:
2017 case INDEX_op_extu_i32_i64:
2018 tcg_out_ext32u(s, a0, a1);
2019 break;
2021 case INDEX_op_sar_i32:
2022 i1 = OPC_SRAV, i2 = OPC_SRA;
2023 goto do_shift;
2024 case INDEX_op_shl_i32:
2025 i1 = OPC_SLLV, i2 = OPC_SLL;
2026 goto do_shift;
2027 case INDEX_op_shr_i32:
2028 i1 = OPC_SRLV, i2 = OPC_SRL;
2029 goto do_shift;
2030 case INDEX_op_rotr_i32:
2031 i1 = OPC_ROTRV, i2 = OPC_ROTR;
2032 do_shift:
2033 if (c2) {
2034 tcg_out_opc_sa(s, i2, a0, a1, a2);
2035 break;
2036 }
2037 do_shiftv:
2038 tcg_out_opc_reg(s, i1, a0, a2, a1);
2039 break;
2040 case INDEX_op_rotl_i32:
2041 if (c2) {
2042 tcg_out_opc_sa(s, OPC_ROTR, a0, a1, 32 - a2);
2043 } else {
2044 tcg_out_opc_reg(s, OPC_SUBU, TCG_TMP0, TCG_REG_ZERO, a2);
2045 tcg_out_opc_reg(s, OPC_ROTRV, a0, TCG_TMP0, a1);
2046 }
2047 break;
2048 case INDEX_op_sar_i64:
2049 if (c2) {
2050 tcg_out_dsra(s, a0, a1, a2);
2051 break;
2052 }
2053 i1 = OPC_DSRAV;
2054 goto do_shiftv;
2055 case INDEX_op_shl_i64:
2056 if (c2) {
2057 tcg_out_dsll(s, a0, a1, a2);
2058 break;
2059 }
2060 i1 = OPC_DSLLV;
2061 goto do_shiftv;
2062 case INDEX_op_shr_i64:
2063 if (c2) {
2064 tcg_out_dsrl(s, a0, a1, a2);
2065 break;
2066 }
2067 i1 = OPC_DSRLV;
2068 goto do_shiftv;
2069 case INDEX_op_rotr_i64:
2070 if (c2) {
2071 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, a2);
2072 break;
2073 }
2074 i1 = OPC_DROTRV;
2075 goto do_shiftv;
2076 case INDEX_op_rotl_i64:
2077 if (c2) {
2078 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, 64 - a2);
2079 } else {
2080 tcg_out_opc_reg(s, OPC_DSUBU, TCG_TMP0, TCG_REG_ZERO, a2);
2081 tcg_out_opc_reg(s, OPC_DROTRV, a0, TCG_TMP0, a1);
2082 }
2083 break;
2085 case INDEX_op_clz_i32:
2086 tcg_out_clz(s, OPC_CLZ, OPC_CLZ_R6, 32, a0, a1, a2);
2087 break;
2088 case INDEX_op_clz_i64:
2089 tcg_out_clz(s, OPC_DCLZ, OPC_DCLZ_R6, 64, a0, a1, a2);
2090 break;
2092 case INDEX_op_deposit_i32:
2093 tcg_out_opc_bf(s, OPC_INS, a0, a2, args[3] + args[4] - 1, args[3]);
2094 break;
2095 case INDEX_op_deposit_i64:
2096 tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2,
2097 args[3] + args[4] - 1, args[3]);
2098 break;
2099 case INDEX_op_extract_i32:
2100 tcg_out_opc_bf(s, OPC_EXT, a0, a1, args[3] - 1, a2);
2101 break;
2102 case INDEX_op_extract_i64:
2103 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1,
2104 args[3] - 1, a2);
2105 break;
2107 case INDEX_op_brcond_i32:
2108 case INDEX_op_brcond_i64:
2109 tcg_out_brcond(s, a2, a0, a1, arg_label(args[3]));
2110 break;
2111 case INDEX_op_brcond2_i32:
2112 tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5]));
2113 break;
2115 case INDEX_op_movcond_i32:
2116 case INDEX_op_movcond_i64:
2117 tcg_out_movcond(s, args[5], a0, a1, a2, args[3], args[4]);
2118 break;
2120 case INDEX_op_setcond_i32:
2121 case INDEX_op_setcond_i64:
2122 tcg_out_setcond(s, args[3], a0, a1, a2);
2123 break;
2124 case INDEX_op_setcond2_i32:
2125 tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]);
2126 break;
2128 case INDEX_op_qemu_ld_i32:
2129 tcg_out_qemu_ld(s, args, false);
2130 break;
2131 case INDEX_op_qemu_ld_i64:
2132 tcg_out_qemu_ld(s, args, true);
2133 break;
2134 case INDEX_op_qemu_st_i32:
2135 tcg_out_qemu_st(s, args, false);
2136 break;
2137 case INDEX_op_qemu_st_i64:
2138 tcg_out_qemu_st(s, args, true);
2139 break;
2141 case INDEX_op_add2_i32:
2142 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
2143 const_args[4], const_args[5], false);
2144 break;
2145 case INDEX_op_sub2_i32:
2146 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
2147 const_args[4], const_args[5], true);
2148 break;
2150 case INDEX_op_mb:
2151 tcg_out_mb(s, a0);
2152 break;
2153 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
2154 case INDEX_op_mov_i64:
2155 case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
2156 case INDEX_op_movi_i64:
2157 case INDEX_op_call: /* Always emitted via tcg_out_call. */
2158 default:
2159 tcg_abort();
2160 }
2161 }
2163 static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
2164 {
2165 static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
2166 static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
2167 static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
2168 static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } };
2169 static const TCGTargetOpDef SZ_S = { .args_ct_str = { "SZ", "S" } };
2170 static const TCGTargetOpDef rZ_rZ = { .args_ct_str = { "rZ", "rZ" } };
2171 static const TCGTargetOpDef r_r_L = { .args_ct_str = { "r", "r", "L" } };
2172 static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } };
2173 static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
2174 static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } };
2175 static const TCGTargetOpDef r_r_rJ = { .args_ct_str = { "r", "r", "rJ" } };
2176 static const TCGTargetOpDef SZ_S_S = { .args_ct_str = { "SZ", "S", "S" } };
2177 static const TCGTargetOpDef SZ_SZ_S
2178 = { .args_ct_str = { "SZ", "SZ", "S" } };
2179 static const TCGTargetOpDef SZ_SZ_S_S
2180 = { .args_ct_str = { "SZ", "SZ", "S", "S" } };
2181 static const TCGTargetOpDef r_rZ_rN
2182 = { .args_ct_str = { "r", "rZ", "rN" } };
2183 static const TCGTargetOpDef r_rZ_rZ
2184 = { .args_ct_str = { "r", "rZ", "rZ" } };
2185 static const TCGTargetOpDef r_r_rIK
2186 = { .args_ct_str = { "r", "r", "rIK" } };
2187 static const TCGTargetOpDef r_r_rWZ
2188 = { .args_ct_str = { "r", "r", "rWZ" } };
2189 static const TCGTargetOpDef r_r_r_r
2190 = { .args_ct_str = { "r", "r", "r", "r" } };
2191 static const TCGTargetOpDef r_r_L_L
2192 = { .args_ct_str = { "r", "r", "L", "L" } };
2193 static const TCGTargetOpDef dep
2194 = { .args_ct_str = { "r", "0", "rZ" } };
2195 static const TCGTargetOpDef movc
2196 = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "0" } };
2197 static const TCGTargetOpDef movc_r6
2198 = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } };
2199 static const TCGTargetOpDef add2
2200 = { .args_ct_str = { "r", "r", "rZ", "rZ", "rN", "rN" } };
2201 static const TCGTargetOpDef br2
2202 = { .args_ct_str = { "rZ", "rZ", "rZ", "rZ" } };
2203 static const TCGTargetOpDef setc2
2204 = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } };
2206 switch (op) {
2207 case INDEX_op_goto_ptr:
2208 return &r;
2210 case INDEX_op_ld8u_i32:
2211 case INDEX_op_ld8s_i32:
2212 case INDEX_op_ld16u_i32:
2213 case INDEX_op_ld16s_i32:
2214 case INDEX_op_ld_i32:
2215 case INDEX_op_not_i32:
2216 case INDEX_op_bswap16_i32:
2217 case INDEX_op_bswap32_i32:
2218 case INDEX_op_ext8s_i32:
2219 case INDEX_op_ext16s_i32:
2220 case INDEX_op_extract_i32:
2221 case INDEX_op_ld8u_i64:
2222 case INDEX_op_ld8s_i64:
2223 case INDEX_op_ld16u_i64:
2224 case INDEX_op_ld16s_i64:
2225 case INDEX_op_ld32s_i64:
2226 case INDEX_op_ld32u_i64:
2227 case INDEX_op_ld_i64:
2228 case INDEX_op_not_i64:
2229 case INDEX_op_bswap16_i64:
2230 case INDEX_op_bswap32_i64:
2231 case INDEX_op_bswap64_i64:
2232 case INDEX_op_ext8s_i64:
2233 case INDEX_op_ext16s_i64:
2234 case INDEX_op_ext32s_i64:
2235 case INDEX_op_ext32u_i64:
2236 case INDEX_op_ext_i32_i64:
2237 case INDEX_op_extu_i32_i64:
2238 case INDEX_op_extrl_i64_i32:
2239 case INDEX_op_extrh_i64_i32:
2240 case INDEX_op_extract_i64:
2241 return &r_r;
2243 case INDEX_op_st8_i32:
2244 case INDEX_op_st16_i32:
2245 case INDEX_op_st_i32:
2246 case INDEX_op_st8_i64:
2247 case INDEX_op_st16_i64:
2248 case INDEX_op_st32_i64:
2249 case INDEX_op_st_i64:
2250 return &rZ_r;
2252 case INDEX_op_add_i32:
2253 case INDEX_op_add_i64:
2254 return &r_r_rJ;
2255 case INDEX_op_sub_i32:
2256 case INDEX_op_sub_i64:
2257 return &r_rZ_rN;
2258 case INDEX_op_mul_i32:
2259 case INDEX_op_mulsh_i32:
2260 case INDEX_op_muluh_i32:
2261 case INDEX_op_div_i32:
2262 case INDEX_op_divu_i32:
2263 case INDEX_op_rem_i32:
2264 case INDEX_op_remu_i32:
2265 case INDEX_op_nor_i32:
2266 case INDEX_op_setcond_i32:
2267 case INDEX_op_mul_i64:
2268 case INDEX_op_mulsh_i64:
2269 case INDEX_op_muluh_i64:
2270 case INDEX_op_div_i64:
2271 case INDEX_op_divu_i64:
2272 case INDEX_op_rem_i64:
2273 case INDEX_op_remu_i64:
2274 case INDEX_op_nor_i64:
2275 case INDEX_op_setcond_i64:
2276 return &r_rZ_rZ;
2277 case INDEX_op_muls2_i32:
2278 case INDEX_op_mulu2_i32:
2279 case INDEX_op_muls2_i64:
2280 case INDEX_op_mulu2_i64:
2281 return &r_r_r_r;
2282 case INDEX_op_and_i32:
2283 case INDEX_op_and_i64:
2284 return &r_r_rIK;
2285 case INDEX_op_or_i32:
2286 case INDEX_op_xor_i32:
2287 case INDEX_op_or_i64:
2288 case INDEX_op_xor_i64:
2289 return &r_r_rI;
2290 case INDEX_op_shl_i32:
2291 case INDEX_op_shr_i32:
2292 case INDEX_op_sar_i32:
2293 case INDEX_op_rotr_i32:
2294 case INDEX_op_rotl_i32:
2295 case INDEX_op_shl_i64:
2296 case INDEX_op_shr_i64:
2297 case INDEX_op_sar_i64:
2298 case INDEX_op_rotr_i64:
2299 case INDEX_op_rotl_i64:
2300 return &r_r_ri;
2301 case INDEX_op_clz_i32:
2302 case INDEX_op_clz_i64:
2303 return &r_r_rWZ;
2305 case INDEX_op_deposit_i32:
2306 case INDEX_op_deposit_i64:
2307 return &dep;
2308 case INDEX_op_brcond_i32:
2309 case INDEX_op_brcond_i64:
2310 return &rZ_rZ;
2311 case INDEX_op_movcond_i32:
2312 case INDEX_op_movcond_i64:
2313 return use_mips32r6_instructions ? &movc_r6 : &movc;
2315 case INDEX_op_add2_i32:
2316 case INDEX_op_sub2_i32:
2317 return &add2;
2318 case INDEX_op_setcond2_i32:
2319 return &setc2;
2320 case INDEX_op_brcond2_i32:
2321 return &br2;
2323 case INDEX_op_qemu_ld_i32:
2324 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
2325 ? &r_L : &r_L_L);
2326 case INDEX_op_qemu_st_i32:
2327 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
2328 ? &SZ_S : &SZ_S_S);
2329 case INDEX_op_qemu_ld_i64:
2330 return (TCG_TARGET_REG_BITS == 64 ? &r_L
2331 : TARGET_LONG_BITS == 32 ? &r_r_L : &r_r_L_L);
2332 case INDEX_op_qemu_st_i64:
2333 return (TCG_TARGET_REG_BITS == 64 ? &SZ_S
2334 : TARGET_LONG_BITS == 32 ? &SZ_SZ_S : &SZ_SZ_S_S);
2336 default:
2337 return NULL;
2338 }
2339 }
2341 static const int tcg_target_callee_save_regs[] = {
2342 TCG_REG_S0, /* used for the global env (TCG_AREG0) */
2343 TCG_REG_S1,
2344 TCG_REG_S2,
2345 TCG_REG_S3,
2346 TCG_REG_S4,
2347 TCG_REG_S5,
2348 TCG_REG_S6,
2349 TCG_REG_S7,
2350 TCG_REG_S8,
2351 TCG_REG_RA, /* should be last for ABI compliance */
2352 };
2354 /* The Linux kernel doesn't provide any information about the available
2355 instruction set. Probe it using a signal handler. */
2358 #ifndef use_movnz_instructions
2359 bool use_movnz_instructions = false;
2360 #endif
2362 #ifndef use_mips32_instructions
2363 bool use_mips32_instructions = false;
2364 #endif
2366 #ifndef use_mips32r2_instructions
2367 bool use_mips32r2_instructions = false;
2368 #endif
2370 static volatile sig_atomic_t got_sigill;
2372 static void sigill_handler(int signo, siginfo_t *si, void *data)
2373 {
2374 /* Skip the faulty instruction */
2375 ucontext_t *uc = (ucontext_t *)data;
2376 uc->uc_mcontext.pc += 4;
2378 got_sigill = 1;
2379 }
2381 static void tcg_target_detect_isa(void)
2382 {
2383 struct sigaction sa_old, sa_new;
2385 memset(&sa_new, 0, sizeof(sa_new));
2386 sa_new.sa_flags = SA_SIGINFO;
2387 sa_new.sa_sigaction = sigill_handler;
2388 sigaction(SIGILL, &sa_new, &sa_old);
2390 /* Probe for movn/movz, necessary to implement movcond. */
2391 #ifndef use_movnz_instructions
2392 got_sigill = 0;
2393 asm volatile(".set push\n"
2394 ".set mips32\n"
2395 "movn $zero, $zero, $zero\n"
2396 "movz $zero, $zero, $zero\n"
2397 ".set pop\n"
2398 : : : );
2399 use_movnz_instructions = !got_sigill;
2400 #endif
2402 /* Probe for MIPS32 instructions. As no subsetting is allowed
2403 by the specification, it is only necessary to probe for one
2404 of the instructions. */
2405 #ifndef use_mips32_instructions
2406 got_sigill = 0;
2407 asm volatile(".set push\n"
2408 ".set mips32\n"
2409 "mul $zero, $zero\n"
2410 ".set pop\n"
2411 : : : );
2412 use_mips32_instructions = !got_sigill;
2413 #endif
2415 /* Probe for MIPS32r2 instructions if MIPS32 instructions are
2416 available. As no subsetting is allowed by the specification,
2417 it is only necessary to probe for one of the instructions. */
2418 #ifndef use_mips32r2_instructions
2419 if (use_mips32_instructions) {
2420 got_sigill = 0;
2421 asm volatile(".set push\n"
2422 ".set mips32r2\n"
2423 "seb $zero, $zero\n"
2424 ".set pop\n"
2425 : : : );
2426 use_mips32r2_instructions = !got_sigill;
2427 }
2428 #endif
2430 sigaction(SIGILL, &sa_old, NULL);
2431 }
2433 static tcg_insn_unit *align_code_ptr(TCGContext *s)
2434 {
2435 uintptr_t p = (uintptr_t)s->code_ptr;
2436 if (p & 15) {
2437 p = (p + 15) & -16;
2438 s->code_ptr = (void *)p;
2439 }
2440 return s->code_ptr;
2441 }
2443 /* Stack frame parameters. */
2444 #define REG_SIZE (TCG_TARGET_REG_BITS / 8)
2445 #define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE)
2446 #define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
2448 #define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \
2449 + TCG_TARGET_STACK_ALIGN - 1) \
2450 & -TCG_TARGET_STACK_ALIGN)
2451 #define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE)
2453 /* We're expecting to be able to use an immediate for frame allocation. */
2454 QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7fff);
2456 /* Generate global QEMU prologue and epilogue code */
2457 static void tcg_target_qemu_prologue(TCGContext *s)
2458 {
2459 int i;
2461 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE);
2463 /* TB prologue */
2464 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE);
2465 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
2466 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
2467 TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
2468 }
2470 #ifndef CONFIG_SOFTMMU
2471 if (guest_base) {
2472 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
2473 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
2474 }
2475 #endif
2477 /* Call generated code */
2478 tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0);
2479 /* delay slot */
2480 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
2482 /*
2483 * Return path for goto_ptr. Set return value to 0, a-la exit_tb,
2484 * and fall through to the rest of the epilogue.
2485 */
2486 s->code_gen_epilogue = s->code_ptr;
2487 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_V0, TCG_REG_ZERO);
2489 /* TB epilogue */
2490 tb_ret_addr = s->code_ptr;
2491 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
2492 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
2493 TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
2494 }
2496 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2497 /* delay slot */
2498 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE);
2500 if (use_mips32r2_instructions) {
2501 return;
2502 }
2504 /* Bswap subroutines: Input in TCG_TMP0, output in TCG_TMP3;
2505 clobbers TCG_TMP1, TCG_TMP2. */
2507 /*
2508 * bswap32 -- 32-bit swap (signed result for mips64). a0 = abcd.
2509 */
2510 bswap32_addr = align_code_ptr(s);
2511 /* t3 = (ssss)d000 */
2512 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP3, TCG_TMP0, 24);
2513 /* t1 = 000a */
2514 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 24);
2515 /* t2 = 00c0 */
2516 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
2517 /* t3 = d00a */
2518 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2519 /* t1 = 0abc */
2520 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8);
2521 /* t2 = 0c00 */
2522 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8);
2523 /* t1 = 00b0 */
2524 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2525 /* t3 = dc0a */
2526 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2527 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2528 /* t3 = dcba -- delay slot */
2529 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2531 if (TCG_TARGET_REG_BITS == 32) {
2532 return;
2533 }
2535 /*
2536 * bswap32u -- unsigned 32-bit swap. a0 = ....abcd.
2537 */
2538 bswap32u_addr = align_code_ptr(s);
2539 /* t1 = (0000)000d */
2540 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP0, 0xff);
2541 /* t3 = 000a */
2542 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, TCG_TMP0, 24);
2543 /* t1 = (0000)d000 */
2544 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24);
2545 /* t2 = 00c0 */
2546 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
2547 /* t3 = d00a */
2548 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2549 /* t1 = 0abc */
2550 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8);
2551 /* t2 = 0c00 */
2552 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8);
2553 /* t1 = 00b0 */
2554 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2555 /* t3 = dc0a */
2556 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2557 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2558 /* t3 = dcba -- delay slot */
2559 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2561 /*
2562 * bswap64 -- 64-bit swap. a0 = abcdefgh
2563 */
2564 bswap64_addr = align_code_ptr(s);
2565 /* t3 = h0000000 */
2566 tcg_out_dsll(s, TCG_TMP3, TCG_TMP0, 56);
2567 /* t1 = 0000000a */
2568 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 56);
2570 /* t2 = 000000g0 */
2571 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
2572 /* t3 = h000000a */
2573 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2574 /* t1 = 00000abc */
2575 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 40);
2576 /* t2 = 0g000000 */
2577 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40);
2578 /* t1 = 000000b0 */
2579 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2581 /* t3 = hg00000a */
2582 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2583 /* t2 = 0000abcd */
2584 tcg_out_dsrl(s, TCG_TMP2, TCG_TMP0, 32);
2585 /* t3 = hg0000ba */
2586 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2588 /* t1 = 000000c0 */
2589 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP2, 0xff00);
2590 /* t2 = 0000000d */
2591 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP2, 0x00ff);
2592 /* t1 = 00000c00 */
2593 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 8);
2594 /* t2 = 0000d000 */
2595 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 24);
2597 /* t3 = hg000cba */
2598 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2599 /* t1 = 00abcdef */
2600 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 16);
2601 /* t3 = hg00dcba */
2602 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2604 /* t2 = 0000000f */
2605 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP1, 0x00ff);
2606 /* t1 = 000000e0 */
2607 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2608 /* t2 = 00f00000 */
2609 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40);
2610 /* t1 = 000e0000 */
2611 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24);
2613 /* t3 = hgf0dcba */
2614 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2615 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2616 /* t3 = hgfedcba -- delay slot */
2617 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2618 }
2620 static void tcg_target_init(TCGContext *s)
2621 {
2622 tcg_target_detect_isa();
2623 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
2624 if (TCG_TARGET_REG_BITS == 64) {
2625 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
2626 }
2628 tcg_target_call_clobber_regs = 0;
2629 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0);
2630 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1);
2631 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A0);
2632 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A1);
2633 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A2);
2634 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A3);
2635 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T0);
2636 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T1);
2637 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T2);
2638 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T3);
2639 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T4);
2640 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T5);
2641 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T6);
2642 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T7);
2643 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T8);
2644 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T9);
2646 s->reserved_regs = 0;
2647 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */
2648 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K0); /* kernel use only */
2649 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1); /* kernel use only */
2650 tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); /* internal use */
2651 tcg_regset_set_reg(s->reserved_regs, TCG_TMP1); /* internal use */
2652 tcg_regset_set_reg(s->reserved_regs, TCG_TMP2); /* internal use */
2653 tcg_regset_set_reg(s->reserved_regs, TCG_TMP3); /* internal use */
2654 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */
2655 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */
2656 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */
2657 }
2659 void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr,
2660 uintptr_t addr)
2661 {
2662 qatomic_set((uint32_t *)jmp_addr, deposit32(OPC_J, 0, 26, addr >> 2));
2663 flush_icache_range(jmp_addr, jmp_addr + 4);
2664 }
2666 typedef struct {
2667 DebugFrameHeader h;
2668 uint8_t fde_def_cfa[4];
2669 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2];
2670 } DebugFrame;
2672 #define ELF_HOST_MACHINE EM_MIPS
2673 /* GDB doesn't appear to require proper setting of ELF_HOST_FLAGS,
2674 which is good because they're really quite complicated for MIPS. */
2676 static const DebugFrame debug_frame = {
2677 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */
2678 .h.cie.id = -1,
2679 .h.cie.version = 1,
2680 .h.cie.code_align = 1,
2681 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */
2682 .h.cie.return_column = TCG_REG_RA,
2684 /* Total FDE size does not include the "len" member. */
2685 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
2687 .fde_def_cfa = {
2688 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */
2689 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
2690 (FRAME_SIZE >> 7)
2691 },
2692 .fde_reg_ofs = {
2693 0x80 + 16, 9, /* DW_CFA_offset, s0, -72 */
2694 0x80 + 17, 8, /* DW_CFA_offset, s2, -64 */
2695 0x80 + 18, 7, /* DW_CFA_offset, s3, -56 */
2696 0x80 + 19, 6, /* DW_CFA_offset, s4, -48 */
2697 0x80 + 20, 5, /* DW_CFA_offset, s5, -40 */
2698 0x80 + 21, 4, /* DW_CFA_offset, s6, -32 */
2699 0x80 + 22, 3, /* DW_CFA_offset, s7, -24 */
2700 0x80 + 30, 2, /* DW_CFA_offset, s8, -16 */
2701 0x80 + 31, 1, /* DW_CFA_offset, ra, -8 */
2702 }
2703 };
2705 void tcg_register_jit(void *buf, size_t buf_size)
2706 {
2707 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
2708 }