| blob | 3b5b5c6d5ba603c961e55e19c787129c0d9f50bd |
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
5 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net>
6 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
27 #include "../tcg-ldst.c.inc"
28 #include "../tcg-pool.c.inc"
30 #if TCG_TARGET_REG_BITS == 32
31 # define LO_OFF (HOST_BIG_ENDIAN * 4)
32 # define HI_OFF (4 - LO_OFF)
33 #else
34 /* Assert at compile-time that these values are never used for 64-bit. */
35 # define LO_OFF ({ qemu_build_not_reached(); 0; })
36 # define HI_OFF ({ qemu_build_not_reached(); 0; })
37 #endif
39 #ifdef CONFIG_DEBUG_TCG
40 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
41 "zero",
42 "at",
43 "v0",
44 "v1",
45 "a0",
46 "a1",
47 "a2",
48 "a3",
49 "t0",
50 "t1",
51 "t2",
52 "t3",
53 "t4",
54 "t5",
55 "t6",
56 "t7",
57 "s0",
58 "s1",
59 "s2",
60 "s3",
61 "s4",
62 "s5",
63 "s6",
64 "s7",
65 "t8",
66 "t9",
67 "k0",
68 "k1",
69 "gp",
70 "sp",
71 "s8",
72 "ra",
73 };
74 #endif
76 #define TCG_TMP0 TCG_REG_AT
77 #define TCG_TMP1 TCG_REG_T9
78 #define TCG_TMP2 TCG_REG_T8
79 #define TCG_TMP3 TCG_REG_T7
81 #define TCG_GUEST_BASE_REG TCG_REG_S7
82 #if TCG_TARGET_REG_BITS == 64
83 #define TCG_REG_TB TCG_REG_S6
84 #else
85 #define TCG_REG_TB ({ qemu_build_not_reached(); TCG_REG_ZERO; })
86 #endif
88 /* check if we really need so many registers :P */
89 static const int tcg_target_reg_alloc_order[] = {
90 /* Call saved registers. */
91 TCG_REG_S0,
92 TCG_REG_S1,
93 TCG_REG_S2,
94 TCG_REG_S3,
95 TCG_REG_S4,
96 TCG_REG_S5,
97 TCG_REG_S6,
98 TCG_REG_S7,
99 TCG_REG_S8,
101 /* Call clobbered registers. */
102 TCG_REG_T4,
103 TCG_REG_T5,
104 TCG_REG_T6,
105 TCG_REG_T7,
106 TCG_REG_T8,
107 TCG_REG_T9,
108 TCG_REG_V1,
109 TCG_REG_V0,
111 /* Argument registers, opposite order of allocation. */
112 TCG_REG_T3,
113 TCG_REG_T2,
114 TCG_REG_T1,
115 TCG_REG_T0,
116 TCG_REG_A3,
117 TCG_REG_A2,
118 TCG_REG_A1,
119 TCG_REG_A0,
120 };
122 static const TCGReg tcg_target_call_iarg_regs[] = {
123 TCG_REG_A0,
124 TCG_REG_A1,
125 TCG_REG_A2,
126 TCG_REG_A3,
127 #if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64
128 TCG_REG_T0,
129 TCG_REG_T1,
130 TCG_REG_T2,
131 TCG_REG_T3,
132 #endif
133 };
135 static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
136 {
137 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL);
138 tcg_debug_assert(slot >= 0 && slot <= 1);
139 return TCG_REG_V0 + slot;
140 }
142 static const tcg_insn_unit *tb_ret_addr;
143 static const tcg_insn_unit *bswap32_addr;
144 static const tcg_insn_unit *bswap32u_addr;
145 static const tcg_insn_unit *bswap64_addr;
147 static bool reloc_pc16(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
148 {
149 /* Let the compiler perform the right-shift as part of the arithmetic. */
150 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
151 ptrdiff_t disp = target - (src_rx + 1);
152 if (disp == (int16_t)disp) {
153 *src_rw = deposit32(*src_rw, 0, 16, disp);
154 return true;
155 }
156 return false;
157 }
159 static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
160 intptr_t value, intptr_t addend)
161 {
162 value += addend;
163 switch (type) {
164 case R_MIPS_PC16:
165 return reloc_pc16(code_ptr, (const tcg_insn_unit *)value);
166 case R_MIPS_16:
167 if (value != (int16_t)value) {
168 return false;
169 }
170 *code_ptr = deposit32(*code_ptr, 0, 16, value);
171 return true;
172 }
173 g_assert_not_reached();
174 }
176 #define TCG_CT_CONST_ZERO 0x100
177 #define TCG_CT_CONST_U16 0x200 /* Unsigned 16-bit: 0 - 0xffff. */
178 #define TCG_CT_CONST_S16 0x400 /* Signed 16-bit: -32768 - 32767 */
179 #define TCG_CT_CONST_P2M1 0x800 /* Power of 2 minus 1. */
180 #define TCG_CT_CONST_N16 0x1000 /* "Negatable" 16-bit: -32767 - 32767 */
181 #define TCG_CT_CONST_WSZ 0x2000 /* word size */
183 #define ALL_GENERAL_REGS 0xffffffffu
185 static bool is_p2m1(tcg_target_long val)
186 {
187 return val && ((val + 1) & val) == 0;
188 }
190 /* test if a constant matches the constraint */
191 static bool tcg_target_const_match(int64_t val, int ct,
192 TCGType type, TCGCond cond, int vece)
193 {
194 if (ct & TCG_CT_CONST) {
195 return 1;
196 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
197 return 1;
198 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) {
199 return 1;
200 } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) {
201 return 1;
202 } else if ((ct & TCG_CT_CONST_N16) && val >= -32767 && val <= 32767) {
203 return 1;
204 } else if ((ct & TCG_CT_CONST_P2M1)
205 && use_mips32r2_instructions && is_p2m1(val)) {
206 return 1;
207 } else if ((ct & TCG_CT_CONST_WSZ)
208 && val == (type == TCG_TYPE_I32 ? 32 : 64)) {
209 return 1;
210 }
211 return 0;
212 }
214 /* instruction opcodes */
215 typedef enum {
216 OPC_J = 002 << 26,
217 OPC_JAL = 003 << 26,
218 OPC_BEQ = 004 << 26,
219 OPC_BNE = 005 << 26,
220 OPC_BLEZ = 006 << 26,
221 OPC_BGTZ = 007 << 26,
222 OPC_ADDIU = 011 << 26,
223 OPC_SLTI = 012 << 26,
224 OPC_SLTIU = 013 << 26,
225 OPC_ANDI = 014 << 26,
226 OPC_ORI = 015 << 26,
227 OPC_XORI = 016 << 26,
228 OPC_LUI = 017 << 26,
229 OPC_BNEL = 025 << 26,
230 OPC_BNEZALC_R6 = 030 << 26,
231 OPC_DADDIU = 031 << 26,
232 OPC_LDL = 032 << 26,
233 OPC_LDR = 033 << 26,
234 OPC_LB = 040 << 26,
235 OPC_LH = 041 << 26,
236 OPC_LWL = 042 << 26,
237 OPC_LW = 043 << 26,
238 OPC_LBU = 044 << 26,
239 OPC_LHU = 045 << 26,
240 OPC_LWR = 046 << 26,
241 OPC_LWU = 047 << 26,
242 OPC_SB = 050 << 26,
243 OPC_SH = 051 << 26,
244 OPC_SWL = 052 << 26,
245 OPC_SW = 053 << 26,
246 OPC_SDL = 054 << 26,
247 OPC_SDR = 055 << 26,
248 OPC_SWR = 056 << 26,
249 OPC_LD = 067 << 26,
250 OPC_SD = 077 << 26,
252 OPC_SPECIAL = 000 << 26,
253 OPC_SLL = OPC_SPECIAL | 000,
254 OPC_SRL = OPC_SPECIAL | 002,
255 OPC_ROTR = OPC_SPECIAL | 002 | (1 << 21),
256 OPC_SRA = OPC_SPECIAL | 003,
257 OPC_SLLV = OPC_SPECIAL | 004,
258 OPC_SRLV = OPC_SPECIAL | 006,
259 OPC_ROTRV = OPC_SPECIAL | 006 | 0100,
260 OPC_SRAV = OPC_SPECIAL | 007,
261 OPC_JR_R5 = OPC_SPECIAL | 010,
262 OPC_JALR = OPC_SPECIAL | 011,
263 OPC_MOVZ = OPC_SPECIAL | 012,
264 OPC_MOVN = OPC_SPECIAL | 013,
265 OPC_SYNC = OPC_SPECIAL | 017,
266 OPC_MFHI = OPC_SPECIAL | 020,
267 OPC_MFLO = OPC_SPECIAL | 022,
268 OPC_DSLLV = OPC_SPECIAL | 024,
269 OPC_DSRLV = OPC_SPECIAL | 026,
270 OPC_DROTRV = OPC_SPECIAL | 026 | 0100,
271 OPC_DSRAV = OPC_SPECIAL | 027,
272 OPC_MULT = OPC_SPECIAL | 030,
273 OPC_MUL_R6 = OPC_SPECIAL | 030 | 0200,
274 OPC_MUH = OPC_SPECIAL | 030 | 0300,
275 OPC_MULTU = OPC_SPECIAL | 031,
276 OPC_MULU = OPC_SPECIAL | 031 | 0200,
277 OPC_MUHU = OPC_SPECIAL | 031 | 0300,
278 OPC_DIV = OPC_SPECIAL | 032,
279 OPC_DIV_R6 = OPC_SPECIAL | 032 | 0200,
280 OPC_MOD = OPC_SPECIAL | 032 | 0300,
281 OPC_DIVU = OPC_SPECIAL | 033,
282 OPC_DIVU_R6 = OPC_SPECIAL | 033 | 0200,
283 OPC_MODU = OPC_SPECIAL | 033 | 0300,
284 OPC_DMULT = OPC_SPECIAL | 034,
285 OPC_DMUL = OPC_SPECIAL | 034 | 0200,
286 OPC_DMUH = OPC_SPECIAL | 034 | 0300,
287 OPC_DMULTU = OPC_SPECIAL | 035,
288 OPC_DMULU = OPC_SPECIAL | 035 | 0200,
289 OPC_DMUHU = OPC_SPECIAL | 035 | 0300,
290 OPC_DDIV = OPC_SPECIAL | 036,
291 OPC_DDIV_R6 = OPC_SPECIAL | 036 | 0200,
292 OPC_DMOD = OPC_SPECIAL | 036 | 0300,
293 OPC_DDIVU = OPC_SPECIAL | 037,
294 OPC_DDIVU_R6 = OPC_SPECIAL | 037 | 0200,
295 OPC_DMODU = OPC_SPECIAL | 037 | 0300,
296 OPC_ADDU = OPC_SPECIAL | 041,
297 OPC_SUBU = OPC_SPECIAL | 043,
298 OPC_AND = OPC_SPECIAL | 044,
299 OPC_OR = OPC_SPECIAL | 045,
300 OPC_XOR = OPC_SPECIAL | 046,
301 OPC_NOR = OPC_SPECIAL | 047,
302 OPC_SLT = OPC_SPECIAL | 052,
303 OPC_SLTU = OPC_SPECIAL | 053,
304 OPC_DADDU = OPC_SPECIAL | 055,
305 OPC_DSUBU = OPC_SPECIAL | 057,
306 OPC_SELEQZ = OPC_SPECIAL | 065,
307 OPC_SELNEZ = OPC_SPECIAL | 067,
308 OPC_DSLL = OPC_SPECIAL | 070,
309 OPC_DSRL = OPC_SPECIAL | 072,
310 OPC_DROTR = OPC_SPECIAL | 072 | (1 << 21),
311 OPC_DSRA = OPC_SPECIAL | 073,
312 OPC_DSLL32 = OPC_SPECIAL | 074,
313 OPC_DSRL32 = OPC_SPECIAL | 076,
314 OPC_DROTR32 = OPC_SPECIAL | 076 | (1 << 21),
315 OPC_DSRA32 = OPC_SPECIAL | 077,
316 OPC_CLZ_R6 = OPC_SPECIAL | 0120,
317 OPC_DCLZ_R6 = OPC_SPECIAL | 0122,
319 OPC_REGIMM = 001 << 26,
320 OPC_BLTZ = OPC_REGIMM | (000 << 16),
321 OPC_BGEZ = OPC_REGIMM | (001 << 16),
323 OPC_SPECIAL2 = 034 << 26,
324 OPC_MUL_R5 = OPC_SPECIAL2 | 002,
325 OPC_CLZ = OPC_SPECIAL2 | 040,
326 OPC_DCLZ = OPC_SPECIAL2 | 044,
328 OPC_SPECIAL3 = 037 << 26,
329 OPC_EXT = OPC_SPECIAL3 | 000,
330 OPC_DEXTM = OPC_SPECIAL3 | 001,
331 OPC_DEXTU = OPC_SPECIAL3 | 002,
332 OPC_DEXT = OPC_SPECIAL3 | 003,
333 OPC_INS = OPC_SPECIAL3 | 004,
334 OPC_DINSM = OPC_SPECIAL3 | 005,
335 OPC_DINSU = OPC_SPECIAL3 | 006,
336 OPC_DINS = OPC_SPECIAL3 | 007,
337 OPC_WSBH = OPC_SPECIAL3 | 00240,
338 OPC_DSBH = OPC_SPECIAL3 | 00244,
339 OPC_DSHD = OPC_SPECIAL3 | 00544,
340 OPC_SEB = OPC_SPECIAL3 | 02040,
341 OPC_SEH = OPC_SPECIAL3 | 03040,
343 /* MIPS r6 doesn't have JR, JALR should be used instead */
344 OPC_JR = use_mips32r6_instructions ? OPC_JALR : OPC_JR_R5,
346 /*
347 * MIPS r6 replaces MUL with an alternative encoding which is
348 * backwards-compatible at the assembly level.
349 */
350 OPC_MUL = use_mips32r6_instructions ? OPC_MUL_R6 : OPC_MUL_R5,
352 /* MIPS r6 introduced names for weaker variants of SYNC. These are
353 backward compatible to previous architecture revisions. */
354 OPC_SYNC_WMB = OPC_SYNC | 0x04 << 6,
355 OPC_SYNC_MB = OPC_SYNC | 0x10 << 6,
356 OPC_SYNC_ACQUIRE = OPC_SYNC | 0x11 << 6,
357 OPC_SYNC_RELEASE = OPC_SYNC | 0x12 << 6,
358 OPC_SYNC_RMB = OPC_SYNC | 0x13 << 6,
360 /* Aliases for convenience. */
361 ALIAS_PADD = sizeof(void *) == 4 ? OPC_ADDU : OPC_DADDU,
362 ALIAS_PADDI = sizeof(void *) == 4 ? OPC_ADDIU : OPC_DADDIU,
363 } MIPSInsn;
365 /*
366 * Type reg
367 */
368 static void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc,
369 TCGReg rd, TCGReg rs, TCGReg rt)
370 {
371 int32_t inst;
373 inst = opc;
374 inst |= (rs & 0x1F) << 21;
375 inst |= (rt & 0x1F) << 16;
376 inst |= (rd & 0x1F) << 11;
377 tcg_out32(s, inst);
378 }
380 /*
381 * Type immediate
382 */
383 static void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc,
384 TCGReg rt, TCGReg rs, TCGArg imm)
385 {
386 int32_t inst;
388 inst = opc;
389 inst |= (rs & 0x1F) << 21;
390 inst |= (rt & 0x1F) << 16;
391 inst |= (imm & 0xffff);
392 tcg_out32(s, inst);
393 }
395 /*
396 * Type bitfield
397 */
398 static void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt,
399 TCGReg rs, int msb, int lsb)
400 {
401 int32_t inst;
403 inst = opc;
404 inst |= (rs & 0x1F) << 21;
405 inst |= (rt & 0x1F) << 16;
406 inst |= (msb & 0x1F) << 11;
407 inst |= (lsb & 0x1F) << 6;
408 tcg_out32(s, inst);
409 }
411 static void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm,
412 MIPSInsn oph, TCGReg rt, TCGReg rs,
413 int msb, int lsb)
414 {
415 if (lsb >= 32) {
416 opc = oph;
417 msb -= 32;
418 lsb -= 32;
419 } else if (msb >= 32) {
420 opc = opm;
421 msb -= 32;
422 }
423 tcg_out_opc_bf(s, opc, rt, rs, msb, lsb);
424 }
426 /*
427 * Type branch
428 */
429 static void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, TCGReg rt, TCGReg rs)
430 {
431 tcg_out_opc_imm(s, opc, rt, rs, 0);
432 }
434 /*
435 * Type sa
436 */
437 static void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc,
438 TCGReg rd, TCGReg rt, TCGArg sa)
439 {
440 int32_t inst;
442 inst = opc;
443 inst |= (rt & 0x1F) << 16;
444 inst |= (rd & 0x1F) << 11;
445 inst |= (sa & 0x1F) << 6;
446 tcg_out32(s, inst);
448 }
450 static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2,
451 TCGReg rd, TCGReg rt, TCGArg sa)
452 {
453 int32_t inst;
455 inst = (sa & 32 ? opc2 : opc1);
456 inst |= (rt & 0x1F) << 16;
457 inst |= (rd & 0x1F) << 11;
458 inst |= (sa & 0x1F) << 6;
459 tcg_out32(s, inst);
460 }
462 /*
463 * Type jump.
464 * Returns true if the branch was in range and the insn was emitted.
465 */
466 static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, const void *target)
467 {
468 uintptr_t dest = (uintptr_t)target;
469 uintptr_t from = (uintptr_t)tcg_splitwx_to_rx(s->code_ptr) + 4;
470 int32_t inst;
472 /* The pc-region branch happens within the 256MB region of
473 the delay slot (thus the +4). */
474 if ((from ^ dest) & -(1 << 28)) {
475 return false;
476 }
477 tcg_debug_assert((dest & 3) == 0);
479 inst = opc;
480 inst |= (dest >> 2) & 0x3ffffff;
481 tcg_out32(s, inst);
482 return true;
483 }
485 static void tcg_out_nop(TCGContext *s)
486 {
487 tcg_out32(s, 0);
488 }
490 static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
491 {
492 memset(p, 0, count * sizeof(tcg_insn_unit));
493 }
495 static void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
496 {
497 tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa);
498 }
500 static void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
501 {
502 tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa);
503 }
505 static void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
506 {
507 tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa);
508 }
510 static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
511 {
512 /* Simple reg-reg move, optimising out the 'do nothing' case */
513 if (ret != arg) {
514 tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO);
515 }
516 return true;
517 }
519 static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long arg)
520 {
521 if (arg == (int16_t)arg) {
522 tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg);
523 return true;
524 }
525 if (arg == (uint16_t)arg) {
526 tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg);
527 return true;
528 }
529 if (arg == (int32_t)arg && (arg & 0xffff) == 0) {
530 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16);
531 return true;
532 }
533 return false;
534 }
536 static bool tcg_out_movi_two(TCGContext *s, TCGReg ret, tcg_target_long arg)
537 {
538 /*
539 * All signed 32-bit constants are loadable with two immediates,
540 * and everything else requires more work.
541 */
542 if (arg == (int32_t)arg) {
543 if (!tcg_out_movi_one(s, ret, arg)) {
544 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16);
545 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff);
546 }
547 return true;
548 }
549 return false;
550 }
552 static void tcg_out_movi_pool(TCGContext *s, TCGReg ret,
553 tcg_target_long arg, TCGReg tbreg)
554 {
555 new_pool_label(s, arg, R_MIPS_16, s->code_ptr, tcg_tbrel_diff(s, NULL));
556 tcg_out_opc_imm(s, OPC_LD, ret, tbreg, 0);
557 }
559 static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
560 tcg_target_long arg, TCGReg tbreg)
561 {
562 tcg_target_long tmp;
563 int sh, lo;
565 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
566 arg = (int32_t)arg;
567 }
569 /* Load all 32-bit constants. */
570 if (tcg_out_movi_two(s, ret, arg)) {
571 return;
572 }
573 assert(TCG_TARGET_REG_BITS == 64);
575 /* Load addresses within 2GB of TB with 1 or 3 insns. */
576 tmp = tcg_tbrel_diff(s, (void *)arg);
577 if (tmp == (int16_t)tmp) {
578 tcg_out_opc_imm(s, OPC_DADDIU, ret, tbreg, tmp);
579 return;
580 }
581 if (tcg_out_movi_two(s, ret, tmp)) {
582 tcg_out_opc_reg(s, OPC_DADDU, ret, ret, tbreg);
583 return;
584 }
586 /*
587 * Load bitmasks with a right-shift. This is good for things
588 * like 0x0fff_ffff_ffff_fff0: ADDUI r,0,0xff00 + DSRL r,r,4.
589 * or similarly using LUI. For this to work, bit 31 must be set.
590 */
591 if (arg > 0 && (int32_t)arg < 0) {
592 sh = clz64(arg);
593 if (tcg_out_movi_one(s, ret, arg << sh)) {
594 tcg_out_dsrl(s, ret, ret, sh);
595 return;
596 }
597 }
599 /*
600 * Load slightly larger constants using left-shift.
601 * Limit this sequence to 3 insns to avoid too much expansion.
602 */
603 sh = ctz64(arg);
604 if (sh && tcg_out_movi_two(s, ret, arg >> sh)) {
605 tcg_out_dsll(s, ret, ret, sh);
606 return;
607 }
609 /*
610 * Load slightly larger constants using left-shift and add/or.
611 * Prefer addi with a negative immediate when that would produce
612 * a larger shift. For this to work, bits 15 and 16 must be set.
613 */
614 lo = arg & 0xffff;
615 if (lo) {
616 if ((arg & 0x18000) == 0x18000) {
617 lo = (int16_t)arg;
618 }
619 tmp = arg - lo;
620 sh = ctz64(tmp);
621 tmp >>= sh;
622 if (tcg_out_movi_one(s, ret, tmp)) {
623 tcg_out_dsll(s, ret, ret, sh);
624 tcg_out_opc_imm(s, lo < 0 ? OPC_DADDIU : OPC_ORI, ret, ret, lo);
625 return;
626 }
627 }
629 /* Otherwise, put 64-bit constants into the constant pool. */
630 tcg_out_movi_pool(s, ret, arg, tbreg);
631 }
633 static void tcg_out_movi(TCGContext *s, TCGType type,
634 TCGReg ret, tcg_target_long arg)
635 {
636 TCGReg tbreg = TCG_TARGET_REG_BITS == 64 ? TCG_REG_TB : 0;
637 tcg_out_movi_int(s, type, ret, arg, tbreg);
638 }
640 static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs)
641 {
642 tcg_debug_assert(TCG_TARGET_HAS_ext8s_i32);
643 tcg_out_opc_reg(s, OPC_SEB, rd, TCG_REG_ZERO, rs);
644 }
646 static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rs)
647 {
648 tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xff);
649 }
651 static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs)
652 {
653 tcg_debug_assert(TCG_TARGET_HAS_ext16s_i32);
654 tcg_out_opc_reg(s, OPC_SEH, rd, TCG_REG_ZERO, rs);
655 }
657 static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rs)
658 {
659 tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xffff);
660 }
662 static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rs)
663 {
664 tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
665 tcg_out_opc_sa(s, OPC_SLL, rd, rs, 0);
666 }
668 static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs)
669 {
670 if (rd != rs) {
671 tcg_out_ext32s(s, rd, rs);
672 }
673 }
675 static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs)
676 {
677 tcg_out_ext32u(s, rd, rs);
678 }
680 static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rs)
681 {
682 tcg_out_ext32s(s, rd, rs);
683 }
685 static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2)
686 {
687 return false;
688 }
690 static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs,
691 tcg_target_long imm)
692 {
693 /* This function is only used for passing structs by reference. */
694 g_assert_not_reached();
695 }
697 static void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg, int flags)
698 {
699 /* ret and arg can't be register tmp0 */
700 tcg_debug_assert(ret != TCG_TMP0);
701 tcg_debug_assert(arg != TCG_TMP0);
703 /* With arg = abcd: */
704 if (use_mips32r2_instructions) {
705 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); /* badc */
706 if (flags & TCG_BSWAP_OS) {
707 tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret); /* ssdc */
708 } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {
709 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xffff); /* 00dc */
710 }
711 return;
712 }
714 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8); /* 0abc */
715 if (!(flags & TCG_BSWAP_IZ)) {
716 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, TCG_TMP0, 0x00ff); /* 000c */
717 }
718 if (flags & TCG_BSWAP_OS) {
719 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); /* d000 */
720 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); /* ssd0 */
721 } else {
722 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8); /* bcd0 */
723 if (flags & TCG_BSWAP_OZ) {
724 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00); /* 00d0 */
725 }
726 }
727 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0); /* ssdc */
728 }
730 static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub)
731 {
732 if (!tcg_out_opc_jmp(s, OPC_JAL, sub)) {
733 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP1, (uintptr_t)sub);
734 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_TMP1, 0);
735 }
736 }
738 static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg, int flags)
739 {
740 if (use_mips32r2_instructions) {
741 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
742 tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16);
743 if (flags & TCG_BSWAP_OZ) {
744 tcg_out_opc_bf(s, OPC_DEXT, ret, ret, 31, 0);
745 }
746 } else {
747 if (flags & TCG_BSWAP_OZ) {
748 tcg_out_bswap_subr(s, bswap32u_addr);
749 } else {
750 tcg_out_bswap_subr(s, bswap32_addr);
751 }
752 /* delay slot -- never omit the insn, like tcg_out_mov might. */
753 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
754 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
755 }
756 }
758 static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg)
759 {
760 if (use_mips32r2_instructions) {
761 tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg);
762 tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret);
763 } else {
764 tcg_out_bswap_subr(s, bswap64_addr);
765 /* delay slot -- never omit the insn, like tcg_out_mov might. */
766 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
767 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
768 }
769 }
771 static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
772 {
773 tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
774 if (use_mips32r2_instructions) {
775 tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0);
776 } else {
777 tcg_out_dsll(s, ret, arg, 32);
778 tcg_out_dsrl(s, ret, ret, 32);
779 }
780 }
782 static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data,
783 TCGReg addr, intptr_t ofs)
784 {
785 int16_t lo = ofs;
786 if (ofs != lo) {
787 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo);
788 if (addr != TCG_REG_ZERO) {
789 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_TMP0, addr);
790 }
791 addr = TCG_TMP0;
792 }
793 tcg_out_opc_imm(s, opc, data, addr, lo);
794 }
796 static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
797 TCGReg arg1, intptr_t arg2)
798 {
799 MIPSInsn opc = OPC_LD;
800 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) {
801 opc = OPC_LW;
802 }
803 tcg_out_ldst(s, opc, arg, arg1, arg2);
804 }
806 static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
807 TCGReg arg1, intptr_t arg2)
808 {
809 MIPSInsn opc = OPC_SD;
810 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) {
811 opc = OPC_SW;
812 }
813 tcg_out_ldst(s, opc, arg, arg1, arg2);
814 }
816 static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
817 TCGReg base, intptr_t ofs)
818 {
819 if (val == 0) {
820 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs);
821 return true;
822 }
823 return false;
824 }
826 static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al,
827 TCGReg ah, TCGArg bl, TCGArg bh, bool cbl,
828 bool cbh, bool is_sub)
829 {
830 TCGReg th = TCG_TMP1;
832 /* If we have a negative constant such that negating it would
833 make the high part zero, we can (usually) eliminate one insn. */
834 if (cbl && cbh && bh == -1 && bl != 0) {
835 bl = -bl;
836 bh = 0;
837 is_sub = !is_sub;
838 }
840 /* By operating on the high part first, we get to use the final
841 carry operation to move back from the temporary. */
842 if (!cbh) {
843 tcg_out_opc_reg(s, (is_sub ? OPC_SUBU : OPC_ADDU), th, ah, bh);
844 } else if (bh != 0 || ah == rl) {
845 tcg_out_opc_imm(s, OPC_ADDIU, th, ah, (is_sub ? -bh : bh));
846 } else {
847 th = ah;
848 }
850 /* Note that tcg optimization should eliminate the bl == 0 case. */
851 if (is_sub) {
852 if (cbl) {
853 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, al, bl);
854 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, -bl);
855 } else {
856 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, al, bl);
857 tcg_out_opc_reg(s, OPC_SUBU, rl, al, bl);
858 }
859 tcg_out_opc_reg(s, OPC_SUBU, rh, th, TCG_TMP0);
860 } else {
861 if (cbl) {
862 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, bl);
863 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, rl, bl);
864 } else if (rl == al && rl == bl) {
865 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, TCG_TARGET_REG_BITS - 1);
866 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl);
867 } else {
868 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl);
869 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, rl, (rl == bl ? al : bl));
870 }
871 tcg_out_opc_reg(s, OPC_ADDU, rh, th, TCG_TMP0);
872 }
873 }
875 #define SETCOND_INV TCG_TARGET_NB_REGS
876 #define SETCOND_NEZ (SETCOND_INV << 1)
877 #define SETCOND_FLAGS (SETCOND_INV | SETCOND_NEZ)
879 static int tcg_out_setcond_int(TCGContext *s, TCGCond cond, TCGReg ret,
880 TCGReg arg1, TCGReg arg2)
881 {
882 int flags = 0;
884 switch (cond) {
885 case TCG_COND_EQ: /* -> NE */
886 case TCG_COND_GE: /* -> LT */
887 case TCG_COND_GEU: /* -> LTU */
888 case TCG_COND_LE: /* -> GT */
889 case TCG_COND_LEU: /* -> GTU */
890 cond = tcg_invert_cond(cond);
891 flags ^= SETCOND_INV;
892 break;
893 default:
894 break;
895 }
897 switch (cond) {
898 case TCG_COND_NE:
899 flags |= SETCOND_NEZ;
900 if (arg2 == 0) {
901 return arg1 | flags;
902 }
903 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2);
904 break;
905 case TCG_COND_LT:
906 tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2);
907 break;
908 case TCG_COND_LTU:
909 tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2);
910 break;
911 case TCG_COND_GT:
912 tcg_out_opc_reg(s, OPC_SLT, ret, arg2, arg1);
913 break;
914 case TCG_COND_GTU:
915 tcg_out_opc_reg(s, OPC_SLTU, ret, arg2, arg1);
916 break;
917 default:
918 g_assert_not_reached();
919 }
920 return ret | flags;
921 }
923 static void tcg_out_setcond_end(TCGContext *s, TCGReg ret, int tmpflags)
924 {
925 if (tmpflags != ret) {
926 TCGReg tmp = tmpflags & ~SETCOND_FLAGS;
928 switch (tmpflags & SETCOND_FLAGS) {
929 case SETCOND_INV:
930 /* Intermediate result is boolean: simply invert. */
931 tcg_out_opc_imm(s, OPC_XORI, ret, tmp, 1);
932 break;
933 case SETCOND_NEZ:
934 /* Intermediate result is zero/non-zero: test != 0. */
935 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, tmp);
936 break;
937 case SETCOND_NEZ | SETCOND_INV:
938 /* Intermediate result is zero/non-zero: test == 0. */
939 tcg_out_opc_imm(s, OPC_SLTIU, ret, tmp, 1);
940 break;
941 default:
942 g_assert_not_reached();
943 }
944 }
945 }
947 static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret,
948 TCGReg arg1, TCGReg arg2)
949 {
950 int tmpflags = tcg_out_setcond_int(s, cond, ret, arg1, arg2);
951 tcg_out_setcond_end(s, ret, tmpflags);
952 }
954 static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1,
955 TCGReg arg2, TCGLabel *l)
956 {
957 static const MIPSInsn b_zero[16] = {
958 [TCG_COND_LT] = OPC_BLTZ,
959 [TCG_COND_GT] = OPC_BGTZ,
960 [TCG_COND_LE] = OPC_BLEZ,
961 [TCG_COND_GE] = OPC_BGEZ,
962 };
964 MIPSInsn b_opc = 0;
966 switch (cond) {
967 case TCG_COND_EQ:
968 b_opc = OPC_BEQ;
969 break;
970 case TCG_COND_NE:
971 b_opc = OPC_BNE;
972 break;
973 case TCG_COND_LT:
974 case TCG_COND_GT:
975 case TCG_COND_LE:
976 case TCG_COND_GE:
977 if (arg2 == 0) {
978 b_opc = b_zero[cond];
979 arg2 = arg1;
980 arg1 = 0;
981 }
982 break;
983 default:
984 break;
985 }
987 if (b_opc == 0) {
988 int tmpflags = tcg_out_setcond_int(s, cond, TCG_TMP0, arg1, arg2);
990 arg2 = TCG_REG_ZERO;
991 arg1 = tmpflags & ~SETCOND_FLAGS;
992 b_opc = tmpflags & SETCOND_INV ? OPC_BEQ : OPC_BNE;
993 }
995 tcg_out_reloc(s, s->code_ptr, R_MIPS_PC16, l, 0);
996 tcg_out_opc_br(s, b_opc, arg1, arg2);
997 tcg_out_nop(s);
998 }
1000 static int tcg_out_setcond2_int(TCGContext *s, TCGCond cond, TCGReg ret,
1001 TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh)
1002 {
1003 int flags = 0;
1005 switch (cond) {
1006 case TCG_COND_EQ:
1007 flags |= SETCOND_INV;
1008 /* fall through */
1009 case TCG_COND_NE:
1010 flags |= SETCOND_NEZ;
1011 tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, al, bl);
1012 tcg_out_opc_reg(s, OPC_XOR, TCG_TMP1, ah, bh);
1013 tcg_out_opc_reg(s, OPC_OR, ret, TCG_TMP0, TCG_TMP1);
1014 break;
1016 default:
1017 tcg_out_setcond(s, TCG_COND_EQ, TCG_TMP0, ah, bh);
1018 tcg_out_setcond(s, tcg_unsigned_cond(cond), TCG_TMP1, al, bl);
1019 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP0);
1020 tcg_out_setcond(s, tcg_high_cond(cond), TCG_TMP0, ah, bh);
1021 tcg_out_opc_reg(s, OPC_OR, ret, TCG_TMP0, TCG_TMP1);
1022 break;
1023 }
1024 return ret | flags;
1025 }
1027 static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret,
1028 TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh)
1029 {
1030 int tmpflags = tcg_out_setcond2_int(s, cond, ret, al, ah, bl, bh);
1031 tcg_out_setcond_end(s, ret, tmpflags);
1032 }
1034 static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah,
1035 TCGReg bl, TCGReg bh, TCGLabel *l)
1036 {
1037 int tmpflags = tcg_out_setcond2_int(s, cond, TCG_TMP0, al, ah, bl, bh);
1038 TCGReg tmp = tmpflags & ~SETCOND_FLAGS;
1039 MIPSInsn b_opc = tmpflags & SETCOND_INV ? OPC_BEQ : OPC_BNE;
1041 tcg_out_reloc(s, s->code_ptr, R_MIPS_PC16, l, 0);
1042 tcg_out_opc_br(s, b_opc, tmp, TCG_REG_ZERO);
1043 tcg_out_nop(s);
1044 }
1046 static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret,
1047 TCGReg c1, TCGReg c2, TCGReg v1, TCGReg v2)
1048 {
1049 int tmpflags;
1050 bool eqz;
1052 /* If one of the values is zero, put it last to match SEL*Z instructions */
1053 if (use_mips32r6_instructions && v1 == 0) {
1054 v1 = v2;
1055 v2 = 0;
1056 cond = tcg_invert_cond(cond);
1057 }
1059 tmpflags = tcg_out_setcond_int(s, cond, TCG_TMP0, c1, c2);
1060 c1 = tmpflags & ~SETCOND_FLAGS;
1061 eqz = tmpflags & SETCOND_INV;
1063 if (use_mips32r6_instructions) {
1064 MIPSInsn m_opc_t = eqz ? OPC_SELEQZ : OPC_SELNEZ;
1065 MIPSInsn m_opc_f = eqz ? OPC_SELNEZ : OPC_SELEQZ;
1067 if (v2 != 0) {
1068 tcg_out_opc_reg(s, m_opc_f, TCG_TMP1, v2, c1);
1069 }
1070 tcg_out_opc_reg(s, m_opc_t, ret, v1, c1);
1071 if (v2 != 0) {
1072 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP1);
1073 }
1074 return;
1075 }
1077 /* This should be guaranteed via constraints */
1078 tcg_debug_assert(v2 == ret);
1080 if (use_movnz_instructions) {
1081 MIPSInsn m_opc = eqz ? OPC_MOVZ : OPC_MOVN;
1082 tcg_out_opc_reg(s, m_opc, ret, v1, c1);
1083 } else {
1084 /* Invert the condition in order to branch over the move. */
1085 MIPSInsn b_opc = eqz ? OPC_BNE : OPC_BEQ;
1086 tcg_out_opc_imm(s, b_opc, c1, TCG_REG_ZERO, 2);
1087 tcg_out_nop(s);
1088 /* Open-code tcg_out_mov, without the nop-move check. */
1089 tcg_out_opc_reg(s, OPC_OR, ret, v1, TCG_REG_ZERO);
1090 }
1091 }
1093 static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail)
1094 {
1095 /*
1096 * Note that __mips_abicalls requires the called function's address
1097 * to be loaded into $25 (t9), even if a direct branch is in range.
1098 *
1099 * For n64, always drop the pointer into the constant pool.
1100 * We can re-use helper addresses often and do not want any
1101 * of the longer sequences tcg_out_movi may try.
1102 */
1103 if (sizeof(uintptr_t) == 8) {
1104 tcg_out_movi_pool(s, TCG_REG_T9, (uintptr_t)arg, TCG_REG_TB);
1105 } else {
1106 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg);
1107 }
1109 /* But do try a direct branch, allowing the cpu better insn prefetch. */
1110 if (tail) {
1111 if (!tcg_out_opc_jmp(s, OPC_J, arg)) {
1112 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_T9, 0);
1113 }
1114 } else {
1115 if (!tcg_out_opc_jmp(s, OPC_JAL, arg)) {
1116 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0);
1117 }
1118 }
1119 }
1121 static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg,
1122 const TCGHelperInfo *info)
1123 {
1124 tcg_out_call_int(s, arg, false);
1125 tcg_out_nop(s);
1126 }
1128 /* We have four temps, we might as well expose three of them. */
1129 static const TCGLdstHelperParam ldst_helper_param = {
1130 .ntmp = 3, .tmp = { TCG_TMP0, TCG_TMP1, TCG_TMP2 }
1131 };
1133 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
1134 {
1135 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr);
1136 MemOp opc = get_memop(l->oi);
1138 /* resolve label address */
1139 if (!reloc_pc16(l->label_ptr[0], tgt_rx)
1140 || (l->label_ptr[1] && !reloc_pc16(l->label_ptr[1], tgt_rx))) {
1141 return false;
1142 }
1144 tcg_out_ld_helper_args(s, l, &ldst_helper_param);
1146 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SSIZE], false);
1147 /* delay slot */
1148 tcg_out_nop(s);
1150 tcg_out_ld_helper_ret(s, l, true, &ldst_helper_param);
1152 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO);
1153 if (!reloc_pc16(s->code_ptr - 1, l->raddr)) {
1154 return false;
1155 }
1157 /* delay slot */
1158 tcg_out_nop(s);
1159 return true;
1160 }
1162 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
1163 {
1164 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr);
1165 MemOp opc = get_memop(l->oi);
1167 /* resolve label address */
1168 if (!reloc_pc16(l->label_ptr[0], tgt_rx)
1169 || (l->label_ptr[1] && !reloc_pc16(l->label_ptr[1], tgt_rx))) {
1170 return false;
1171 }
1173 tcg_out_st_helper_args(s, l, &ldst_helper_param);
1175 tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE], false);
1176 /* delay slot */
1177 tcg_out_nop(s);
1179 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO);
1180 if (!reloc_pc16(s->code_ptr - 1, l->raddr)) {
1181 return false;
1182 }
1184 /* delay slot */
1185 tcg_out_nop(s);
1186 return true;
1187 }
1189 typedef struct {
1190 TCGReg base;
1191 TCGAtomAlign aa;
1192 } HostAddress;
1194 bool tcg_target_has_memory_bswap(MemOp memop)
1195 {
1196 return false;
1197 }
1199 /* We expect to use a 16-bit negative offset from ENV. */
1200 #define MIN_TLB_MASK_TABLE_OFS -32768
1202 /*
1203 * For system-mode, perform the TLB load and compare.
1204 * For user-mode, perform any required alignment tests.
1205 * In both cases, return a TCGLabelQemuLdst structure if the slow path
1206 * is required and fill in @h with the host address for the fast path.
1207 */
1208 static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
1209 TCGReg addrlo, TCGReg addrhi,
1210 MemOpIdx oi, bool is_ld)
1211 {
1212 TCGType addr_type = s->addr_type;
1213 TCGLabelQemuLdst *ldst = NULL;
1214 MemOp opc = get_memop(oi);
1215 MemOp a_bits;
1216 unsigned s_bits = opc & MO_SIZE;
1217 unsigned a_mask;
1218 TCGReg base;
1220 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false);
1221 a_bits = h->aa.align;
1222 a_mask = (1 << a_bits) - 1;
1224 if (tcg_use_softmmu) {
1225 unsigned s_mask = (1 << s_bits) - 1;
1226 int mem_index = get_mmuidx(oi);
1227 int fast_off = tlb_mask_table_ofs(s, mem_index);
1228 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
1229 int table_off = fast_off + offsetof(CPUTLBDescFast, table);
1230 int add_off = offsetof(CPUTLBEntry, addend);
1231 int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read)
1232 : offsetof(CPUTLBEntry, addr_write);
1234 ldst = new_ldst_label(s);
1235 ldst->is_ld = is_ld;
1236 ldst->oi = oi;
1237 ldst->addrlo_reg = addrlo;
1238 ldst->addrhi_reg = addrhi;
1240 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
1241 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off);
1242 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off);
1244 /* Extract the TLB index from the address into TMP3. */
1245 if (TCG_TARGET_REG_BITS == 32 || addr_type == TCG_TYPE_I32) {
1246 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, addrlo,
1247 s->page_bits - CPU_TLB_ENTRY_BITS);
1248 } else {
1249 tcg_out_dsrl(s, TCG_TMP3, addrlo,
1250 s->page_bits - CPU_TLB_ENTRY_BITS);
1251 }
1252 tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0);
1254 /* Add the tlb_table pointer, creating the CPUTLBEntry address. */
1255 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1);
1257 if (TCG_TARGET_REG_BITS == 32 || addr_type == TCG_TYPE_I32) {
1258 /* Load the (low half) tlb comparator. */
1259 tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3,
1260 cmp_off + HOST_BIG_ENDIAN * 4);
1261 } else {
1262 tcg_out_ld(s, TCG_TYPE_I64, TCG_TMP0, TCG_TMP3, cmp_off);
1263 }
1265 if (TCG_TARGET_REG_BITS == 64 || addr_type == TCG_TYPE_I32) {
1266 /* Load the tlb addend for the fast path. */
1267 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off);
1268 }
1270 /*
1271 * Mask the page bits, keeping the alignment bits to compare against.
1272 * For unaligned accesses, compare against the end of the access to
1273 * verify that it does not cross a page boundary.
1274 */
1275 tcg_out_movi(s, addr_type, TCG_TMP1, s->page_mask | a_mask);
1276 if (a_mask < s_mask) {
1277 tcg_out_opc_imm(s, (TCG_TARGET_REG_BITS == 32
1278 || addr_type == TCG_TYPE_I32
1279 ? OPC_ADDIU : OPC_DADDIU),
1280 TCG_TMP2, addrlo, s_mask - a_mask);
1281 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2);
1282 } else {
1283 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrlo);
1284 }
1286 /* Zero extend a 32-bit guest address for a 64-bit host. */
1287 if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) {
1288 tcg_out_ext32u(s, TCG_TMP2, addrlo);
1289 addrlo = TCG_TMP2;
1290 }
1292 ldst->label_ptr[0] = s->code_ptr;
1293 tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0);
1295 /* Load and test the high half tlb comparator. */
1296 if (TCG_TARGET_REG_BITS == 32 && addr_type != TCG_TYPE_I32) {
1297 /* delay slot */
1298 tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF);
1300 /* Load the tlb addend for the fast path. */
1301 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off);
1303 ldst->label_ptr[1] = s->code_ptr;
1304 tcg_out_opc_br(s, OPC_BNE, addrhi, TCG_TMP0);
1305 }
1307 /* delay slot */
1308 base = TCG_TMP3;
1309 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP3, addrlo);
1310 } else {
1311 if (a_mask && (use_mips32r6_instructions || a_bits != s_bits)) {
1312 ldst = new_ldst_label(s);
1314 ldst->is_ld = is_ld;
1315 ldst->oi = oi;
1316 ldst->addrlo_reg = addrlo;
1317 ldst->addrhi_reg = addrhi;
1319 /* We are expecting a_bits to max out at 7, much lower than ANDI. */
1320 tcg_debug_assert(a_bits < 16);
1321 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, addrlo, a_mask);
1323 ldst->label_ptr[0] = s->code_ptr;
1324 if (use_mips32r6_instructions) {
1325 tcg_out_opc_br(s, OPC_BNEZALC_R6, TCG_REG_ZERO, TCG_TMP0);
1326 } else {
1327 tcg_out_opc_br(s, OPC_BNEL, TCG_TMP0, TCG_REG_ZERO);
1328 tcg_out_nop(s);
1329 }
1330 }
1332 base = addrlo;
1333 if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) {
1334 tcg_out_ext32u(s, TCG_REG_A0, base);
1335 base = TCG_REG_A0;
1336 }
1337 if (guest_base) {
1338 if (guest_base == (int16_t)guest_base) {
1339 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, base, guest_base);
1340 } else {
1341 tcg_out_opc_reg(s, ALIAS_PADD, TCG_REG_A0, base,
1342 TCG_GUEST_BASE_REG);
1343 }
1344 base = TCG_REG_A0;
1345 }
1346 }
1348 h->base = base;
1349 return ldst;
1350 }
1352 static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
1353 TCGReg base, MemOp opc, TCGType type)
1354 {
1355 switch (opc & MO_SSIZE) {
1356 case MO_UB:
1357 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0);
1358 break;
1359 case MO_SB:
1360 tcg_out_opc_imm(s, OPC_LB, lo, base, 0);
1361 break;
1362 case MO_UW:
1363 tcg_out_opc_imm(s, OPC_LHU, lo, base, 0);
1364 break;
1365 case MO_SW:
1366 tcg_out_opc_imm(s, OPC_LH, lo, base, 0);
1367 break;
1368 case MO_UL:
1369 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64) {
1370 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0);
1371 break;
1372 }
1373 /* FALLTHRU */
1374 case MO_SL:
1375 tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
1376 break;
1377 case MO_UQ:
1378 /* Prefer to load from offset 0 first, but allow for overlap. */
1379 if (TCG_TARGET_REG_BITS == 64) {
1380 tcg_out_opc_imm(s, OPC_LD, lo, base, 0);
1381 } else if (HOST_BIG_ENDIAN ? hi != base : lo == base) {
1382 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF);
1383 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF);
1384 } else {
1385 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF);
1386 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF);
1387 }
1388 break;
1389 default:
1390 g_assert_not_reached();
1391 }
1392 }
1394 static void tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi,
1395 TCGReg base, MemOp opc, TCGType type)
1396 {
1397 const MIPSInsn lw1 = HOST_BIG_ENDIAN ? OPC_LWL : OPC_LWR;
1398 const MIPSInsn lw2 = HOST_BIG_ENDIAN ? OPC_LWR : OPC_LWL;
1399 const MIPSInsn ld1 = HOST_BIG_ENDIAN ? OPC_LDL : OPC_LDR;
1400 const MIPSInsn ld2 = HOST_BIG_ENDIAN ? OPC_LDR : OPC_LDL;
1401 bool sgn = opc & MO_SIGN;
1403 switch (opc & MO_SIZE) {
1404 case MO_16:
1405 if (HOST_BIG_ENDIAN) {
1406 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 0);
1407 tcg_out_opc_imm(s, OPC_LBU, lo, base, 1);
1408 if (use_mips32r2_instructions) {
1409 tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8);
1410 } else {
1411 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP0, TCG_TMP0, 8);
1412 tcg_out_opc_reg(s, OPC_OR, lo, lo, TCG_TMP0);
1413 }
1414 } else if (use_mips32r2_instructions && lo != base) {
1415 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0);
1416 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 1);
1417 tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8);
1418 } else {
1419 tcg_out_opc_imm(s, OPC_LBU, TCG_TMP0, base, 0);
1420 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP1, base, 1);
1421 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP1, TCG_TMP1, 8);
1422 tcg_out_opc_reg(s, OPC_OR, lo, TCG_TMP0, TCG_TMP1);
1423 }
1424 break;
1426 case MO_32:
1427 tcg_out_opc_imm(s, lw1, lo, base, 0);
1428 tcg_out_opc_imm(s, lw2, lo, base, 3);
1429 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64 && !sgn) {
1430 tcg_out_ext32u(s, lo, lo);
1431 }
1432 break;
1434 case MO_64:
1435 if (TCG_TARGET_REG_BITS == 64) {
1436 tcg_out_opc_imm(s, ld1, lo, base, 0);
1437 tcg_out_opc_imm(s, ld2, lo, base, 7);
1438 } else {
1439 tcg_out_opc_imm(s, lw1, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 0);
1440 tcg_out_opc_imm(s, lw2, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 3);
1441 tcg_out_opc_imm(s, lw1, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 0);
1442 tcg_out_opc_imm(s, lw2, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 3);
1443 }
1444 break;
1446 default:
1447 g_assert_not_reached();
1448 }
1449 }
1451 static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi,
1452 TCGReg addrlo, TCGReg addrhi,
1453 MemOpIdx oi, TCGType data_type)
1454 {
1455 MemOp opc = get_memop(oi);
1456 TCGLabelQemuLdst *ldst;
1457 HostAddress h;
1459 ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, true);
1461 if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) {
1462 tcg_out_qemu_ld_direct(s, datalo, datahi, h.base, opc, data_type);
1463 } else {
1464 tcg_out_qemu_ld_unalign(s, datalo, datahi, h.base, opc, data_type);
1465 }
1467 if (ldst) {
1468 ldst->type = data_type;
1469 ldst->datalo_reg = datalo;
1470 ldst->datahi_reg = datahi;
1471 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr);
1472 }
1473 }
1475 static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,
1476 TCGReg base, MemOp opc)
1477 {
1478 switch (opc & MO_SIZE) {
1479 case MO_8:
1480 tcg_out_opc_imm(s, OPC_SB, lo, base, 0);
1481 break;
1482 case MO_16:
1483 tcg_out_opc_imm(s, OPC_SH, lo, base, 0);
1484 break;
1485 case MO_32:
1486 tcg_out_opc_imm(s, OPC_SW, lo, base, 0);
1487 break;
1488 case MO_64:
1489 if (TCG_TARGET_REG_BITS == 64) {
1490 tcg_out_opc_imm(s, OPC_SD, lo, base, 0);
1491 } else {
1492 tcg_out_opc_imm(s, OPC_SW, HOST_BIG_ENDIAN ? hi : lo, base, 0);
1493 tcg_out_opc_imm(s, OPC_SW, HOST_BIG_ENDIAN ? lo : hi, base, 4);
1494 }
1495 break;
1496 default:
1497 g_assert_not_reached();
1498 }
1499 }
1501 static void tcg_out_qemu_st_unalign(TCGContext *s, TCGReg lo, TCGReg hi,
1502 TCGReg base, MemOp opc)
1503 {
1504 const MIPSInsn sw1 = HOST_BIG_ENDIAN ? OPC_SWL : OPC_SWR;
1505 const MIPSInsn sw2 = HOST_BIG_ENDIAN ? OPC_SWR : OPC_SWL;
1506 const MIPSInsn sd1 = HOST_BIG_ENDIAN ? OPC_SDL : OPC_SDR;
1507 const MIPSInsn sd2 = HOST_BIG_ENDIAN ? OPC_SDR : OPC_SDL;
1509 switch (opc & MO_SIZE) {
1510 case MO_16:
1511 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, lo, 8);
1512 tcg_out_opc_imm(s, OPC_SB, HOST_BIG_ENDIAN ? TCG_TMP0 : lo, base, 0);
1513 tcg_out_opc_imm(s, OPC_SB, HOST_BIG_ENDIAN ? lo : TCG_TMP0, base, 1);
1514 break;
1516 case MO_32:
1517 tcg_out_opc_imm(s, sw1, lo, base, 0);
1518 tcg_out_opc_imm(s, sw2, lo, base, 3);
1519 break;
1521 case MO_64:
1522 if (TCG_TARGET_REG_BITS == 64) {
1523 tcg_out_opc_imm(s, sd1, lo, base, 0);
1524 tcg_out_opc_imm(s, sd2, lo, base, 7);
1525 } else {
1526 tcg_out_opc_imm(s, sw1, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 0);
1527 tcg_out_opc_imm(s, sw2, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 3);
1528 tcg_out_opc_imm(s, sw1, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 0);
1529 tcg_out_opc_imm(s, sw2, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 3);
1530 }
1531 break;
1533 default:
1534 g_assert_not_reached();
1535 }
1536 }
1538 static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi,
1539 TCGReg addrlo, TCGReg addrhi,
1540 MemOpIdx oi, TCGType data_type)
1541 {
1542 MemOp opc = get_memop(oi);
1543 TCGLabelQemuLdst *ldst;
1544 HostAddress h;
1546 ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, false);
1548 if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) {
1549 tcg_out_qemu_st_direct(s, datalo, datahi, h.base, opc);
1550 } else {
1551 tcg_out_qemu_st_unalign(s, datalo, datahi, h.base, opc);
1552 }
1554 if (ldst) {
1555 ldst->type = data_type;
1556 ldst->datalo_reg = datalo;
1557 ldst->datahi_reg = datahi;
1558 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr);
1559 }
1560 }
1562 static void tcg_out_mb(TCGContext *s, TCGArg a0)
1563 {
1564 static const MIPSInsn sync[] = {
1565 /* Note that SYNC_MB is a slightly weaker than SYNC 0,
1566 as the former is an ordering barrier and the latter
1567 is a completion barrier. */
1568 [0 ... TCG_MO_ALL] = OPC_SYNC_MB,
1569 [TCG_MO_LD_LD] = OPC_SYNC_RMB,
1570 [TCG_MO_ST_ST] = OPC_SYNC_WMB,
1571 [TCG_MO_LD_ST] = OPC_SYNC_RELEASE,
1572 [TCG_MO_LD_ST | TCG_MO_ST_ST] = OPC_SYNC_RELEASE,
1573 [TCG_MO_LD_ST | TCG_MO_LD_LD] = OPC_SYNC_ACQUIRE,
1574 };
1575 tcg_out32(s, sync[a0 & TCG_MO_ALL]);
1576 }
1578 static void tcg_out_clz(TCGContext *s, MIPSInsn opcv2, MIPSInsn opcv6,
1579 int width, TCGReg a0, TCGReg a1, TCGArg a2)
1580 {
1581 if (use_mips32r6_instructions) {
1582 if (a2 == width) {
1583 tcg_out_opc_reg(s, opcv6, a0, a1, 0);
1584 } else {
1585 tcg_out_opc_reg(s, opcv6, TCG_TMP0, a1, 0);
1586 tcg_out_movcond(s, TCG_COND_EQ, a0, a1, 0, a2, TCG_TMP0);
1587 }
1588 } else {
1589 if (a2 == width) {
1590 tcg_out_opc_reg(s, opcv2, a0, a1, a1);
1591 } else if (a0 == a2) {
1592 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1);
1593 tcg_out_opc_reg(s, OPC_MOVN, a0, TCG_TMP0, a1);
1594 } else if (a0 != a1) {
1595 tcg_out_opc_reg(s, opcv2, a0, a1, a1);
1596 tcg_out_opc_reg(s, OPC_MOVZ, a0, a2, a1);
1597 } else {
1598 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1);
1599 tcg_out_opc_reg(s, OPC_MOVZ, TCG_TMP0, a2, a1);
1600 tcg_out_mov(s, TCG_TYPE_REG, a0, TCG_TMP0);
1601 }
1602 }
1603 }
1605 static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0)
1606 {
1607 TCGReg base = TCG_REG_ZERO;
1608 int16_t lo = 0;
1610 if (a0) {
1611 intptr_t ofs;
1612 if (TCG_TARGET_REG_BITS == 64) {
1613 ofs = tcg_tbrel_diff(s, (void *)a0);
1614 lo = ofs;
1615 if (ofs == lo) {
1616 base = TCG_REG_TB;
1617 } else {
1618 base = TCG_REG_V0;
1619 tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo);
1620 tcg_out_opc_reg(s, ALIAS_PADD, base, base, TCG_REG_TB);
1621 }
1622 } else {
1623 ofs = a0;
1624 lo = ofs;
1625 base = TCG_REG_V0;
1626 tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo);
1627 }
1628 }
1629 if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) {
1630 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)tb_ret_addr);
1631 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0);
1632 }
1633 /* delay slot */
1634 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_V0, base, lo);
1635 }
1637 static void tcg_out_goto_tb(TCGContext *s, int which)
1638 {
1639 intptr_t ofs = get_jmp_target_addr(s, which);
1640 TCGReg base, dest;
1642 /* indirect jump method */
1643 if (TCG_TARGET_REG_BITS == 64) {
1644 dest = TCG_REG_TB;
1645 base = TCG_REG_TB;
1646 ofs = tcg_tbrel_diff(s, (void *)ofs);
1647 } else {
1648 dest = TCG_TMP0;
1649 base = TCG_REG_ZERO;
1650 }
1651 tcg_out_ld(s, TCG_TYPE_PTR, dest, base, ofs);
1652 tcg_out_opc_reg(s, OPC_JR, 0, dest, 0);
1653 /* delay slot */
1654 tcg_out_nop(s);
1656 set_jmp_reset_offset(s, which);
1657 if (TCG_TARGET_REG_BITS == 64) {
1658 /* For the unlinked case, need to reset TCG_REG_TB. */
1659 tcg_out_ldst(s, ALIAS_PADDI, TCG_REG_TB, TCG_REG_TB,
1660 -tcg_current_code_size(s));
1661 }
1662 }
1664 void tb_target_set_jmp_target(const TranslationBlock *tb, int n,
1665 uintptr_t jmp_rx, uintptr_t jmp_rw)
1666 {
1667 /* Always indirect, nothing to do */
1668 }
1670 static void tcg_out_op(TCGContext *s, TCGOpcode opc,
1671 const TCGArg args[TCG_MAX_OP_ARGS],
1672 const int const_args[TCG_MAX_OP_ARGS])
1673 {
1674 MIPSInsn i1, i2;
1675 TCGArg a0, a1, a2;
1676 int c2;
1678 /*
1679 * Note that many operands use the constraint set "rZ".
1680 * We make use of the fact that 0 is the ZERO register,
1681 * and hence such cases need not check for const_args.
1682 */
1683 a0 = args[0];
1684 a1 = args[1];
1685 a2 = args[2];
1686 c2 = const_args[2];
1688 switch (opc) {
1689 case INDEX_op_goto_ptr:
1690 /* jmp to the given host address (could be epilogue) */
1691 tcg_out_opc_reg(s, OPC_JR, 0, a0, 0);
1692 if (TCG_TARGET_REG_BITS == 64) {
1693 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0);
1694 } else {
1695 tcg_out_nop(s);
1696 }
1697 break;
1698 case INDEX_op_br:
1699 tcg_out_brcond(s, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO,
1700 arg_label(a0));
1701 break;
1703 case INDEX_op_ld8u_i32:
1704 case INDEX_op_ld8u_i64:
1705 i1 = OPC_LBU;
1706 goto do_ldst;
1707 case INDEX_op_ld8s_i32:
1708 case INDEX_op_ld8s_i64:
1709 i1 = OPC_LB;
1710 goto do_ldst;
1711 case INDEX_op_ld16u_i32:
1712 case INDEX_op_ld16u_i64:
1713 i1 = OPC_LHU;
1714 goto do_ldst;
1715 case INDEX_op_ld16s_i32:
1716 case INDEX_op_ld16s_i64:
1717 i1 = OPC_LH;
1718 goto do_ldst;
1719 case INDEX_op_ld_i32:
1720 case INDEX_op_ld32s_i64:
1721 i1 = OPC_LW;
1722 goto do_ldst;
1723 case INDEX_op_ld32u_i64:
1724 i1 = OPC_LWU;
1725 goto do_ldst;
1726 case INDEX_op_ld_i64:
1727 i1 = OPC_LD;
1728 goto do_ldst;
1729 case INDEX_op_st8_i32:
1730 case INDEX_op_st8_i64:
1731 i1 = OPC_SB;
1732 goto do_ldst;
1733 case INDEX_op_st16_i32:
1734 case INDEX_op_st16_i64:
1735 i1 = OPC_SH;
1736 goto do_ldst;
1737 case INDEX_op_st_i32:
1738 case INDEX_op_st32_i64:
1739 i1 = OPC_SW;
1740 goto do_ldst;
1741 case INDEX_op_st_i64:
1742 i1 = OPC_SD;
1743 do_ldst:
1744 tcg_out_ldst(s, i1, a0, a1, a2);
1745 break;
1747 case INDEX_op_add_i32:
1748 i1 = OPC_ADDU, i2 = OPC_ADDIU;
1749 goto do_binary;
1750 case INDEX_op_add_i64:
1751 i1 = OPC_DADDU, i2 = OPC_DADDIU;
1752 goto do_binary;
1753 case INDEX_op_or_i32:
1754 case INDEX_op_or_i64:
1755 i1 = OPC_OR, i2 = OPC_ORI;
1756 goto do_binary;
1757 case INDEX_op_xor_i32:
1758 case INDEX_op_xor_i64:
1759 i1 = OPC_XOR, i2 = OPC_XORI;
1760 do_binary:
1761 if (c2) {
1762 tcg_out_opc_imm(s, i2, a0, a1, a2);
1763 break;
1764 }
1765 do_binaryv:
1766 tcg_out_opc_reg(s, i1, a0, a1, a2);
1767 break;
1769 case INDEX_op_sub_i32:
1770 i1 = OPC_SUBU, i2 = OPC_ADDIU;
1771 goto do_subtract;
1772 case INDEX_op_sub_i64:
1773 i1 = OPC_DSUBU, i2 = OPC_DADDIU;
1774 do_subtract:
1775 if (c2) {
1776 tcg_out_opc_imm(s, i2, a0, a1, -a2);
1777 break;
1778 }
1779 goto do_binaryv;
1780 case INDEX_op_and_i32:
1781 if (c2 && a2 != (uint16_t)a2) {
1782 int msb = ctz32(~a2) - 1;
1783 tcg_debug_assert(use_mips32r2_instructions);
1784 tcg_debug_assert(is_p2m1(a2));
1785 tcg_out_opc_bf(s, OPC_EXT, a0, a1, msb, 0);
1786 break;
1787 }
1788 i1 = OPC_AND, i2 = OPC_ANDI;
1789 goto do_binary;
1790 case INDEX_op_and_i64:
1791 if (c2 && a2 != (uint16_t)a2) {
1792 int msb = ctz64(~a2) - 1;
1793 tcg_debug_assert(use_mips32r2_instructions);
1794 tcg_debug_assert(is_p2m1(a2));
1795 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, msb, 0);
1796 break;
1797 }
1798 i1 = OPC_AND, i2 = OPC_ANDI;
1799 goto do_binary;
1800 case INDEX_op_nor_i32:
1801 case INDEX_op_nor_i64:
1802 i1 = OPC_NOR;
1803 goto do_binaryv;
1805 case INDEX_op_mul_i32:
1806 if (use_mips32_instructions) {
1807 tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2);
1808 break;
1809 }
1810 i1 = OPC_MULT, i2 = OPC_MFLO;
1811 goto do_hilo1;
1812 case INDEX_op_mulsh_i32:
1813 if (use_mips32r6_instructions) {
1814 tcg_out_opc_reg(s, OPC_MUH, a0, a1, a2);
1815 break;
1816 }
1817 i1 = OPC_MULT, i2 = OPC_MFHI;
1818 goto do_hilo1;
1819 case INDEX_op_muluh_i32:
1820 if (use_mips32r6_instructions) {
1821 tcg_out_opc_reg(s, OPC_MUHU, a0, a1, a2);
1822 break;
1823 }
1824 i1 = OPC_MULTU, i2 = OPC_MFHI;
1825 goto do_hilo1;
1826 case INDEX_op_div_i32:
1827 if (use_mips32r6_instructions) {
1828 tcg_out_opc_reg(s, OPC_DIV_R6, a0, a1, a2);
1829 break;
1830 }
1831 i1 = OPC_DIV, i2 = OPC_MFLO;
1832 goto do_hilo1;
1833 case INDEX_op_divu_i32:
1834 if (use_mips32r6_instructions) {
1835 tcg_out_opc_reg(s, OPC_DIVU_R6, a0, a1, a2);
1836 break;
1837 }
1838 i1 = OPC_DIVU, i2 = OPC_MFLO;
1839 goto do_hilo1;
1840 case INDEX_op_rem_i32:
1841 if (use_mips32r6_instructions) {
1842 tcg_out_opc_reg(s, OPC_MOD, a0, a1, a2);
1843 break;
1844 }
1845 i1 = OPC_DIV, i2 = OPC_MFHI;
1846 goto do_hilo1;
1847 case INDEX_op_remu_i32:
1848 if (use_mips32r6_instructions) {
1849 tcg_out_opc_reg(s, OPC_MODU, a0, a1, a2);
1850 break;
1851 }
1852 i1 = OPC_DIVU, i2 = OPC_MFHI;
1853 goto do_hilo1;
1854 case INDEX_op_mul_i64:
1855 if (use_mips32r6_instructions) {
1856 tcg_out_opc_reg(s, OPC_DMUL, a0, a1, a2);
1857 break;
1858 }
1859 i1 = OPC_DMULT, i2 = OPC_MFLO;
1860 goto do_hilo1;
1861 case INDEX_op_mulsh_i64:
1862 if (use_mips32r6_instructions) {
1863 tcg_out_opc_reg(s, OPC_DMUH, a0, a1, a2);
1864 break;
1865 }
1866 i1 = OPC_DMULT, i2 = OPC_MFHI;
1867 goto do_hilo1;
1868 case INDEX_op_muluh_i64:
1869 if (use_mips32r6_instructions) {
1870 tcg_out_opc_reg(s, OPC_DMUHU, a0, a1, a2);
1871 break;
1872 }
1873 i1 = OPC_DMULTU, i2 = OPC_MFHI;
1874 goto do_hilo1;
1875 case INDEX_op_div_i64:
1876 if (use_mips32r6_instructions) {
1877 tcg_out_opc_reg(s, OPC_DDIV_R6, a0, a1, a2);
1878 break;
1879 }
1880 i1 = OPC_DDIV, i2 = OPC_MFLO;
1881 goto do_hilo1;
1882 case INDEX_op_divu_i64:
1883 if (use_mips32r6_instructions) {
1884 tcg_out_opc_reg(s, OPC_DDIVU_R6, a0, a1, a2);
1885 break;
1886 }
1887 i1 = OPC_DDIVU, i2 = OPC_MFLO;
1888 goto do_hilo1;
1889 case INDEX_op_rem_i64:
1890 if (use_mips32r6_instructions) {
1891 tcg_out_opc_reg(s, OPC_DMOD, a0, a1, a2);
1892 break;
1893 }
1894 i1 = OPC_DDIV, i2 = OPC_MFHI;
1895 goto do_hilo1;
1896 case INDEX_op_remu_i64:
1897 if (use_mips32r6_instructions) {
1898 tcg_out_opc_reg(s, OPC_DMODU, a0, a1, a2);
1899 break;
1900 }
1901 i1 = OPC_DDIVU, i2 = OPC_MFHI;
1902 do_hilo1:
1903 tcg_out_opc_reg(s, i1, 0, a1, a2);
1904 tcg_out_opc_reg(s, i2, a0, 0, 0);
1905 break;
1907 case INDEX_op_muls2_i32:
1908 i1 = OPC_MULT;
1909 goto do_hilo2;
1910 case INDEX_op_mulu2_i32:
1911 i1 = OPC_MULTU;
1912 goto do_hilo2;
1913 case INDEX_op_muls2_i64:
1914 i1 = OPC_DMULT;
1915 goto do_hilo2;
1916 case INDEX_op_mulu2_i64:
1917 i1 = OPC_DMULTU;
1918 do_hilo2:
1919 tcg_out_opc_reg(s, i1, 0, a2, args[3]);
1920 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0);
1921 tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0);
1922 break;
1924 case INDEX_op_neg_i32:
1925 i1 = OPC_SUBU;
1926 goto do_unary;
1927 case INDEX_op_neg_i64:
1928 i1 = OPC_DSUBU;
1929 goto do_unary;
1930 case INDEX_op_not_i32:
1931 case INDEX_op_not_i64:
1932 i1 = OPC_NOR;
1933 goto do_unary;
1934 do_unary:
1935 tcg_out_opc_reg(s, i1, a0, TCG_REG_ZERO, a1);
1936 break;
1938 case INDEX_op_bswap16_i32:
1939 case INDEX_op_bswap16_i64:
1940 tcg_out_bswap16(s, a0, a1, a2);
1941 break;
1942 case INDEX_op_bswap32_i32:
1943 tcg_out_bswap32(s, a0, a1, 0);
1944 break;
1945 case INDEX_op_bswap32_i64:
1946 tcg_out_bswap32(s, a0, a1, a2);
1947 break;
1948 case INDEX_op_bswap64_i64:
1949 tcg_out_bswap64(s, a0, a1);
1950 break;
1951 case INDEX_op_extrh_i64_i32:
1952 tcg_out_dsra(s, a0, a1, 32);
1953 break;
1955 case INDEX_op_sar_i32:
1956 i1 = OPC_SRAV, i2 = OPC_SRA;
1957 goto do_shift;
1958 case INDEX_op_shl_i32:
1959 i1 = OPC_SLLV, i2 = OPC_SLL;
1960 goto do_shift;
1961 case INDEX_op_shr_i32:
1962 i1 = OPC_SRLV, i2 = OPC_SRL;
1963 goto do_shift;
1964 case INDEX_op_rotr_i32:
1965 i1 = OPC_ROTRV, i2 = OPC_ROTR;
1966 do_shift:
1967 if (c2) {
1968 tcg_out_opc_sa(s, i2, a0, a1, a2);
1969 break;
1970 }
1971 do_shiftv:
1972 tcg_out_opc_reg(s, i1, a0, a2, a1);
1973 break;
1974 case INDEX_op_rotl_i32:
1975 if (c2) {
1976 tcg_out_opc_sa(s, OPC_ROTR, a0, a1, 32 - a2);
1977 } else {
1978 tcg_out_opc_reg(s, OPC_SUBU, TCG_TMP0, TCG_REG_ZERO, a2);
1979 tcg_out_opc_reg(s, OPC_ROTRV, a0, TCG_TMP0, a1);
1980 }
1981 break;
1982 case INDEX_op_sar_i64:
1983 if (c2) {
1984 tcg_out_dsra(s, a0, a1, a2);
1985 break;
1986 }
1987 i1 = OPC_DSRAV;
1988 goto do_shiftv;
1989 case INDEX_op_shl_i64:
1990 if (c2) {
1991 tcg_out_dsll(s, a0, a1, a2);
1992 break;
1993 }
1994 i1 = OPC_DSLLV;
1995 goto do_shiftv;
1996 case INDEX_op_shr_i64:
1997 if (c2) {
1998 tcg_out_dsrl(s, a0, a1, a2);
1999 break;
2000 }
2001 i1 = OPC_DSRLV;
2002 goto do_shiftv;
2003 case INDEX_op_rotr_i64:
2004 if (c2) {
2005 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, a2);
2006 break;
2007 }
2008 i1 = OPC_DROTRV;
2009 goto do_shiftv;
2010 case INDEX_op_rotl_i64:
2011 if (c2) {
2012 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, 64 - a2);
2013 } else {
2014 tcg_out_opc_reg(s, OPC_DSUBU, TCG_TMP0, TCG_REG_ZERO, a2);
2015 tcg_out_opc_reg(s, OPC_DROTRV, a0, TCG_TMP0, a1);
2016 }
2017 break;
2019 case INDEX_op_clz_i32:
2020 tcg_out_clz(s, OPC_CLZ, OPC_CLZ_R6, 32, a0, a1, a2);
2021 break;
2022 case INDEX_op_clz_i64:
2023 tcg_out_clz(s, OPC_DCLZ, OPC_DCLZ_R6, 64, a0, a1, a2);
2024 break;
2026 case INDEX_op_deposit_i32:
2027 tcg_out_opc_bf(s, OPC_INS, a0, a2, args[3] + args[4] - 1, args[3]);
2028 break;
2029 case INDEX_op_deposit_i64:
2030 tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2,
2031 args[3] + args[4] - 1, args[3]);
2032 break;
2033 case INDEX_op_extract_i32:
2034 tcg_out_opc_bf(s, OPC_EXT, a0, a1, args[3] - 1, a2);
2035 break;
2036 case INDEX_op_extract_i64:
2037 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1,
2038 args[3] - 1, a2);
2039 break;
2041 case INDEX_op_brcond_i32:
2042 case INDEX_op_brcond_i64:
2043 tcg_out_brcond(s, a2, a0, a1, arg_label(args[3]));
2044 break;
2045 case INDEX_op_brcond2_i32:
2046 tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5]));
2047 break;
2049 case INDEX_op_movcond_i32:
2050 case INDEX_op_movcond_i64:
2051 tcg_out_movcond(s, args[5], a0, a1, a2, args[3], args[4]);
2052 break;
2054 case INDEX_op_setcond_i32:
2055 case INDEX_op_setcond_i64:
2056 tcg_out_setcond(s, args[3], a0, a1, a2);
2057 break;
2058 case INDEX_op_setcond2_i32:
2059 tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]);
2060 break;
2062 case INDEX_op_qemu_ld_a64_i32:
2063 if (TCG_TARGET_REG_BITS == 32) {
2064 tcg_out_qemu_ld(s, a0, 0, a1, a2, args[3], TCG_TYPE_I32);
2065 break;
2066 }
2067 /* fall through */
2068 case INDEX_op_qemu_ld_a32_i32:
2069 tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I32);
2070 break;
2071 case INDEX_op_qemu_ld_a32_i64:
2072 if (TCG_TARGET_REG_BITS == 64) {
2073 tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I64);
2074 } else {
2075 tcg_out_qemu_ld(s, a0, a1, a2, 0, args[3], TCG_TYPE_I64);
2076 }
2077 break;
2078 case INDEX_op_qemu_ld_a64_i64:
2079 if (TCG_TARGET_REG_BITS == 64) {
2080 tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I64);
2081 } else {
2082 tcg_out_qemu_ld(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64);
2083 }
2084 break;
2086 case INDEX_op_qemu_st_a64_i32:
2087 if (TCG_TARGET_REG_BITS == 32) {
2088 tcg_out_qemu_st(s, a0, 0, a1, a2, args[3], TCG_TYPE_I32);
2089 break;
2090 }
2091 /* fall through */
2092 case INDEX_op_qemu_st_a32_i32:
2093 tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I32);
2094 break;
2095 case INDEX_op_qemu_st_a32_i64:
2096 if (TCG_TARGET_REG_BITS == 64) {
2097 tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I64);
2098 } else {
2099 tcg_out_qemu_st(s, a0, a1, a2, 0, args[3], TCG_TYPE_I64);
2100 }
2101 break;
2102 case INDEX_op_qemu_st_a64_i64:
2103 if (TCG_TARGET_REG_BITS == 64) {
2104 tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I64);
2105 } else {
2106 tcg_out_qemu_st(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64);
2107 }
2108 break;
2110 case INDEX_op_add2_i32:
2111 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
2112 const_args[4], const_args[5], false);
2113 break;
2114 case INDEX_op_sub2_i32:
2115 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
2116 const_args[4], const_args[5], true);
2117 break;
2119 case INDEX_op_mb:
2120 tcg_out_mb(s, a0);
2121 break;
2122 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
2123 case INDEX_op_mov_i64:
2124 case INDEX_op_call: /* Always emitted via tcg_out_call. */
2125 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */
2126 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */
2127 case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */
2128 case INDEX_op_ext8s_i64:
2129 case INDEX_op_ext8u_i32:
2130 case INDEX_op_ext8u_i64:
2131 case INDEX_op_ext16s_i32:
2132 case INDEX_op_ext16s_i64:
2133 case INDEX_op_ext32s_i64:
2134 case INDEX_op_ext32u_i64:
2135 case INDEX_op_ext_i32_i64:
2136 case INDEX_op_extu_i32_i64:
2137 case INDEX_op_extrl_i64_i32:
2138 default:
2139 g_assert_not_reached();
2140 }
2141 }
2143 static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
2144 {
2145 switch (op) {
2146 case INDEX_op_goto_ptr:
2147 return C_O0_I1(r);
2149 case INDEX_op_ld8u_i32:
2150 case INDEX_op_ld8s_i32:
2151 case INDEX_op_ld16u_i32:
2152 case INDEX_op_ld16s_i32:
2153 case INDEX_op_ld_i32:
2154 case INDEX_op_neg_i32:
2155 case INDEX_op_not_i32:
2156 case INDEX_op_bswap16_i32:
2157 case INDEX_op_bswap32_i32:
2158 case INDEX_op_ext8s_i32:
2159 case INDEX_op_ext16s_i32:
2160 case INDEX_op_extract_i32:
2161 case INDEX_op_ld8u_i64:
2162 case INDEX_op_ld8s_i64:
2163 case INDEX_op_ld16u_i64:
2164 case INDEX_op_ld16s_i64:
2165 case INDEX_op_ld32s_i64:
2166 case INDEX_op_ld32u_i64:
2167 case INDEX_op_ld_i64:
2168 case INDEX_op_neg_i64:
2169 case INDEX_op_not_i64:
2170 case INDEX_op_bswap16_i64:
2171 case INDEX_op_bswap32_i64:
2172 case INDEX_op_bswap64_i64:
2173 case INDEX_op_ext8s_i64:
2174 case INDEX_op_ext16s_i64:
2175 case INDEX_op_ext32s_i64:
2176 case INDEX_op_ext32u_i64:
2177 case INDEX_op_ext_i32_i64:
2178 case INDEX_op_extu_i32_i64:
2179 case INDEX_op_extrl_i64_i32:
2180 case INDEX_op_extrh_i64_i32:
2181 case INDEX_op_extract_i64:
2182 return C_O1_I1(r, r);
2184 case INDEX_op_st8_i32:
2185 case INDEX_op_st16_i32:
2186 case INDEX_op_st_i32:
2187 case INDEX_op_st8_i64:
2188 case INDEX_op_st16_i64:
2189 case INDEX_op_st32_i64:
2190 case INDEX_op_st_i64:
2191 return C_O0_I2(rZ, r);
2193 case INDEX_op_add_i32:
2194 case INDEX_op_add_i64:
2195 return C_O1_I2(r, r, rJ);
2196 case INDEX_op_sub_i32:
2197 case INDEX_op_sub_i64:
2198 return C_O1_I2(r, rZ, rN);
2199 case INDEX_op_mul_i32:
2200 case INDEX_op_mulsh_i32:
2201 case INDEX_op_muluh_i32:
2202 case INDEX_op_div_i32:
2203 case INDEX_op_divu_i32:
2204 case INDEX_op_rem_i32:
2205 case INDEX_op_remu_i32:
2206 case INDEX_op_nor_i32:
2207 case INDEX_op_setcond_i32:
2208 case INDEX_op_mul_i64:
2209 case INDEX_op_mulsh_i64:
2210 case INDEX_op_muluh_i64:
2211 case INDEX_op_div_i64:
2212 case INDEX_op_divu_i64:
2213 case INDEX_op_rem_i64:
2214 case INDEX_op_remu_i64:
2215 case INDEX_op_nor_i64:
2216 case INDEX_op_setcond_i64:
2217 return C_O1_I2(r, rZ, rZ);
2218 case INDEX_op_muls2_i32:
2219 case INDEX_op_mulu2_i32:
2220 case INDEX_op_muls2_i64:
2221 case INDEX_op_mulu2_i64:
2222 return C_O2_I2(r, r, r, r);
2223 case INDEX_op_and_i32:
2224 case INDEX_op_and_i64:
2225 return C_O1_I2(r, r, rIK);
2226 case INDEX_op_or_i32:
2227 case INDEX_op_xor_i32:
2228 case INDEX_op_or_i64:
2229 case INDEX_op_xor_i64:
2230 return C_O1_I2(r, r, rI);
2231 case INDEX_op_shl_i32:
2232 case INDEX_op_shr_i32:
2233 case INDEX_op_sar_i32:
2234 case INDEX_op_rotr_i32:
2235 case INDEX_op_rotl_i32:
2236 case INDEX_op_shl_i64:
2237 case INDEX_op_shr_i64:
2238 case INDEX_op_sar_i64:
2239 case INDEX_op_rotr_i64:
2240 case INDEX_op_rotl_i64:
2241 return C_O1_I2(r, r, ri);
2242 case INDEX_op_clz_i32:
2243 case INDEX_op_clz_i64:
2244 return C_O1_I2(r, r, rWZ);
2246 case INDEX_op_deposit_i32:
2247 case INDEX_op_deposit_i64:
2248 return C_O1_I2(r, 0, rZ);
2249 case INDEX_op_brcond_i32:
2250 case INDEX_op_brcond_i64:
2251 return C_O0_I2(rZ, rZ);
2252 case INDEX_op_movcond_i32:
2253 case INDEX_op_movcond_i64:
2254 return (use_mips32r6_instructions
2255 ? C_O1_I4(r, rZ, rZ, rZ, rZ)
2256 : C_O1_I4(r, rZ, rZ, rZ, 0));
2257 case INDEX_op_add2_i32:
2258 case INDEX_op_sub2_i32:
2259 return C_O2_I4(r, r, rZ, rZ, rN, rN);
2260 case INDEX_op_setcond2_i32:
2261 return C_O1_I4(r, rZ, rZ, rZ, rZ);
2262 case INDEX_op_brcond2_i32:
2263 return C_O0_I4(rZ, rZ, rZ, rZ);
2265 case INDEX_op_qemu_ld_a32_i32:
2266 return C_O1_I1(r, r);
2267 case INDEX_op_qemu_ld_a64_i32:
2268 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O1_I2(r, r, r);
2269 case INDEX_op_qemu_st_a32_i32:
2270 return C_O0_I2(rZ, r);
2271 case INDEX_op_qemu_st_a64_i32:
2272 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(rZ, r) : C_O0_I3(rZ, r, r);
2273 case INDEX_op_qemu_ld_a32_i64:
2274 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I1(r, r, r);
2275 case INDEX_op_qemu_ld_a64_i64:
2276 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I2(r, r, r, r);
2277 case INDEX_op_qemu_st_a32_i64:
2278 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(rZ, r) : C_O0_I3(rZ, rZ, r);
2279 case INDEX_op_qemu_st_a64_i64:
2280 return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(rZ, r)
2281 : C_O0_I4(rZ, rZ, r, r));
2283 default:
2284 g_assert_not_reached();
2285 }
2286 }
2288 static const int tcg_target_callee_save_regs[] = {
2289 TCG_REG_S0,
2290 TCG_REG_S1,
2291 TCG_REG_S2,
2292 TCG_REG_S3,
2293 TCG_REG_S4,
2294 TCG_REG_S5,
2295 TCG_REG_S6, /* used for the tb base (TCG_REG_TB) */
2296 TCG_REG_S7, /* used for guest_base */
2297 TCG_REG_S8, /* used for the global env (TCG_AREG0) */
2298 TCG_REG_RA, /* should be last for ABI compliance */
2299 };
2301 /* The Linux kernel doesn't provide any information about the available
2302 instruction set. Probe it using a signal handler. */
2305 #ifndef use_movnz_instructions
2306 bool use_movnz_instructions = false;
2307 #endif
2309 #ifndef use_mips32_instructions
2310 bool use_mips32_instructions = false;
2311 #endif
2313 #ifndef use_mips32r2_instructions
2314 bool use_mips32r2_instructions = false;
2315 #endif
2317 static volatile sig_atomic_t got_sigill;
2319 static void sigill_handler(int signo, siginfo_t *si, void *data)
2320 {
2321 /* Skip the faulty instruction */
2322 ucontext_t *uc = (ucontext_t *)data;
2323 uc->uc_mcontext.pc += 4;
2325 got_sigill = 1;
2326 }
2328 static void tcg_target_detect_isa(void)
2329 {
2330 struct sigaction sa_old, sa_new;
2332 memset(&sa_new, 0, sizeof(sa_new));
2333 sa_new.sa_flags = SA_SIGINFO;
2334 sa_new.sa_sigaction = sigill_handler;
2335 sigaction(SIGILL, &sa_new, &sa_old);
2337 /* Probe for movn/movz, necessary to implement movcond. */
2338 #ifndef use_movnz_instructions
2339 got_sigill = 0;
2340 asm volatile(".set push\n"
2341 ".set mips32\n"
2342 "movn $zero, $zero, $zero\n"
2343 "movz $zero, $zero, $zero\n"
2344 ".set pop\n"
2345 : : : );
2346 use_movnz_instructions = !got_sigill;
2347 #endif
2349 /* Probe for MIPS32 instructions. As no subsetting is allowed
2350 by the specification, it is only necessary to probe for one
2351 of the instructions. */
2352 #ifndef use_mips32_instructions
2353 got_sigill = 0;
2354 asm volatile(".set push\n"
2355 ".set mips32\n"
2356 "mul $zero, $zero\n"
2357 ".set pop\n"
2358 : : : );
2359 use_mips32_instructions = !got_sigill;
2360 #endif
2362 /* Probe for MIPS32r2 instructions if MIPS32 instructions are
2363 available. As no subsetting is allowed by the specification,
2364 it is only necessary to probe for one of the instructions. */
2365 #ifndef use_mips32r2_instructions
2366 if (use_mips32_instructions) {
2367 got_sigill = 0;
2368 asm volatile(".set push\n"
2369 ".set mips32r2\n"
2370 "seb $zero, $zero\n"
2371 ".set pop\n"
2372 : : : );
2373 use_mips32r2_instructions = !got_sigill;
2374 }
2375 #endif
2377 sigaction(SIGILL, &sa_old, NULL);
2378 }
2380 static tcg_insn_unit *align_code_ptr(TCGContext *s)
2381 {
2382 uintptr_t p = (uintptr_t)s->code_ptr;
2383 if (p & 15) {
2384 p = (p + 15) & -16;
2385 s->code_ptr = (void *)p;
2386 }
2387 return s->code_ptr;
2388 }
2390 /* Stack frame parameters. */
2391 #define REG_SIZE (TCG_TARGET_REG_BITS / 8)
2392 #define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE)
2393 #define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
2395 #define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \
2396 + TCG_TARGET_STACK_ALIGN - 1) \
2397 & -TCG_TARGET_STACK_ALIGN)
2398 #define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE)
2400 /* We're expecting to be able to use an immediate for frame allocation. */
2401 QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7fff);
2403 /* Generate global QEMU prologue and epilogue code */
2404 static void tcg_target_qemu_prologue(TCGContext *s)
2405 {
2406 int i;
2408 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE);
2410 /* TB prologue */
2411 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE);
2412 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
2413 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
2414 TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
2415 }
2417 if (!tcg_use_softmmu && guest_base != (int16_t)guest_base) {
2418 /*
2419 * The function call abi for n32 and n64 will have loaded $25 (t9)
2420 * with the address of the prologue, so we can use that instead
2421 * of TCG_REG_TB.
2422 */
2423 #if TCG_TARGET_REG_BITS == 64 && !defined(__mips_abicalls)
2424 # error "Unknown mips abi"
2425 #endif
2426 tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base,
2427 TCG_TARGET_REG_BITS == 64 ? TCG_REG_T9 : 0);
2428 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
2429 }
2431 if (TCG_TARGET_REG_BITS == 64) {
2432 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]);
2433 }
2435 /* Call generated code */
2436 tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0);
2437 /* delay slot */
2438 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
2440 /*
2441 * Return path for goto_ptr. Set return value to 0, a-la exit_tb,
2442 * and fall through to the rest of the epilogue.
2443 */
2444 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr);
2445 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_V0, TCG_REG_ZERO);
2447 /* TB epilogue */
2448 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr);
2449 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
2450 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
2451 TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
2452 }
2454 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2455 /* delay slot */
2456 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE);
2458 if (use_mips32r2_instructions) {
2459 return;
2460 }
2462 /* Bswap subroutines: Input in TCG_TMP0, output in TCG_TMP3;
2463 clobbers TCG_TMP1, TCG_TMP2. */
2465 /*
2466 * bswap32 -- 32-bit swap (signed result for mips64). a0 = abcd.
2467 */
2468 bswap32_addr = tcg_splitwx_to_rx(align_code_ptr(s));
2469 /* t3 = (ssss)d000 */
2470 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP3, TCG_TMP0, 24);
2471 /* t1 = 000a */
2472 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 24);
2473 /* t2 = 00c0 */
2474 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
2475 /* t3 = d00a */
2476 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2477 /* t1 = 0abc */
2478 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8);
2479 /* t2 = 0c00 */
2480 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8);
2481 /* t1 = 00b0 */
2482 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2483 /* t3 = dc0a */
2484 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2485 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2486 /* t3 = dcba -- delay slot */
2487 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2489 if (TCG_TARGET_REG_BITS == 32) {
2490 return;
2491 }
2493 /*
2494 * bswap32u -- unsigned 32-bit swap. a0 = ....abcd.
2495 */
2496 bswap32u_addr = tcg_splitwx_to_rx(align_code_ptr(s));
2497 /* t1 = (0000)000d */
2498 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP0, 0xff);
2499 /* t3 = 000a */
2500 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, TCG_TMP0, 24);
2501 /* t1 = (0000)d000 */
2502 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24);
2503 /* t2 = 00c0 */
2504 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
2505 /* t3 = d00a */
2506 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2507 /* t1 = 0abc */
2508 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8);
2509 /* t2 = 0c00 */
2510 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8);
2511 /* t1 = 00b0 */
2512 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2513 /* t3 = dc0a */
2514 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2515 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2516 /* t3 = dcba -- delay slot */
2517 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2519 /*
2520 * bswap64 -- 64-bit swap. a0 = abcdefgh
2521 */
2522 bswap64_addr = tcg_splitwx_to_rx(align_code_ptr(s));
2523 /* t3 = h0000000 */
2524 tcg_out_dsll(s, TCG_TMP3, TCG_TMP0, 56);
2525 /* t1 = 0000000a */
2526 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 56);
2528 /* t2 = 000000g0 */
2529 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
2530 /* t3 = h000000a */
2531 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2532 /* t1 = 00000abc */
2533 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 40);
2534 /* t2 = 0g000000 */
2535 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40);
2536 /* t1 = 000000b0 */
2537 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2539 /* t3 = hg00000a */
2540 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2541 /* t2 = 0000abcd */
2542 tcg_out_dsrl(s, TCG_TMP2, TCG_TMP0, 32);
2543 /* t3 = hg0000ba */
2544 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2546 /* t1 = 000000c0 */
2547 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP2, 0xff00);
2548 /* t2 = 0000000d */
2549 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP2, 0x00ff);
2550 /* t1 = 00000c00 */
2551 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 8);
2552 /* t2 = 0000d000 */
2553 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 24);
2555 /* t3 = hg000cba */
2556 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2557 /* t1 = 00abcdef */
2558 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 16);
2559 /* t3 = hg00dcba */
2560 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2562 /* t2 = 0000000f */
2563 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP1, 0x00ff);
2564 /* t1 = 000000e0 */
2565 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2566 /* t2 = 00f00000 */
2567 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40);
2568 /* t1 = 000e0000 */
2569 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24);
2571 /* t3 = hgf0dcba */
2572 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2573 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2574 /* t3 = hgfedcba -- delay slot */
2575 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2576 }
2578 static void tcg_out_tb_start(TCGContext *s)
2579 {
2580 /* nothing to do */
2581 }
2583 static void tcg_target_init(TCGContext *s)
2584 {
2585 tcg_target_detect_isa();
2586 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
2587 if (TCG_TARGET_REG_BITS == 64) {
2588 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
2589 }
2591 tcg_target_call_clobber_regs = 0;
2592 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0);
2593 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1);
2594 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A0);
2595 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A1);
2596 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A2);
2597 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A3);
2598 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T0);
2599 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T1);
2600 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T2);
2601 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T3);
2602 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T4);
2603 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T5);
2604 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T6);
2605 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T7);
2606 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T8);
2607 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T9);
2609 s->reserved_regs = 0;
2610 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */
2611 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K0); /* kernel use only */
2612 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1); /* kernel use only */
2613 tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); /* internal use */
2614 tcg_regset_set_reg(s->reserved_regs, TCG_TMP1); /* internal use */
2615 tcg_regset_set_reg(s->reserved_regs, TCG_TMP2); /* internal use */
2616 tcg_regset_set_reg(s->reserved_regs, TCG_TMP3); /* internal use */
2617 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */
2618 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */
2619 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */
2620 if (TCG_TARGET_REG_BITS == 64) {
2621 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tc->tc_ptr */
2622 }
2623 }
2625 typedef struct {
2626 DebugFrameHeader h;
2627 uint8_t fde_def_cfa[4];
2628 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2];
2629 } DebugFrame;
2631 #define ELF_HOST_MACHINE EM_MIPS
2632 /* GDB doesn't appear to require proper setting of ELF_HOST_FLAGS,
2633 which is good because they're really quite complicated for MIPS. */
2635 static const DebugFrame debug_frame = {
2636 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */
2637 .h.cie.id = -1,
2638 .h.cie.version = 1,
2639 .h.cie.code_align = 1,
2640 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */
2641 .h.cie.return_column = TCG_REG_RA,
2643 /* Total FDE size does not include the "len" member. */
2644 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
2646 .fde_def_cfa = {
2647 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */
2648 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
2649 (FRAME_SIZE >> 7)
2650 },
2651 .fde_reg_ofs = {
2652 0x80 + 16, 9, /* DW_CFA_offset, s0, -72 */
2653 0x80 + 17, 8, /* DW_CFA_offset, s2, -64 */
2654 0x80 + 18, 7, /* DW_CFA_offset, s3, -56 */
2655 0x80 + 19, 6, /* DW_CFA_offset, s4, -48 */
2656 0x80 + 20, 5, /* DW_CFA_offset, s5, -40 */
2657 0x80 + 21, 4, /* DW_CFA_offset, s6, -32 */
2658 0x80 + 22, 3, /* DW_CFA_offset, s7, -24 */
2659 0x80 + 30, 2, /* DW_CFA_offset, s8, -16 */
2660 0x80 + 31, 1, /* DW_CFA_offset, ra, -8 */
2661 }
2662 };
2664 void tcg_register_jit(const void *buf, size_t buf_size)
2665 {
2666 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
2667 }