2 * ARM Generic/Distributed Interrupt Controller
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
10 /* This file contains implementation code for the RealView EB interrupt
11 * controller, MPCore distributed interrupt controller and ARMv7-M
12 * Nested Vectored Interrupt Controller.
13 * It is compiled in two ways:
14 * (1) as a standalone file to produce a sysbus device which is a GIC
15 * that can be used on the realview board and as one of the builtin
16 * private peripherals for the ARM MP CPUs (11MPCore, A9, etc)
17 * (2) by being directly #included into armv7m_nvic.c to produce the
21 #include "qemu/osdep.h"
22 #include "hw/sysbus.h"
23 #include "gic_internal.h"
24 #include "qapi/error.h"
32 #define DPRINTF(fmt, ...) \
33 do { fprintf(stderr, "arm_gic: " fmt , ## __VA_ARGS__); } while (0)
35 #define DPRINTF(fmt, ...) do {} while(0)
38 static const uint8_t gic_id_11mpcore
[] = {
39 0x00, 0x00, 0x00, 0x00, 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1
42 static const uint8_t gic_id_gicv1
[] = {
43 0x04, 0x00, 0x00, 0x00, 0x90, 0xb3, 0x1b, 0x00, 0x0d, 0xf0, 0x05, 0xb1
46 static const uint8_t gic_id_gicv2
[] = {
47 0x04, 0x00, 0x00, 0x00, 0x90, 0xb4, 0x2b, 0x00, 0x0d, 0xf0, 0x05, 0xb1
50 static inline int gic_get_current_cpu(GICState
*s
)
53 return current_cpu
->cpu_index
;
58 /* Return true if this GIC config has interrupt groups, which is
59 * true if we're a GICv2, or a GICv1 with the security extensions.
61 static inline bool gic_has_groups(GICState
*s
)
63 return s
->revision
== 2 || s
->security_extn
;
66 /* TODO: Many places that call this routine could be optimized. */
67 /* Update interrupt status after enabled or pending bits have been changed. */
68 void gic_update(GICState
*s
)
73 int irq_level
, fiq_level
;
77 for (cpu
= 0; cpu
< s
->num_cpu
; cpu
++) {
79 s
->current_pending
[cpu
] = 1023;
80 if (!(s
->ctlr
& (GICD_CTLR_EN_GRP0
| GICD_CTLR_EN_GRP1
))
81 || !(s
->cpu_ctlr
[cpu
] & (GICC_CTLR_EN_GRP0
| GICC_CTLR_EN_GRP1
))) {
82 qemu_irq_lower(s
->parent_irq
[cpu
]);
83 qemu_irq_lower(s
->parent_fiq
[cpu
]);
88 for (irq
= 0; irq
< s
->num_irq
; irq
++) {
89 if (GIC_TEST_ENABLED(irq
, cm
) && gic_test_pending(s
, irq
, cm
) &&
90 (irq
< GIC_INTERNAL
|| GIC_TARGET(irq
) & cm
)) {
91 if (GIC_GET_PRIORITY(irq
, cpu
) < best_prio
) {
92 best_prio
= GIC_GET_PRIORITY(irq
, cpu
);
98 if (best_irq
!= 1023) {
99 trace_gic_update_bestirq(cpu
, best_irq
, best_prio
,
100 s
->priority_mask
[cpu
], s
->running_priority
[cpu
]);
103 irq_level
= fiq_level
= 0;
105 if (best_prio
< s
->priority_mask
[cpu
]) {
106 s
->current_pending
[cpu
] = best_irq
;
107 if (best_prio
< s
->running_priority
[cpu
]) {
108 int group
= GIC_TEST_GROUP(best_irq
, cm
);
110 if (extract32(s
->ctlr
, group
, 1) &&
111 extract32(s
->cpu_ctlr
[cpu
], group
, 1)) {
112 if (group
== 0 && s
->cpu_ctlr
[cpu
] & GICC_CTLR_FIQ_EN
) {
113 DPRINTF("Raised pending FIQ %d (cpu %d)\n",
116 trace_gic_update_set_irq(cpu
, "fiq", fiq_level
);
118 DPRINTF("Raised pending IRQ %d (cpu %d)\n",
121 trace_gic_update_set_irq(cpu
, "irq", irq_level
);
127 qemu_set_irq(s
->parent_irq
[cpu
], irq_level
);
128 qemu_set_irq(s
->parent_fiq
[cpu
], fiq_level
);
132 void gic_set_pending_private(GICState
*s
, int cpu
, int irq
)
136 if (gic_test_pending(s
, irq
, cm
)) {
140 DPRINTF("Set %d pending cpu %d\n", irq
, cpu
);
141 GIC_SET_PENDING(irq
, cm
);
145 static void gic_set_irq_11mpcore(GICState
*s
, int irq
, int level
,
149 GIC_SET_LEVEL(irq
, cm
);
150 if (GIC_TEST_EDGE_TRIGGER(irq
) || GIC_TEST_ENABLED(irq
, cm
)) {
151 DPRINTF("Set %d pending mask %x\n", irq
, target
);
152 GIC_SET_PENDING(irq
, target
);
155 GIC_CLEAR_LEVEL(irq
, cm
);
159 static void gic_set_irq_nvic(GICState
*s
, int irq
, int level
,
163 GIC_SET_LEVEL(irq
, cm
);
164 GIC_SET_PENDING(irq
, target
);
166 GIC_CLEAR_LEVEL(irq
, cm
);
170 static void gic_set_irq_generic(GICState
*s
, int irq
, int level
,
174 GIC_SET_LEVEL(irq
, cm
);
175 DPRINTF("Set %d pending mask %x\n", irq
, target
);
176 if (GIC_TEST_EDGE_TRIGGER(irq
)) {
177 GIC_SET_PENDING(irq
, target
);
180 GIC_CLEAR_LEVEL(irq
, cm
);
184 /* Process a change in an external IRQ input. */
185 static void gic_set_irq(void *opaque
, int irq
, int level
)
187 /* Meaning of the 'irq' parameter:
188 * [0..N-1] : external interrupts
189 * [N..N+31] : PPI (internal) interrupts for CPU 0
190 * [N+32..N+63] : PPI (internal interrupts for CPU 1
193 GICState
*s
= (GICState
*)opaque
;
195 if (irq
< (s
->num_irq
- GIC_INTERNAL
)) {
196 /* The first external input line is internal interrupt 32. */
199 target
= GIC_TARGET(irq
);
202 irq
-= (s
->num_irq
- GIC_INTERNAL
);
203 cpu
= irq
/ GIC_INTERNAL
;
209 assert(irq
>= GIC_NR_SGIS
);
211 if (level
== GIC_TEST_LEVEL(irq
, cm
)) {
215 if (s
->revision
== REV_11MPCORE
) {
216 gic_set_irq_11mpcore(s
, irq
, level
, cm
, target
);
217 } else if (s
->revision
== REV_NVIC
) {
218 gic_set_irq_nvic(s
, irq
, level
, cm
, target
);
220 gic_set_irq_generic(s
, irq
, level
, cm
, target
);
222 trace_gic_set_irq(irq
, level
, cm
, target
);
227 static uint16_t gic_get_current_pending_irq(GICState
*s
, int cpu
,
230 uint16_t pending_irq
= s
->current_pending
[cpu
];
232 if (pending_irq
< GIC_MAXIRQ
&& gic_has_groups(s
)) {
233 int group
= GIC_TEST_GROUP(pending_irq
, (1 << cpu
));
234 /* On a GIC without the security extensions, reading this register
235 * behaves in the same way as a secure access to a GIC with them.
237 bool secure
= !s
->security_extn
|| attrs
.secure
;
239 if (group
== 0 && !secure
) {
240 /* Group0 interrupts hidden from Non-secure access */
243 if (group
== 1 && secure
&& !(s
->cpu_ctlr
[cpu
] & GICC_CTLR_ACK_CTL
)) {
244 /* Group1 interrupts only seen by Secure access if
253 static int gic_get_group_priority(GICState
*s
, int cpu
, int irq
)
255 /* Return the group priority of the specified interrupt
256 * (which is the top bits of its priority, with the number
257 * of bits masked determined by the applicable binary point register).
262 if (gic_has_groups(s
) &&
263 !(s
->cpu_ctlr
[cpu
] & GICC_CTLR_CBPR
) &&
264 GIC_TEST_GROUP(irq
, (1 << cpu
))) {
270 /* a BPR of 0 means the group priority bits are [7:1];
271 * a BPR of 1 means they are [7:2], and so on down to
272 * a BPR of 7 meaning no group priority bits at all.
274 mask
= ~0U << ((bpr
& 7) + 1);
276 return GIC_GET_PRIORITY(irq
, cpu
) & mask
;
279 static void gic_activate_irq(GICState
*s
, int cpu
, int irq
)
281 /* Set the appropriate Active Priority Register bit for this IRQ,
282 * and update the running priority.
284 int prio
= gic_get_group_priority(s
, cpu
, irq
);
285 int preemption_level
= prio
>> (GIC_MIN_BPR
+ 1);
286 int regno
= preemption_level
/ 32;
287 int bitno
= preemption_level
% 32;
289 if (gic_has_groups(s
) && GIC_TEST_GROUP(irq
, (1 << cpu
))) {
290 s
->nsapr
[regno
][cpu
] |= (1 << bitno
);
292 s
->apr
[regno
][cpu
] |= (1 << bitno
);
295 s
->running_priority
[cpu
] = prio
;
296 GIC_SET_ACTIVE(irq
, 1 << cpu
);
299 static int gic_get_prio_from_apr_bits(GICState
*s
, int cpu
)
301 /* Recalculate the current running priority for this CPU based
302 * on the set bits in the Active Priority Registers.
305 for (i
= 0; i
< GIC_NR_APRS
; i
++) {
306 uint32_t apr
= s
->apr
[i
][cpu
] | s
->nsapr
[i
][cpu
];
310 return (i
* 32 + ctz32(apr
)) << (GIC_MIN_BPR
+ 1);
315 static void gic_drop_prio(GICState
*s
, int cpu
, int group
)
317 /* Drop the priority of the currently active interrupt in the
320 * Note that we can guarantee (because of the requirement to nest
321 * GICC_IAR reads [which activate an interrupt and raise priority]
322 * with GICC_EOIR writes [which drop the priority for the interrupt])
323 * that the interrupt we're being called for is the highest priority
324 * active interrupt, meaning that it has the lowest set bit in the
327 * If the guest does not honour the ordering constraints then the
328 * behaviour of the GIC is UNPREDICTABLE, which for us means that
329 * the values of the APR registers might become incorrect and the
330 * running priority will be wrong, so interrupts that should preempt
331 * might not do so, and interrupts that should not preempt might do so.
335 for (i
= 0; i
< GIC_NR_APRS
; i
++) {
336 uint32_t *papr
= group
? &s
->nsapr
[i
][cpu
] : &s
->apr
[i
][cpu
];
340 /* Clear lowest set bit */
345 s
->running_priority
[cpu
] = gic_get_prio_from_apr_bits(s
, cpu
);
348 uint32_t gic_acknowledge_irq(GICState
*s
, int cpu
, MemTxAttrs attrs
)
353 /* gic_get_current_pending_irq() will return 1022 or 1023 appropriately
354 * for the case where this GIC supports grouping and the pending interrupt
355 * is in the wrong group.
357 irq
= gic_get_current_pending_irq(s
, cpu
, attrs
);
358 trace_gic_acknowledge_irq(cpu
, irq
);
360 if (irq
>= GIC_MAXIRQ
) {
361 DPRINTF("ACK, no pending interrupt or it is hidden: %d\n", irq
);
365 if (GIC_GET_PRIORITY(irq
, cpu
) >= s
->running_priority
[cpu
]) {
366 DPRINTF("ACK, pending interrupt (%d) has insufficient priority\n", irq
);
370 if (s
->revision
== REV_11MPCORE
|| s
->revision
== REV_NVIC
) {
371 /* Clear pending flags for both level and edge triggered interrupts.
372 * Level triggered IRQs will be reasserted once they become inactive.
374 GIC_CLEAR_PENDING(irq
, GIC_TEST_MODEL(irq
) ? ALL_CPU_MASK
: cm
);
377 if (irq
< GIC_NR_SGIS
) {
378 /* Lookup the source CPU for the SGI and clear this in the
379 * sgi_pending map. Return the src and clear the overall pending
380 * state on this CPU if the SGI is not pending from any CPUs.
382 assert(s
->sgi_pending
[irq
][cpu
] != 0);
383 src
= ctz32(s
->sgi_pending
[irq
][cpu
]);
384 s
->sgi_pending
[irq
][cpu
] &= ~(1 << src
);
385 if (s
->sgi_pending
[irq
][cpu
] == 0) {
386 GIC_CLEAR_PENDING(irq
, GIC_TEST_MODEL(irq
) ? ALL_CPU_MASK
: cm
);
388 ret
= irq
| ((src
& 0x7) << 10);
390 /* Clear pending state for both level and edge triggered
391 * interrupts. (level triggered interrupts with an active line
392 * remain pending, see gic_test_pending)
394 GIC_CLEAR_PENDING(irq
, GIC_TEST_MODEL(irq
) ? ALL_CPU_MASK
: cm
);
399 gic_activate_irq(s
, cpu
, irq
);
401 DPRINTF("ACK %d\n", irq
);
405 void gic_set_priority(GICState
*s
, int cpu
, int irq
, uint8_t val
,
408 if (s
->security_extn
&& !attrs
.secure
) {
409 if (!GIC_TEST_GROUP(irq
, (1 << cpu
))) {
410 return; /* Ignore Non-secure access of Group0 IRQ */
412 val
= 0x80 | (val
>> 1); /* Non-secure view */
415 if (irq
< GIC_INTERNAL
) {
416 s
->priority1
[irq
][cpu
] = val
;
418 s
->priority2
[(irq
) - GIC_INTERNAL
] = val
;
422 static uint32_t gic_get_priority(GICState
*s
, int cpu
, int irq
,
425 uint32_t prio
= GIC_GET_PRIORITY(irq
, cpu
);
427 if (s
->security_extn
&& !attrs
.secure
) {
428 if (!GIC_TEST_GROUP(irq
, (1 << cpu
))) {
429 return 0; /* Non-secure access cannot read priority of Group0 IRQ */
431 prio
= (prio
<< 1) & 0xff; /* Non-secure view */
436 static void gic_set_priority_mask(GICState
*s
, int cpu
, uint8_t pmask
,
439 if (s
->security_extn
&& !attrs
.secure
) {
440 if (s
->priority_mask
[cpu
] & 0x80) {
441 /* Priority Mask in upper half */
442 pmask
= 0x80 | (pmask
>> 1);
444 /* Non-secure write ignored if priority mask is in lower half */
448 s
->priority_mask
[cpu
] = pmask
;
451 static uint32_t gic_get_priority_mask(GICState
*s
, int cpu
, MemTxAttrs attrs
)
453 uint32_t pmask
= s
->priority_mask
[cpu
];
455 if (s
->security_extn
&& !attrs
.secure
) {
457 /* Priority Mask in upper half, return Non-secure view */
458 pmask
= (pmask
<< 1) & 0xff;
460 /* Priority Mask in lower half, RAZ */
467 static uint32_t gic_get_cpu_control(GICState
*s
, int cpu
, MemTxAttrs attrs
)
469 uint32_t ret
= s
->cpu_ctlr
[cpu
];
471 if (s
->security_extn
&& !attrs
.secure
) {
472 /* Construct the NS banked view of GICC_CTLR from the correct
473 * bits of the S banked view. We don't need to move the bypass
474 * control bits because we don't implement that (IMPDEF) part
475 * of the GIC architecture.
477 ret
= (ret
& (GICC_CTLR_EN_GRP1
| GICC_CTLR_EOIMODE_NS
)) >> 1;
482 static void gic_set_cpu_control(GICState
*s
, int cpu
, uint32_t value
,
487 if (s
->security_extn
&& !attrs
.secure
) {
488 /* The NS view can only write certain bits in the register;
489 * the rest are unchanged
491 mask
= GICC_CTLR_EN_GRP1
;
492 if (s
->revision
== 2) {
493 mask
|= GICC_CTLR_EOIMODE_NS
;
495 s
->cpu_ctlr
[cpu
] &= ~mask
;
496 s
->cpu_ctlr
[cpu
] |= (value
<< 1) & mask
;
498 if (s
->revision
== 2) {
499 mask
= s
->security_extn
? GICC_CTLR_V2_S_MASK
: GICC_CTLR_V2_MASK
;
501 mask
= s
->security_extn
? GICC_CTLR_V1_S_MASK
: GICC_CTLR_V1_MASK
;
503 s
->cpu_ctlr
[cpu
] = value
& mask
;
505 DPRINTF("CPU Interface %d: Group0 Interrupts %sabled, "
506 "Group1 Interrupts %sabled\n", cpu
,
507 (s
->cpu_ctlr
[cpu
] & GICC_CTLR_EN_GRP0
) ? "En" : "Dis",
508 (s
->cpu_ctlr
[cpu
] & GICC_CTLR_EN_GRP1
) ? "En" : "Dis");
511 static uint8_t gic_get_running_priority(GICState
*s
, int cpu
, MemTxAttrs attrs
)
513 if (s
->security_extn
&& !attrs
.secure
) {
514 if (s
->running_priority
[cpu
] & 0x80) {
515 /* Running priority in upper half of range: return the Non-secure
516 * view of the priority.
518 return s
->running_priority
[cpu
] << 1;
520 /* Running priority in lower half of range: RAZ */
524 return s
->running_priority
[cpu
];
528 /* Return true if we should split priority drop and interrupt deactivation,
529 * ie whether the relevant EOIMode bit is set.
531 static bool gic_eoi_split(GICState
*s
, int cpu
, MemTxAttrs attrs
)
533 if (s
->revision
!= 2) {
534 /* Before GICv2 prio-drop and deactivate are not separable */
537 if (s
->security_extn
&& !attrs
.secure
) {
538 return s
->cpu_ctlr
[cpu
] & GICC_CTLR_EOIMODE_NS
;
540 return s
->cpu_ctlr
[cpu
] & GICC_CTLR_EOIMODE
;
543 static void gic_deactivate_irq(GICState
*s
, int cpu
, int irq
, MemTxAttrs attrs
)
546 int group
= gic_has_groups(s
) && GIC_TEST_GROUP(irq
, cm
);
548 if (!gic_eoi_split(s
, cpu
, attrs
)) {
549 /* This is UNPREDICTABLE; we choose to ignore it */
550 qemu_log_mask(LOG_GUEST_ERROR
,
551 "gic_deactivate_irq: GICC_DIR write when EOIMode clear");
555 if (s
->security_extn
&& !attrs
.secure
&& !group
) {
556 DPRINTF("Non-secure DI for Group0 interrupt %d ignored\n", irq
);
560 GIC_CLEAR_ACTIVE(irq
, cm
);
563 void gic_complete_irq(GICState
*s
, int cpu
, int irq
, MemTxAttrs attrs
)
568 DPRINTF("EOI %d\n", irq
);
569 if (irq
>= s
->num_irq
) {
570 /* This handles two cases:
571 * 1. If software writes the ID of a spurious interrupt [ie 1023]
572 * to the GICC_EOIR, the GIC ignores that write.
573 * 2. If software writes the number of a non-existent interrupt
574 * this must be a subcase of "value written does not match the last
575 * valid interrupt value read from the Interrupt Acknowledge
576 * register" and so this is UNPREDICTABLE. We choose to ignore it.
580 if (s
->running_priority
[cpu
] == 0x100) {
581 return; /* No active IRQ. */
584 if (s
->revision
== REV_11MPCORE
) {
585 /* Mark level triggered interrupts as pending if they are still
587 if (!GIC_TEST_EDGE_TRIGGER(irq
) && GIC_TEST_ENABLED(irq
, cm
)
588 && GIC_TEST_LEVEL(irq
, cm
) && (GIC_TARGET(irq
) & cm
) != 0) {
589 DPRINTF("Set %d pending mask %x\n", irq
, cm
);
590 GIC_SET_PENDING(irq
, cm
);
592 } else if (s
->revision
== REV_NVIC
) {
593 if (GIC_TEST_LEVEL(irq
, cm
)) {
594 DPRINTF("Set nvic %d pending mask %x\n", irq
, cm
);
595 GIC_SET_PENDING(irq
, cm
);
599 group
= gic_has_groups(s
) && GIC_TEST_GROUP(irq
, cm
);
601 if (s
->security_extn
&& !attrs
.secure
&& !group
) {
602 DPRINTF("Non-secure EOI for Group0 interrupt %d ignored\n", irq
);
606 /* Secure EOI with GICC_CTLR.AckCtl == 0 when the IRQ is a Group 1
607 * interrupt is UNPREDICTABLE. We choose to handle it as if AckCtl == 1,
608 * i.e. go ahead and complete the irq anyway.
611 gic_drop_prio(s
, cpu
, group
);
613 /* In GICv2 the guest can choose to split priority-drop and deactivate */
614 if (!gic_eoi_split(s
, cpu
, attrs
)) {
615 GIC_CLEAR_ACTIVE(irq
, cm
);
620 static uint32_t gic_dist_readb(void *opaque
, hwaddr offset
, MemTxAttrs attrs
)
622 GICState
*s
= (GICState
*)opaque
;
630 cpu
= gic_get_current_cpu(s
);
632 if (offset
< 0x100) {
633 if (offset
== 0) { /* GICD_CTLR */
634 if (s
->security_extn
&& !attrs
.secure
) {
635 /* The NS bank of this register is just an alias of the
636 * EnableGrp1 bit in the S bank version.
638 return extract32(s
->ctlr
, 1, 1);
644 /* Interrupt Controller Type Register */
645 return ((s
->num_irq
/ 32) - 1)
646 | ((s
->num_cpu
- 1) << 5)
647 | (s
->security_extn
<< 10);
650 if (offset
>= 0x80) {
651 /* Interrupt Group Registers: these RAZ/WI if this is an NS
652 * access to a GIC with the security extensions, or if the GIC
653 * doesn't have groups at all.
656 if (!(s
->security_extn
&& !attrs
.secure
) && gic_has_groups(s
)) {
657 /* Every byte offset holds 8 group status bits */
658 irq
= (offset
- 0x080) * 8 + GIC_BASE_IRQ
;
659 if (irq
>= s
->num_irq
) {
662 for (i
= 0; i
< 8; i
++) {
663 if (GIC_TEST_GROUP(irq
+ i
, cm
)) {
671 } else if (offset
< 0x200) {
672 /* Interrupt Set/Clear Enable. */
674 irq
= (offset
- 0x100) * 8;
676 irq
= (offset
- 0x180) * 8;
678 if (irq
>= s
->num_irq
)
681 for (i
= 0; i
< 8; i
++) {
682 if (s
->security_extn
&& !attrs
.secure
&&
683 !GIC_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
684 continue; /* Ignore Non-secure access of Group0 IRQ */
687 if (GIC_TEST_ENABLED(irq
+ i
, cm
)) {
691 } else if (offset
< 0x300) {
692 /* Interrupt Set/Clear Pending. */
694 irq
= (offset
- 0x200) * 8;
696 irq
= (offset
- 0x280) * 8;
698 if (irq
>= s
->num_irq
)
701 mask
= (irq
< GIC_INTERNAL
) ? cm
: ALL_CPU_MASK
;
702 for (i
= 0; i
< 8; i
++) {
703 if (s
->security_extn
&& !attrs
.secure
&&
704 !GIC_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
705 continue; /* Ignore Non-secure access of Group0 IRQ */
708 if (gic_test_pending(s
, irq
+ i
, mask
)) {
712 } else if (offset
< 0x400) {
713 /* Interrupt Active. */
714 irq
= (offset
- 0x300) * 8 + GIC_BASE_IRQ
;
715 if (irq
>= s
->num_irq
)
718 mask
= (irq
< GIC_INTERNAL
) ? cm
: ALL_CPU_MASK
;
719 for (i
= 0; i
< 8; i
++) {
720 if (s
->security_extn
&& !attrs
.secure
&&
721 !GIC_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
722 continue; /* Ignore Non-secure access of Group0 IRQ */
725 if (GIC_TEST_ACTIVE(irq
+ i
, mask
)) {
729 } else if (offset
< 0x800) {
730 /* Interrupt Priority. */
731 irq
= (offset
- 0x400) + GIC_BASE_IRQ
;
732 if (irq
>= s
->num_irq
)
734 res
= gic_get_priority(s
, cpu
, irq
, attrs
);
735 } else if (offset
< 0xc00) {
736 /* Interrupt CPU Target. */
737 if (s
->num_cpu
== 1 && s
->revision
!= REV_11MPCORE
) {
738 /* For uniprocessor GICs these RAZ/WI */
741 irq
= (offset
- 0x800) + GIC_BASE_IRQ
;
742 if (irq
>= s
->num_irq
) {
745 if (irq
>= 29 && irq
<= 31) {
748 res
= GIC_TARGET(irq
);
751 } else if (offset
< 0xf00) {
752 /* Interrupt Configuration. */
753 irq
= (offset
- 0xc00) * 4 + GIC_BASE_IRQ
;
754 if (irq
>= s
->num_irq
)
757 for (i
= 0; i
< 4; i
++) {
758 if (s
->security_extn
&& !attrs
.secure
&&
759 !GIC_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
760 continue; /* Ignore Non-secure access of Group0 IRQ */
763 if (GIC_TEST_MODEL(irq
+ i
))
764 res
|= (1 << (i
* 2));
765 if (GIC_TEST_EDGE_TRIGGER(irq
+ i
))
766 res
|= (2 << (i
* 2));
768 } else if (offset
< 0xf10) {
770 } else if (offset
< 0xf30) {
771 if (s
->revision
== REV_11MPCORE
|| s
->revision
== REV_NVIC
) {
775 if (offset
< 0xf20) {
776 /* GICD_CPENDSGIRn */
777 irq
= (offset
- 0xf10);
779 irq
= (offset
- 0xf20);
780 /* GICD_SPENDSGIRn */
783 if (s
->security_extn
&& !attrs
.secure
&&
784 !GIC_TEST_GROUP(irq
, 1 << cpu
)) {
785 res
= 0; /* Ignore Non-secure access of Group0 IRQ */
787 res
= s
->sgi_pending
[irq
][cpu
];
789 } else if (offset
< 0xfd0) {
791 } else if (offset
< 0x1000) {
795 switch (s
->revision
) {
797 res
= gic_id_11mpcore
[(offset
- 0xfd0) >> 2];
800 res
= gic_id_gicv1
[(offset
- 0xfd0) >> 2];
803 res
= gic_id_gicv2
[(offset
- 0xfd0) >> 2];
806 /* Shouldn't be able to get here */
813 g_assert_not_reached();
817 qemu_log_mask(LOG_GUEST_ERROR
,
818 "gic_dist_readb: Bad offset %x\n", (int)offset
);
822 static MemTxResult
gic_dist_read(void *opaque
, hwaddr offset
, uint64_t *data
,
823 unsigned size
, MemTxAttrs attrs
)
827 *data
= gic_dist_readb(opaque
, offset
, attrs
);
830 *data
= gic_dist_readb(opaque
, offset
, attrs
);
831 *data
|= gic_dist_readb(opaque
, offset
+ 1, attrs
) << 8;
834 *data
= gic_dist_readb(opaque
, offset
, attrs
);
835 *data
|= gic_dist_readb(opaque
, offset
+ 1, attrs
) << 8;
836 *data
|= gic_dist_readb(opaque
, offset
+ 2, attrs
) << 16;
837 *data
|= gic_dist_readb(opaque
, offset
+ 3, attrs
) << 24;
844 static void gic_dist_writeb(void *opaque
, hwaddr offset
,
845 uint32_t value
, MemTxAttrs attrs
)
847 GICState
*s
= (GICState
*)opaque
;
852 cpu
= gic_get_current_cpu(s
);
853 if (offset
< 0x100) {
855 if (s
->security_extn
&& !attrs
.secure
) {
856 /* NS version is just an alias of the S version's bit 1 */
857 s
->ctlr
= deposit32(s
->ctlr
, 1, 1, value
);
858 } else if (gic_has_groups(s
)) {
859 s
->ctlr
= value
& (GICD_CTLR_EN_GRP0
| GICD_CTLR_EN_GRP1
);
861 s
->ctlr
= value
& GICD_CTLR_EN_GRP0
;
863 DPRINTF("Distributor: Group0 %sabled; Group 1 %sabled\n",
864 s
->ctlr
& GICD_CTLR_EN_GRP0
? "En" : "Dis",
865 s
->ctlr
& GICD_CTLR_EN_GRP1
? "En" : "Dis");
866 } else if (offset
< 4) {
868 } else if (offset
>= 0x80) {
869 /* Interrupt Group Registers: RAZ/WI for NS access to secure
870 * GIC, or for GICs without groups.
872 if (!(s
->security_extn
&& !attrs
.secure
) && gic_has_groups(s
)) {
873 /* Every byte offset holds 8 group status bits */
874 irq
= (offset
- 0x80) * 8 + GIC_BASE_IRQ
;
875 if (irq
>= s
->num_irq
) {
878 for (i
= 0; i
< 8; i
++) {
879 /* Group bits are banked for private interrupts */
880 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
881 if (value
& (1 << i
)) {
882 /* Group1 (Non-secure) */
883 GIC_SET_GROUP(irq
+ i
, cm
);
885 /* Group0 (Secure) */
886 GIC_CLEAR_GROUP(irq
+ i
, cm
);
893 } else if (offset
< 0x180) {
894 /* Interrupt Set Enable. */
895 irq
= (offset
- 0x100) * 8 + GIC_BASE_IRQ
;
896 if (irq
>= s
->num_irq
)
898 if (irq
< GIC_NR_SGIS
) {
902 for (i
= 0; i
< 8; i
++) {
903 if (value
& (1 << i
)) {
905 (irq
< GIC_INTERNAL
) ? (1 << cpu
) : GIC_TARGET(irq
+ i
);
906 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
908 if (s
->security_extn
&& !attrs
.secure
&&
909 !GIC_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
910 continue; /* Ignore Non-secure access of Group0 IRQ */
913 if (!GIC_TEST_ENABLED(irq
+ i
, cm
)) {
914 DPRINTF("Enabled IRQ %d\n", irq
+ i
);
915 trace_gic_enable_irq(irq
+ i
);
917 GIC_SET_ENABLED(irq
+ i
, cm
);
918 /* If a raised level triggered IRQ enabled then mark
920 if (GIC_TEST_LEVEL(irq
+ i
, mask
)
921 && !GIC_TEST_EDGE_TRIGGER(irq
+ i
)) {
922 DPRINTF("Set %d pending mask %x\n", irq
+ i
, mask
);
923 GIC_SET_PENDING(irq
+ i
, mask
);
927 } else if (offset
< 0x200) {
928 /* Interrupt Clear Enable. */
929 irq
= (offset
- 0x180) * 8 + GIC_BASE_IRQ
;
930 if (irq
>= s
->num_irq
)
932 if (irq
< GIC_NR_SGIS
) {
936 for (i
= 0; i
< 8; i
++) {
937 if (value
& (1 << i
)) {
938 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
940 if (s
->security_extn
&& !attrs
.secure
&&
941 !GIC_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
942 continue; /* Ignore Non-secure access of Group0 IRQ */
945 if (GIC_TEST_ENABLED(irq
+ i
, cm
)) {
946 DPRINTF("Disabled IRQ %d\n", irq
+ i
);
947 trace_gic_disable_irq(irq
+ i
);
949 GIC_CLEAR_ENABLED(irq
+ i
, cm
);
952 } else if (offset
< 0x280) {
953 /* Interrupt Set Pending. */
954 irq
= (offset
- 0x200) * 8 + GIC_BASE_IRQ
;
955 if (irq
>= s
->num_irq
)
957 if (irq
< GIC_NR_SGIS
) {
961 for (i
= 0; i
< 8; i
++) {
962 if (value
& (1 << i
)) {
963 if (s
->security_extn
&& !attrs
.secure
&&
964 !GIC_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
965 continue; /* Ignore Non-secure access of Group0 IRQ */
968 GIC_SET_PENDING(irq
+ i
, GIC_TARGET(irq
+ i
));
971 } else if (offset
< 0x300) {
972 /* Interrupt Clear Pending. */
973 irq
= (offset
- 0x280) * 8 + GIC_BASE_IRQ
;
974 if (irq
>= s
->num_irq
)
976 if (irq
< GIC_NR_SGIS
) {
980 for (i
= 0; i
< 8; i
++) {
981 if (s
->security_extn
&& !attrs
.secure
&&
982 !GIC_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
983 continue; /* Ignore Non-secure access of Group0 IRQ */
986 /* ??? This currently clears the pending bit for all CPUs, even
987 for per-CPU interrupts. It's unclear whether this is the
989 if (value
& (1 << i
)) {
990 GIC_CLEAR_PENDING(irq
+ i
, ALL_CPU_MASK
);
993 } else if (offset
< 0x400) {
994 /* Interrupt Active. */
996 } else if (offset
< 0x800) {
997 /* Interrupt Priority. */
998 irq
= (offset
- 0x400) + GIC_BASE_IRQ
;
999 if (irq
>= s
->num_irq
)
1001 gic_set_priority(s
, cpu
, irq
, value
, attrs
);
1002 } else if (offset
< 0xc00) {
1003 /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the
1004 * annoying exception of the 11MPCore's GIC.
1006 if (s
->num_cpu
!= 1 || s
->revision
== REV_11MPCORE
) {
1007 irq
= (offset
- 0x800) + GIC_BASE_IRQ
;
1008 if (irq
>= s
->num_irq
) {
1013 } else if (irq
< GIC_INTERNAL
) {
1014 value
= ALL_CPU_MASK
;
1016 s
->irq_target
[irq
] = value
& ALL_CPU_MASK
;
1018 } else if (offset
< 0xf00) {
1019 /* Interrupt Configuration. */
1020 irq
= (offset
- 0xc00) * 4 + GIC_BASE_IRQ
;
1021 if (irq
>= s
->num_irq
)
1023 if (irq
< GIC_NR_SGIS
)
1025 for (i
= 0; i
< 4; i
++) {
1026 if (s
->security_extn
&& !attrs
.secure
&&
1027 !GIC_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1028 continue; /* Ignore Non-secure access of Group0 IRQ */
1031 if (s
->revision
== REV_11MPCORE
|| s
->revision
== REV_NVIC
) {
1032 if (value
& (1 << (i
* 2))) {
1033 GIC_SET_MODEL(irq
+ i
);
1035 GIC_CLEAR_MODEL(irq
+ i
);
1038 if (value
& (2 << (i
* 2))) {
1039 GIC_SET_EDGE_TRIGGER(irq
+ i
);
1041 GIC_CLEAR_EDGE_TRIGGER(irq
+ i
);
1044 } else if (offset
< 0xf10) {
1045 /* 0xf00 is only handled for 32-bit writes. */
1047 } else if (offset
< 0xf20) {
1048 /* GICD_CPENDSGIRn */
1049 if (s
->revision
== REV_11MPCORE
|| s
->revision
== REV_NVIC
) {
1052 irq
= (offset
- 0xf10);
1054 if (!s
->security_extn
|| attrs
.secure
||
1055 GIC_TEST_GROUP(irq
, 1 << cpu
)) {
1056 s
->sgi_pending
[irq
][cpu
] &= ~value
;
1057 if (s
->sgi_pending
[irq
][cpu
] == 0) {
1058 GIC_CLEAR_PENDING(irq
, 1 << cpu
);
1061 } else if (offset
< 0xf30) {
1062 /* GICD_SPENDSGIRn */
1063 if (s
->revision
== REV_11MPCORE
|| s
->revision
== REV_NVIC
) {
1066 irq
= (offset
- 0xf20);
1068 if (!s
->security_extn
|| attrs
.secure
||
1069 GIC_TEST_GROUP(irq
, 1 << cpu
)) {
1070 GIC_SET_PENDING(irq
, 1 << cpu
);
1071 s
->sgi_pending
[irq
][cpu
] |= value
;
1079 qemu_log_mask(LOG_GUEST_ERROR
,
1080 "gic_dist_writeb: Bad offset %x\n", (int)offset
);
1083 static void gic_dist_writew(void *opaque
, hwaddr offset
,
1084 uint32_t value
, MemTxAttrs attrs
)
1086 gic_dist_writeb(opaque
, offset
, value
& 0xff, attrs
);
1087 gic_dist_writeb(opaque
, offset
+ 1, value
>> 8, attrs
);
1090 static void gic_dist_writel(void *opaque
, hwaddr offset
,
1091 uint32_t value
, MemTxAttrs attrs
)
1093 GICState
*s
= (GICState
*)opaque
;
1094 if (offset
== 0xf00) {
1100 cpu
= gic_get_current_cpu(s
);
1101 irq
= value
& 0x3ff;
1102 switch ((value
>> 24) & 3) {
1104 mask
= (value
>> 16) & ALL_CPU_MASK
;
1107 mask
= ALL_CPU_MASK
^ (1 << cpu
);
1113 DPRINTF("Bad Soft Int target filter\n");
1114 mask
= ALL_CPU_MASK
;
1117 GIC_SET_PENDING(irq
, mask
);
1118 target_cpu
= ctz32(mask
);
1119 while (target_cpu
< GIC_NCPU
) {
1120 s
->sgi_pending
[irq
][target_cpu
] |= (1 << cpu
);
1121 mask
&= ~(1 << target_cpu
);
1122 target_cpu
= ctz32(mask
);
1127 gic_dist_writew(opaque
, offset
, value
& 0xffff, attrs
);
1128 gic_dist_writew(opaque
, offset
+ 2, value
>> 16, attrs
);
1131 static MemTxResult
gic_dist_write(void *opaque
, hwaddr offset
, uint64_t data
,
1132 unsigned size
, MemTxAttrs attrs
)
1136 gic_dist_writeb(opaque
, offset
, data
, attrs
);
1139 gic_dist_writew(opaque
, offset
, data
, attrs
);
1142 gic_dist_writel(opaque
, offset
, data
, attrs
);
1149 static inline uint32_t gic_apr_ns_view(GICState
*s
, int cpu
, int regno
)
1151 /* Return the Nonsecure view of GICC_APR<regno>. This is the
1152 * second half of GICC_NSAPR.
1154 switch (GIC_MIN_BPR
) {
1157 return s
->nsapr
[regno
+ 2][cpu
];
1162 return s
->nsapr
[regno
+ 1][cpu
];
1167 return extract32(s
->nsapr
[0][cpu
], 16, 16);
1172 return extract32(s
->nsapr
[0][cpu
], 8, 8);
1176 g_assert_not_reached();
1181 static inline void gic_apr_write_ns_view(GICState
*s
, int cpu
, int regno
,
1184 /* Write the Nonsecure view of GICC_APR<regno>. */
1185 switch (GIC_MIN_BPR
) {
1188 s
->nsapr
[regno
+ 2][cpu
] = value
;
1193 s
->nsapr
[regno
+ 1][cpu
] = value
;
1198 s
->nsapr
[0][cpu
] = deposit32(s
->nsapr
[0][cpu
], 16, 16, value
);
1203 s
->nsapr
[0][cpu
] = deposit32(s
->nsapr
[0][cpu
], 8, 8, value
);
1207 g_assert_not_reached();
1211 static MemTxResult
gic_cpu_read(GICState
*s
, int cpu
, int offset
,
1212 uint64_t *data
, MemTxAttrs attrs
)
1215 case 0x00: /* Control */
1216 *data
= gic_get_cpu_control(s
, cpu
, attrs
);
1218 case 0x04: /* Priority mask */
1219 *data
= gic_get_priority_mask(s
, cpu
, attrs
);
1221 case 0x08: /* Binary Point */
1222 if (s
->security_extn
&& !attrs
.secure
) {
1223 /* BPR is banked. Non-secure copy stored in ABPR. */
1224 *data
= s
->abpr
[cpu
];
1226 *data
= s
->bpr
[cpu
];
1229 case 0x0c: /* Acknowledge */
1230 *data
= gic_acknowledge_irq(s
, cpu
, attrs
);
1232 case 0x14: /* Running Priority */
1233 *data
= gic_get_running_priority(s
, cpu
, attrs
);
1235 case 0x18: /* Highest Pending Interrupt */
1236 *data
= gic_get_current_pending_irq(s
, cpu
, attrs
);
1238 case 0x1c: /* Aliased Binary Point */
1239 /* GIC v2, no security: ABPR
1240 * GIC v1, no security: not implemented (RAZ/WI)
1241 * With security extensions, secure access: ABPR (alias of NS BPR)
1242 * With security extensions, nonsecure access: RAZ/WI
1244 if (!gic_has_groups(s
) || (s
->security_extn
&& !attrs
.secure
)) {
1247 *data
= s
->abpr
[cpu
];
1250 case 0xd0: case 0xd4: case 0xd8: case 0xdc:
1252 int regno
= (offset
- 0xd0) / 4;
1254 if (regno
>= GIC_NR_APRS
|| s
->revision
!= 2) {
1256 } else if (s
->security_extn
&& !attrs
.secure
) {
1257 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */
1258 *data
= gic_apr_ns_view(s
, regno
, cpu
);
1260 *data
= s
->apr
[regno
][cpu
];
1264 case 0xe0: case 0xe4: case 0xe8: case 0xec:
1266 int regno
= (offset
- 0xe0) / 4;
1268 if (regno
>= GIC_NR_APRS
|| s
->revision
!= 2 || !gic_has_groups(s
) ||
1269 (s
->security_extn
&& !attrs
.secure
)) {
1272 *data
= s
->nsapr
[regno
][cpu
];
1277 qemu_log_mask(LOG_GUEST_ERROR
,
1278 "gic_cpu_read: Bad offset %x\n", (int)offset
);
1284 static MemTxResult
gic_cpu_write(GICState
*s
, int cpu
, int offset
,
1285 uint32_t value
, MemTxAttrs attrs
)
1288 case 0x00: /* Control */
1289 gic_set_cpu_control(s
, cpu
, value
, attrs
);
1291 case 0x04: /* Priority mask */
1292 gic_set_priority_mask(s
, cpu
, value
, attrs
);
1294 case 0x08: /* Binary Point */
1295 if (s
->security_extn
&& !attrs
.secure
) {
1296 s
->abpr
[cpu
] = MAX(value
& 0x7, GIC_MIN_ABPR
);
1298 s
->bpr
[cpu
] = MAX(value
& 0x7, GIC_MIN_BPR
);
1301 case 0x10: /* End Of Interrupt */
1302 gic_complete_irq(s
, cpu
, value
& 0x3ff, attrs
);
1304 case 0x1c: /* Aliased Binary Point */
1305 if (!gic_has_groups(s
) || (s
->security_extn
&& !attrs
.secure
)) {
1306 /* unimplemented, or NS access: RAZ/WI */
1309 s
->abpr
[cpu
] = MAX(value
& 0x7, GIC_MIN_ABPR
);
1312 case 0xd0: case 0xd4: case 0xd8: case 0xdc:
1314 int regno
= (offset
- 0xd0) / 4;
1316 if (regno
>= GIC_NR_APRS
|| s
->revision
!= 2) {
1319 if (s
->security_extn
&& !attrs
.secure
) {
1320 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */
1321 gic_apr_write_ns_view(s
, regno
, cpu
, value
);
1323 s
->apr
[regno
][cpu
] = value
;
1327 case 0xe0: case 0xe4: case 0xe8: case 0xec:
1329 int regno
= (offset
- 0xe0) / 4;
1331 if (regno
>= GIC_NR_APRS
|| s
->revision
!= 2) {
1334 if (!gic_has_groups(s
) || (s
->security_extn
&& !attrs
.secure
)) {
1337 s
->nsapr
[regno
][cpu
] = value
;
1342 gic_deactivate_irq(s
, cpu
, value
& 0x3ff, attrs
);
1345 qemu_log_mask(LOG_GUEST_ERROR
,
1346 "gic_cpu_write: Bad offset %x\n", (int)offset
);
1353 /* Wrappers to read/write the GIC CPU interface for the current CPU */
1354 static MemTxResult
gic_thiscpu_read(void *opaque
, hwaddr addr
, uint64_t *data
,
1355 unsigned size
, MemTxAttrs attrs
)
1357 GICState
*s
= (GICState
*)opaque
;
1358 return gic_cpu_read(s
, gic_get_current_cpu(s
), addr
, data
, attrs
);
1361 static MemTxResult
gic_thiscpu_write(void *opaque
, hwaddr addr
,
1362 uint64_t value
, unsigned size
,
1365 GICState
*s
= (GICState
*)opaque
;
1366 return gic_cpu_write(s
, gic_get_current_cpu(s
), addr
, value
, attrs
);
1369 /* Wrappers to read/write the GIC CPU interface for a specific CPU.
1370 * These just decode the opaque pointer into GICState* + cpu id.
1372 static MemTxResult
gic_do_cpu_read(void *opaque
, hwaddr addr
, uint64_t *data
,
1373 unsigned size
, MemTxAttrs attrs
)
1375 GICState
**backref
= (GICState
**)opaque
;
1376 GICState
*s
= *backref
;
1377 int id
= (backref
- s
->backref
);
1378 return gic_cpu_read(s
, id
, addr
, data
, attrs
);
1381 static MemTxResult
gic_do_cpu_write(void *opaque
, hwaddr addr
,
1382 uint64_t value
, unsigned size
,
1385 GICState
**backref
= (GICState
**)opaque
;
1386 GICState
*s
= *backref
;
1387 int id
= (backref
- s
->backref
);
1388 return gic_cpu_write(s
, id
, addr
, value
, attrs
);
1391 static const MemoryRegionOps gic_ops
[2] = {
1393 .read_with_attrs
= gic_dist_read
,
1394 .write_with_attrs
= gic_dist_write
,
1395 .endianness
= DEVICE_NATIVE_ENDIAN
,
1398 .read_with_attrs
= gic_thiscpu_read
,
1399 .write_with_attrs
= gic_thiscpu_write
,
1400 .endianness
= DEVICE_NATIVE_ENDIAN
,
1404 static const MemoryRegionOps gic_cpu_ops
= {
1405 .read_with_attrs
= gic_do_cpu_read
,
1406 .write_with_attrs
= gic_do_cpu_write
,
1407 .endianness
= DEVICE_NATIVE_ENDIAN
,
1410 /* This function is used by nvic model */
1411 void gic_init_irqs_and_distributor(GICState
*s
)
1413 gic_init_irqs_and_mmio(s
, gic_set_irq
, gic_ops
);
1416 static void arm_gic_realize(DeviceState
*dev
, Error
**errp
)
1418 /* Device instance realize function for the GIC sysbus device */
1420 GICState
*s
= ARM_GIC(dev
);
1421 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
1422 ARMGICClass
*agc
= ARM_GIC_GET_CLASS(s
);
1423 Error
*local_err
= NULL
;
1425 agc
->parent_realize(dev
, &local_err
);
1427 error_propagate(errp
, local_err
);
1431 /* This creates distributor and main CPU interface (s->cpuiomem[0]) */
1432 gic_init_irqs_and_mmio(s
, gic_set_irq
, gic_ops
);
1434 /* Extra core-specific regions for the CPU interfaces. This is
1435 * necessary for "franken-GIC" implementations, for example on
1437 * NB that the memory region size of 0x100 applies for the 11MPCore
1438 * and also cores following the GIC v1 spec (ie A9).
1439 * GIC v2 defines a larger memory region (0x1000) so this will need
1440 * to be extended when we implement A15.
1442 for (i
= 0; i
< s
->num_cpu
; i
++) {
1444 memory_region_init_io(&s
->cpuiomem
[i
+1], OBJECT(s
), &gic_cpu_ops
,
1445 &s
->backref
[i
], "gic_cpu", 0x100);
1446 sysbus_init_mmio(sbd
, &s
->cpuiomem
[i
+1]);
1450 static void arm_gic_class_init(ObjectClass
*klass
, void *data
)
1452 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1453 ARMGICClass
*agc
= ARM_GIC_CLASS(klass
);
1455 agc
->parent_realize
= dc
->realize
;
1456 dc
->realize
= arm_gic_realize
;
1459 static const TypeInfo arm_gic_info
= {
1460 .name
= TYPE_ARM_GIC
,
1461 .parent
= TYPE_ARM_GIC_COMMON
,
1462 .instance_size
= sizeof(GICState
),
1463 .class_init
= arm_gic_class_init
,
1464 .class_size
= sizeof(ARMGICClass
),
1467 static void arm_gic_register_types(void)
1469 type_register_static(&arm_gic_info
);
1472 type_init(arm_gic_register_types
)