?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
ppc/pnv: activate the "dumpdtb" option on the powernv machine
[qemu/ar7.git] / hw / ppc / pnv.c
blobed689246679332ae036ff836db22e8e38fa75223
1 /*
2 * QEMU PowerPC PowerNV machine model
3 *
4 * Copyright (c) 2016, IBM Corporation.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu/units.h"
22 #include "qapi/error.h"
23 #include "sysemu/sysemu.h"
24 #include "sysemu/numa.h"
25 #include "sysemu/cpus.h"
26 #include "sysemu/device_tree.h"
27 #include "hw/hw.h"
28 #include "target/ppc/cpu.h"
29 #include "qemu/log.h"
30 #include "hw/ppc/fdt.h"
31 #include "hw/ppc/ppc.h"
32 #include "hw/ppc/pnv.h"
33 #include "hw/ppc/pnv_core.h"
34 #include "hw/loader.h"
35 #include "exec/address-spaces.h"
36 #include "qapi/visitor.h"
37 #include "monitor/monitor.h"
38 #include "hw/intc/intc.h"
39 #include "hw/ipmi/ipmi.h"
40 #include "target/ppc/mmu-hash64.h"
41
42 #include "hw/ppc/xics.h"
43 #include "hw/ppc/pnv_xscom.h"
44
45 #include "hw/isa/isa.h"
46 #include "hw/char/serial.h"
47 #include "hw/timer/mc146818rtc.h"
48
49 #include <libfdt.h>
50
51 #define FDT_MAX_SIZE (1 * MiB)
52
53 #define FW_FILE_NAME "skiboot.lid"
54 #define FW_LOAD_ADDR 0x0
55 #define FW_MAX_SIZE (4 * MiB)
56
57 #define KERNEL_LOAD_ADDR 0x20000000
58 #define KERNEL_MAX_SIZE (256 * MiB)
59 #define INITRD_LOAD_ADDR 0x60000000
60 #define INITRD_MAX_SIZE (256 * MiB)
61
62 static const char *pnv_chip_core_typename(const PnvChip *o)
63 {
64 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o)));
65 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX);
66 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type);
67 const char *core_type = object_class_get_name(object_class_by_name(s));
68 g_free(s);
69 return core_type;
70 }
71
72 /*
73 * On Power Systems E880 (POWER8), the max cpus (threads) should be :
74 * 4 * 4 sockets * 12 cores * 8 threads = 1536
75 * Let's make it 2^11
76 */
77 #define MAX_CPUS 2048
78
79 /*
80 * Memory nodes are created by hostboot, one for each range of memory
81 * that has a different "affinity". In practice, it means one range
82 * per chip.
83 */
84 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size)
85 {
86 char *mem_name;
87 uint64_t mem_reg_property[2];
88 int off;
89
90 mem_reg_property[0] = cpu_to_be64(start);
91 mem_reg_property[1] = cpu_to_be64(size);
92
93 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start);
94 off = fdt_add_subnode(fdt, 0, mem_name);
95 g_free(mem_name);
96
97 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
98 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
99 sizeof(mem_reg_property))));
100 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id)));
101 }
102
103 static int get_cpus_node(void *fdt)
104 {
105 int cpus_offset = fdt_path_offset(fdt, "/cpus");
106
107 if (cpus_offset < 0) {
108 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
109 if (cpus_offset) {
110 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
111 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
112 }
113 }
114 _FDT(cpus_offset);
115 return cpus_offset;
116 }
117
118 /*
119 * The PowerNV cores (and threads) need to use real HW ids and not an
120 * incremental index like it has been done on other platforms. This HW
121 * id is stored in the CPU PIR, it is used to create cpu nodes in the
122 * device tree, used in XSCOM to address cores and in interrupt
123 * servers.
124 */
125 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
126 {
127 PowerPCCPU *cpu = pc->threads[0];
128 CPUState *cs = CPU(cpu);
129 DeviceClass *dc = DEVICE_GET_CLASS(cs);
130 int smt_threads = CPU_CORE(pc)->nr_threads;
131 CPUPPCState *env = &cpu->env;
132 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
133 uint32_t servers_prop[smt_threads];
134 int i;
135 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
136 0xffffffff, 0xffffffff};
137 uint32_t tbfreq = PNV_TIMEBASE_FREQ;
138 uint32_t cpufreq = 1000000000;
139 uint32_t page_sizes_prop[64];
140 size_t page_sizes_prop_size;
141 const uint8_t pa_features[] = { 24, 0,
142 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
143 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
144 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
145 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
146 int offset;
147 char *nodename;
148 int cpus_offset = get_cpus_node(fdt);
149
150 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir);
151 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
152 _FDT(offset);
153 g_free(nodename);
154
155 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id)));
156
157 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir)));
158 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir)));
159 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
160
161 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
162 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
163 env->dcache_line_size)));
164 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
165 env->dcache_line_size)));
166 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
167 env->icache_line_size)));
168 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
169 env->icache_line_size)));
170
171 if (pcc->l1_dcache_size) {
172 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
173 pcc->l1_dcache_size)));
174 } else {
175 warn_report("Unknown L1 dcache size for cpu");
176 }
177 if (pcc->l1_icache_size) {
178 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
179 pcc->l1_icache_size)));
180 } else {
181 warn_report("Unknown L1 icache size for cpu");
182 }
183
184 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
185 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
186 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size)));
187 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
188 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
189
190 if (env->spr_cb[SPR_PURR].oea_read) {
191 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
192 }
193
194 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) {
195 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
196 segs, sizeof(segs))));
197 }
198
199 /* Advertise VMX/VSX (vector extensions) if available
200 * 0 / no property == no vector extensions
201 * 1 == VMX / Altivec available
202 * 2 == VSX available */
203 if (env->insns_flags & PPC_ALTIVEC) {
204 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
205
206 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
207 }
208
209 /* Advertise DFP (Decimal Floating Point) if available
210 * 0 / no property == no DFP
211 * 1 == DFP available */
212 if (env->insns_flags2 & PPC2_DFP) {
213 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
214 }
215
216 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
217 sizeof(page_sizes_prop));
218 if (page_sizes_prop_size) {
219 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
220 page_sizes_prop, page_sizes_prop_size)));
221 }
222
223 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
224 pa_features, sizeof(pa_features))));
225
226 /* Build interrupt servers properties */
227 for (i = 0; i < smt_threads; i++) {
228 servers_prop[i] = cpu_to_be32(pc->pir + i);
229 }
230 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
231 servers_prop, sizeof(servers_prop))));
232 }
233
234 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir,
235 uint32_t nr_threads)
236 {
237 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12);
238 char *name;
239 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp";
240 uint32_t irange[2], i, rsize;
241 uint64_t *reg;
242 int offset;
243
244 irange[0] = cpu_to_be32(pir);
245 irange[1] = cpu_to_be32(nr_threads);
246
247 rsize = sizeof(uint64_t) * 2 * nr_threads;
248 reg = g_malloc(rsize);
249 for (i = 0; i < nr_threads; i++) {
250 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000));
251 reg[i * 2 + 1] = cpu_to_be64(0x1000);
252 }
253
254 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr);
255 offset = fdt_add_subnode(fdt, 0, name);
256 _FDT(offset);
257 g_free(name);
258
259 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat))));
260 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize)));
261 _FDT((fdt_setprop_string(fdt, offset, "device_type",
262 "PowerPC-External-Interrupt-Presentation")));
263 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0)));
264 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges",
265 irange, sizeof(irange))));
266 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1)));
267 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0)));
268 g_free(reg);
269 }
270
271 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
272 {
273 const char *typename = pnv_chip_core_typename(chip);
274 size_t typesize = object_type_get_instance_size(typename);
275 int i;
276
277 pnv_dt_xscom(chip, fdt, 0);
278
279 for (i = 0; i < chip->nr_cores; i++) {
280 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize);
281
282 pnv_dt_core(chip, pnv_core, fdt);
283
284 /* Interrupt Control Presenters (ICP). One per core. */
285 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads);
286 }
287
288 if (chip->ram_size) {
289 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
290 }
291 }
292
293 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
294 {
295 const char *typename = pnv_chip_core_typename(chip);
296 size_t typesize = object_type_get_instance_size(typename);
297 int i;
298
299 pnv_dt_xscom(chip, fdt, 0);
300
301 for (i = 0; i < chip->nr_cores; i++) {
302 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize);
303
304 pnv_dt_core(chip, pnv_core, fdt);
305 }
306
307 if (chip->ram_size) {
308 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
309 }
310
311 pnv_dt_lpc(chip, fdt, 0);
312 }
313
314 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off)
315 {
316 uint32_t io_base = d->ioport_id;
317 uint32_t io_regs[] = {
318 cpu_to_be32(1),
319 cpu_to_be32(io_base),
320 cpu_to_be32(2)
321 };
322 char *name;
323 int node;
324
325 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
326 node = fdt_add_subnode(fdt, lpc_off, name);
327 _FDT(node);
328 g_free(name);
329
330 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
331 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00")));
332 }
333
334 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off)
335 {
336 const char compatible[] = "ns16550\0pnpPNP,501";
337 uint32_t io_base = d->ioport_id;
338 uint32_t io_regs[] = {
339 cpu_to_be32(1),
340 cpu_to_be32(io_base),
341 cpu_to_be32(8)
342 };
343 char *name;
344 int node;
345
346 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
347 node = fdt_add_subnode(fdt, lpc_off, name);
348 _FDT(node);
349 g_free(name);
350
351 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
352 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
353 sizeof(compatible))));
354
355 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200)));
356 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200)));
357 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0])));
358 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
359 fdt_get_phandle(fdt, lpc_off))));
360
361 /* This is needed by Linux */
362 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial")));
363 }
364
365 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off)
366 {
367 const char compatible[] = "bt\0ipmi-bt";
368 uint32_t io_base;
369 uint32_t io_regs[] = {
370 cpu_to_be32(1),
371 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */
372 cpu_to_be32(3)
373 };
374 uint32_t irq;
375 char *name;
376 int node;
377
378 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal);
379 io_regs[1] = cpu_to_be32(io_base);
380
381 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal);
382
383 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
384 node = fdt_add_subnode(fdt, lpc_off, name);
385 _FDT(node);
386 g_free(name);
387
388 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
389 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
390 sizeof(compatible))));
391
392 /* Mark it as reserved to avoid Linux trying to claim it */
393 _FDT((fdt_setprop_string(fdt, node, "status", "reserved")));
394 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq)));
395 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
396 fdt_get_phandle(fdt, lpc_off))));
397 }
398
399 typedef struct ForeachPopulateArgs {
400 void *fdt;
401 int offset;
402 } ForeachPopulateArgs;
403
404 static int pnv_dt_isa_device(DeviceState *dev, void *opaque)
405 {
406 ForeachPopulateArgs *args = opaque;
407 ISADevice *d = ISA_DEVICE(dev);
408
409 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) {
410 pnv_dt_rtc(d, args->fdt, args->offset);
411 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) {
412 pnv_dt_serial(d, args->fdt, args->offset);
413 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) {
414 pnv_dt_ipmi_bt(d, args->fdt, args->offset);
415 } else {
416 error_report("unknown isa device %s@i%x", qdev_fw_name(dev),
417 d->ioport_id);
418 }
419
420 return 0;
421 }
422
423 /* The default LPC bus of a multichip system is on chip 0. It's
424 * recognized by the firmware (skiboot) using a "primary" property.
425 */
426 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt)
427 {
428 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename);
429 ForeachPopulateArgs args = {
430 .fdt = fdt,
431 .offset = isa_offset,
432 };
433
434 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0)));
435
436 /* ISA devices are not necessarily parented to the ISA bus so we
437 * can not use object_child_foreach() */
438 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL,
439 &args);
440 }
441
442 static void pnv_dt_power_mgt(void *fdt)
443 {
444 int off;
445
446 off = fdt_add_subnode(fdt, 0, "ibm,opal");
447 off = fdt_add_subnode(fdt, off, "power-mgt");
448
449 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000));
450 }
451
452 static void *pnv_dt_create(MachineState *machine)
453 {
454 const char plat_compat8[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv";
455 const char plat_compat9[] = "qemu,powernv9\0ibm,powernv";
456 PnvMachineState *pnv = PNV_MACHINE(machine);
457 void *fdt;
458 char *buf;
459 int off;
460 int i;
461
462 fdt = g_malloc0(FDT_MAX_SIZE);
463 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
464
465 /* Root node */
466 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2)));
467 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2)));
468 _FDT((fdt_setprop_string(fdt, 0, "model",
469 "IBM PowerNV (emulated by qemu)")));
470 if (pnv_is_power9(pnv)) {
471 _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat9,
472 sizeof(plat_compat9))));
473 } else {
474 _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat8,
475 sizeof(plat_compat8))));
476 }
477
478
479 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
480 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf)));
481 if (qemu_uuid_set) {
482 _FDT((fdt_property_string(fdt, "system-id", buf)));
483 }
484 g_free(buf);
485
486 off = fdt_add_subnode(fdt, 0, "chosen");
487 if (machine->kernel_cmdline) {
488 _FDT((fdt_setprop_string(fdt, off, "bootargs",
489 machine->kernel_cmdline)));
490 }
491
492 if (pnv->initrd_size) {
493 uint32_t start_prop = cpu_to_be32(pnv->initrd_base);
494 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size);
495
496 _FDT((fdt_setprop(fdt, off, "linux,initrd-start",
497 &start_prop, sizeof(start_prop))));
498 _FDT((fdt_setprop(fdt, off, "linux,initrd-end",
499 &end_prop, sizeof(end_prop))));
500 }
501
502 /* Populate device tree for each chip */
503 for (i = 0; i < pnv->num_chips; i++) {
504 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt);
505 }
506
507 /* Populate ISA devices on chip 0 */
508 pnv_dt_isa(pnv, fdt);
509
510 if (pnv->bmc) {
511 pnv_dt_bmc_sensors(pnv->bmc, fdt);
512 }
513
514 /* Create an extra node for power management on Power9 */
515 if (pnv_is_power9(pnv)) {
516 pnv_dt_power_mgt(fdt);
517 }
518
519 return fdt;
520 }
521
522 static void pnv_powerdown_notify(Notifier *n, void *opaque)
523 {
524 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
525
526 if (pnv->bmc) {
527 pnv_bmc_powerdown(pnv->bmc);
528 }
529 }
530
531 static void pnv_reset(void)
532 {
533 MachineState *machine = MACHINE(qdev_get_machine());
534 PnvMachineState *pnv = PNV_MACHINE(machine);
535 void *fdt;
536 Object *obj;
537
538 qemu_devices_reset();
539
540 /* OpenPOWER systems have a BMC, which can be defined on the
541 * command line with:
542 *
543 * -device ipmi-bmc-sim,id=bmc0
544 *
545 * This is the internal simulator but it could also be an external
546 * BMC.
547 */
548 obj = object_resolve_path_type("", "ipmi-bmc-sim", NULL);
549 if (obj) {
550 pnv->bmc = IPMI_BMC(obj);
551 }
552
553 fdt = pnv_dt_create(machine);
554
555 /* Pack resulting tree */
556 _FDT((fdt_pack(fdt)));
557
558 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
559 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt));
560 }
561
562 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp)
563 {
564 Pnv8Chip *chip8 = PNV8_CHIP(chip);
565 return pnv_lpc_isa_create(&chip8->lpc, true, errp);
566 }
567
568 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp)
569 {
570 Pnv8Chip *chip8 = PNV8_CHIP(chip);
571 return pnv_lpc_isa_create(&chip8->lpc, false, errp);
572 }
573
574 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp)
575 {
576 Pnv9Chip *chip9 = PNV9_CHIP(chip);
577 return pnv_lpc_isa_create(&chip9->lpc, false, errp);
578 }
579
580 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp)
581 {
582 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp);
583 }
584
585 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon)
586 {
587 Pnv8Chip *chip8 = PNV8_CHIP(chip);
588
589 ics_pic_print_info(&chip8->psi.ics, mon);
590 }
591
592 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon)
593 {
594 Pnv9Chip *chip9 = PNV9_CHIP(chip);
595
596 pnv_xive_pic_print_info(&chip9->xive, mon);
597 pnv_psi_pic_print_info(&chip9->psi, mon);
598 }
599
600 static void pnv_init(MachineState *machine)
601 {
602 PnvMachineState *pnv = PNV_MACHINE(machine);
603 MemoryRegion *ram;
604 char *fw_filename;
605 long fw_size;
606 int i;
607 char *chip_typename;
608
609 /* allocate RAM */
610 if (machine->ram_size < (1 * GiB)) {
611 warn_report("skiboot may not work with < 1GB of RAM");
612 }
613
614 ram = g_new(MemoryRegion, 1);
615 memory_region_allocate_system_memory(ram, NULL, "pnv.ram",
616 machine->ram_size);
617 memory_region_add_subregion(get_system_memory(), 0, ram);
618
619 /* load skiboot firmware */
620 if (bios_name == NULL) {
621 bios_name = FW_FILE_NAME;
622 }
623
624 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
625 if (!fw_filename) {
626 error_report("Could not find OPAL firmware '%s'", bios_name);
627 exit(1);
628 }
629
630 fw_size = load_image_targphys(fw_filename, FW_LOAD_ADDR, FW_MAX_SIZE);
631 if (fw_size < 0) {
632 error_report("Could not load OPAL firmware '%s'", fw_filename);
633 exit(1);
634 }
635 g_free(fw_filename);
636
637 /* load kernel */
638 if (machine->kernel_filename) {
639 long kernel_size;
640
641 kernel_size = load_image_targphys(machine->kernel_filename,
642 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE);
643 if (kernel_size < 0) {
644 error_report("Could not load kernel '%s'",
645 machine->kernel_filename);
646 exit(1);
647 }
648 }
649
650 /* load initrd */
651 if (machine->initrd_filename) {
652 pnv->initrd_base = INITRD_LOAD_ADDR;
653 pnv->initrd_size = load_image_targphys(machine->initrd_filename,
654 pnv->initrd_base, INITRD_MAX_SIZE);
655 if (pnv->initrd_size < 0) {
656 error_report("Could not load initial ram disk '%s'",
657 machine->initrd_filename);
658 exit(1);
659 }
660 }
661
662 /* Create the processor chips */
663 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
664 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"),
665 i, machine->cpu_type);
666 if (!object_class_by_name(chip_typename)) {
667 error_report("invalid CPU model '%.*s' for %s machine",
668 i, machine->cpu_type, MACHINE_GET_CLASS(machine)->name);
669 exit(1);
670 }
671
672 pnv->chips = g_new0(PnvChip *, pnv->num_chips);
673 for (i = 0; i < pnv->num_chips; i++) {
674 char chip_name[32];
675 Object *chip = object_new(chip_typename);
676
677 pnv->chips[i] = PNV_CHIP(chip);
678
679 /* TODO: put all the memory in one node on chip 0 until we find a
680 * way to specify different ranges for each chip
681 */
682 if (i == 0) {
683 object_property_set_int(chip, machine->ram_size, "ram-size",
684 &error_fatal);
685 }
686
687 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i));
688 object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal);
689 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id",
690 &error_fatal);
691 object_property_set_int(chip, smp_cores, "nr-cores", &error_fatal);
692 object_property_set_bool(chip, true, "realized", &error_fatal);
693 }
694 g_free(chip_typename);
695
696 /* Instantiate ISA bus on chip 0 */
697 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal);
698
699 /* Create serial port */
700 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS);
701
702 /* Create an RTC ISA device too */
703 mc146818_rtc_init(pnv->isa_bus, 2000, NULL);
704
705 /* OpenPOWER systems use a IPMI SEL Event message to notify the
706 * host to powerdown */
707 pnv->powerdown_notifier.notify = pnv_powerdown_notify;
708 qemu_register_powerdown_notifier(&pnv->powerdown_notifier);
709 }
710
711 /*
712 * 0:21 Reserved - Read as zeros
713 * 22:24 Chip ID
714 * 25:28 Core number
715 * 29:31 Thread ID
716 */
717 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id)
718 {
719 return (chip->chip_id << 7) | (core_id << 3);
720 }
721
722 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu,
723 Error **errp)
724 {
725 Error *local_err = NULL;
726 Object *obj;
727 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
728
729 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, XICS_FABRIC(qdev_get_machine()),
730 &local_err);
731 if (local_err) {
732 error_propagate(errp, local_err);
733 return;
734 }
735
736 pnv_cpu->intc = obj;
737 }
738
739 /*
740 * 0:48 Reserved - Read as zeroes
741 * 49:52 Node ID
742 * 53:55 Chip ID
743 * 56 Reserved - Read as zero
744 * 57:61 Core number
745 * 62:63 Thread ID
746 *
747 * We only care about the lower bits. uint32_t is fine for the moment.
748 */
749 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id)
750 {
751 return (chip->chip_id << 8) | (core_id << 2);
752 }
753
754 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu,
755 Error **errp)
756 {
757 Pnv9Chip *chip9 = PNV9_CHIP(chip);
758 Error *local_err = NULL;
759 Object *obj;
760 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
761
762 /*
763 * The core creates its interrupt presenter but the XIVE interrupt
764 * controller object is initialized afterwards. Hopefully, it's
765 * only used at runtime.
766 */
767 obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(&chip9->xive), &local_err);
768 if (local_err) {
769 error_propagate(errp, local_err);
770 return;
771 }
772
773 pnv_cpu->intc = obj;
774 }
775
776 /* Allowed core identifiers on a POWER8 Processor Chip :
777 *
778 * <EX0 reserved>
779 * EX1 - Venice only
780 * EX2 - Venice only
781 * EX3 - Venice only
782 * EX4
783 * EX5
784 * EX6
785 * <EX7,8 reserved> <reserved>
786 * EX9 - Venice only
787 * EX10 - Venice only
788 * EX11 - Venice only
789 * EX12
790 * EX13
791 * EX14
792 * <EX15 reserved>
793 */
794 #define POWER8E_CORE_MASK (0x7070ull)
795 #define POWER8_CORE_MASK (0x7e7eull)
796
797 /*
798 * POWER9 has 24 cores, ids starting at 0x0
799 */
800 #define POWER9_CORE_MASK (0xffffffffffffffull)
801
802 static void pnv_chip_power8_instance_init(Object *obj)
803 {
804 Pnv8Chip *chip8 = PNV8_CHIP(obj);
805
806 object_initialize_child(obj, "psi", &chip8->psi, sizeof(chip8->psi),
807 TYPE_PNV8_PSI, &error_abort, NULL);
808 object_property_add_const_link(OBJECT(&chip8->psi), "xics",
809 OBJECT(qdev_get_machine()), &error_abort);
810
811 object_initialize_child(obj, "lpc", &chip8->lpc, sizeof(chip8->lpc),
812 TYPE_PNV8_LPC, &error_abort, NULL);
813 object_property_add_const_link(OBJECT(&chip8->lpc), "psi",
814 OBJECT(&chip8->psi), &error_abort);
815
816 object_initialize_child(obj, "occ", &chip8->occ, sizeof(chip8->occ),
817 TYPE_PNV8_OCC, &error_abort, NULL);
818 object_property_add_const_link(OBJECT(&chip8->occ), "psi",
819 OBJECT(&chip8->psi), &error_abort);
820 }
821
822 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
823 {
824 PnvChip *chip = PNV_CHIP(chip8);
825 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
826 const char *typename = pnv_chip_core_typename(chip);
827 size_t typesize = object_type_get_instance_size(typename);
828 int i, j;
829 char *name;
830 XICSFabric *xi = XICS_FABRIC(qdev_get_machine());
831
832 name = g_strdup_printf("icp-%x", chip->chip_id);
833 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE);
834 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio);
835 g_free(name);
836
837 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip));
838
839 /* Map the ICP registers for each thread */
840 for (i = 0; i < chip->nr_cores; i++) {
841 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize);
842 int core_hwid = CPU_CORE(pnv_core)->core_id;
843
844 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) {
845 uint32_t pir = pcc->core_pir(chip, core_hwid) + j;
846 PnvICPState *icp = PNV_ICP(xics_icp_get(xi, pir));
847
848 memory_region_add_subregion(&chip8->icp_mmio, pir << 12,
849 &icp->mmio);
850 }
851 }
852 }
853
854 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
855 {
856 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
857 PnvChip *chip = PNV_CHIP(dev);
858 Pnv8Chip *chip8 = PNV8_CHIP(dev);
859 Pnv8Psi *psi8 = &chip8->psi;
860 Error *local_err = NULL;
861
862 pcc->parent_realize(dev, &local_err);
863 if (local_err) {
864 error_propagate(errp, local_err);
865 return;
866 }
867
868 /* Processor Service Interface (PSI) Host Bridge */
869 object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip),
870 "bar", &error_fatal);
871 object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local_err);
872 if (local_err) {
873 error_propagate(errp, local_err);
874 return;
875 }
876 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE,
877 &PNV_PSI(psi8)->xscom_regs);
878
879 /* Create LPC controller */
880 object_property_set_bool(OBJECT(&chip8->lpc), true, "realized",
881 &error_fatal);
882 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs);
883
884 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x",
885 (uint64_t) PNV_XSCOM_BASE(chip),
886 PNV_XSCOM_LPC_BASE);
887
888 /* Interrupt Management Area. This is the memory region holding
889 * all the Interrupt Control Presenter (ICP) registers */
890 pnv_chip_icp_realize(chip8, &local_err);
891 if (local_err) {
892 error_propagate(errp, local_err);
893 return;
894 }
895
896 /* Create the simplified OCC model */
897 object_property_set_bool(OBJECT(&chip8->occ), true, "realized", &local_err);
898 if (local_err) {
899 error_propagate(errp, local_err);
900 return;
901 }
902 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs);
903 }
904
905 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
906 {
907 DeviceClass *dc = DEVICE_CLASS(klass);
908 PnvChipClass *k = PNV_CHIP_CLASS(klass);
909
910 k->chip_type = PNV_CHIP_POWER8E;
911 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */
912 k->cores_mask = POWER8E_CORE_MASK;
913 k->core_pir = pnv_chip_core_pir_p8;
914 k->intc_create = pnv_chip_power8_intc_create;
915 k->isa_create = pnv_chip_power8_isa_create;
916 k->dt_populate = pnv_chip_power8_dt_populate;
917 k->pic_print_info = pnv_chip_power8_pic_print_info;
918 k->xscom_base = 0x003fc0000000000ull;
919 dc->desc = "PowerNV Chip POWER8E";
920
921 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
922 &k->parent_realize);
923 }
924
925 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
926 {
927 DeviceClass *dc = DEVICE_CLASS(klass);
928 PnvChipClass *k = PNV_CHIP_CLASS(klass);
929
930 k->chip_type = PNV_CHIP_POWER8;
931 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
932 k->cores_mask = POWER8_CORE_MASK;
933 k->core_pir = pnv_chip_core_pir_p8;
934 k->intc_create = pnv_chip_power8_intc_create;
935 k->isa_create = pnv_chip_power8_isa_create;
936 k->dt_populate = pnv_chip_power8_dt_populate;
937 k->pic_print_info = pnv_chip_power8_pic_print_info;
938 k->xscom_base = 0x003fc0000000000ull;
939 dc->desc = "PowerNV Chip POWER8";
940
941 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
942 &k->parent_realize);
943 }
944
945 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
946 {
947 DeviceClass *dc = DEVICE_CLASS(klass);
948 PnvChipClass *k = PNV_CHIP_CLASS(klass);
949
950 k->chip_type = PNV_CHIP_POWER8NVL;
951 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */
952 k->cores_mask = POWER8_CORE_MASK;
953 k->core_pir = pnv_chip_core_pir_p8;
954 k->intc_create = pnv_chip_power8_intc_create;
955 k->isa_create = pnv_chip_power8nvl_isa_create;
956 k->dt_populate = pnv_chip_power8_dt_populate;
957 k->pic_print_info = pnv_chip_power8_pic_print_info;
958 k->xscom_base = 0x003fc0000000000ull;
959 dc->desc = "PowerNV Chip POWER8NVL";
960
961 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
962 &k->parent_realize);
963 }
964
965 static void pnv_chip_power9_instance_init(Object *obj)
966 {
967 Pnv9Chip *chip9 = PNV9_CHIP(obj);
968
969 object_initialize_child(obj, "xive", &chip9->xive, sizeof(chip9->xive),
970 TYPE_PNV_XIVE, &error_abort, NULL);
971 object_property_add_const_link(OBJECT(&chip9->xive), "chip", obj,
972 &error_abort);
973
974 object_initialize_child(obj, "psi", &chip9->psi, sizeof(chip9->psi),
975 TYPE_PNV9_PSI, &error_abort, NULL);
976 object_property_add_const_link(OBJECT(&chip9->psi), "chip", obj,
977 &error_abort);
978
979 object_initialize_child(obj, "lpc", &chip9->lpc, sizeof(chip9->lpc),
980 TYPE_PNV9_LPC, &error_abort, NULL);
981 object_property_add_const_link(OBJECT(&chip9->lpc), "psi",
982 OBJECT(&chip9->psi), &error_abort);
983
984 object_initialize_child(obj, "occ", &chip9->occ, sizeof(chip9->occ),
985 TYPE_PNV9_OCC, &error_abort, NULL);
986 object_property_add_const_link(OBJECT(&chip9->occ), "psi",
987 OBJECT(&chip9->psi), &error_abort);
988 }
989
990 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
991 {
992 PnvChip *chip = PNV_CHIP(chip9);
993 const char *typename = pnv_chip_core_typename(chip);
994 size_t typesize = object_type_get_instance_size(typename);
995 int i;
996
997 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
998 chip9->quads = g_new0(PnvQuad, chip9->nr_quads);
999
1000 for (i = 0; i < chip9->nr_quads; i++) {
1001 char eq_name[32];
1002 PnvQuad *eq = &chip9->quads[i];
1003 PnvCore *pnv_core = PNV_CORE(chip->cores + (i * 4) * typesize);
1004 int core_id = CPU_CORE(pnv_core)->core_id;
1005
1006 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id);
1007 object_initialize_child(OBJECT(chip), eq_name, eq, sizeof(*eq),
1008 TYPE_PNV_QUAD, &error_fatal, NULL);
1009
1010 object_property_set_int(OBJECT(eq), core_id, "id", &error_fatal);
1011 object_property_set_bool(OBJECT(eq), true, "realized", &error_fatal);
1012
1013 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id),
1014 &eq->xscom_regs);
1015 }
1016 }
1017
1018 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
1019 {
1020 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1021 Pnv9Chip *chip9 = PNV9_CHIP(dev);
1022 PnvChip *chip = PNV_CHIP(dev);
1023 Pnv9Psi *psi9 = &chip9->psi;
1024 Error *local_err = NULL;
1025
1026 pcc->parent_realize(dev, &local_err);
1027 if (local_err) {
1028 error_propagate(errp, local_err);
1029 return;
1030 }
1031
1032 pnv_chip_quad_realize(chip9, &local_err);
1033 if (local_err) {
1034 error_propagate(errp, local_err);
1035 return;
1036 }
1037
1038 /* XIVE interrupt controller (POWER9) */
1039 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_IC_BASE(chip),
1040 "ic-bar", &error_fatal);
1041 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_VC_BASE(chip),
1042 "vc-bar", &error_fatal);
1043 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_PC_BASE(chip),
1044 "pc-bar", &error_fatal);
1045 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_TM_BASE(chip),
1046 "tm-bar", &error_fatal);
1047 object_property_set_bool(OBJECT(&chip9->xive), true, "realized",
1048 &local_err);
1049 if (local_err) {
1050 error_propagate(errp, local_err);
1051 return;
1052 }
1053 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE,
1054 &chip9->xive.xscom_regs);
1055
1056 /* Processor Service Interface (PSI) Host Bridge */
1057 object_property_set_int(OBJECT(&chip9->psi), PNV9_PSIHB_BASE(chip),
1058 "bar", &error_fatal);
1059 object_property_set_bool(OBJECT(&chip9->psi), true, "realized", &local_err);
1060 if (local_err) {
1061 error_propagate(errp, local_err);
1062 return;
1063 }
1064 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE,
1065 &PNV_PSI(psi9)->xscom_regs);
1066
1067 /* LPC */
1068 object_property_set_bool(OBJECT(&chip9->lpc), true, "realized", &local_err);
1069 if (local_err) {
1070 error_propagate(errp, local_err);
1071 return;
1072 }
1073 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip),
1074 &chip9->lpc.xscom_regs);
1075
1076 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
1077 (uint64_t) PNV9_LPCM_BASE(chip));
1078
1079 /* Create the simplified OCC model */
1080 object_property_set_bool(OBJECT(&chip9->occ), true, "realized", &local_err);
1081 if (local_err) {
1082 error_propagate(errp, local_err);
1083 return;
1084 }
1085 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs);
1086 }
1087
1088 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
1089 {
1090 DeviceClass *dc = DEVICE_CLASS(klass);
1091 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1092
1093 k->chip_type = PNV_CHIP_POWER9;
1094 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */
1095 k->cores_mask = POWER9_CORE_MASK;
1096 k->core_pir = pnv_chip_core_pir_p9;
1097 k->intc_create = pnv_chip_power9_intc_create;
1098 k->isa_create = pnv_chip_power9_isa_create;
1099 k->dt_populate = pnv_chip_power9_dt_populate;
1100 k->pic_print_info = pnv_chip_power9_pic_print_info;
1101 k->xscom_base = 0x00603fc00000000ull;
1102 dc->desc = "PowerNV Chip POWER9";
1103
1104 device_class_set_parent_realize(dc, pnv_chip_power9_realize,
1105 &k->parent_realize);
1106 }
1107
1108 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp)
1109 {
1110 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1111 int cores_max;
1112
1113 /*
1114 * No custom mask for this chip, let's use the default one from *
1115 * the chip class
1116 */
1117 if (!chip->cores_mask) {
1118 chip->cores_mask = pcc->cores_mask;
1119 }
1120
1121 /* filter alien core ids ! some are reserved */
1122 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) {
1123 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !",
1124 chip->cores_mask);
1125 return;
1126 }
1127 chip->cores_mask &= pcc->cores_mask;
1128
1129 /* now that we have a sane layout, let check the number of cores */
1130 cores_max = ctpop64(chip->cores_mask);
1131 if (chip->nr_cores > cores_max) {
1132 error_setg(errp, "warning: too many cores for chip ! Limit is %d",
1133 cores_max);
1134 return;
1135 }
1136 }
1137
1138 static void pnv_chip_instance_init(Object *obj)
1139 {
1140 PNV_CHIP(obj)->xscom_base = PNV_CHIP_GET_CLASS(obj)->xscom_base;
1141 }
1142
1143 static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
1144 {
1145 Error *error = NULL;
1146 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1147 const char *typename = pnv_chip_core_typename(chip);
1148 size_t typesize = object_type_get_instance_size(typename);
1149 int i, core_hwid;
1150
1151 if (!object_class_by_name(typename)) {
1152 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename);
1153 return;
1154 }
1155
1156 /* Cores */
1157 pnv_chip_core_sanitize(chip, &error);
1158 if (error) {
1159 error_propagate(errp, error);
1160 return;
1161 }
1162
1163 chip->cores = g_malloc0(typesize * chip->nr_cores);
1164
1165 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8)
1166 && (i < chip->nr_cores); core_hwid++) {
1167 char core_name[32];
1168 void *pnv_core = chip->cores + i * typesize;
1169 uint64_t xscom_core_base;
1170
1171 if (!(chip->cores_mask & (1ull << core_hwid))) {
1172 continue;
1173 }
1174
1175 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid);
1176 object_initialize_child(OBJECT(chip), core_name, pnv_core, typesize,
1177 typename, &error_fatal, NULL);
1178 object_property_set_int(OBJECT(pnv_core), smp_threads, "nr-threads",
1179 &error_fatal);
1180 object_property_set_int(OBJECT(pnv_core), core_hwid,
1181 CPU_CORE_PROP_CORE_ID, &error_fatal);
1182 object_property_set_int(OBJECT(pnv_core),
1183 pcc->core_pir(chip, core_hwid),
1184 "pir", &error_fatal);
1185 object_property_add_const_link(OBJECT(pnv_core), "chip",
1186 OBJECT(chip), &error_fatal);
1187 object_property_set_bool(OBJECT(pnv_core), true, "realized",
1188 &error_fatal);
1189
1190 /* Each core has an XSCOM MMIO region */
1191 if (!pnv_chip_is_power9(chip)) {
1192 xscom_core_base = PNV_XSCOM_EX_BASE(core_hwid);
1193 } else {
1194 xscom_core_base = PNV9_XSCOM_EC_BASE(core_hwid);
1195 }
1196
1197 pnv_xscom_add_subregion(chip, xscom_core_base,
1198 &PNV_CORE(pnv_core)->xscom_regs);
1199 i++;
1200 }
1201 }
1202
1203 static void pnv_chip_realize(DeviceState *dev, Error **errp)
1204 {
1205 PnvChip *chip = PNV_CHIP(dev);
1206 Error *error = NULL;
1207
1208 /* XSCOM bridge */
1209 pnv_xscom_realize(chip, &error);
1210 if (error) {
1211 error_propagate(errp, error);
1212 return;
1213 }
1214 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip));
1215
1216 /* Cores */
1217 pnv_chip_core_realize(chip, &error);
1218 if (error) {
1219 error_propagate(errp, error);
1220 return;
1221 }
1222 }
1223
1224 static Property pnv_chip_properties[] = {
1225 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0),
1226 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0),
1227 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0),
1228 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1),
1229 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
1230 DEFINE_PROP_END_OF_LIST(),
1231 };
1232
1233 static void pnv_chip_class_init(ObjectClass *klass, void *data)
1234 {
1235 DeviceClass *dc = DEVICE_CLASS(klass);
1236
1237 set_bit(DEVICE_CATEGORY_CPU, dc->categories);
1238 dc->realize = pnv_chip_realize;
1239 dc->props = pnv_chip_properties;
1240 dc->desc = "PowerNV Chip";
1241 }
1242
1243 static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
1244 {
1245 PnvMachineState *pnv = PNV_MACHINE(xi);
1246 int i;
1247
1248 for (i = 0; i < pnv->num_chips; i++) {
1249 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
1250
1251 if (ics_valid_irq(&chip8->psi.ics, irq)) {
1252 return &chip8->psi.ics;
1253 }
1254 }
1255 return NULL;
1256 }
1257
1258 static void pnv_ics_resend(XICSFabric *xi)
1259 {
1260 PnvMachineState *pnv = PNV_MACHINE(xi);
1261 int i;
1262
1263 for (i = 0; i < pnv->num_chips; i++) {
1264 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
1265 ics_resend(&chip8->psi.ics);
1266 }
1267 }
1268
1269 static ICPState *pnv_icp_get(XICSFabric *xi, int pir)
1270 {
1271 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir);
1272
1273 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL;
1274 }
1275
1276 static void pnv_pic_print_info(InterruptStatsProvider *obj,
1277 Monitor *mon)
1278 {
1279 PnvMachineState *pnv = PNV_MACHINE(obj);
1280 int i;
1281 CPUState *cs;
1282
1283 CPU_FOREACH(cs) {
1284 PowerPCCPU *cpu = POWERPC_CPU(cs);
1285
1286 if (pnv_chip_is_power9(pnv->chips[0])) {
1287 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon);
1288 } else {
1289 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon);
1290 }
1291 }
1292
1293 for (i = 0; i < pnv->num_chips; i++) {
1294 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon);
1295 }
1296 }
1297
1298 static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name,
1299 void *opaque, Error **errp)
1300 {
1301 visit_type_uint32(v, name, &PNV_MACHINE(obj)->num_chips, errp);
1302 }
1303
1304 static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name,
1305 void *opaque, Error **errp)
1306 {
1307 PnvMachineState *pnv = PNV_MACHINE(obj);
1308 uint32_t num_chips;
1309 Error *local_err = NULL;
1310
1311 visit_type_uint32(v, name, &num_chips, &local_err);
1312 if (local_err) {
1313 error_propagate(errp, local_err);
1314 return;
1315 }
1316
1317 /*
1318 * TODO: should we decide on how many chips we can create based
1319 * on #cores and Venice vs. Murano vs. Naples chip type etc...,
1320 */
1321 if (!is_power_of_2(num_chips) || num_chips > 4) {
1322 error_setg(errp, "invalid number of chips: '%d'", num_chips);
1323 return;
1324 }
1325
1326 pnv->num_chips = num_chips;
1327 }
1328
1329 static void pnv_machine_instance_init(Object *obj)
1330 {
1331 PnvMachineState *pnv = PNV_MACHINE(obj);
1332 pnv->num_chips = 1;
1333 }
1334
1335 static void pnv_machine_class_props_init(ObjectClass *oc)
1336 {
1337 object_class_property_add(oc, "num-chips", "uint32",
1338 pnv_get_num_chips, pnv_set_num_chips,
1339 NULL, NULL, NULL);
1340 object_class_property_set_description(oc, "num-chips",
1341 "Specifies the number of processor chips",
1342 NULL);
1343 }
1344
1345 static void pnv_machine_class_init(ObjectClass *oc, void *data)
1346 {
1347 MachineClass *mc = MACHINE_CLASS(oc);
1348 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
1349 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
1350
1351 mc->desc = "IBM PowerNV (Non-Virtualized)";
1352 mc->init = pnv_init;
1353 mc->reset = pnv_reset;
1354 mc->max_cpus = MAX_CPUS;
1355 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
1356 mc->block_default_type = IF_IDE; /* Pnv provides a AHCI device for
1357 * storage */
1358 mc->no_parallel = 1;
1359 mc->default_boot_order = NULL;
1360 mc->default_ram_size = 1 * GiB;
1361 xic->icp_get = pnv_icp_get;
1362 xic->ics_get = pnv_ics_get;
1363 xic->ics_resend = pnv_ics_resend;
1364 ispc->print_info = pnv_pic_print_info;
1365
1366 pnv_machine_class_props_init(oc);
1367 }
1368
1369 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \
1370 { \
1371 .name = type, \
1372 .class_init = class_initfn, \
1373 .parent = TYPE_PNV8_CHIP, \
1374 }
1375
1376 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \
1377 { \
1378 .name = type, \
1379 .class_init = class_initfn, \
1380 .parent = TYPE_PNV9_CHIP, \
1381 }
1382
1383 static const TypeInfo types[] = {
1384 {
1385 .name = TYPE_PNV_MACHINE,
1386 .parent = TYPE_MACHINE,
1387 .instance_size = sizeof(PnvMachineState),
1388 .instance_init = pnv_machine_instance_init,
1389 .class_init = pnv_machine_class_init,
1390 .interfaces = (InterfaceInfo[]) {
1391 { TYPE_XICS_FABRIC },
1392 { TYPE_INTERRUPT_STATS_PROVIDER },
1393 { },
1394 },
1395 },
1396 {
1397 .name = TYPE_PNV_CHIP,
1398 .parent = TYPE_SYS_BUS_DEVICE,
1399 .class_init = pnv_chip_class_init,
1400 .instance_init = pnv_chip_instance_init,
1401 .instance_size = sizeof(PnvChip),
1402 .class_size = sizeof(PnvChipClass),
1403 .abstract = true,
1404 },
1405
1406 /*
1407 * P9 chip and variants
1408 */
1409 {
1410 .name = TYPE_PNV9_CHIP,
1411 .parent = TYPE_PNV_CHIP,
1412 .instance_init = pnv_chip_power9_instance_init,
1413 .instance_size = sizeof(Pnv9Chip),
1414 },
1415 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init),
1416
1417 /*
1418 * P8 chip and variants
1419 */
1420 {
1421 .name = TYPE_PNV8_CHIP,
1422 .parent = TYPE_PNV_CHIP,
1423 .instance_init = pnv_chip_power8_instance_init,
1424 .instance_size = sizeof(Pnv8Chip),
1425 },
1426 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init),
1427 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init),
1428 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL,
1429 pnv_chip_power8nvl_class_init),
1430 };
1431
1432 DEFINE_TYPES(types)
AR7 emulation for QEMU