target-s390x/cpu.h

   1 /*
   2  * S/390 virtual CPU header
   3  *
   4  *  Copyright (c) 2009 Ulrich Hecht
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * Contributions after 2012-10-29 are licensed under the terms of the
  17  * GNU GPL, version 2 or (at your option) any later version.
  18  *
  19  * You should have received a copy of the GNU (Lesser) General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  */
  22 #ifndef CPU_S390X_H
  23 #define CPU_S390X_H
  24
  25 #include "config.h"
  26 #include "qemu-common.h"
  27
  28 #define TARGET_LONG_BITS 64
  29
  30 #define ELF_MACHINE     EM_S390
  31
  32 #define CPUArchState struct CPUS390XState
  33
  34 #include "exec/cpu-defs.h"
  35 #define TARGET_PAGE_BITS 12
  36
  37 /* Actually 64-bits, limited by the memory API to 62 bits.  We
  38  * never use that much.
  39  */
  40 #define TARGET_PHYS_ADDR_SPACE_BITS 62
  41 #define TARGET_VIRT_ADDR_SPACE_BITS 64
  42
  43 #include "exec/cpu-all.h"
  44
  45 #include "fpu/softfloat.h"
  46
  47 #define NB_MMU_MODES 3
  48
  49 #define MMU_MODE0_SUFFIX _primary
  50 #define MMU_MODE1_SUFFIX _secondary
  51 #define MMU_MODE2_SUFFIX _home
  52
  53 #define MMU_USER_IDX 1
  54
  55 #define MAX_EXT_QUEUE 16
  56 #define MAX_IO_QUEUE 16
  57 #define MAX_MCHK_QUEUE 16
  58
  59 #define PSW_MCHK_MASK 0x0004000000000000
  60 #define PSW_IO_MASK 0x0200000000000000
  61
  62 typedef struct PSW {
  63     uint64_t mask;
  64     uint64_t addr;
  65 } PSW;
  66
  67 typedef struct ExtQueue {
  68     uint32_t code;
  69     uint32_t param;
  70     uint32_t param64;
  71 } ExtQueue;
  72
  73 typedef struct IOIntQueue {
  74     uint16_t id;
  75     uint16_t nr;
  76     uint32_t parm;
  77     uint32_t word;
  78 } IOIntQueue;
  79
  80 typedef struct MchkQueue {
  81     uint16_t type;
  82 } MchkQueue;
  83
  84 /* Defined values for CPUS390XState.runtime_reg_dirty_mask */
  85 #define KVM_S390_RUNTIME_DIRTY_NONE     0
  86 #define KVM_S390_RUNTIME_DIRTY_PARTIAL  1
  87 #define KVM_S390_RUNTIME_DIRTY_FULL     2
  88
  89 typedef struct CPUS390XState {
  90     uint64_t regs[16];     /* GP registers */
  91     CPU_DoubleU fregs[16]; /* FP registers */
  92     uint32_t aregs[16];    /* access registers */
  93
  94     uint32_t fpc;          /* floating-point control register */
  95     uint32_t cc_op;
  96
  97     float_status fpu_status; /* passed to softfloat lib */
  98
  99     /* The low part of a 128-bit return, or remainder of a divide.  */
 100     uint64_t retxl;
 101
 102     PSW psw;
 103
 104     uint64_t cc_src;
 105     uint64_t cc_dst;
 106     uint64_t cc_vr;
 107
 108     uint64_t __excp_addr;
 109     uint64_t psa;
 110
 111     uint32_t int_pgm_code;
 112     uint32_t int_pgm_ilen;
 113
 114     uint32_t int_svc_code;
 115     uint32_t int_svc_ilen;
 116
 117     uint64_t cregs[16]; /* control registers */
 118
 119     ExtQueue ext_queue[MAX_EXT_QUEUE];
 120     IOIntQueue io_queue[MAX_IO_QUEUE][8];
 121     MchkQueue mchk_queue[MAX_MCHK_QUEUE];
 122
 123     int pending_int;
 124     int ext_index;
 125     int io_index[8];
 126     int mchk_index;
 127
 128     uint64_t ckc;
 129     uint64_t cputm;
 130     uint32_t todpr;
 131
 132     /* on S390 the runtime register set has two dirty states:
 133      * a partial dirty state in which only the registers that
 134      * are needed all the time are fetched. And a fully dirty
 135      * state in which all runtime registers are fetched.
 136      */
 137     uint32_t runtime_reg_dirty_mask;
 138
 139     CPU_COMMON
 140
 141     /* reset does memset(0) up to here */
 142
 143     int cpu_num;
 144     uint8_t *storage_keys;
 145
 146     uint64_t tod_offset;
 147     uint64_t tod_basetime;
 148     QEMUTimer *tod_timer;
 149
 150     QEMUTimer *cpu_timer;
 151 } CPUS390XState;
 152
 153 #include "cpu-qom.h"
 154
 155 #if defined(CONFIG_USER_ONLY)
 156 static inline void cpu_clone_regs(CPUS390XState *env, target_ulong newsp)
 157 {
 158     if (newsp) {
 159         env->regs[15] = newsp;
 160     }
 161     env->regs[2] = 0;
 162 }
 163 #endif
 164
 165 /* distinguish between 24 bit and 31 bit addressing */
 166 #define HIGH_ORDER_BIT 0x80000000
 167
 168 /* Interrupt Codes */
 169 /* Program Interrupts */
 170 #define PGM_OPERATION                   0x0001
 171 #define PGM_PRIVILEGED                  0x0002
 172 #define PGM_EXECUTE                     0x0003
 173 #define PGM_PROTECTION                  0x0004
 174 #define PGM_ADDRESSING                  0x0005
 175 #define PGM_SPECIFICATION               0x0006
 176 #define PGM_DATA                        0x0007
 177 #define PGM_FIXPT_OVERFLOW              0x0008
 178 #define PGM_FIXPT_DIVIDE                0x0009
 179 #define PGM_DEC_OVERFLOW                0x000a
 180 #define PGM_DEC_DIVIDE                  0x000b
 181 #define PGM_HFP_EXP_OVERFLOW            0x000c
 182 #define PGM_HFP_EXP_UNDERFLOW           0x000d
 183 #define PGM_HFP_SIGNIFICANCE            0x000e
 184 #define PGM_HFP_DIVIDE                  0x000f
 185 #define PGM_SEGMENT_TRANS               0x0010
 186 #define PGM_PAGE_TRANS                  0x0011
 187 #define PGM_TRANS_SPEC                  0x0012
 188 #define PGM_SPECIAL_OP                  0x0013
 189 #define PGM_OPERAND                     0x0015
 190 #define PGM_TRACE_TABLE                 0x0016
 191 #define PGM_SPACE_SWITCH                0x001c
 192 #define PGM_HFP_SQRT                    0x001d
 193 #define PGM_PC_TRANS_SPEC               0x001f
 194 #define PGM_AFX_TRANS                   0x0020
 195 #define PGM_ASX_TRANS                   0x0021
 196 #define PGM_LX_TRANS                    0x0022
 197 #define PGM_EX_TRANS                    0x0023
 198 #define PGM_PRIM_AUTH                   0x0024
 199 #define PGM_SEC_AUTH                    0x0025
 200 #define PGM_ALET_SPEC                   0x0028
 201 #define PGM_ALEN_SPEC                   0x0029
 202 #define PGM_ALE_SEQ                     0x002a
 203 #define PGM_ASTE_VALID                  0x002b
 204 #define PGM_ASTE_SEQ                    0x002c
 205 #define PGM_EXT_AUTH                    0x002d
 206 #define PGM_STACK_FULL                  0x0030
 207 #define PGM_STACK_EMPTY                 0x0031
 208 #define PGM_STACK_SPEC                  0x0032
 209 #define PGM_STACK_TYPE                  0x0033
 210 #define PGM_STACK_OP                    0x0034
 211 #define PGM_ASCE_TYPE                   0x0038
 212 #define PGM_REG_FIRST_TRANS             0x0039
 213 #define PGM_REG_SEC_TRANS               0x003a
 214 #define PGM_REG_THIRD_TRANS             0x003b
 215 #define PGM_MONITOR                     0x0040
 216 #define PGM_PER                         0x0080
 217 #define PGM_CRYPTO                      0x0119
 218
 219 /* External Interrupts */
 220 #define EXT_INTERRUPT_KEY               0x0040
 221 #define EXT_CLOCK_COMP                  0x1004
 222 #define EXT_CPU_TIMER                   0x1005
 223 #define EXT_MALFUNCTION                 0x1200
 224 #define EXT_EMERGENCY                   0x1201
 225 #define EXT_EXTERNAL_CALL               0x1202
 226 #define EXT_ETR                         0x1406
 227 #define EXT_SERVICE                     0x2401
 228 #define EXT_VIRTIO                      0x2603
 229
 230 /* PSW defines */
 231 #undef PSW_MASK_PER
 232 #undef PSW_MASK_DAT
 233 #undef PSW_MASK_IO
 234 #undef PSW_MASK_EXT
 235 #undef PSW_MASK_KEY
 236 #undef PSW_SHIFT_KEY
 237 #undef PSW_MASK_MCHECK
 238 #undef PSW_MASK_WAIT
 239 #undef PSW_MASK_PSTATE
 240 #undef PSW_MASK_ASC
 241 #undef PSW_MASK_CC
 242 #undef PSW_MASK_PM
 243 #undef PSW_MASK_64
 244
 245 #define PSW_MASK_PER            0x4000000000000000ULL
 246 #define PSW_MASK_DAT            0x0400000000000000ULL
 247 #define PSW_MASK_IO             0x0200000000000000ULL
 248 #define PSW_MASK_EXT            0x0100000000000000ULL
 249 #define PSW_MASK_KEY            0x00F0000000000000ULL
 250 #define PSW_SHIFT_KEY           56
 251 #define PSW_MASK_MCHECK         0x0004000000000000ULL
 252 #define PSW_MASK_WAIT           0x0002000000000000ULL
 253 #define PSW_MASK_PSTATE         0x0001000000000000ULL
 254 #define PSW_MASK_ASC            0x0000C00000000000ULL
 255 #define PSW_MASK_CC             0x0000300000000000ULL
 256 #define PSW_MASK_PM             0x00000F0000000000ULL
 257 #define PSW_MASK_64             0x0000000100000000ULL
 258 #define PSW_MASK_32             0x0000000080000000ULL
 259
 260 #undef PSW_ASC_PRIMARY
 261 #undef PSW_ASC_ACCREG
 262 #undef PSW_ASC_SECONDARY
 263 #undef PSW_ASC_HOME
 264
 265 #define PSW_ASC_PRIMARY         0x0000000000000000ULL
 266 #define PSW_ASC_ACCREG          0x0000400000000000ULL
 267 #define PSW_ASC_SECONDARY       0x0000800000000000ULL
 268 #define PSW_ASC_HOME            0x0000C00000000000ULL
 269
 270 /* tb flags */
 271
 272 #define FLAG_MASK_PER           (PSW_MASK_PER    >> 32)
 273 #define FLAG_MASK_DAT           (PSW_MASK_DAT    >> 32)
 274 #define FLAG_MASK_IO            (PSW_MASK_IO     >> 32)
 275 #define FLAG_MASK_EXT           (PSW_MASK_EXT    >> 32)
 276 #define FLAG_MASK_KEY           (PSW_MASK_KEY    >> 32)
 277 #define FLAG_MASK_MCHECK        (PSW_MASK_MCHECK >> 32)
 278 #define FLAG_MASK_WAIT          (PSW_MASK_WAIT   >> 32)
 279 #define FLAG_MASK_PSTATE        (PSW_MASK_PSTATE >> 32)
 280 #define FLAG_MASK_ASC           (PSW_MASK_ASC    >> 32)
 281 #define FLAG_MASK_CC            (PSW_MASK_CC     >> 32)
 282 #define FLAG_MASK_PM            (PSW_MASK_PM     >> 32)
 283 #define FLAG_MASK_64            (PSW_MASK_64     >> 32)
 284 #define FLAG_MASK_32            0x00001000
 285
 286 static inline int cpu_mmu_index (CPUS390XState *env)
 287 {
 288     if (env->psw.mask & PSW_MASK_PSTATE) {
 289         return 1;
 290     }
 291
 292     return 0;
 293 }
 294
 295 static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
 296                                         target_ulong *cs_base, int *flags)
 297 {
 298     *pc = env->psw.addr;
 299     *cs_base = 0;
 300     *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
 301              ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
 302 }
 303
 304 /* While the PoO talks about ILC (a number between 1-3) what is actually
 305    stored in LowCore is shifted left one bit (an even between 2-6).  As
 306    this is the actual length of the insn and therefore more useful, that
 307    is what we want to pass around and manipulate.  To make sure that we
 308    have applied this distinction universally, rename the "ILC" to "ILEN".  */
 309 static inline int get_ilen(uint8_t opc)
 310 {
 311     switch (opc >> 6) {
 312     case 0:
 313         return 2;
 314     case 1:
 315     case 2:
 316         return 4;
 317     default:
 318         return 6;
 319     }
 320 }
 321
 322 #ifndef CONFIG_USER_ONLY
 323 /* In several cases of runtime exceptions, we havn't recorded the true
 324    instruction length.  Use these codes when raising exceptions in order
 325    to re-compute the length by examining the insn in memory.  */
 326 #define ILEN_LATER       0x20
 327 #define ILEN_LATER_INC   0x21
 328 #endif
 329
 330 S390CPU *cpu_s390x_init(const char *cpu_model);
 331 void s390x_translate_init(void);
 332 int cpu_s390x_exec(CPUS390XState *s);
 333
 334 /* you can call this signal handler from your SIGBUS and SIGSEGV
 335    signal handlers to inform the virtual CPU of exceptions. non zero
 336    is returned if the signal was handled by the virtual CPU.  */
 337 int cpu_s390x_signal_handler(int host_signum, void *pinfo,
 338                            void *puc);
 339 int cpu_s390x_handle_mmu_fault (CPUS390XState *env, target_ulong address, int rw,
 340                                 int mmu_idx);
 341 #define cpu_handle_mmu_fault cpu_s390x_handle_mmu_fault
 342
 343 #include "ioinst.h"
 344
 345 #ifndef CONFIG_USER_ONLY
 346 void *s390_cpu_physical_memory_map(CPUS390XState *env, hwaddr addr, hwaddr *len,
 347                                    int is_write);
 348 void s390_cpu_physical_memory_unmap(CPUS390XState *env, void *addr, hwaddr len,
 349                                     int is_write);
 350 static inline hwaddr decode_basedisp_s(CPUS390XState *env, uint32_t ipb)
 351 {
 352     hwaddr addr = 0;
 353     uint8_t reg;
 354
 355     reg = ipb >> 28;
 356     if (reg > 0) {
 357         addr = env->regs[reg];
 358     }
 359     addr += (ipb >> 16) & 0xfff;
 360
 361     return addr;
 362 }
 363
 364 void s390x_tod_timer(void *opaque);
 365 void s390x_cpu_timer(void *opaque);
 366
 367 int s390_virtio_hypercall(CPUS390XState *env);
 368
 369 #ifdef CONFIG_KVM
 370 void kvm_s390_interrupt(S390CPU *cpu, int type, uint32_t code);
 371 void kvm_s390_virtio_irq(S390CPU *cpu, int config_change, uint64_t token);
 372 void kvm_s390_interrupt_internal(S390CPU *cpu, int type, uint32_t parm,
 373                                  uint64_t parm64, int vm);
 374 #else
 375 static inline void kvm_s390_interrupt(S390CPU *cpu, int type, uint32_t code)
 376 {
 377 }
 378
 379 static inline void kvm_s390_virtio_irq(S390CPU *cpu, int config_change,
 380                                        uint64_t token)
 381 {
 382 }
 383
 384 static inline void kvm_s390_interrupt_internal(S390CPU *cpu, int type,
 385                                                uint32_t parm, uint64_t parm64,
 386                                                int vm)
 387 {
 388 }
 389 #endif
 390 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
 391 void s390_add_running_cpu(S390CPU *cpu);
 392 unsigned s390_del_running_cpu(S390CPU *cpu);
 393
 394 /* service interrupts are floating therefore we must not pass an cpustate */
 395 void s390_sclp_extint(uint32_t parm);
 396
 397 /* from s390-virtio-bus */
 398 extern const hwaddr virtio_size;
 399
 400 #else
 401 static inline void s390_add_running_cpu(S390CPU *cpu)
 402 {
 403 }
 404
 405 static inline unsigned s390_del_running_cpu(S390CPU *cpu)
 406 {
 407     return 0;
 408 }
 409 #endif
 410 void cpu_lock(void);
 411 void cpu_unlock(void);
 412
 413 typedef struct SubchDev SubchDev;
 414
 415 #ifndef CONFIG_USER_ONLY
 416 SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
 417                          uint16_t schid);
 418 bool css_subch_visible(SubchDev *sch);
 419 void css_conditional_io_interrupt(SubchDev *sch);
 420 int css_do_stsch(SubchDev *sch, SCHIB *schib);
 421 bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid);
 422 int css_do_msch(SubchDev *sch, SCHIB *schib);
 423 int css_do_xsch(SubchDev *sch);
 424 int css_do_csch(SubchDev *sch);
 425 int css_do_hsch(SubchDev *sch);
 426 int css_do_ssch(SubchDev *sch, ORB *orb);
 427 int css_do_tsch(SubchDev *sch, IRB *irb);
 428 int css_do_stcrw(CRW *crw);
 429 int css_do_tpi(IOIntCode *int_code, int lowcore);
 430 int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid,
 431                          int rfmt, void *buf);
 432 void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo);
 433 int css_enable_mcsse(void);
 434 int css_enable_mss(void);
 435 int css_do_rsch(SubchDev *sch);
 436 int css_do_rchp(uint8_t cssid, uint8_t chpid);
 437 bool css_present(uint8_t cssid);
 438 #else
 439 static inline SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
 440                                        uint16_t schid)
 441 {
 442     return NULL;
 443 }
 444 static inline bool css_subch_visible(SubchDev *sch)
 445 {
 446     return false;
 447 }
 448 static inline void css_conditional_io_interrupt(SubchDev *sch)
 449 {
 450 }
 451 static inline int css_do_stsch(SubchDev *sch, SCHIB *schib)
 452 {
 453     return -ENODEV;
 454 }
 455 static inline bool css_schid_final(uint8_t cssid, uint8_t ssid, uint16_t schid)
 456 {
 457     return true;
 458 }
 459 static inline int css_do_msch(SubchDev *sch, SCHIB *schib)
 460 {
 461     return -ENODEV;
 462 }
 463 static inline int css_do_xsch(SubchDev *sch)
 464 {
 465     return -ENODEV;
 466 }
 467 static inline int css_do_csch(SubchDev *sch)
 468 {
 469     return -ENODEV;
 470 }
 471 static inline int css_do_hsch(SubchDev *sch)
 472 {
 473     return -ENODEV;
 474 }
 475 static inline int css_do_ssch(SubchDev *sch, ORB *orb)
 476 {
 477     return -ENODEV;
 478 }
 479 static inline int css_do_tsch(SubchDev *sch, IRB *irb)
 480 {
 481     return -ENODEV;
 482 }
 483 static inline int css_do_stcrw(CRW *crw)
 484 {
 485     return 1;
 486 }
 487 static inline int css_do_tpi(IOIntCode *int_code, int lowcore)
 488 {
 489     return 0;
 490 }
 491 static inline int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid,
 492                                        int rfmt, uint8_t l_chpid, void *buf)
 493 {
 494     return 0;
 495 }
 496 static inline void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo)
 497 {
 498 }
 499 static inline int css_enable_mss(void)
 500 {
 501     return -EINVAL;
 502 }
 503 static inline int css_enable_mcsse(void)
 504 {
 505     return -EINVAL;
 506 }
 507 static inline int css_do_rsch(SubchDev *sch)
 508 {
 509     return -ENODEV;
 510 }
 511 static inline int css_do_rchp(uint8_t cssid, uint8_t chpid)
 512 {
 513     return -ENODEV;
 514 }
 515 static inline bool css_present(uint8_t cssid)
 516 {
 517     return false;
 518 }
 519 #endif
 520
 521 static inline void cpu_set_tls(CPUS390XState *env, target_ulong newtls)
 522 {
 523     env->aregs[0] = newtls >> 32;
 524     env->aregs[1] = newtls & 0xffffffffULL;
 525 }
 526
 527 #define cpu_init(model) (&cpu_s390x_init(model)->env)
 528 #define cpu_exec cpu_s390x_exec
 529 #define cpu_gen_code cpu_s390x_gen_code
 530 #define cpu_signal_handler cpu_s390x_signal_handler
 531
 532 void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 533 #define cpu_list s390_cpu_list
 534
 535 #include "exec/exec-all.h"
 536
 537 #define EXCP_EXT 1 /* external interrupt */
 538 #define EXCP_SVC 2 /* supervisor call (syscall) */
 539 #define EXCP_PGM 3 /* program interruption */
 540 #define EXCP_IO  7 /* I/O interrupt */
 541 #define EXCP_MCHK 8 /* machine check */
 542
 543 #define INTERRUPT_EXT        (1 << 0)
 544 #define INTERRUPT_TOD        (1 << 1)
 545 #define INTERRUPT_CPUTIMER   (1 << 2)
 546 #define INTERRUPT_IO         (1 << 3)
 547 #define INTERRUPT_MCHK       (1 << 4)
 548
 549 /* Program Status Word.  */
 550 #define S390_PSWM_REGNUM 0
 551 #define S390_PSWA_REGNUM 1
 552 /* General Purpose Registers.  */
 553 #define S390_R0_REGNUM 2
 554 #define S390_R1_REGNUM 3
 555 #define S390_R2_REGNUM 4
 556 #define S390_R3_REGNUM 5
 557 #define S390_R4_REGNUM 6
 558 #define S390_R5_REGNUM 7
 559 #define S390_R6_REGNUM 8
 560 #define S390_R7_REGNUM 9
 561 #define S390_R8_REGNUM 10
 562 #define S390_R9_REGNUM 11
 563 #define S390_R10_REGNUM 12
 564 #define S390_R11_REGNUM 13
 565 #define S390_R12_REGNUM 14
 566 #define S390_R13_REGNUM 15
 567 #define S390_R14_REGNUM 16
 568 #define S390_R15_REGNUM 17
 569 /* Access Registers.  */
 570 #define S390_A0_REGNUM 18
 571 #define S390_A1_REGNUM 19
 572 #define S390_A2_REGNUM 20
 573 #define S390_A3_REGNUM 21
 574 #define S390_A4_REGNUM 22
 575 #define S390_A5_REGNUM 23
 576 #define S390_A6_REGNUM 24
 577 #define S390_A7_REGNUM 25
 578 #define S390_A8_REGNUM 26
 579 #define S390_A9_REGNUM 27
 580 #define S390_A10_REGNUM 28
 581 #define S390_A11_REGNUM 29
 582 #define S390_A12_REGNUM 30
 583 #define S390_A13_REGNUM 31
 584 #define S390_A14_REGNUM 32
 585 #define S390_A15_REGNUM 33
 586 /* Floating Point Control Word.  */
 587 #define S390_FPC_REGNUM 34
 588 /* Floating Point Registers.  */
 589 #define S390_F0_REGNUM 35
 590 #define S390_F1_REGNUM 36
 591 #define S390_F2_REGNUM 37
 592 #define S390_F3_REGNUM 38
 593 #define S390_F4_REGNUM 39
 594 #define S390_F5_REGNUM 40
 595 #define S390_F6_REGNUM 41
 596 #define S390_F7_REGNUM 42
 597 #define S390_F8_REGNUM 43
 598 #define S390_F9_REGNUM 44
 599 #define S390_F10_REGNUM 45
 600 #define S390_F11_REGNUM 46
 601 #define S390_F12_REGNUM 47
 602 #define S390_F13_REGNUM 48
 603 #define S390_F14_REGNUM 49
 604 #define S390_F15_REGNUM 50
 605 /* Total.  */
 606 #define S390_NUM_REGS 51
 607
 608 /* CC optimization */
 609
 610 enum cc_op {
 611     CC_OP_CONST0 = 0,           /* CC is 0 */
 612     CC_OP_CONST1,               /* CC is 1 */
 613     CC_OP_CONST2,               /* CC is 2 */
 614     CC_OP_CONST3,               /* CC is 3 */
 615
 616     CC_OP_DYNAMIC,              /* CC calculation defined by env->cc_op */
 617     CC_OP_STATIC,               /* CC value is env->cc_op */
 618
 619     CC_OP_NZ,                   /* env->cc_dst != 0 */
 620     CC_OP_LTGT_32,              /* signed less/greater than (32bit) */
 621     CC_OP_LTGT_64,              /* signed less/greater than (64bit) */
 622     CC_OP_LTUGTU_32,            /* unsigned less/greater than (32bit) */
 623     CC_OP_LTUGTU_64,            /* unsigned less/greater than (64bit) */
 624     CC_OP_LTGT0_32,             /* signed less/greater than 0 (32bit) */
 625     CC_OP_LTGT0_64,             /* signed less/greater than 0 (64bit) */
 626
 627     CC_OP_ADD_64,               /* overflow on add (64bit) */
 628     CC_OP_ADDU_64,              /* overflow on unsigned add (64bit) */
 629     CC_OP_ADDC_64,              /* overflow on unsigned add-carry (64bit) */
 630     CC_OP_SUB_64,               /* overflow on subtraction (64bit) */
 631     CC_OP_SUBU_64,              /* overflow on unsigned subtraction (64bit) */
 632     CC_OP_SUBB_64,              /* overflow on unsigned sub-borrow (64bit) */
 633     CC_OP_ABS_64,               /* sign eval on abs (64bit) */
 634     CC_OP_NABS_64,              /* sign eval on nabs (64bit) */
 635
 636     CC_OP_ADD_32,               /* overflow on add (32bit) */
 637     CC_OP_ADDU_32,              /* overflow on unsigned add (32bit) */
 638     CC_OP_ADDC_32,              /* overflow on unsigned add-carry (32bit) */
 639     CC_OP_SUB_32,               /* overflow on subtraction (32bit) */
 640     CC_OP_SUBU_32,              /* overflow on unsigned subtraction (32bit) */
 641     CC_OP_SUBB_32,              /* overflow on unsigned sub-borrow (32bit) */
 642     CC_OP_ABS_32,               /* sign eval on abs (64bit) */
 643     CC_OP_NABS_32,              /* sign eval on nabs (64bit) */
 644
 645     CC_OP_COMP_32,              /* complement */
 646     CC_OP_COMP_64,              /* complement */
 647
 648     CC_OP_TM_32,                /* test under mask (32bit) */
 649     CC_OP_TM_64,                /* test under mask (64bit) */
 650
 651     CC_OP_NZ_F32,               /* FP dst != 0 (32bit) */
 652     CC_OP_NZ_F64,               /* FP dst != 0 (64bit) */
 653     CC_OP_NZ_F128,              /* FP dst != 0 (128bit) */
 654
 655     CC_OP_ICM,                  /* insert characters under mask */
 656     CC_OP_SLA_32,               /* Calculate shift left signed (32bit) */
 657     CC_OP_SLA_64,               /* Calculate shift left signed (64bit) */
 658     CC_OP_FLOGR,                /* find leftmost one */
 659     CC_OP_MAX
 660 };
 661
 662 static const char *cc_names[] = {
 663     [CC_OP_CONST0]    = "CC_OP_CONST0",
 664     [CC_OP_CONST1]    = "CC_OP_CONST1",
 665     [CC_OP_CONST2]    = "CC_OP_CONST2",
 666     [CC_OP_CONST3]    = "CC_OP_CONST3",
 667     [CC_OP_DYNAMIC]   = "CC_OP_DYNAMIC",
 668     [CC_OP_STATIC]    = "CC_OP_STATIC",
 669     [CC_OP_NZ]        = "CC_OP_NZ",
 670     [CC_OP_LTGT_32]   = "CC_OP_LTGT_32",
 671     [CC_OP_LTGT_64]   = "CC_OP_LTGT_64",
 672     [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
 673     [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
 674     [CC_OP_LTGT0_32]  = "CC_OP_LTGT0_32",
 675     [CC_OP_LTGT0_64]  = "CC_OP_LTGT0_64",
 676     [CC_OP_ADD_64]    = "CC_OP_ADD_64",
 677     [CC_OP_ADDU_64]   = "CC_OP_ADDU_64",
 678     [CC_OP_ADDC_64]   = "CC_OP_ADDC_64",
 679     [CC_OP_SUB_64]    = "CC_OP_SUB_64",
 680     [CC_OP_SUBU_64]   = "CC_OP_SUBU_64",
 681     [CC_OP_SUBB_64]   = "CC_OP_SUBB_64",
 682     [CC_OP_ABS_64]    = "CC_OP_ABS_64",
 683     [CC_OP_NABS_64]   = "CC_OP_NABS_64",
 684     [CC_OP_ADD_32]    = "CC_OP_ADD_32",
 685     [CC_OP_ADDU_32]   = "CC_OP_ADDU_32",
 686     [CC_OP_ADDC_32]   = "CC_OP_ADDC_32",
 687     [CC_OP_SUB_32]    = "CC_OP_SUB_32",
 688     [CC_OP_SUBU_32]   = "CC_OP_SUBU_32",
 689     [CC_OP_SUBB_32]   = "CC_OP_SUBB_32",
 690     [CC_OP_ABS_32]    = "CC_OP_ABS_32",
 691     [CC_OP_NABS_32]   = "CC_OP_NABS_32",
 692     [CC_OP_COMP_32]   = "CC_OP_COMP_32",
 693     [CC_OP_COMP_64]   = "CC_OP_COMP_64",
 694     [CC_OP_TM_32]     = "CC_OP_TM_32",
 695     [CC_OP_TM_64]     = "CC_OP_TM_64",
 696     [CC_OP_NZ_F32]    = "CC_OP_NZ_F32",
 697     [CC_OP_NZ_F64]    = "CC_OP_NZ_F64",
 698     [CC_OP_NZ_F128]   = "CC_OP_NZ_F128",
 699     [CC_OP_ICM]       = "CC_OP_ICM",
 700     [CC_OP_SLA_32]    = "CC_OP_SLA_32",
 701     [CC_OP_SLA_64]    = "CC_OP_SLA_64",
 702     [CC_OP_FLOGR]     = "CC_OP_FLOGR",
 703 };
 704
 705 static inline const char *cc_name(int cc_op)
 706 {
 707     return cc_names[cc_op];
 708 }
 709
 710 typedef struct LowCore
 711 {
 712     /* prefix area: defined by architecture */
 713     uint32_t        ccw1[2];                  /* 0x000 */
 714     uint32_t        ccw2[4];                  /* 0x008 */
 715     uint8_t         pad1[0x80-0x18];          /* 0x018 */
 716     uint32_t        ext_params;               /* 0x080 */
 717     uint16_t        cpu_addr;                 /* 0x084 */
 718     uint16_t        ext_int_code;             /* 0x086 */
 719     uint16_t        svc_ilen;                 /* 0x088 */
 720     uint16_t        svc_code;                 /* 0x08a */
 721     uint16_t        pgm_ilen;                 /* 0x08c */
 722     uint16_t        pgm_code;                 /* 0x08e */
 723     uint32_t        data_exc_code;            /* 0x090 */
 724     uint16_t        mon_class_num;            /* 0x094 */
 725     uint16_t        per_perc_atmid;           /* 0x096 */
 726     uint64_t        per_address;              /* 0x098 */
 727     uint8_t         exc_access_id;            /* 0x0a0 */
 728     uint8_t         per_access_id;            /* 0x0a1 */
 729     uint8_t         op_access_id;             /* 0x0a2 */
 730     uint8_t         ar_access_id;             /* 0x0a3 */
 731     uint8_t         pad2[0xA8-0xA4];          /* 0x0a4 */
 732     uint64_t        trans_exc_code;           /* 0x0a8 */
 733     uint64_t        monitor_code;             /* 0x0b0 */
 734     uint16_t        subchannel_id;            /* 0x0b8 */
 735     uint16_t        subchannel_nr;            /* 0x0ba */
 736     uint32_t        io_int_parm;              /* 0x0bc */
 737     uint32_t        io_int_word;              /* 0x0c0 */
 738     uint8_t         pad3[0xc8-0xc4];          /* 0x0c4 */
 739     uint32_t        stfl_fac_list;            /* 0x0c8 */
 740     uint8_t         pad4[0xe8-0xcc];          /* 0x0cc */
 741     uint32_t        mcck_interruption_code[2]; /* 0x0e8 */
 742     uint8_t         pad5[0xf4-0xf0];          /* 0x0f0 */
 743     uint32_t        external_damage_code;     /* 0x0f4 */
 744     uint64_t        failing_storage_address;  /* 0x0f8 */
 745     uint8_t         pad6[0x120-0x100];        /* 0x100 */
 746     PSW             restart_old_psw;          /* 0x120 */
 747     PSW             external_old_psw;         /* 0x130 */
 748     PSW             svc_old_psw;              /* 0x140 */
 749     PSW             program_old_psw;          /* 0x150 */
 750     PSW             mcck_old_psw;             /* 0x160 */
 751     PSW             io_old_psw;               /* 0x170 */
 752     uint8_t         pad7[0x1a0-0x180];        /* 0x180 */
 753     PSW             restart_psw;              /* 0x1a0 */
 754     PSW             external_new_psw;         /* 0x1b0 */
 755     PSW             svc_new_psw;              /* 0x1c0 */
 756     PSW             program_new_psw;          /* 0x1d0 */
 757     PSW             mcck_new_psw;             /* 0x1e0 */
 758     PSW             io_new_psw;               /* 0x1f0 */
 759     PSW             return_psw;               /* 0x200 */
 760     uint8_t         irb[64];                  /* 0x210 */
 761     uint64_t        sync_enter_timer;         /* 0x250 */
 762     uint64_t        async_enter_timer;        /* 0x258 */
 763     uint64_t        exit_timer;               /* 0x260 */
 764     uint64_t        last_update_timer;        /* 0x268 */
 765     uint64_t        user_timer;               /* 0x270 */
 766     uint64_t        system_timer;             /* 0x278 */
 767     uint64_t        last_update_clock;        /* 0x280 */
 768     uint64_t        steal_clock;              /* 0x288 */
 769     PSW             return_mcck_psw;          /* 0x290 */
 770     uint8_t         pad8[0xc00-0x2a0];        /* 0x2a0 */
 771     /* System info area */
 772     uint64_t        save_area[16];            /* 0xc00 */
 773     uint8_t         pad9[0xd40-0xc80];        /* 0xc80 */
 774     uint64_t        kernel_stack;             /* 0xd40 */
 775     uint64_t        thread_info;              /* 0xd48 */
 776     uint64_t        async_stack;              /* 0xd50 */
 777     uint64_t        kernel_asce;              /* 0xd58 */
 778     uint64_t        user_asce;                /* 0xd60 */
 779     uint64_t        panic_stack;              /* 0xd68 */
 780     uint64_t        user_exec_asce;           /* 0xd70 */
 781     uint8_t         pad10[0xdc0-0xd78];       /* 0xd78 */
 782
 783     /* SMP info area: defined by DJB */
 784     uint64_t        clock_comparator;         /* 0xdc0 */
 785     uint64_t        ext_call_fast;            /* 0xdc8 */
 786     uint64_t        percpu_offset;            /* 0xdd0 */
 787     uint64_t        current_task;             /* 0xdd8 */
 788     uint32_t        softirq_pending;          /* 0xde0 */
 789     uint32_t        pad_0x0de4;               /* 0xde4 */
 790     uint64_t        int_clock;                /* 0xde8 */
 791     uint8_t         pad12[0xe00-0xdf0];       /* 0xdf0 */
 792
 793     /* 0xe00 is used as indicator for dump tools */
 794     /* whether the kernel died with panic() or not */
 795     uint32_t        panic_magic;              /* 0xe00 */
 796
 797     uint8_t         pad13[0x11b8-0xe04];      /* 0xe04 */
 798
 799     /* 64 bit extparam used for pfault, diag 250 etc  */
 800     uint64_t        ext_params2;               /* 0x11B8 */
 801
 802     uint8_t         pad14[0x1200-0x11C0];      /* 0x11C0 */
 803
 804     /* System info area */
 805
 806     uint64_t        floating_pt_save_area[16]; /* 0x1200 */
 807     uint64_t        gpregs_save_area[16];      /* 0x1280 */
 808     uint32_t        st_status_fixed_logout[4]; /* 0x1300 */
 809     uint8_t         pad15[0x1318-0x1310];      /* 0x1310 */
 810     uint32_t        prefixreg_save_area;       /* 0x1318 */
 811     uint32_t        fpt_creg_save_area;        /* 0x131c */
 812     uint8_t         pad16[0x1324-0x1320];      /* 0x1320 */
 813     uint32_t        tod_progreg_save_area;     /* 0x1324 */
 814     uint32_t        cpu_timer_save_area[2];    /* 0x1328 */
 815     uint32_t        clock_comp_save_area[2];   /* 0x1330 */
 816     uint8_t         pad17[0x1340-0x1338];      /* 0x1338 */
 817     uint32_t        access_regs_save_area[16]; /* 0x1340 */
 818     uint64_t        cregs_save_area[16];       /* 0x1380 */
 819
 820     /* align to the top of the prefix area */
 821
 822     uint8_t         pad18[0x2000-0x1400];      /* 0x1400 */
 823 } QEMU_PACKED LowCore;
 824
 825 /* STSI */
 826 #define STSI_LEVEL_MASK         0x00000000f0000000ULL
 827 #define STSI_LEVEL_CURRENT      0x0000000000000000ULL
 828 #define STSI_LEVEL_1            0x0000000010000000ULL
 829 #define STSI_LEVEL_2            0x0000000020000000ULL
 830 #define STSI_LEVEL_3            0x0000000030000000ULL
 831 #define STSI_R0_RESERVED_MASK   0x000000000fffff00ULL
 832 #define STSI_R0_SEL1_MASK       0x00000000000000ffULL
 833 #define STSI_R1_RESERVED_MASK   0x00000000ffff0000ULL
 834 #define STSI_R1_SEL2_MASK       0x000000000000ffffULL
 835
 836 /* Basic Machine Configuration */
 837 struct sysib_111 {
 838     uint32_t res1[8];
 839     uint8_t  manuf[16];
 840     uint8_t  type[4];
 841     uint8_t  res2[12];
 842     uint8_t  model[16];
 843     uint8_t  sequence[16];
 844     uint8_t  plant[4];
 845     uint8_t  res3[156];
 846 };
 847
 848 /* Basic Machine CPU */
 849 struct sysib_121 {
 850     uint32_t res1[80];
 851     uint8_t  sequence[16];
 852     uint8_t  plant[4];
 853     uint8_t  res2[2];
 854     uint16_t cpu_addr;
 855     uint8_t  res3[152];
 856 };
 857
 858 /* Basic Machine CPUs */
 859 struct sysib_122 {
 860     uint8_t res1[32];
 861     uint32_t capability;
 862     uint16_t total_cpus;
 863     uint16_t active_cpus;
 864     uint16_t standby_cpus;
 865     uint16_t reserved_cpus;
 866     uint16_t adjustments[2026];
 867 };
 868
 869 /* LPAR CPU */
 870 struct sysib_221 {
 871     uint32_t res1[80];
 872     uint8_t  sequence[16];
 873     uint8_t  plant[4];
 874     uint16_t cpu_id;
 875     uint16_t cpu_addr;
 876     uint8_t  res3[152];
 877 };
 878
 879 /* LPAR CPUs */
 880 struct sysib_222 {
 881     uint32_t res1[32];
 882     uint16_t lpar_num;
 883     uint8_t  res2;
 884     uint8_t  lcpuc;
 885     uint16_t total_cpus;
 886     uint16_t conf_cpus;
 887     uint16_t standby_cpus;
 888     uint16_t reserved_cpus;
 889     uint8_t  name[8];
 890     uint32_t caf;
 891     uint8_t  res3[16];
 892     uint16_t dedicated_cpus;
 893     uint16_t shared_cpus;
 894     uint8_t  res4[180];
 895 };
 896
 897 /* VM CPUs */
 898 struct sysib_322 {
 899     uint8_t  res1[31];
 900     uint8_t  count;
 901     struct {
 902         uint8_t  res2[4];
 903         uint16_t total_cpus;
 904         uint16_t conf_cpus;
 905         uint16_t standby_cpus;
 906         uint16_t reserved_cpus;
 907         uint8_t  name[8];
 908         uint32_t caf;
 909         uint8_t  cpi[16];
 910         uint8_t  res3[24];
 911     } vm[8];
 912     uint8_t res4[3552];
 913 };
 914
 915 /* MMU defines */
 916 #define _ASCE_ORIGIN            ~0xfffULL /* segment table origin             */
 917 #define _ASCE_SUBSPACE          0x200     /* subspace group control           */
 918 #define _ASCE_PRIVATE_SPACE     0x100     /* private space control            */
 919 #define _ASCE_ALT_EVENT         0x80      /* storage alteration event control */
 920 #define _ASCE_SPACE_SWITCH      0x40      /* space switch event               */
 921 #define _ASCE_REAL_SPACE        0x20      /* real space control               */
 922 #define _ASCE_TYPE_MASK         0x0c      /* asce table type mask             */
 923 #define _ASCE_TYPE_REGION1      0x0c      /* region first table type          */
 924 #define _ASCE_TYPE_REGION2      0x08      /* region second table type         */
 925 #define _ASCE_TYPE_REGION3      0x04      /* region third table type          */
 926 #define _ASCE_TYPE_SEGMENT      0x00      /* segment table type               */
 927 #define _ASCE_TABLE_LENGTH      0x03      /* region table length              */
 928
 929 #define _REGION_ENTRY_ORIGIN    ~0xfffULL /* region/segment table origin      */
 930 #define _REGION_ENTRY_INV       0x20      /* invalid region table entry       */
 931 #define _REGION_ENTRY_TYPE_MASK 0x0c      /* region/segment table type mask   */
 932 #define _REGION_ENTRY_TYPE_R1   0x0c      /* region first table type          */
 933 #define _REGION_ENTRY_TYPE_R2   0x08      /* region second table type         */
 934 #define _REGION_ENTRY_TYPE_R3   0x04      /* region third table type          */
 935 #define _REGION_ENTRY_LENGTH    0x03      /* region third length              */
 936
 937 #define _SEGMENT_ENTRY_ORIGIN   ~0x7ffULL /* segment table origin             */
 938 #define _SEGMENT_ENTRY_RO       0x200     /* page protection bit              */
 939 #define _SEGMENT_ENTRY_INV      0x20      /* invalid segment table entry      */
 940
 941 #define _PAGE_RO        0x200            /* HW read-only bit  */
 942 #define _PAGE_INVALID   0x400            /* HW invalid bit    */
 943
 944 #define SK_C                    (0x1 << 1)
 945 #define SK_R                    (0x1 << 2)
 946 #define SK_F                    (0x1 << 3)
 947 #define SK_ACC_MASK             (0xf << 4)
 948
 949 #define SIGP_SENSE             0x01
 950 #define SIGP_EXTERNAL_CALL     0x02
 951 #define SIGP_EMERGENCY         0x03
 952 #define SIGP_START             0x04
 953 #define SIGP_STOP              0x05
 954 #define SIGP_RESTART           0x06
 955 #define SIGP_STOP_STORE_STATUS 0x09
 956 #define SIGP_INITIAL_CPU_RESET 0x0b
 957 #define SIGP_CPU_RESET         0x0c
 958 #define SIGP_SET_PREFIX        0x0d
 959 #define SIGP_STORE_STATUS_ADDR 0x0e
 960 #define SIGP_SET_ARCH          0x12
 961
 962 /* cpu status bits */
 963 #define SIGP_STAT_EQUIPMENT_CHECK   0x80000000UL
 964 #define SIGP_STAT_INCORRECT_STATE   0x00000200UL
 965 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
 966 #define SIGP_STAT_EXT_CALL_PENDING  0x00000080UL
 967 #define SIGP_STAT_STOPPED           0x00000040UL
 968 #define SIGP_STAT_OPERATOR_INTERV   0x00000020UL
 969 #define SIGP_STAT_CHECK_STOP        0x00000010UL
 970 #define SIGP_STAT_INOPERATIVE       0x00000004UL
 971 #define SIGP_STAT_INVALID_ORDER     0x00000002UL
 972 #define SIGP_STAT_RECEIVER_CHECK    0x00000001UL
 973
 974 void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
 975 int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
 976                   target_ulong *raddr, int *flags);
 977 int sclp_service_call(uint32_t sccb, uint64_t code);
 978 uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
 979                  uint64_t vr);
 980
 981 #define TARGET_HAS_ICE 1
 982
 983 /* The value of the TOD clock for 1.1.1970. */
 984 #define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
 985
 986 /* Converts ns to s390's clock format */
 987 static inline uint64_t time2tod(uint64_t ns) {
 988     return (ns << 9) / 125;
 989 }
 990
 991 static inline void cpu_inject_ext(S390CPU *cpu, uint32_t code, uint32_t param,
 992                                   uint64_t param64)
 993 {
 994     CPUS390XState *env = &cpu->env;
 995
 996     if (env->ext_index == MAX_EXT_QUEUE - 1) {
 997         /* ugh - can't queue anymore. Let's drop. */
 998         return;
 999     }
1000
1001     env->ext_index++;
1002     assert(env->ext_index < MAX_EXT_QUEUE);
1003
1004     env->ext_queue[env->ext_index].code = code;
1005     env->ext_queue[env->ext_index].param = param;
1006     env->ext_queue[env->ext_index].param64 = param64;
1007
1008     env->pending_int |= INTERRUPT_EXT;
1009     cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
1010 }
1011
1012 static inline void cpu_inject_io(S390CPU *cpu, uint16_t subchannel_id,
1013                                  uint16_t subchannel_number,
1014                                  uint32_t io_int_parm, uint32_t io_int_word)
1015 {
1016     CPUS390XState *env = &cpu->env;
1017     int isc = IO_INT_WORD_ISC(io_int_word);
1018
1019     if (env->io_index[isc] == MAX_IO_QUEUE - 1) {
1020         /* ugh - can't queue anymore. Let's drop. */
1021         return;
1022     }
1023
1024     env->io_index[isc]++;
1025     assert(env->io_index[isc] < MAX_IO_QUEUE);
1026
1027     env->io_queue[env->io_index[isc]][isc].id = subchannel_id;
1028     env->io_queue[env->io_index[isc]][isc].nr = subchannel_number;
1029     env->io_queue[env->io_index[isc]][isc].parm = io_int_parm;
1030     env->io_queue[env->io_index[isc]][isc].word = io_int_word;
1031
1032     env->pending_int |= INTERRUPT_IO;
1033     cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
1034 }
1035
1036 static inline void cpu_inject_crw_mchk(S390CPU *cpu)
1037 {
1038     CPUS390XState *env = &cpu->env;
1039
1040     if (env->mchk_index == MAX_MCHK_QUEUE - 1) {
1041         /* ugh - can't queue anymore. Let's drop. */
1042         return;
1043     }
1044
1045     env->mchk_index++;
1046     assert(env->mchk_index < MAX_MCHK_QUEUE);
1047
1048     env->mchk_queue[env->mchk_index].type = 1;
1049
1050     env->pending_int |= INTERRUPT_MCHK;
1051     cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
1052 }
1053
1054 static inline bool cpu_has_work(CPUState *cpu)
1055 {
1056     S390CPU *s390_cpu = S390_CPU(cpu);
1057     CPUS390XState *env = &s390_cpu->env;
1058
1059     return (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
1060         (env->psw.mask & PSW_MASK_EXT);
1061 }
1062
1063 static inline void cpu_pc_from_tb(CPUS390XState *env, TranslationBlock* tb)
1064 {
1065     env->psw.addr = tb->pc;
1066 }
1067
1068 /* fpu_helper.c */
1069 uint32_t set_cc_nz_f32(float32 v);
1070 uint32_t set_cc_nz_f64(float64 v);
1071 uint32_t set_cc_nz_f128(float128 v);
1072
1073 /* misc_helper.c */
1074 void program_interrupt(CPUS390XState *env, uint32_t code, int ilen);
1075 void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
1076                                      uintptr_t retaddr);
1077
1078 #include <sysemu/kvm.h>
1079
1080 #ifdef CONFIG_KVM
1081 void kvm_s390_io_interrupt(S390CPU *cpu, uint16_t subchannel_id,
1082                            uint16_t subchannel_nr, uint32_t io_int_parm,
1083                            uint32_t io_int_word);
1084 void kvm_s390_crw_mchk(S390CPU *cpu);
1085 void kvm_s390_enable_css_support(S390CPU *cpu);
1086 int kvm_s390_get_registers_partial(CPUState *cpu);
1087 #else
1088 static inline void kvm_s390_io_interrupt(S390CPU *cpu,
1089                                         uint16_t subchannel_id,
1090                                         uint16_t subchannel_nr,
1091                                         uint32_t io_int_parm,
1092                                         uint32_t io_int_word)
1093 {
1094 }
1095 static inline void kvm_s390_crw_mchk(S390CPU *cpu)
1096 {
1097 }
1098 static inline void kvm_s390_enable_css_support(S390CPU *cpu)
1099 {
1100 }
1101 static inline int kvm_s390_get_registers_partial(CPUState *cpu)
1102 {
1103     return -ENOSYS;
1104 }
1105 #endif
1106
1107 static inline void s390_io_interrupt(S390CPU *cpu,
1108                                      uint16_t subchannel_id,
1109                                      uint16_t subchannel_nr,
1110                                      uint32_t io_int_parm,
1111                                      uint32_t io_int_word)
1112 {
1113     if (kvm_enabled()) {
1114         kvm_s390_io_interrupt(cpu, subchannel_id, subchannel_nr, io_int_parm,
1115                               io_int_word);
1116     } else {
1117         cpu_inject_io(cpu, subchannel_id, subchannel_nr, io_int_parm,
1118                       io_int_word);
1119     }
1120 }
1121
1122 static inline void s390_crw_mchk(S390CPU *cpu)
1123 {
1124     if (kvm_enabled()) {
1125         kvm_s390_crw_mchk(cpu);
1126     } else {
1127         cpu_inject_crw_mchk(cpu);
1128     }
1129 }
1130
1131 #endif