2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * * Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * * Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * * Neither the name of the Open Source and Linux Lab nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 #include "qemu/osdep.h"
29 #include "qemu/units.h"
30 #include "qapi/error.h"
32 #include "sysemu/sysemu.h"
33 #include "hw/boards.h"
34 #include "hw/loader.h"
35 #include "hw/qdev-properties.h"
37 #include "exec/memory.h"
38 #include "exec/address-spaces.h"
39 #include "hw/char/serial.h"
41 #include "hw/sysbus.h"
42 #include "hw/block/flash.h"
43 #include "chardev/char.h"
44 #include "sysemu/device_tree.h"
45 #include "sysemu/reset.h"
46 #include "sysemu/runstate.h"
47 #include "qemu/error-report.h"
48 #include "qemu/option.h"
49 #include "bootparam.h"
50 #include "xtensa_memory.h"
51 #include "hw/xtensa/mx_pic.h"
52 #include "migration/vmstate.h"
54 typedef struct XtfpgaFlashDesc
{
61 typedef struct XtfpgaBoardDesc
{
62 const XtfpgaFlashDesc
*flash
;
67 typedef struct XtfpgaFpgaState
{
74 static void xtfpga_fpga_reset(void *opaque
)
76 XtfpgaFpgaState
*s
= opaque
;
82 static uint64_t xtfpga_fpga_read(void *opaque
, hwaddr addr
,
85 XtfpgaFpgaState
*s
= opaque
;
88 case 0x0: /*build date code*/
91 case 0x4: /*processor clock frequency, Hz*/
94 case 0x8: /*LEDs (off = 0, on = 1)*/
97 case 0xc: /*DIP switches (off = 0, on = 1)*/
103 static void xtfpga_fpga_write(void *opaque
, hwaddr addr
,
104 uint64_t val
, unsigned size
)
106 XtfpgaFpgaState
*s
= opaque
;
109 case 0x8: /*LEDs (off = 0, on = 1)*/
113 case 0x10: /*board reset*/
115 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
121 static const MemoryRegionOps xtfpga_fpga_ops
= {
122 .read
= xtfpga_fpga_read
,
123 .write
= xtfpga_fpga_write
,
124 .endianness
= DEVICE_NATIVE_ENDIAN
,
127 static XtfpgaFpgaState
*xtfpga_fpga_init(MemoryRegion
*address_space
,
128 hwaddr base
, uint32_t freq
)
130 XtfpgaFpgaState
*s
= g_malloc(sizeof(XtfpgaFpgaState
));
132 memory_region_init_io(&s
->iomem
, NULL
, &xtfpga_fpga_ops
, s
,
133 "xtfpga.fpga", 0x10000);
134 memory_region_add_subregion(address_space
, base
, &s
->iomem
);
136 xtfpga_fpga_reset(s
);
137 qemu_register_reset(xtfpga_fpga_reset
, s
);
141 static void xtfpga_net_init(MemoryRegion
*address_space
,
145 qemu_irq irq
, NICInfo
*nd
)
151 dev
= qdev_new("open_eth");
152 qdev_set_nic_properties(dev
, nd
);
154 s
= SYS_BUS_DEVICE(dev
);
155 sysbus_realize_and_unref(s
, &error_fatal
);
156 sysbus_connect_irq(s
, 0, irq
);
157 memory_region_add_subregion(address_space
, base
,
158 sysbus_mmio_get_region(s
, 0));
159 memory_region_add_subregion(address_space
, descriptors
,
160 sysbus_mmio_get_region(s
, 1));
162 ram
= g_malloc(sizeof(*ram
));
163 memory_region_init_ram_nomigrate(ram
, OBJECT(s
), "open_eth.ram", 16 * KiB
,
165 vmstate_register_ram_global(ram
);
166 memory_region_add_subregion(address_space
, buffers
, ram
);
169 static PFlashCFI01
*xtfpga_flash_init(MemoryRegion
*address_space
,
170 const XtfpgaBoardDesc
*board
,
171 DriveInfo
*dinfo
, int be
)
174 DeviceState
*dev
= qdev_new(TYPE_PFLASH_CFI01
);
176 qdev_prop_set_drive(dev
, "drive", blk_by_legacy_dinfo(dinfo
));
177 qdev_prop_set_uint32(dev
, "num-blocks",
178 board
->flash
->size
/ board
->flash
->sector_size
);
179 qdev_prop_set_uint64(dev
, "sector-length", board
->flash
->sector_size
);
180 qdev_prop_set_uint8(dev
, "width", 2);
181 qdev_prop_set_bit(dev
, "big-endian", be
);
182 qdev_prop_set_string(dev
, "name", "xtfpga.io.flash");
183 s
= SYS_BUS_DEVICE(dev
);
184 sysbus_realize_and_unref(s
, &error_fatal
);
185 memory_region_add_subregion(address_space
, board
->flash
->base
,
186 sysbus_mmio_get_region(s
, 0));
187 return PFLASH_CFI01(dev
);
190 static uint64_t translate_phys_addr(void *opaque
, uint64_t addr
)
192 XtensaCPU
*cpu
= opaque
;
194 return cpu_get_phys_page_debug(CPU(cpu
), addr
);
197 static void xtfpga_reset(void *opaque
)
199 XtensaCPU
*cpu
= opaque
;
204 static uint64_t xtfpga_io_read(void *opaque
, hwaddr addr
,
210 static void xtfpga_io_write(void *opaque
, hwaddr addr
,
211 uint64_t val
, unsigned size
)
215 static const MemoryRegionOps xtfpga_io_ops
= {
216 .read
= xtfpga_io_read
,
217 .write
= xtfpga_io_write
,
218 .endianness
= DEVICE_NATIVE_ENDIAN
,
221 static void xtfpga_init(const XtfpgaBoardDesc
*board
, MachineState
*machine
)
223 #ifdef TARGET_WORDS_BIGENDIAN
228 MemoryRegion
*system_memory
= get_system_memory();
229 XtensaCPU
*cpu
= NULL
;
230 CPUXtensaState
*env
= NULL
;
231 MemoryRegion
*system_io
;
232 XtensaMxPic
*mx_pic
= NULL
;
235 PFlashCFI01
*flash
= NULL
;
236 const char *kernel_filename
= machine
->kernel_filename
;
237 const char *kernel_cmdline
= machine
->kernel_cmdline
;
238 const char *dtb_filename
= machine
->dtb
;
239 const char *initrd_filename
= machine
->initrd_filename
;
240 const unsigned system_io_size
= 224 * MiB
;
241 uint32_t freq
= 10000000;
243 unsigned int smp_cpus
= machine
->smp
.cpus
;
246 mx_pic
= xtensa_mx_pic_init(31);
247 qemu_register_reset(xtensa_mx_pic_reset
, mx_pic
);
249 for (n
= 0; n
< smp_cpus
; n
++) {
250 CPUXtensaState
*cenv
= NULL
;
252 cpu
= XTENSA_CPU(cpu_create(machine
->cpu_type
));
256 freq
= env
->config
->clock_freq_khz
* 1000;
260 MemoryRegion
*mx_eri
;
262 mx_eri
= xtensa_mx_pic_register_cpu(mx_pic
,
263 xtensa_get_extints(cenv
),
264 xtensa_get_runstall(cenv
));
265 memory_region_add_subregion(xtensa_get_er_region(cenv
),
268 cenv
->sregs
[PRID
] = n
;
269 xtensa_select_static_vectors(cenv
, n
!= 0);
270 qemu_register_reset(xtfpga_reset
, cpu
);
271 /* Need MMU initialized prior to ELF loading,
272 * so that ELF gets loaded into virtual addresses
277 extints
= xtensa_mx_pic_get_extints(mx_pic
);
279 extints
= xtensa_get_extints(env
);
283 XtensaMemory sysram
= env
->config
->sysram
;
285 sysram
.location
[0].size
= machine
->ram_size
;
286 xtensa_create_memory_regions(&env
->config
->instrom
, "xtensa.instrom",
288 xtensa_create_memory_regions(&env
->config
->instram
, "xtensa.instram",
290 xtensa_create_memory_regions(&env
->config
->datarom
, "xtensa.datarom",
292 xtensa_create_memory_regions(&env
->config
->dataram
, "xtensa.dataram",
294 xtensa_create_memory_regions(&sysram
, "xtensa.sysram",
298 system_io
= g_malloc(sizeof(*system_io
));
299 memory_region_init_io(system_io
, NULL
, &xtfpga_io_ops
, NULL
, "xtfpga.io",
301 memory_region_add_subregion(system_memory
, board
->io
[0], system_io
);
303 MemoryRegion
*io
= g_malloc(sizeof(*io
));
305 memory_region_init_alias(io
, NULL
, "xtfpga.io.cached",
306 system_io
, 0, system_io_size
);
307 memory_region_add_subregion(system_memory
, board
->io
[1], io
);
309 xtfpga_fpga_init(system_io
, 0x0d020000, freq
);
310 if (nd_table
[0].used
) {
311 xtfpga_net_init(system_io
, 0x0d030000, 0x0d030400, 0x0d800000,
312 extints
[1], nd_table
);
315 serial_mm_init(system_io
, 0x0d050020, 2, extints
[0],
316 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN
);
318 dinfo
= drive_get(IF_PFLASH
, 0, 0);
320 flash
= xtfpga_flash_init(system_io
, board
, dinfo
, be
);
323 /* Use presence of kernel file name as 'boot from SRAM' switch. */
324 if (kernel_filename
) {
325 uint32_t entry_point
= env
->pc
;
326 size_t bp_size
= 3 * get_tag_size(0); /* first/last and memory tags */
327 uint32_t tagptr
= env
->config
->sysrom
.location
[0].addr
+
330 BpMemInfo memory_location
= {
331 .type
= tswap32(MEMORY_TYPE_CONVENTIONAL
),
332 .start
= tswap32(env
->config
->sysram
.location
[0].addr
),
333 .end
= tswap32(env
->config
->sysram
.location
[0].addr
+
336 uint32_t lowmem_end
= machine
->ram_size
< 0x08000000 ?
337 machine
->ram_size
: 0x08000000;
338 uint32_t cur_lowmem
= QEMU_ALIGN_UP(lowmem_end
/ 2, 4096);
340 lowmem_end
+= env
->config
->sysram
.location
[0].addr
;
341 cur_lowmem
+= env
->config
->sysram
.location
[0].addr
;
343 xtensa_create_memory_regions(&env
->config
->sysrom
, "xtensa.sysrom",
346 if (kernel_cmdline
) {
347 bp_size
+= get_tag_size(strlen(kernel_cmdline
) + 1);
350 bp_size
+= get_tag_size(sizeof(uint32_t));
352 if (initrd_filename
) {
353 bp_size
+= get_tag_size(sizeof(BpMemInfo
));
356 /* Put kernel bootparameters to the end of that SRAM */
357 tagptr
= (tagptr
- bp_size
) & ~0xff;
358 cur_tagptr
= put_tag(tagptr
, BP_TAG_FIRST
, 0, NULL
);
359 cur_tagptr
= put_tag(cur_tagptr
, BP_TAG_MEMORY
,
360 sizeof(memory_location
), &memory_location
);
362 if (kernel_cmdline
) {
363 cur_tagptr
= put_tag(cur_tagptr
, BP_TAG_COMMAND_LINE
,
364 strlen(kernel_cmdline
) + 1, kernel_cmdline
);
369 void *fdt
= load_device_tree(dtb_filename
, &fdt_size
);
370 uint32_t dtb_addr
= tswap32(cur_lowmem
);
373 error_report("could not load DTB '%s'", dtb_filename
);
377 cpu_physical_memory_write(cur_lowmem
, fdt
, fdt_size
);
378 cur_tagptr
= put_tag(cur_tagptr
, BP_TAG_FDT
,
379 sizeof(dtb_addr
), &dtb_addr
);
380 cur_lowmem
= QEMU_ALIGN_UP(cur_lowmem
+ fdt_size
, 4 * KiB
);
385 error_report("could not load DTB '%s': "
386 "FDT support is not configured in QEMU",
391 if (initrd_filename
) {
392 BpMemInfo initrd_location
= { 0 };
393 int initrd_size
= load_ramdisk(initrd_filename
, cur_lowmem
,
394 lowmem_end
- cur_lowmem
);
396 if (initrd_size
< 0) {
397 initrd_size
= load_image_targphys(initrd_filename
,
399 lowmem_end
- cur_lowmem
);
401 if (initrd_size
< 0) {
402 error_report("could not load initrd '%s'", initrd_filename
);
405 initrd_location
.start
= tswap32(cur_lowmem
);
406 initrd_location
.end
= tswap32(cur_lowmem
+ initrd_size
);
407 cur_tagptr
= put_tag(cur_tagptr
, BP_TAG_INITRD
,
408 sizeof(initrd_location
), &initrd_location
);
409 cur_lowmem
= QEMU_ALIGN_UP(cur_lowmem
+ initrd_size
, 4 * KiB
);
411 cur_tagptr
= put_tag(cur_tagptr
, BP_TAG_LAST
, 0, NULL
);
412 env
->regs
[2] = tagptr
;
415 int success
= load_elf(kernel_filename
, NULL
, translate_phys_addr
, cpu
,
416 &elf_entry
, NULL
, NULL
, NULL
, be
, EM_XTENSA
, 0, 0);
418 entry_point
= elf_entry
;
422 success
= load_uimage(kernel_filename
, &ep
, NULL
, &is_linux
,
423 translate_phys_addr
, cpu
);
424 if (success
> 0 && is_linux
) {
427 error_report("could not load kernel '%s'",
432 if (entry_point
!= env
->pc
) {
434 #ifdef TARGET_WORDS_BIGENDIAN
435 0x60, 0x00, 0x08, /* j 1f */
436 0x00, /* .literal_position */
437 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */
438 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */
440 0x10, 0xff, 0xfe, /* l32r a0, entry_pc */
441 0x12, 0xff, 0xfe, /* l32r a2, entry_a2 */
442 0x0a, 0x00, 0x00, /* jx a0 */
444 0x06, 0x02, 0x00, /* j 1f */
445 0x00, /* .literal_position */
446 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */
447 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */
449 0x01, 0xfe, 0xff, /* l32r a0, entry_pc */
450 0x21, 0xfe, 0xff, /* l32r a2, entry_a2 */
451 0xa0, 0x00, 0x00, /* jx a0 */
454 uint32_t entry_pc
= tswap32(entry_point
);
455 uint32_t entry_a2
= tswap32(tagptr
);
457 memcpy(boot
+ 4, &entry_pc
, sizeof(entry_pc
));
458 memcpy(boot
+ 8, &entry_a2
, sizeof(entry_a2
));
459 cpu_physical_memory_write(env
->pc
, boot
, sizeof(boot
));
463 MemoryRegion
*flash_mr
= pflash_cfi01_get_memory(flash
);
464 MemoryRegion
*flash_io
= g_malloc(sizeof(*flash_io
));
465 uint32_t size
= env
->config
->sysrom
.location
[0].size
;
467 if (board
->flash
->size
- board
->flash
->boot_base
< size
) {
468 size
= board
->flash
->size
- board
->flash
->boot_base
;
471 memory_region_init_alias(flash_io
, NULL
, "xtfpga.flash",
472 flash_mr
, board
->flash
->boot_base
, size
);
473 memory_region_add_subregion(system_memory
,
474 env
->config
->sysrom
.location
[0].addr
,
477 xtensa_create_memory_regions(&env
->config
->sysrom
, "xtensa.sysrom",
483 #define XTFPGA_MMU_RESERVED_MEMORY_SIZE (128 * MiB)
485 static const hwaddr xtfpga_mmu_io
[2] = {
489 static const hwaddr xtfpga_nommu_io
[2] = {
494 static const XtfpgaFlashDesc lx60_flash
= {
497 .sector_size
= 0x10000,
500 static void xtfpga_lx60_init(MachineState
*machine
)
502 static const XtfpgaBoardDesc lx60_board
= {
503 .flash
= &lx60_flash
,
504 .sram_size
= 0x20000,
507 xtfpga_init(&lx60_board
, machine
);
510 static void xtfpga_lx60_nommu_init(MachineState
*machine
)
512 static const XtfpgaBoardDesc lx60_board
= {
513 .flash
= &lx60_flash
,
514 .sram_size
= 0x20000,
515 .io
= xtfpga_nommu_io
,
517 xtfpga_init(&lx60_board
, machine
);
520 static const XtfpgaFlashDesc lx200_flash
= {
523 .sector_size
= 0x20000,
526 static void xtfpga_lx200_init(MachineState
*machine
)
528 static const XtfpgaBoardDesc lx200_board
= {
529 .flash
= &lx200_flash
,
530 .sram_size
= 0x2000000,
533 xtfpga_init(&lx200_board
, machine
);
536 static void xtfpga_lx200_nommu_init(MachineState
*machine
)
538 static const XtfpgaBoardDesc lx200_board
= {
539 .flash
= &lx200_flash
,
540 .sram_size
= 0x2000000,
541 .io
= xtfpga_nommu_io
,
543 xtfpga_init(&lx200_board
, machine
);
546 static const XtfpgaFlashDesc ml605_flash
= {
549 .sector_size
= 0x20000,
552 static void xtfpga_ml605_init(MachineState
*machine
)
554 static const XtfpgaBoardDesc ml605_board
= {
555 .flash
= &ml605_flash
,
556 .sram_size
= 0x2000000,
559 xtfpga_init(&ml605_board
, machine
);
562 static void xtfpga_ml605_nommu_init(MachineState
*machine
)
564 static const XtfpgaBoardDesc ml605_board
= {
565 .flash
= &ml605_flash
,
566 .sram_size
= 0x2000000,
567 .io
= xtfpga_nommu_io
,
569 xtfpga_init(&ml605_board
, machine
);
572 static const XtfpgaFlashDesc kc705_flash
= {
575 .boot_base
= 0x06000000,
576 .sector_size
= 0x20000,
579 static void xtfpga_kc705_init(MachineState
*machine
)
581 static const XtfpgaBoardDesc kc705_board
= {
582 .flash
= &kc705_flash
,
583 .sram_size
= 0x2000000,
586 xtfpga_init(&kc705_board
, machine
);
589 static void xtfpga_kc705_nommu_init(MachineState
*machine
)
591 static const XtfpgaBoardDesc kc705_board
= {
592 .flash
= &kc705_flash
,
593 .sram_size
= 0x2000000,
594 .io
= xtfpga_nommu_io
,
596 xtfpga_init(&kc705_board
, machine
);
599 static void xtfpga_lx60_class_init(ObjectClass
*oc
, void *data
)
601 MachineClass
*mc
= MACHINE_CLASS(oc
);
603 mc
->desc
= "lx60 EVB (" XTENSA_DEFAULT_CPU_MODEL
")";
604 mc
->init
= xtfpga_lx60_init
;
606 mc
->default_cpu_type
= XTENSA_DEFAULT_CPU_TYPE
;
607 mc
->default_ram_size
= 64 * MiB
;
610 static const TypeInfo xtfpga_lx60_type
= {
611 .name
= MACHINE_TYPE_NAME("lx60"),
612 .parent
= TYPE_MACHINE
,
613 .class_init
= xtfpga_lx60_class_init
,
616 static void xtfpga_lx60_nommu_class_init(ObjectClass
*oc
, void *data
)
618 MachineClass
*mc
= MACHINE_CLASS(oc
);
620 mc
->desc
= "lx60 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL
")";
621 mc
->init
= xtfpga_lx60_nommu_init
;
623 mc
->default_cpu_type
= XTENSA_DEFAULT_CPU_NOMMU_TYPE
;
624 mc
->default_ram_size
= 64 * MiB
;
627 static const TypeInfo xtfpga_lx60_nommu_type
= {
628 .name
= MACHINE_TYPE_NAME("lx60-nommu"),
629 .parent
= TYPE_MACHINE
,
630 .class_init
= xtfpga_lx60_nommu_class_init
,
633 static void xtfpga_lx200_class_init(ObjectClass
*oc
, void *data
)
635 MachineClass
*mc
= MACHINE_CLASS(oc
);
637 mc
->desc
= "lx200 EVB (" XTENSA_DEFAULT_CPU_MODEL
")";
638 mc
->init
= xtfpga_lx200_init
;
640 mc
->default_cpu_type
= XTENSA_DEFAULT_CPU_TYPE
;
641 mc
->default_ram_size
= 96 * MiB
;
644 static const TypeInfo xtfpga_lx200_type
= {
645 .name
= MACHINE_TYPE_NAME("lx200"),
646 .parent
= TYPE_MACHINE
,
647 .class_init
= xtfpga_lx200_class_init
,
650 static void xtfpga_lx200_nommu_class_init(ObjectClass
*oc
, void *data
)
652 MachineClass
*mc
= MACHINE_CLASS(oc
);
654 mc
->desc
= "lx200 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL
")";
655 mc
->init
= xtfpga_lx200_nommu_init
;
657 mc
->default_cpu_type
= XTENSA_DEFAULT_CPU_NOMMU_TYPE
;
658 mc
->default_ram_size
= 96 * MiB
;
661 static const TypeInfo xtfpga_lx200_nommu_type
= {
662 .name
= MACHINE_TYPE_NAME("lx200-nommu"),
663 .parent
= TYPE_MACHINE
,
664 .class_init
= xtfpga_lx200_nommu_class_init
,
667 static void xtfpga_ml605_class_init(ObjectClass
*oc
, void *data
)
669 MachineClass
*mc
= MACHINE_CLASS(oc
);
671 mc
->desc
= "ml605 EVB (" XTENSA_DEFAULT_CPU_MODEL
")";
672 mc
->init
= xtfpga_ml605_init
;
674 mc
->default_cpu_type
= XTENSA_DEFAULT_CPU_TYPE
;
675 mc
->default_ram_size
= 512 * MiB
- XTFPGA_MMU_RESERVED_MEMORY_SIZE
;
678 static const TypeInfo xtfpga_ml605_type
= {
679 .name
= MACHINE_TYPE_NAME("ml605"),
680 .parent
= TYPE_MACHINE
,
681 .class_init
= xtfpga_ml605_class_init
,
684 static void xtfpga_ml605_nommu_class_init(ObjectClass
*oc
, void *data
)
686 MachineClass
*mc
= MACHINE_CLASS(oc
);
688 mc
->desc
= "ml605 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL
")";
689 mc
->init
= xtfpga_ml605_nommu_init
;
691 mc
->default_cpu_type
= XTENSA_DEFAULT_CPU_NOMMU_TYPE
;
692 mc
->default_ram_size
= 256 * MiB
;
695 static const TypeInfo xtfpga_ml605_nommu_type
= {
696 .name
= MACHINE_TYPE_NAME("ml605-nommu"),
697 .parent
= TYPE_MACHINE
,
698 .class_init
= xtfpga_ml605_nommu_class_init
,
701 static void xtfpga_kc705_class_init(ObjectClass
*oc
, void *data
)
703 MachineClass
*mc
= MACHINE_CLASS(oc
);
705 mc
->desc
= "kc705 EVB (" XTENSA_DEFAULT_CPU_MODEL
")";
706 mc
->init
= xtfpga_kc705_init
;
708 mc
->default_cpu_type
= XTENSA_DEFAULT_CPU_TYPE
;
709 mc
->default_ram_size
= 1 * GiB
- XTFPGA_MMU_RESERVED_MEMORY_SIZE
;
712 static const TypeInfo xtfpga_kc705_type
= {
713 .name
= MACHINE_TYPE_NAME("kc705"),
714 .parent
= TYPE_MACHINE
,
715 .class_init
= xtfpga_kc705_class_init
,
718 static void xtfpga_kc705_nommu_class_init(ObjectClass
*oc
, void *data
)
720 MachineClass
*mc
= MACHINE_CLASS(oc
);
722 mc
->desc
= "kc705 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL
")";
723 mc
->init
= xtfpga_kc705_nommu_init
;
725 mc
->default_cpu_type
= XTENSA_DEFAULT_CPU_NOMMU_TYPE
;
726 mc
->default_ram_size
= 256 * MiB
;
729 static const TypeInfo xtfpga_kc705_nommu_type
= {
730 .name
= MACHINE_TYPE_NAME("kc705-nommu"),
731 .parent
= TYPE_MACHINE
,
732 .class_init
= xtfpga_kc705_nommu_class_init
,
735 static void xtfpga_machines_init(void)
737 type_register_static(&xtfpga_lx60_type
);
738 type_register_static(&xtfpga_lx200_type
);
739 type_register_static(&xtfpga_ml605_type
);
740 type_register_static(&xtfpga_kc705_type
);
741 type_register_static(&xtfpga_lx60_nommu_type
);
742 type_register_static(&xtfpga_lx200_nommu_type
);
743 type_register_static(&xtfpga_ml605_nommu_type
);
744 type_register_static(&xtfpga_kc705_nommu_type
);
747 type_init(xtfpga_machines_init
)