2 * QEMU emulation of an Intel IOMMU (VT-d)
3 * (DMA Remapping device)
5 * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com>
6 * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 #include "qemu/osdep.h"
23 #include "qemu/error-report.h"
24 #include "qemu/main-loop.h"
25 #include "qapi/error.h"
26 #include "hw/sysbus.h"
27 #include "exec/address-spaces.h"
28 #include "intel_iommu_internal.h"
29 #include "hw/pci/pci.h"
30 #include "hw/pci/pci_bus.h"
31 #include "hw/qdev-properties.h"
32 #include "hw/i386/pc.h"
33 #include "hw/i386/apic-msidef.h"
34 #include "hw/boards.h"
35 #include "hw/i386/x86-iommu.h"
36 #include "hw/pci-host/q35.h"
37 #include "sysemu/kvm.h"
38 #include "sysemu/sysemu.h"
39 #include "hw/i386/apic_internal.h"
41 #include "migration/vmstate.h"
44 /* context entry operations */
45 #define VTD_CE_GET_RID2PASID(ce) \
46 ((ce)->val[1] & VTD_SM_CONTEXT_ENTRY_RID2PASID_MASK)
47 #define VTD_CE_GET_PASID_DIR_TABLE(ce) \
48 ((ce)->val[0] & VTD_PASID_DIR_BASE_ADDR_MASK)
51 #define VTD_PE_GET_TYPE(pe) ((pe)->val[0] & VTD_SM_PASID_ENTRY_PGTT)
52 #define VTD_PE_GET_LEVEL(pe) (2 + (((pe)->val[0] >> 2) & VTD_SM_PASID_ENTRY_AW))
53 #define VTD_PE_GET_FPD_ERR(ret_fr, is_fpd_set, s, source_id, addr, is_write) {\
56 if (is_fpd_set && vtd_is_qualified_fault(ret_fr)) { \
57 trace_vtd_fault_disabled(); \
59 vtd_report_dmar_fault(s, source_id, addr, ret_fr, is_write); \
65 static void vtd_address_space_refresh_all(IntelIOMMUState
*s
);
66 static void vtd_address_space_unmap(VTDAddressSpace
*as
, IOMMUNotifier
*n
);
68 static void vtd_panic_require_caching_mode(void)
70 error_report("We need to set caching-mode=on for intel-iommu to enable "
71 "device assignment with IOMMU protection.");
75 static void vtd_define_quad(IntelIOMMUState
*s
, hwaddr addr
, uint64_t val
,
76 uint64_t wmask
, uint64_t w1cmask
)
78 stq_le_p(&s
->csr
[addr
], val
);
79 stq_le_p(&s
->wmask
[addr
], wmask
);
80 stq_le_p(&s
->w1cmask
[addr
], w1cmask
);
83 static void vtd_define_quad_wo(IntelIOMMUState
*s
, hwaddr addr
, uint64_t mask
)
85 stq_le_p(&s
->womask
[addr
], mask
);
88 static void vtd_define_long(IntelIOMMUState
*s
, hwaddr addr
, uint32_t val
,
89 uint32_t wmask
, uint32_t w1cmask
)
91 stl_le_p(&s
->csr
[addr
], val
);
92 stl_le_p(&s
->wmask
[addr
], wmask
);
93 stl_le_p(&s
->w1cmask
[addr
], w1cmask
);
96 static void vtd_define_long_wo(IntelIOMMUState
*s
, hwaddr addr
, uint32_t mask
)
98 stl_le_p(&s
->womask
[addr
], mask
);
101 /* "External" get/set operations */
102 static void vtd_set_quad(IntelIOMMUState
*s
, hwaddr addr
, uint64_t val
)
104 uint64_t oldval
= ldq_le_p(&s
->csr
[addr
]);
105 uint64_t wmask
= ldq_le_p(&s
->wmask
[addr
]);
106 uint64_t w1cmask
= ldq_le_p(&s
->w1cmask
[addr
]);
107 stq_le_p(&s
->csr
[addr
],
108 ((oldval
& ~wmask
) | (val
& wmask
)) & ~(w1cmask
& val
));
111 static void vtd_set_long(IntelIOMMUState
*s
, hwaddr addr
, uint32_t val
)
113 uint32_t oldval
= ldl_le_p(&s
->csr
[addr
]);
114 uint32_t wmask
= ldl_le_p(&s
->wmask
[addr
]);
115 uint32_t w1cmask
= ldl_le_p(&s
->w1cmask
[addr
]);
116 stl_le_p(&s
->csr
[addr
],
117 ((oldval
& ~wmask
) | (val
& wmask
)) & ~(w1cmask
& val
));
120 static uint64_t vtd_get_quad(IntelIOMMUState
*s
, hwaddr addr
)
122 uint64_t val
= ldq_le_p(&s
->csr
[addr
]);
123 uint64_t womask
= ldq_le_p(&s
->womask
[addr
]);
124 return val
& ~womask
;
127 static uint32_t vtd_get_long(IntelIOMMUState
*s
, hwaddr addr
)
129 uint32_t val
= ldl_le_p(&s
->csr
[addr
]);
130 uint32_t womask
= ldl_le_p(&s
->womask
[addr
]);
131 return val
& ~womask
;
134 /* "Internal" get/set operations */
135 static uint64_t vtd_get_quad_raw(IntelIOMMUState
*s
, hwaddr addr
)
137 return ldq_le_p(&s
->csr
[addr
]);
140 static uint32_t vtd_get_long_raw(IntelIOMMUState
*s
, hwaddr addr
)
142 return ldl_le_p(&s
->csr
[addr
]);
145 static void vtd_set_quad_raw(IntelIOMMUState
*s
, hwaddr addr
, uint64_t val
)
147 stq_le_p(&s
->csr
[addr
], val
);
150 static uint32_t vtd_set_clear_mask_long(IntelIOMMUState
*s
, hwaddr addr
,
151 uint32_t clear
, uint32_t mask
)
153 uint32_t new_val
= (ldl_le_p(&s
->csr
[addr
]) & ~clear
) | mask
;
154 stl_le_p(&s
->csr
[addr
], new_val
);
158 static uint64_t vtd_set_clear_mask_quad(IntelIOMMUState
*s
, hwaddr addr
,
159 uint64_t clear
, uint64_t mask
)
161 uint64_t new_val
= (ldq_le_p(&s
->csr
[addr
]) & ~clear
) | mask
;
162 stq_le_p(&s
->csr
[addr
], new_val
);
166 static inline void vtd_iommu_lock(IntelIOMMUState
*s
)
168 qemu_mutex_lock(&s
->iommu_lock
);
171 static inline void vtd_iommu_unlock(IntelIOMMUState
*s
)
173 qemu_mutex_unlock(&s
->iommu_lock
);
176 static void vtd_update_scalable_state(IntelIOMMUState
*s
)
178 uint64_t val
= vtd_get_quad_raw(s
, DMAR_RTADDR_REG
);
180 if (s
->scalable_mode
) {
181 s
->root_scalable
= val
& VTD_RTADDR_SMT
;
185 /* Whether the address space needs to notify new mappings */
186 static inline gboolean
vtd_as_has_map_notifier(VTDAddressSpace
*as
)
188 return as
->notifier_flags
& IOMMU_NOTIFIER_MAP
;
191 /* GHashTable functions */
192 static gboolean
vtd_uint64_equal(gconstpointer v1
, gconstpointer v2
)
194 return *((const uint64_t *)v1
) == *((const uint64_t *)v2
);
197 static guint
vtd_uint64_hash(gconstpointer v
)
199 return (guint
)*(const uint64_t *)v
;
202 static gboolean
vtd_hash_remove_by_domain(gpointer key
, gpointer value
,
205 VTDIOTLBEntry
*entry
= (VTDIOTLBEntry
*)value
;
206 uint16_t domain_id
= *(uint16_t *)user_data
;
207 return entry
->domain_id
== domain_id
;
210 /* The shift of an addr for a certain level of paging structure */
211 static inline uint32_t vtd_slpt_level_shift(uint32_t level
)
214 return VTD_PAGE_SHIFT_4K
+ (level
- 1) * VTD_SL_LEVEL_BITS
;
217 static inline uint64_t vtd_slpt_level_page_mask(uint32_t level
)
219 return ~((1ULL << vtd_slpt_level_shift(level
)) - 1);
222 static gboolean
vtd_hash_remove_by_page(gpointer key
, gpointer value
,
225 VTDIOTLBEntry
*entry
= (VTDIOTLBEntry
*)value
;
226 VTDIOTLBPageInvInfo
*info
= (VTDIOTLBPageInvInfo
*)user_data
;
227 uint64_t gfn
= (info
->addr
>> VTD_PAGE_SHIFT_4K
) & info
->mask
;
228 uint64_t gfn_tlb
= (info
->addr
& entry
->mask
) >> VTD_PAGE_SHIFT_4K
;
229 return (entry
->domain_id
== info
->domain_id
) &&
230 (((entry
->gfn
& info
->mask
) == gfn
) ||
231 (entry
->gfn
== gfn_tlb
));
234 /* Reset all the gen of VTDAddressSpace to zero and set the gen of
235 * IntelIOMMUState to 1. Must be called with IOMMU lock held.
237 static void vtd_reset_context_cache_locked(IntelIOMMUState
*s
)
239 VTDAddressSpace
*vtd_as
;
241 GHashTableIter bus_it
;
244 trace_vtd_context_cache_reset();
246 g_hash_table_iter_init(&bus_it
, s
->vtd_as_by_busptr
);
248 while (g_hash_table_iter_next (&bus_it
, NULL
, (void**)&vtd_bus
)) {
249 for (devfn_it
= 0; devfn_it
< PCI_DEVFN_MAX
; ++devfn_it
) {
250 vtd_as
= vtd_bus
->dev_as
[devfn_it
];
254 vtd_as
->context_cache_entry
.context_cache_gen
= 0;
257 s
->context_cache_gen
= 1;
260 /* Must be called with IOMMU lock held. */
261 static void vtd_reset_iotlb_locked(IntelIOMMUState
*s
)
264 g_hash_table_remove_all(s
->iotlb
);
267 static void vtd_reset_iotlb(IntelIOMMUState
*s
)
270 vtd_reset_iotlb_locked(s
);
274 static void vtd_reset_caches(IntelIOMMUState
*s
)
277 vtd_reset_iotlb_locked(s
);
278 vtd_reset_context_cache_locked(s
);
282 static uint64_t vtd_get_iotlb_key(uint64_t gfn
, uint16_t source_id
,
285 return gfn
| ((uint64_t)(source_id
) << VTD_IOTLB_SID_SHIFT
) |
286 ((uint64_t)(level
) << VTD_IOTLB_LVL_SHIFT
);
289 static uint64_t vtd_get_iotlb_gfn(hwaddr addr
, uint32_t level
)
291 return (addr
& vtd_slpt_level_page_mask(level
)) >> VTD_PAGE_SHIFT_4K
;
294 /* Must be called with IOMMU lock held */
295 static VTDIOTLBEntry
*vtd_lookup_iotlb(IntelIOMMUState
*s
, uint16_t source_id
,
298 VTDIOTLBEntry
*entry
;
302 for (level
= VTD_SL_PT_LEVEL
; level
< VTD_SL_PML4_LEVEL
; level
++) {
303 key
= vtd_get_iotlb_key(vtd_get_iotlb_gfn(addr
, level
),
305 entry
= g_hash_table_lookup(s
->iotlb
, &key
);
315 /* Must be with IOMMU lock held */
316 static void vtd_update_iotlb(IntelIOMMUState
*s
, uint16_t source_id
,
317 uint16_t domain_id
, hwaddr addr
, uint64_t slpte
,
318 uint8_t access_flags
, uint32_t level
)
320 VTDIOTLBEntry
*entry
= g_malloc(sizeof(*entry
));
321 uint64_t *key
= g_malloc(sizeof(*key
));
322 uint64_t gfn
= vtd_get_iotlb_gfn(addr
, level
);
324 trace_vtd_iotlb_page_update(source_id
, addr
, slpte
, domain_id
);
325 if (g_hash_table_size(s
->iotlb
) >= VTD_IOTLB_MAX_SIZE
) {
326 trace_vtd_iotlb_reset("iotlb exceeds size limit");
327 vtd_reset_iotlb_locked(s
);
331 entry
->domain_id
= domain_id
;
332 entry
->slpte
= slpte
;
333 entry
->access_flags
= access_flags
;
334 entry
->mask
= vtd_slpt_level_page_mask(level
);
335 *key
= vtd_get_iotlb_key(gfn
, source_id
, level
);
336 g_hash_table_replace(s
->iotlb
, key
, entry
);
339 /* Given the reg addr of both the message data and address, generate an
342 static void vtd_generate_interrupt(IntelIOMMUState
*s
, hwaddr mesg_addr_reg
,
343 hwaddr mesg_data_reg
)
347 assert(mesg_data_reg
< DMAR_REG_SIZE
);
348 assert(mesg_addr_reg
< DMAR_REG_SIZE
);
350 msi
.address
= vtd_get_long_raw(s
, mesg_addr_reg
);
351 msi
.data
= vtd_get_long_raw(s
, mesg_data_reg
);
353 trace_vtd_irq_generate(msi
.address
, msi
.data
);
355 apic_get_class()->send_msi(&msi
);
358 /* Generate a fault event to software via MSI if conditions are met.
359 * Notice that the value of FSTS_REG being passed to it should be the one
362 static void vtd_generate_fault_event(IntelIOMMUState
*s
, uint32_t pre_fsts
)
364 if (pre_fsts
& VTD_FSTS_PPF
|| pre_fsts
& VTD_FSTS_PFO
||
365 pre_fsts
& VTD_FSTS_IQE
) {
366 error_report_once("There are previous interrupt conditions "
367 "to be serviced by software, fault event "
371 vtd_set_clear_mask_long(s
, DMAR_FECTL_REG
, 0, VTD_FECTL_IP
);
372 if (vtd_get_long_raw(s
, DMAR_FECTL_REG
) & VTD_FECTL_IM
) {
373 error_report_once("Interrupt Mask set, irq is not generated");
375 vtd_generate_interrupt(s
, DMAR_FEADDR_REG
, DMAR_FEDATA_REG
);
376 vtd_set_clear_mask_long(s
, DMAR_FECTL_REG
, VTD_FECTL_IP
, 0);
380 /* Check if the Fault (F) field of the Fault Recording Register referenced by
383 static bool vtd_is_frcd_set(IntelIOMMUState
*s
, uint16_t index
)
385 /* Each reg is 128-bit */
386 hwaddr addr
= DMAR_FRCD_REG_OFFSET
+ (((uint64_t)index
) << 4);
387 addr
+= 8; /* Access the high 64-bit half */
389 assert(index
< DMAR_FRCD_REG_NR
);
391 return vtd_get_quad_raw(s
, addr
) & VTD_FRCD_F
;
394 /* Update the PPF field of Fault Status Register.
395 * Should be called whenever change the F field of any fault recording
398 static void vtd_update_fsts_ppf(IntelIOMMUState
*s
)
401 uint32_t ppf_mask
= 0;
403 for (i
= 0; i
< DMAR_FRCD_REG_NR
; i
++) {
404 if (vtd_is_frcd_set(s
, i
)) {
405 ppf_mask
= VTD_FSTS_PPF
;
409 vtd_set_clear_mask_long(s
, DMAR_FSTS_REG
, VTD_FSTS_PPF
, ppf_mask
);
410 trace_vtd_fsts_ppf(!!ppf_mask
);
413 static void vtd_set_frcd_and_update_ppf(IntelIOMMUState
*s
, uint16_t index
)
415 /* Each reg is 128-bit */
416 hwaddr addr
= DMAR_FRCD_REG_OFFSET
+ (((uint64_t)index
) << 4);
417 addr
+= 8; /* Access the high 64-bit half */
419 assert(index
< DMAR_FRCD_REG_NR
);
421 vtd_set_clear_mask_quad(s
, addr
, 0, VTD_FRCD_F
);
422 vtd_update_fsts_ppf(s
);
425 /* Must not update F field now, should be done later */
426 static void vtd_record_frcd(IntelIOMMUState
*s
, uint16_t index
,
427 uint16_t source_id
, hwaddr addr
,
428 VTDFaultReason fault
, bool is_write
)
431 hwaddr frcd_reg_addr
= DMAR_FRCD_REG_OFFSET
+ (((uint64_t)index
) << 4);
433 assert(index
< DMAR_FRCD_REG_NR
);
435 lo
= VTD_FRCD_FI(addr
);
436 hi
= VTD_FRCD_SID(source_id
) | VTD_FRCD_FR(fault
);
440 vtd_set_quad_raw(s
, frcd_reg_addr
, lo
);
441 vtd_set_quad_raw(s
, frcd_reg_addr
+ 8, hi
);
443 trace_vtd_frr_new(index
, hi
, lo
);
446 /* Try to collapse multiple pending faults from the same requester */
447 static bool vtd_try_collapse_fault(IntelIOMMUState
*s
, uint16_t source_id
)
451 hwaddr addr
= DMAR_FRCD_REG_OFFSET
+ 8; /* The high 64-bit half */
453 for (i
= 0; i
< DMAR_FRCD_REG_NR
; i
++) {
454 frcd_reg
= vtd_get_quad_raw(s
, addr
);
455 if ((frcd_reg
& VTD_FRCD_F
) &&
456 ((frcd_reg
& VTD_FRCD_SID_MASK
) == source_id
)) {
459 addr
+= 16; /* 128-bit for each */
464 /* Log and report an DMAR (address translation) fault to software */
465 static void vtd_report_dmar_fault(IntelIOMMUState
*s
, uint16_t source_id
,
466 hwaddr addr
, VTDFaultReason fault
,
469 uint32_t fsts_reg
= vtd_get_long_raw(s
, DMAR_FSTS_REG
);
471 assert(fault
< VTD_FR_MAX
);
473 if (fault
== VTD_FR_RESERVED_ERR
) {
474 /* This is not a normal fault reason case. Drop it. */
478 trace_vtd_dmar_fault(source_id
, fault
, addr
, is_write
);
480 if (fsts_reg
& VTD_FSTS_PFO
) {
481 error_report_once("New fault is not recorded due to "
482 "Primary Fault Overflow");
486 if (vtd_try_collapse_fault(s
, source_id
)) {
487 error_report_once("New fault is not recorded due to "
488 "compression of faults");
492 if (vtd_is_frcd_set(s
, s
->next_frcd_reg
)) {
493 error_report_once("Next Fault Recording Reg is used, "
494 "new fault is not recorded, set PFO field");
495 vtd_set_clear_mask_long(s
, DMAR_FSTS_REG
, 0, VTD_FSTS_PFO
);
499 vtd_record_frcd(s
, s
->next_frcd_reg
, source_id
, addr
, fault
, is_write
);
501 if (fsts_reg
& VTD_FSTS_PPF
) {
502 error_report_once("There are pending faults already, "
503 "fault event is not generated");
504 vtd_set_frcd_and_update_ppf(s
, s
->next_frcd_reg
);
506 if (s
->next_frcd_reg
== DMAR_FRCD_REG_NR
) {
507 s
->next_frcd_reg
= 0;
510 vtd_set_clear_mask_long(s
, DMAR_FSTS_REG
, VTD_FSTS_FRI_MASK
,
511 VTD_FSTS_FRI(s
->next_frcd_reg
));
512 vtd_set_frcd_and_update_ppf(s
, s
->next_frcd_reg
); /* Will set PPF */
514 if (s
->next_frcd_reg
== DMAR_FRCD_REG_NR
) {
515 s
->next_frcd_reg
= 0;
517 /* This case actually cause the PPF to be Set.
518 * So generate fault event (interrupt).
520 vtd_generate_fault_event(s
, fsts_reg
);
524 /* Handle Invalidation Queue Errors of queued invalidation interface error
527 static void vtd_handle_inv_queue_error(IntelIOMMUState
*s
)
529 uint32_t fsts_reg
= vtd_get_long_raw(s
, DMAR_FSTS_REG
);
531 vtd_set_clear_mask_long(s
, DMAR_FSTS_REG
, 0, VTD_FSTS_IQE
);
532 vtd_generate_fault_event(s
, fsts_reg
);
535 /* Set the IWC field and try to generate an invalidation completion interrupt */
536 static void vtd_generate_completion_event(IntelIOMMUState
*s
)
538 if (vtd_get_long_raw(s
, DMAR_ICS_REG
) & VTD_ICS_IWC
) {
539 trace_vtd_inv_desc_wait_irq("One pending, skip current");
542 vtd_set_clear_mask_long(s
, DMAR_ICS_REG
, 0, VTD_ICS_IWC
);
543 vtd_set_clear_mask_long(s
, DMAR_IECTL_REG
, 0, VTD_IECTL_IP
);
544 if (vtd_get_long_raw(s
, DMAR_IECTL_REG
) & VTD_IECTL_IM
) {
545 trace_vtd_inv_desc_wait_irq("IM in IECTL_REG is set, "
546 "new event not generated");
549 /* Generate the interrupt event */
550 trace_vtd_inv_desc_wait_irq("Generating complete event");
551 vtd_generate_interrupt(s
, DMAR_IEADDR_REG
, DMAR_IEDATA_REG
);
552 vtd_set_clear_mask_long(s
, DMAR_IECTL_REG
, VTD_IECTL_IP
, 0);
556 static inline bool vtd_root_entry_present(IntelIOMMUState
*s
,
560 if (s
->root_scalable
&& devfn
> UINT8_MAX
/ 2) {
561 return re
->hi
& VTD_ROOT_ENTRY_P
;
564 return re
->lo
& VTD_ROOT_ENTRY_P
;
567 static int vtd_get_root_entry(IntelIOMMUState
*s
, uint8_t index
,
572 addr
= s
->root
+ index
* sizeof(*re
);
573 if (dma_memory_read(&address_space_memory
, addr
, re
, sizeof(*re
))) {
575 return -VTD_FR_ROOT_TABLE_INV
;
577 re
->lo
= le64_to_cpu(re
->lo
);
578 re
->hi
= le64_to_cpu(re
->hi
);
582 static inline bool vtd_ce_present(VTDContextEntry
*context
)
584 return context
->lo
& VTD_CONTEXT_ENTRY_P
;
587 static int vtd_get_context_entry_from_root(IntelIOMMUState
*s
,
592 dma_addr_t addr
, ce_size
;
594 /* we have checked that root entry is present */
595 ce_size
= s
->root_scalable
? VTD_CTX_ENTRY_SCALABLE_SIZE
:
596 VTD_CTX_ENTRY_LEGACY_SIZE
;
598 if (s
->root_scalable
&& index
> UINT8_MAX
/ 2) {
599 index
= index
& (~VTD_DEVFN_CHECK_MASK
);
600 addr
= re
->hi
& VTD_ROOT_ENTRY_CTP
;
602 addr
= re
->lo
& VTD_ROOT_ENTRY_CTP
;
605 addr
= addr
+ index
* ce_size
;
606 if (dma_memory_read(&address_space_memory
, addr
, ce
, ce_size
)) {
607 return -VTD_FR_CONTEXT_TABLE_INV
;
610 ce
->lo
= le64_to_cpu(ce
->lo
);
611 ce
->hi
= le64_to_cpu(ce
->hi
);
612 if (ce_size
== VTD_CTX_ENTRY_SCALABLE_SIZE
) {
613 ce
->val
[2] = le64_to_cpu(ce
->val
[2]);
614 ce
->val
[3] = le64_to_cpu(ce
->val
[3]);
619 static inline dma_addr_t
vtd_ce_get_slpt_base(VTDContextEntry
*ce
)
621 return ce
->lo
& VTD_CONTEXT_ENTRY_SLPTPTR
;
624 static inline uint64_t vtd_get_slpte_addr(uint64_t slpte
, uint8_t aw
)
626 return slpte
& VTD_SL_PT_BASE_ADDR_MASK(aw
);
629 /* Whether the pte indicates the address of the page frame */
630 static inline bool vtd_is_last_slpte(uint64_t slpte
, uint32_t level
)
632 return level
== VTD_SL_PT_LEVEL
|| (slpte
& VTD_SL_PT_PAGE_SIZE_MASK
);
635 /* Get the content of a spte located in @base_addr[@index] */
636 static uint64_t vtd_get_slpte(dma_addr_t base_addr
, uint32_t index
)
640 assert(index
< VTD_SL_PT_ENTRY_NR
);
642 if (dma_memory_read(&address_space_memory
,
643 base_addr
+ index
* sizeof(slpte
), &slpte
,
645 slpte
= (uint64_t)-1;
648 slpte
= le64_to_cpu(slpte
);
652 /* Given an iova and the level of paging structure, return the offset
655 static inline uint32_t vtd_iova_level_offset(uint64_t iova
, uint32_t level
)
657 return (iova
>> vtd_slpt_level_shift(level
)) &
658 ((1ULL << VTD_SL_LEVEL_BITS
) - 1);
661 /* Check Capability Register to see if the @level of page-table is supported */
662 static inline bool vtd_is_level_supported(IntelIOMMUState
*s
, uint32_t level
)
664 return VTD_CAP_SAGAW_MASK
& s
->cap
&
665 (1ULL << (level
- 2 + VTD_CAP_SAGAW_SHIFT
));
668 /* Return true if check passed, otherwise false */
669 static inline bool vtd_pe_type_check(X86IOMMUState
*x86_iommu
,
672 switch (VTD_PE_GET_TYPE(pe
)) {
673 case VTD_SM_PASID_ENTRY_FLT
:
674 case VTD_SM_PASID_ENTRY_SLT
:
675 case VTD_SM_PASID_ENTRY_NESTED
:
677 case VTD_SM_PASID_ENTRY_PT
:
678 if (!x86_iommu
->pt_supported
) {
689 static inline bool vtd_pdire_present(VTDPASIDDirEntry
*pdire
)
691 return pdire
->val
& 1;
695 * Caller of this function should check present bit if wants
696 * to use pdir entry for futher usage except for fpd bit check.
698 static int vtd_get_pdire_from_pdir_table(dma_addr_t pasid_dir_base
,
700 VTDPASIDDirEntry
*pdire
)
703 dma_addr_t addr
, entry_size
;
705 index
= VTD_PASID_DIR_INDEX(pasid
);
706 entry_size
= VTD_PASID_DIR_ENTRY_SIZE
;
707 addr
= pasid_dir_base
+ index
* entry_size
;
708 if (dma_memory_read(&address_space_memory
, addr
, pdire
, entry_size
)) {
709 return -VTD_FR_PASID_TABLE_INV
;
715 static inline bool vtd_pe_present(VTDPASIDEntry
*pe
)
717 return pe
->val
[0] & VTD_PASID_ENTRY_P
;
720 static int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUState
*s
,
726 dma_addr_t entry_size
;
727 X86IOMMUState
*x86_iommu
= X86_IOMMU_DEVICE(s
);
729 index
= VTD_PASID_TABLE_INDEX(pasid
);
730 entry_size
= VTD_PASID_ENTRY_SIZE
;
731 addr
= addr
+ index
* entry_size
;
732 if (dma_memory_read(&address_space_memory
, addr
, pe
, entry_size
)) {
733 return -VTD_FR_PASID_TABLE_INV
;
736 /* Do translation type check */
737 if (!vtd_pe_type_check(x86_iommu
, pe
)) {
738 return -VTD_FR_PASID_TABLE_INV
;
741 if (!vtd_is_level_supported(s
, VTD_PE_GET_LEVEL(pe
))) {
742 return -VTD_FR_PASID_TABLE_INV
;
749 * Caller of this function should check present bit if wants
750 * to use pasid entry for futher usage except for fpd bit check.
752 static int vtd_get_pe_from_pdire(IntelIOMMUState
*s
,
754 VTDPASIDDirEntry
*pdire
,
757 dma_addr_t addr
= pdire
->val
& VTD_PASID_TABLE_BASE_ADDR_MASK
;
759 return vtd_get_pe_in_pasid_leaf_table(s
, pasid
, addr
, pe
);
763 * This function gets a pasid entry from a specified pasid
764 * table (includes dir and leaf table) with a specified pasid.
765 * Sanity check should be done to ensure return a present
766 * pasid entry to caller.
768 static int vtd_get_pe_from_pasid_table(IntelIOMMUState
*s
,
769 dma_addr_t pasid_dir_base
,
774 VTDPASIDDirEntry pdire
;
776 ret
= vtd_get_pdire_from_pdir_table(pasid_dir_base
,
782 if (!vtd_pdire_present(&pdire
)) {
783 return -VTD_FR_PASID_TABLE_INV
;
786 ret
= vtd_get_pe_from_pdire(s
, pasid
, &pdire
, pe
);
791 if (!vtd_pe_present(pe
)) {
792 return -VTD_FR_PASID_TABLE_INV
;
798 static int vtd_ce_get_rid2pasid_entry(IntelIOMMUState
*s
,
803 dma_addr_t pasid_dir_base
;
806 pasid
= VTD_CE_GET_RID2PASID(ce
);
807 pasid_dir_base
= VTD_CE_GET_PASID_DIR_TABLE(ce
);
808 ret
= vtd_get_pe_from_pasid_table(s
, pasid_dir_base
, pasid
, pe
);
813 static int vtd_ce_get_pasid_fpd(IntelIOMMUState
*s
,
819 dma_addr_t pasid_dir_base
;
820 VTDPASIDDirEntry pdire
;
823 pasid
= VTD_CE_GET_RID2PASID(ce
);
824 pasid_dir_base
= VTD_CE_GET_PASID_DIR_TABLE(ce
);
827 * No present bit check since fpd is meaningful even
828 * if the present bit is clear.
830 ret
= vtd_get_pdire_from_pdir_table(pasid_dir_base
, pasid
, &pdire
);
835 if (pdire
.val
& VTD_PASID_DIR_FPD
) {
840 if (!vtd_pdire_present(&pdire
)) {
841 return -VTD_FR_PASID_TABLE_INV
;
845 * No present bit check since fpd is meaningful even
846 * if the present bit is clear.
848 ret
= vtd_get_pe_from_pdire(s
, pasid
, &pdire
, &pe
);
853 if (pe
.val
[0] & VTD_PASID_ENTRY_FPD
) {
860 /* Get the page-table level that hardware should use for the second-level
861 * page-table walk from the Address Width field of context-entry.
863 static inline uint32_t vtd_ce_get_level(VTDContextEntry
*ce
)
865 return 2 + (ce
->hi
& VTD_CONTEXT_ENTRY_AW
);
868 static uint32_t vtd_get_iova_level(IntelIOMMUState
*s
,
873 if (s
->root_scalable
) {
874 vtd_ce_get_rid2pasid_entry(s
, ce
, &pe
);
875 return VTD_PE_GET_LEVEL(&pe
);
878 return vtd_ce_get_level(ce
);
881 static inline uint32_t vtd_ce_get_agaw(VTDContextEntry
*ce
)
883 return 30 + (ce
->hi
& VTD_CONTEXT_ENTRY_AW
) * 9;
886 static uint32_t vtd_get_iova_agaw(IntelIOMMUState
*s
,
891 if (s
->root_scalable
) {
892 vtd_ce_get_rid2pasid_entry(s
, ce
, &pe
);
893 return 30 + ((pe
.val
[0] >> 2) & VTD_SM_PASID_ENTRY_AW
) * 9;
896 return vtd_ce_get_agaw(ce
);
899 static inline uint32_t vtd_ce_get_type(VTDContextEntry
*ce
)
901 return ce
->lo
& VTD_CONTEXT_ENTRY_TT
;
904 /* Only for Legacy Mode. Return true if check passed, otherwise false */
905 static inline bool vtd_ce_type_check(X86IOMMUState
*x86_iommu
,
908 switch (vtd_ce_get_type(ce
)) {
909 case VTD_CONTEXT_TT_MULTI_LEVEL
:
910 /* Always supported */
912 case VTD_CONTEXT_TT_DEV_IOTLB
:
913 if (!x86_iommu
->dt_supported
) {
914 error_report_once("%s: DT specified but not supported", __func__
);
918 case VTD_CONTEXT_TT_PASS_THROUGH
:
919 if (!x86_iommu
->pt_supported
) {
920 error_report_once("%s: PT specified but not supported", __func__
);
926 error_report_once("%s: unknown ce type: %"PRIu32
, __func__
,
927 vtd_ce_get_type(ce
));
933 static inline uint64_t vtd_iova_limit(IntelIOMMUState
*s
,
934 VTDContextEntry
*ce
, uint8_t aw
)
936 uint32_t ce_agaw
= vtd_get_iova_agaw(s
, ce
);
937 return 1ULL << MIN(ce_agaw
, aw
);
940 /* Return true if IOVA passes range check, otherwise false. */
941 static inline bool vtd_iova_range_check(IntelIOMMUState
*s
,
942 uint64_t iova
, VTDContextEntry
*ce
,
946 * Check if @iova is above 2^X-1, where X is the minimum of MGAW
947 * in CAP_REG and AW in context-entry.
949 return !(iova
& ~(vtd_iova_limit(s
, ce
, aw
) - 1));
952 static dma_addr_t
vtd_get_iova_pgtbl_base(IntelIOMMUState
*s
,
957 if (s
->root_scalable
) {
958 vtd_ce_get_rid2pasid_entry(s
, ce
, &pe
);
959 return pe
.val
[0] & VTD_SM_PASID_ENTRY_SLPTPTR
;
962 return vtd_ce_get_slpt_base(ce
);
966 * Rsvd field masks for spte:
967 * vtd_spte_rsvd 4k pages
968 * vtd_spte_rsvd_large large pages
970 static uint64_t vtd_spte_rsvd
[5];
971 static uint64_t vtd_spte_rsvd_large
[5];
973 static bool vtd_slpte_nonzero_rsvd(uint64_t slpte
, uint32_t level
)
975 uint64_t rsvd_mask
= vtd_spte_rsvd
[level
];
977 if ((level
== VTD_SL_PD_LEVEL
|| level
== VTD_SL_PDP_LEVEL
) &&
978 (slpte
& VTD_SL_PT_PAGE_SIZE_MASK
)) {
980 rsvd_mask
= vtd_spte_rsvd_large
[level
];
983 return slpte
& rsvd_mask
;
986 /* Find the VTD address space associated with a given bus number */
987 static VTDBus
*vtd_find_as_from_bus_num(IntelIOMMUState
*s
, uint8_t bus_num
)
989 VTDBus
*vtd_bus
= s
->vtd_as_by_bus_num
[bus_num
];
997 * Iterate over the registered buses to find the one which
998 * currently holds this bus number and update the bus_num
1001 g_hash_table_iter_init(&iter
, s
->vtd_as_by_busptr
);
1002 while (g_hash_table_iter_next(&iter
, NULL
, (void **)&vtd_bus
)) {
1003 if (pci_bus_num(vtd_bus
->bus
) == bus_num
) {
1004 s
->vtd_as_by_bus_num
[bus_num
] = vtd_bus
;
1012 /* Given the @iova, get relevant @slptep. @slpte_level will be the last level
1013 * of the translation, can be used for deciding the size of large page.
1015 static int vtd_iova_to_slpte(IntelIOMMUState
*s
, VTDContextEntry
*ce
,
1016 uint64_t iova
, bool is_write
,
1017 uint64_t *slptep
, uint32_t *slpte_level
,
1018 bool *reads
, bool *writes
, uint8_t aw_bits
)
1020 dma_addr_t addr
= vtd_get_iova_pgtbl_base(s
, ce
);
1021 uint32_t level
= vtd_get_iova_level(s
, ce
);
1024 uint64_t access_right_check
;
1026 if (!vtd_iova_range_check(s
, iova
, ce
, aw_bits
)) {
1027 error_report_once("%s: detected IOVA overflow (iova=0x%" PRIx64
")",
1029 return -VTD_FR_ADDR_BEYOND_MGAW
;
1032 /* FIXME: what is the Atomics request here? */
1033 access_right_check
= is_write
? VTD_SL_W
: VTD_SL_R
;
1036 offset
= vtd_iova_level_offset(iova
, level
);
1037 slpte
= vtd_get_slpte(addr
, offset
);
1039 if (slpte
== (uint64_t)-1) {
1040 error_report_once("%s: detected read error on DMAR slpte "
1041 "(iova=0x%" PRIx64
")", __func__
, iova
);
1042 if (level
== vtd_get_iova_level(s
, ce
)) {
1043 /* Invalid programming of context-entry */
1044 return -VTD_FR_CONTEXT_ENTRY_INV
;
1046 return -VTD_FR_PAGING_ENTRY_INV
;
1049 *reads
= (*reads
) && (slpte
& VTD_SL_R
);
1050 *writes
= (*writes
) && (slpte
& VTD_SL_W
);
1051 if (!(slpte
& access_right_check
)) {
1052 error_report_once("%s: detected slpte permission error "
1053 "(iova=0x%" PRIx64
", level=0x%" PRIx32
", "
1054 "slpte=0x%" PRIx64
", write=%d)", __func__
,
1055 iova
, level
, slpte
, is_write
);
1056 return is_write
? -VTD_FR_WRITE
: -VTD_FR_READ
;
1058 if (vtd_slpte_nonzero_rsvd(slpte
, level
)) {
1059 error_report_once("%s: detected splte reserve non-zero "
1060 "iova=0x%" PRIx64
", level=0x%" PRIx32
1061 "slpte=0x%" PRIx64
")", __func__
, iova
,
1063 return -VTD_FR_PAGING_ENTRY_RSVD
;
1066 if (vtd_is_last_slpte(slpte
, level
)) {
1068 *slpte_level
= level
;
1071 addr
= vtd_get_slpte_addr(slpte
, aw_bits
);
1076 typedef int (*vtd_page_walk_hook
)(IOMMUTLBEntry
*entry
, void *private);
1079 * Constant information used during page walking
1081 * @hook_fn: hook func to be called when detected page
1082 * @private: private data to be passed into hook func
1083 * @notify_unmap: whether we should notify invalid entries
1084 * @as: VT-d address space of the device
1085 * @aw: maximum address width
1086 * @domain: domain ID of the page walk
1089 VTDAddressSpace
*as
;
1090 vtd_page_walk_hook hook_fn
;
1095 } vtd_page_walk_info
;
1097 static int vtd_page_walk_one(IOMMUTLBEntry
*entry
, vtd_page_walk_info
*info
)
1099 VTDAddressSpace
*as
= info
->as
;
1100 vtd_page_walk_hook hook_fn
= info
->hook_fn
;
1101 void *private = info
->private;
1103 .iova
= entry
->iova
,
1104 .size
= entry
->addr_mask
,
1105 .translated_addr
= entry
->translated_addr
,
1106 .perm
= entry
->perm
,
1108 DMAMap
*mapped
= iova_tree_find(as
->iova_tree
, &target
);
1110 if (entry
->perm
== IOMMU_NONE
&& !info
->notify_unmap
) {
1111 trace_vtd_page_walk_one_skip_unmap(entry
->iova
, entry
->addr_mask
);
1117 /* Update local IOVA mapped ranges */
1120 /* If it's exactly the same translation, skip */
1121 if (!memcmp(mapped
, &target
, sizeof(target
))) {
1122 trace_vtd_page_walk_one_skip_map(entry
->iova
, entry
->addr_mask
,
1123 entry
->translated_addr
);
1127 * Translation changed. Normally this should not
1128 * happen, but it can happen when with buggy guest
1129 * OSes. Note that there will be a small window that
1130 * we don't have map at all. But that's the best
1131 * effort we can do. The ideal way to emulate this is
1132 * atomically modify the PTE to follow what has
1133 * changed, but we can't. One example is that vfio
1134 * driver only has VFIO_IOMMU_[UN]MAP_DMA but no
1135 * interface to modify a mapping (meanwhile it seems
1136 * meaningless to even provide one). Anyway, let's
1137 * mark this as a TODO in case one day we'll have
1138 * a better solution.
1140 IOMMUAccessFlags cache_perm
= entry
->perm
;
1143 /* Emulate an UNMAP */
1144 entry
->perm
= IOMMU_NONE
;
1145 trace_vtd_page_walk_one(info
->domain_id
,
1147 entry
->translated_addr
,
1150 ret
= hook_fn(entry
, private);
1154 /* Drop any existing mapping */
1155 iova_tree_remove(as
->iova_tree
, &target
);
1156 /* Recover the correct permission */
1157 entry
->perm
= cache_perm
;
1160 iova_tree_insert(as
->iova_tree
, &target
);
1163 /* Skip since we didn't map this range at all */
1164 trace_vtd_page_walk_one_skip_unmap(entry
->iova
, entry
->addr_mask
);
1167 iova_tree_remove(as
->iova_tree
, &target
);
1170 trace_vtd_page_walk_one(info
->domain_id
, entry
->iova
,
1171 entry
->translated_addr
, entry
->addr_mask
,
1173 return hook_fn(entry
, private);
1177 * vtd_page_walk_level - walk over specific level for IOVA range
1179 * @addr: base GPA addr to start the walk
1180 * @start: IOVA range start address
1181 * @end: IOVA range end address (start <= addr < end)
1182 * @read: whether parent level has read permission
1183 * @write: whether parent level has write permission
1184 * @info: constant information for the page walk
1186 static int vtd_page_walk_level(dma_addr_t addr
, uint64_t start
,
1187 uint64_t end
, uint32_t level
, bool read
,
1188 bool write
, vtd_page_walk_info
*info
)
1190 bool read_cur
, write_cur
, entry_valid
;
1193 uint64_t subpage_size
, subpage_mask
;
1194 IOMMUTLBEntry entry
;
1195 uint64_t iova
= start
;
1199 trace_vtd_page_walk_level(addr
, level
, start
, end
);
1201 subpage_size
= 1ULL << vtd_slpt_level_shift(level
);
1202 subpage_mask
= vtd_slpt_level_page_mask(level
);
1204 while (iova
< end
) {
1205 iova_next
= (iova
& subpage_mask
) + subpage_size
;
1207 offset
= vtd_iova_level_offset(iova
, level
);
1208 slpte
= vtd_get_slpte(addr
, offset
);
1210 if (slpte
== (uint64_t)-1) {
1211 trace_vtd_page_walk_skip_read(iova
, iova_next
);
1215 if (vtd_slpte_nonzero_rsvd(slpte
, level
)) {
1216 trace_vtd_page_walk_skip_reserve(iova
, iova_next
);
1220 /* Permissions are stacked with parents' */
1221 read_cur
= read
&& (slpte
& VTD_SL_R
);
1222 write_cur
= write
&& (slpte
& VTD_SL_W
);
1225 * As long as we have either read/write permission, this is a
1226 * valid entry. The rule works for both page entries and page
1229 entry_valid
= read_cur
| write_cur
;
1231 if (!vtd_is_last_slpte(slpte
, level
) && entry_valid
) {
1233 * This is a valid PDE (or even bigger than PDE). We need
1234 * to walk one further level.
1236 ret
= vtd_page_walk_level(vtd_get_slpte_addr(slpte
, info
->aw
),
1237 iova
, MIN(iova_next
, end
), level
- 1,
1238 read_cur
, write_cur
, info
);
1241 * This means we are either:
1243 * (1) the real page entry (either 4K page, or huge page)
1244 * (2) the whole range is invalid
1246 * In either case, we send an IOTLB notification down.
1248 entry
.target_as
= &address_space_memory
;
1249 entry
.iova
= iova
& subpage_mask
;
1250 entry
.perm
= IOMMU_ACCESS_FLAG(read_cur
, write_cur
);
1251 entry
.addr_mask
= ~subpage_mask
;
1252 /* NOTE: this is only meaningful if entry_valid == true */
1253 entry
.translated_addr
= vtd_get_slpte_addr(slpte
, info
->aw
);
1254 ret
= vtd_page_walk_one(&entry
, info
);
1269 * vtd_page_walk - walk specific IOVA range, and call the hook
1271 * @s: intel iommu state
1272 * @ce: context entry to walk upon
1273 * @start: IOVA address to start the walk
1274 * @end: IOVA range end address (start <= addr < end)
1275 * @info: page walking information struct
1277 static int vtd_page_walk(IntelIOMMUState
*s
, VTDContextEntry
*ce
,
1278 uint64_t start
, uint64_t end
,
1279 vtd_page_walk_info
*info
)
1281 dma_addr_t addr
= vtd_get_iova_pgtbl_base(s
, ce
);
1282 uint32_t level
= vtd_get_iova_level(s
, ce
);
1284 if (!vtd_iova_range_check(s
, start
, ce
, info
->aw
)) {
1285 return -VTD_FR_ADDR_BEYOND_MGAW
;
1288 if (!vtd_iova_range_check(s
, end
, ce
, info
->aw
)) {
1289 /* Fix end so that it reaches the maximum */
1290 end
= vtd_iova_limit(s
, ce
, info
->aw
);
1293 return vtd_page_walk_level(addr
, start
, end
, level
, true, true, info
);
1296 static int vtd_root_entry_rsvd_bits_check(IntelIOMMUState
*s
,
1299 /* Legacy Mode reserved bits check */
1300 if (!s
->root_scalable
&&
1301 (re
->hi
|| (re
->lo
& VTD_ROOT_ENTRY_RSVD(s
->aw_bits
))))
1304 /* Scalable Mode reserved bits check */
1305 if (s
->root_scalable
&&
1306 ((re
->lo
& VTD_ROOT_ENTRY_RSVD(s
->aw_bits
)) ||
1307 (re
->hi
& VTD_ROOT_ENTRY_RSVD(s
->aw_bits
))))
1313 error_report_once("%s: invalid root entry: hi=0x%"PRIx64
1315 __func__
, re
->hi
, re
->lo
);
1316 return -VTD_FR_ROOT_ENTRY_RSVD
;
1319 static inline int vtd_context_entry_rsvd_bits_check(IntelIOMMUState
*s
,
1320 VTDContextEntry
*ce
)
1322 if (!s
->root_scalable
&&
1323 (ce
->hi
& VTD_CONTEXT_ENTRY_RSVD_HI
||
1324 ce
->lo
& VTD_CONTEXT_ENTRY_RSVD_LO(s
->aw_bits
))) {
1325 error_report_once("%s: invalid context entry: hi=%"PRIx64
1326 ", lo=%"PRIx64
" (reserved nonzero)",
1327 __func__
, ce
->hi
, ce
->lo
);
1328 return -VTD_FR_CONTEXT_ENTRY_RSVD
;
1331 if (s
->root_scalable
&&
1332 (ce
->val
[0] & VTD_SM_CONTEXT_ENTRY_RSVD_VAL0(s
->aw_bits
) ||
1333 ce
->val
[1] & VTD_SM_CONTEXT_ENTRY_RSVD_VAL1
||
1336 error_report_once("%s: invalid context entry: val[3]=%"PRIx64
1339 ", val[0]=%"PRIx64
" (reserved nonzero)",
1340 __func__
, ce
->val
[3], ce
->val
[2],
1341 ce
->val
[1], ce
->val
[0]);
1342 return -VTD_FR_CONTEXT_ENTRY_RSVD
;
1348 static int vtd_ce_rid2pasid_check(IntelIOMMUState
*s
,
1349 VTDContextEntry
*ce
)
1354 * Make sure in Scalable Mode, a present context entry
1355 * has valid rid2pasid setting, which includes valid
1356 * rid2pasid field and corresponding pasid entry setting
1358 return vtd_ce_get_rid2pasid_entry(s
, ce
, &pe
);
1361 /* Map a device to its corresponding domain (context-entry) */
1362 static int vtd_dev_to_context_entry(IntelIOMMUState
*s
, uint8_t bus_num
,
1363 uint8_t devfn
, VTDContextEntry
*ce
)
1367 X86IOMMUState
*x86_iommu
= X86_IOMMU_DEVICE(s
);
1369 ret_fr
= vtd_get_root_entry(s
, bus_num
, &re
);
1374 if (!vtd_root_entry_present(s
, &re
, devfn
)) {
1375 /* Not error - it's okay we don't have root entry. */
1376 trace_vtd_re_not_present(bus_num
);
1377 return -VTD_FR_ROOT_ENTRY_P
;
1380 ret_fr
= vtd_root_entry_rsvd_bits_check(s
, &re
);
1385 ret_fr
= vtd_get_context_entry_from_root(s
, &re
, devfn
, ce
);
1390 if (!vtd_ce_present(ce
)) {
1391 /* Not error - it's okay we don't have context entry. */
1392 trace_vtd_ce_not_present(bus_num
, devfn
);
1393 return -VTD_FR_CONTEXT_ENTRY_P
;
1396 ret_fr
= vtd_context_entry_rsvd_bits_check(s
, ce
);
1401 /* Check if the programming of context-entry is valid */
1402 if (!s
->root_scalable
&&
1403 !vtd_is_level_supported(s
, vtd_ce_get_level(ce
))) {
1404 error_report_once("%s: invalid context entry: hi=%"PRIx64
1405 ", lo=%"PRIx64
" (level %d not supported)",
1406 __func__
, ce
->hi
, ce
->lo
,
1407 vtd_ce_get_level(ce
));
1408 return -VTD_FR_CONTEXT_ENTRY_INV
;
1411 if (!s
->root_scalable
) {
1412 /* Do translation type check */
1413 if (!vtd_ce_type_check(x86_iommu
, ce
)) {
1414 /* Errors dumped in vtd_ce_type_check() */
1415 return -VTD_FR_CONTEXT_ENTRY_INV
;
1419 * Check if the programming of context-entry.rid2pasid
1420 * and corresponding pasid setting is valid, and thus
1421 * avoids to check pasid entry fetching result in future
1422 * helper function calling.
1424 ret_fr
= vtd_ce_rid2pasid_check(s
, ce
);
1433 static int vtd_sync_shadow_page_hook(IOMMUTLBEntry
*entry
,
1436 memory_region_notify_iommu((IOMMUMemoryRegion
*)private, 0, *entry
);
1440 static uint16_t vtd_get_domain_id(IntelIOMMUState
*s
,
1441 VTDContextEntry
*ce
)
1445 if (s
->root_scalable
) {
1446 vtd_ce_get_rid2pasid_entry(s
, ce
, &pe
);
1447 return VTD_SM_PASID_ENTRY_DID(pe
.val
[1]);
1450 return VTD_CONTEXT_ENTRY_DID(ce
->hi
);
1453 static int vtd_sync_shadow_page_table_range(VTDAddressSpace
*vtd_as
,
1454 VTDContextEntry
*ce
,
1455 hwaddr addr
, hwaddr size
)
1457 IntelIOMMUState
*s
= vtd_as
->iommu_state
;
1458 vtd_page_walk_info info
= {
1459 .hook_fn
= vtd_sync_shadow_page_hook
,
1460 .private = (void *)&vtd_as
->iommu
,
1461 .notify_unmap
= true,
1464 .domain_id
= vtd_get_domain_id(s
, ce
),
1467 return vtd_page_walk(s
, ce
, addr
, addr
+ size
, &info
);
1470 static int vtd_sync_shadow_page_table(VTDAddressSpace
*vtd_as
)
1476 ret
= vtd_dev_to_context_entry(vtd_as
->iommu_state
,
1477 pci_bus_num(vtd_as
->bus
),
1478 vtd_as
->devfn
, &ce
);
1480 if (ret
== -VTD_FR_CONTEXT_ENTRY_P
) {
1482 * It's a valid scenario to have a context entry that is
1483 * not present. For example, when a device is removed
1484 * from an existing domain then the context entry will be
1485 * zeroed by the guest before it was put into another
1486 * domain. When this happens, instead of synchronizing
1487 * the shadow pages we should invalidate all existing
1488 * mappings and notify the backends.
1490 IOMMU_NOTIFIER_FOREACH(n
, &vtd_as
->iommu
) {
1491 vtd_address_space_unmap(vtd_as
, n
);
1498 return vtd_sync_shadow_page_table_range(vtd_as
, &ce
, 0, UINT64_MAX
);
1502 * Check if specific device is configed to bypass address
1503 * translation for DMA requests. In Scalable Mode, bypass
1504 * 1st-level translation or 2nd-level translation, it depends
1507 static bool vtd_dev_pt_enabled(VTDAddressSpace
*as
)
1516 s
= as
->iommu_state
;
1517 ret
= vtd_dev_to_context_entry(s
, pci_bus_num(as
->bus
),
1521 * Possibly failed to parse the context entry for some reason
1522 * (e.g., during init, or any guest configuration errors on
1523 * context entries). We should assume PT not enabled for
1529 if (s
->root_scalable
) {
1530 ret
= vtd_ce_get_rid2pasid_entry(s
, &ce
, &pe
);
1532 error_report_once("%s: vtd_ce_get_rid2pasid_entry error: %"PRId32
,
1536 return (VTD_PE_GET_TYPE(&pe
) == VTD_SM_PASID_ENTRY_PT
);
1539 return (vtd_ce_get_type(&ce
) == VTD_CONTEXT_TT_PASS_THROUGH
);
1542 /* Return whether the device is using IOMMU translation. */
1543 static bool vtd_switch_address_space(VTDAddressSpace
*as
)
1546 /* Whether we need to take the BQL on our own */
1547 bool take_bql
= !qemu_mutex_iothread_locked();
1551 use_iommu
= as
->iommu_state
->dmar_enabled
&& !vtd_dev_pt_enabled(as
);
1553 trace_vtd_switch_address_space(pci_bus_num(as
->bus
),
1554 VTD_PCI_SLOT(as
->devfn
),
1555 VTD_PCI_FUNC(as
->devfn
),
1559 * It's possible that we reach here without BQL, e.g., when called
1560 * from vtd_pt_enable_fast_path(). However the memory APIs need
1561 * it. We'd better make sure we have had it already, or, take it.
1564 qemu_mutex_lock_iothread();
1567 /* Turn off first then on the other */
1569 memory_region_set_enabled(&as
->nodmar
, false);
1570 memory_region_set_enabled(MEMORY_REGION(&as
->iommu
), true);
1572 memory_region_set_enabled(MEMORY_REGION(&as
->iommu
), false);
1573 memory_region_set_enabled(&as
->nodmar
, true);
1577 qemu_mutex_unlock_iothread();
1583 static void vtd_switch_address_space_all(IntelIOMMUState
*s
)
1585 GHashTableIter iter
;
1589 g_hash_table_iter_init(&iter
, s
->vtd_as_by_busptr
);
1590 while (g_hash_table_iter_next(&iter
, NULL
, (void **)&vtd_bus
)) {
1591 for (i
= 0; i
< PCI_DEVFN_MAX
; i
++) {
1592 if (!vtd_bus
->dev_as
[i
]) {
1595 vtd_switch_address_space(vtd_bus
->dev_as
[i
]);
1600 static inline uint16_t vtd_make_source_id(uint8_t bus_num
, uint8_t devfn
)
1602 return ((bus_num
& 0xffUL
) << 8) | (devfn
& 0xffUL
);
1605 static const bool vtd_qualified_faults
[] = {
1606 [VTD_FR_RESERVED
] = false,
1607 [VTD_FR_ROOT_ENTRY_P
] = false,
1608 [VTD_FR_CONTEXT_ENTRY_P
] = true,
1609 [VTD_FR_CONTEXT_ENTRY_INV
] = true,
1610 [VTD_FR_ADDR_BEYOND_MGAW
] = true,
1611 [VTD_FR_WRITE
] = true,
1612 [VTD_FR_READ
] = true,
1613 [VTD_FR_PAGING_ENTRY_INV
] = true,
1614 [VTD_FR_ROOT_TABLE_INV
] = false,
1615 [VTD_FR_CONTEXT_TABLE_INV
] = false,
1616 [VTD_FR_ROOT_ENTRY_RSVD
] = false,
1617 [VTD_FR_PAGING_ENTRY_RSVD
] = true,
1618 [VTD_FR_CONTEXT_ENTRY_TT
] = true,
1619 [VTD_FR_PASID_TABLE_INV
] = false,
1620 [VTD_FR_RESERVED_ERR
] = false,
1621 [VTD_FR_MAX
] = false,
1624 /* To see if a fault condition is "qualified", which is reported to software
1625 * only if the FPD field in the context-entry used to process the faulting
1628 static inline bool vtd_is_qualified_fault(VTDFaultReason fault
)
1630 return vtd_qualified_faults
[fault
];
1633 static inline bool vtd_is_interrupt_addr(hwaddr addr
)
1635 return VTD_INTERRUPT_ADDR_FIRST
<= addr
&& addr
<= VTD_INTERRUPT_ADDR_LAST
;
1638 static void vtd_pt_enable_fast_path(IntelIOMMUState
*s
, uint16_t source_id
)
1641 VTDAddressSpace
*vtd_as
;
1642 bool success
= false;
1644 vtd_bus
= vtd_find_as_from_bus_num(s
, VTD_SID_TO_BUS(source_id
));
1649 vtd_as
= vtd_bus
->dev_as
[VTD_SID_TO_DEVFN(source_id
)];
1654 if (vtd_switch_address_space(vtd_as
) == false) {
1655 /* We switched off IOMMU region successfully. */
1660 trace_vtd_pt_enable_fast_path(source_id
, success
);
1663 /* Map dev to context-entry then do a paging-structures walk to do a iommu
1666 * Called from RCU critical section.
1668 * @bus_num: The bus number
1669 * @devfn: The devfn, which is the combined of device and function number
1670 * @is_write: The access is a write operation
1671 * @entry: IOMMUTLBEntry that contain the addr to be translated and result
1673 * Returns true if translation is successful, otherwise false.
1675 static bool vtd_do_iommu_translate(VTDAddressSpace
*vtd_as
, PCIBus
*bus
,
1676 uint8_t devfn
, hwaddr addr
, bool is_write
,
1677 IOMMUTLBEntry
*entry
)
1679 IntelIOMMUState
*s
= vtd_as
->iommu_state
;
1681 uint8_t bus_num
= pci_bus_num(bus
);
1682 VTDContextCacheEntry
*cc_entry
;
1683 uint64_t slpte
, page_mask
;
1685 uint16_t source_id
= vtd_make_source_id(bus_num
, devfn
);
1687 bool is_fpd_set
= false;
1690 uint8_t access_flags
;
1691 VTDIOTLBEntry
*iotlb_entry
;
1694 * We have standalone memory region for interrupt addresses, we
1695 * should never receive translation requests in this region.
1697 assert(!vtd_is_interrupt_addr(addr
));
1701 cc_entry
= &vtd_as
->context_cache_entry
;
1703 /* Try to fetch slpte form IOTLB */
1704 iotlb_entry
= vtd_lookup_iotlb(s
, source_id
, addr
);
1706 trace_vtd_iotlb_page_hit(source_id
, addr
, iotlb_entry
->slpte
,
1707 iotlb_entry
->domain_id
);
1708 slpte
= iotlb_entry
->slpte
;
1709 access_flags
= iotlb_entry
->access_flags
;
1710 page_mask
= iotlb_entry
->mask
;
1714 /* Try to fetch context-entry from cache first */
1715 if (cc_entry
->context_cache_gen
== s
->context_cache_gen
) {
1716 trace_vtd_iotlb_cc_hit(bus_num
, devfn
, cc_entry
->context_entry
.hi
,
1717 cc_entry
->context_entry
.lo
,
1718 cc_entry
->context_cache_gen
);
1719 ce
= cc_entry
->context_entry
;
1720 is_fpd_set
= ce
.lo
& VTD_CONTEXT_ENTRY_FPD
;
1721 if (!is_fpd_set
&& s
->root_scalable
) {
1722 ret_fr
= vtd_ce_get_pasid_fpd(s
, &ce
, &is_fpd_set
);
1723 VTD_PE_GET_FPD_ERR(ret_fr
, is_fpd_set
, s
, source_id
, addr
, is_write
);
1726 ret_fr
= vtd_dev_to_context_entry(s
, bus_num
, devfn
, &ce
);
1727 is_fpd_set
= ce
.lo
& VTD_CONTEXT_ENTRY_FPD
;
1728 if (!ret_fr
&& !is_fpd_set
&& s
->root_scalable
) {
1729 ret_fr
= vtd_ce_get_pasid_fpd(s
, &ce
, &is_fpd_set
);
1731 VTD_PE_GET_FPD_ERR(ret_fr
, is_fpd_set
, s
, source_id
, addr
, is_write
);
1732 /* Update context-cache */
1733 trace_vtd_iotlb_cc_update(bus_num
, devfn
, ce
.hi
, ce
.lo
,
1734 cc_entry
->context_cache_gen
,
1735 s
->context_cache_gen
);
1736 cc_entry
->context_entry
= ce
;
1737 cc_entry
->context_cache_gen
= s
->context_cache_gen
;
1741 * We don't need to translate for pass-through context entries.
1742 * Also, let's ignore IOTLB caching as well for PT devices.
1744 if (vtd_ce_get_type(&ce
) == VTD_CONTEXT_TT_PASS_THROUGH
) {
1745 entry
->iova
= addr
& VTD_PAGE_MASK_4K
;
1746 entry
->translated_addr
= entry
->iova
;
1747 entry
->addr_mask
= ~VTD_PAGE_MASK_4K
;
1748 entry
->perm
= IOMMU_RW
;
1749 trace_vtd_translate_pt(source_id
, entry
->iova
);
1752 * When this happens, it means firstly caching-mode is not
1753 * enabled, and this is the first passthrough translation for
1754 * the device. Let's enable the fast path for passthrough.
1756 * When passthrough is disabled again for the device, we can
1757 * capture it via the context entry invalidation, then the
1758 * IOMMU region can be swapped back.
1760 vtd_pt_enable_fast_path(s
, source_id
);
1761 vtd_iommu_unlock(s
);
1765 ret_fr
= vtd_iova_to_slpte(s
, &ce
, addr
, is_write
, &slpte
, &level
,
1766 &reads
, &writes
, s
->aw_bits
);
1767 VTD_PE_GET_FPD_ERR(ret_fr
, is_fpd_set
, s
, source_id
, addr
, is_write
);
1769 page_mask
= vtd_slpt_level_page_mask(level
);
1770 access_flags
= IOMMU_ACCESS_FLAG(reads
, writes
);
1771 vtd_update_iotlb(s
, source_id
, vtd_get_domain_id(s
, &ce
), addr
, slpte
,
1772 access_flags
, level
);
1774 vtd_iommu_unlock(s
);
1775 entry
->iova
= addr
& page_mask
;
1776 entry
->translated_addr
= vtd_get_slpte_addr(slpte
, s
->aw_bits
) & page_mask
;
1777 entry
->addr_mask
= ~page_mask
;
1778 entry
->perm
= access_flags
;
1782 vtd_iommu_unlock(s
);
1784 entry
->translated_addr
= 0;
1785 entry
->addr_mask
= 0;
1786 entry
->perm
= IOMMU_NONE
;
1790 static void vtd_root_table_setup(IntelIOMMUState
*s
)
1792 s
->root
= vtd_get_quad_raw(s
, DMAR_RTADDR_REG
);
1793 s
->root
&= VTD_RTADDR_ADDR_MASK(s
->aw_bits
);
1795 vtd_update_scalable_state(s
);
1797 trace_vtd_reg_dmar_root(s
->root
, s
->root_scalable
);
1800 static void vtd_iec_notify_all(IntelIOMMUState
*s
, bool global
,
1801 uint32_t index
, uint32_t mask
)
1803 x86_iommu_iec_notify_all(X86_IOMMU_DEVICE(s
), global
, index
, mask
);
1806 static void vtd_interrupt_remap_table_setup(IntelIOMMUState
*s
)
1809 value
= vtd_get_quad_raw(s
, DMAR_IRTA_REG
);
1810 s
->intr_size
= 1UL << ((value
& VTD_IRTA_SIZE_MASK
) + 1);
1811 s
->intr_root
= value
& VTD_IRTA_ADDR_MASK(s
->aw_bits
);
1812 s
->intr_eime
= value
& VTD_IRTA_EIME
;
1814 /* Notify global invalidation */
1815 vtd_iec_notify_all(s
, true, 0, 0);
1817 trace_vtd_reg_ir_root(s
->intr_root
, s
->intr_size
);
1820 static void vtd_iommu_replay_all(IntelIOMMUState
*s
)
1822 VTDAddressSpace
*vtd_as
;
1824 QLIST_FOREACH(vtd_as
, &s
->vtd_as_with_notifiers
, next
) {
1825 vtd_sync_shadow_page_table(vtd_as
);
1829 static void vtd_context_global_invalidate(IntelIOMMUState
*s
)
1831 trace_vtd_inv_desc_cc_global();
1832 /* Protects context cache */
1834 s
->context_cache_gen
++;
1835 if (s
->context_cache_gen
== VTD_CONTEXT_CACHE_GEN_MAX
) {
1836 vtd_reset_context_cache_locked(s
);
1838 vtd_iommu_unlock(s
);
1839 vtd_address_space_refresh_all(s
);
1841 * From VT-d spec 6.5.2.1, a global context entry invalidation
1842 * should be followed by a IOTLB global invalidation, so we should
1843 * be safe even without this. Hoewever, let's replay the region as
1844 * well to be safer, and go back here when we need finer tunes for
1845 * VT-d emulation codes.
1847 vtd_iommu_replay_all(s
);
1850 /* Do a context-cache device-selective invalidation.
1851 * @func_mask: FM field after shifting
1853 static void vtd_context_device_invalidate(IntelIOMMUState
*s
,
1859 VTDAddressSpace
*vtd_as
;
1860 uint8_t bus_n
, devfn
;
1863 trace_vtd_inv_desc_cc_devices(source_id
, func_mask
);
1865 switch (func_mask
& 3) {
1867 mask
= 0; /* No bits in the SID field masked */
1870 mask
= 4; /* Mask bit 2 in the SID field */
1873 mask
= 6; /* Mask bit 2:1 in the SID field */
1876 mask
= 7; /* Mask bit 2:0 in the SID field */
1881 bus_n
= VTD_SID_TO_BUS(source_id
);
1882 vtd_bus
= vtd_find_as_from_bus_num(s
, bus_n
);
1884 devfn
= VTD_SID_TO_DEVFN(source_id
);
1885 for (devfn_it
= 0; devfn_it
< PCI_DEVFN_MAX
; ++devfn_it
) {
1886 vtd_as
= vtd_bus
->dev_as
[devfn_it
];
1887 if (vtd_as
&& ((devfn_it
& mask
) == (devfn
& mask
))) {
1888 trace_vtd_inv_desc_cc_device(bus_n
, VTD_PCI_SLOT(devfn_it
),
1889 VTD_PCI_FUNC(devfn_it
));
1891 vtd_as
->context_cache_entry
.context_cache_gen
= 0;
1892 vtd_iommu_unlock(s
);
1894 * Do switch address space when needed, in case if the
1895 * device passthrough bit is switched.
1897 vtd_switch_address_space(vtd_as
);
1899 * So a device is moving out of (or moving into) a
1900 * domain, resync the shadow page table.
1901 * This won't bring bad even if we have no such
1902 * notifier registered - the IOMMU notification
1903 * framework will skip MAP notifications if that
1906 vtd_sync_shadow_page_table(vtd_as
);
1912 /* Context-cache invalidation
1913 * Returns the Context Actual Invalidation Granularity.
1914 * @val: the content of the CCMD_REG
1916 static uint64_t vtd_context_cache_invalidate(IntelIOMMUState
*s
, uint64_t val
)
1919 uint64_t type
= val
& VTD_CCMD_CIRG_MASK
;
1922 case VTD_CCMD_DOMAIN_INVL
:
1924 case VTD_CCMD_GLOBAL_INVL
:
1925 caig
= VTD_CCMD_GLOBAL_INVL_A
;
1926 vtd_context_global_invalidate(s
);
1929 case VTD_CCMD_DEVICE_INVL
:
1930 caig
= VTD_CCMD_DEVICE_INVL_A
;
1931 vtd_context_device_invalidate(s
, VTD_CCMD_SID(val
), VTD_CCMD_FM(val
));
1935 error_report_once("%s: invalid context: 0x%" PRIx64
,
1942 static void vtd_iotlb_global_invalidate(IntelIOMMUState
*s
)
1944 trace_vtd_inv_desc_iotlb_global();
1946 vtd_iommu_replay_all(s
);
1949 static void vtd_iotlb_domain_invalidate(IntelIOMMUState
*s
, uint16_t domain_id
)
1952 VTDAddressSpace
*vtd_as
;
1954 trace_vtd_inv_desc_iotlb_domain(domain_id
);
1957 g_hash_table_foreach_remove(s
->iotlb
, vtd_hash_remove_by_domain
,
1959 vtd_iommu_unlock(s
);
1961 QLIST_FOREACH(vtd_as
, &s
->vtd_as_with_notifiers
, next
) {
1962 if (!vtd_dev_to_context_entry(s
, pci_bus_num(vtd_as
->bus
),
1963 vtd_as
->devfn
, &ce
) &&
1964 domain_id
== vtd_get_domain_id(s
, &ce
)) {
1965 vtd_sync_shadow_page_table(vtd_as
);
1970 static void vtd_iotlb_page_invalidate_notify(IntelIOMMUState
*s
,
1971 uint16_t domain_id
, hwaddr addr
,
1974 VTDAddressSpace
*vtd_as
;
1977 hwaddr size
= (1 << am
) * VTD_PAGE_SIZE
;
1979 QLIST_FOREACH(vtd_as
, &(s
->vtd_as_with_notifiers
), next
) {
1980 ret
= vtd_dev_to_context_entry(s
, pci_bus_num(vtd_as
->bus
),
1981 vtd_as
->devfn
, &ce
);
1982 if (!ret
&& domain_id
== vtd_get_domain_id(s
, &ce
)) {
1983 if (vtd_as_has_map_notifier(vtd_as
)) {
1985 * As long as we have MAP notifications registered in
1986 * any of our IOMMU notifiers, we need to sync the
1987 * shadow page table.
1989 vtd_sync_shadow_page_table_range(vtd_as
, &ce
, addr
, size
);
1992 * For UNMAP-only notifiers, we don't need to walk the
1993 * page tables. We just deliver the PSI down to
1994 * invalidate caches.
1996 IOMMUTLBEntry entry
= {
1997 .target_as
= &address_space_memory
,
1999 .translated_addr
= 0,
2000 .addr_mask
= size
- 1,
2003 memory_region_notify_iommu(&vtd_as
->iommu
, 0, entry
);
2009 static void vtd_iotlb_page_invalidate(IntelIOMMUState
*s
, uint16_t domain_id
,
2010 hwaddr addr
, uint8_t am
)
2012 VTDIOTLBPageInvInfo info
;
2014 trace_vtd_inv_desc_iotlb_pages(domain_id
, addr
, am
);
2016 assert(am
<= VTD_MAMV
);
2017 info
.domain_id
= domain_id
;
2019 info
.mask
= ~((1 << am
) - 1);
2021 g_hash_table_foreach_remove(s
->iotlb
, vtd_hash_remove_by_page
, &info
);
2022 vtd_iommu_unlock(s
);
2023 vtd_iotlb_page_invalidate_notify(s
, domain_id
, addr
, am
);
2027 * Returns the IOTLB Actual Invalidation Granularity.
2028 * @val: the content of the IOTLB_REG
2030 static uint64_t vtd_iotlb_flush(IntelIOMMUState
*s
, uint64_t val
)
2033 uint64_t type
= val
& VTD_TLB_FLUSH_GRANU_MASK
;
2039 case VTD_TLB_GLOBAL_FLUSH
:
2040 iaig
= VTD_TLB_GLOBAL_FLUSH_A
;
2041 vtd_iotlb_global_invalidate(s
);
2044 case VTD_TLB_DSI_FLUSH
:
2045 domain_id
= VTD_TLB_DID(val
);
2046 iaig
= VTD_TLB_DSI_FLUSH_A
;
2047 vtd_iotlb_domain_invalidate(s
, domain_id
);
2050 case VTD_TLB_PSI_FLUSH
:
2051 domain_id
= VTD_TLB_DID(val
);
2052 addr
= vtd_get_quad_raw(s
, DMAR_IVA_REG
);
2053 am
= VTD_IVA_AM(addr
);
2054 addr
= VTD_IVA_ADDR(addr
);
2055 if (am
> VTD_MAMV
) {
2056 error_report_once("%s: address mask overflow: 0x%" PRIx64
,
2057 __func__
, vtd_get_quad_raw(s
, DMAR_IVA_REG
));
2061 iaig
= VTD_TLB_PSI_FLUSH_A
;
2062 vtd_iotlb_page_invalidate(s
, domain_id
, addr
, am
);
2066 error_report_once("%s: invalid granularity: 0x%" PRIx64
,
2073 static void vtd_fetch_inv_desc(IntelIOMMUState
*s
);
2075 static inline bool vtd_queued_inv_disable_check(IntelIOMMUState
*s
)
2077 return s
->qi_enabled
&& (s
->iq_tail
== s
->iq_head
) &&
2078 (s
->iq_last_desc_type
== VTD_INV_DESC_WAIT
);
2081 static void vtd_handle_gcmd_qie(IntelIOMMUState
*s
, bool en
)
2083 uint64_t iqa_val
= vtd_get_quad_raw(s
, DMAR_IQA_REG
);
2085 trace_vtd_inv_qi_enable(en
);
2088 s
->iq
= iqa_val
& VTD_IQA_IQA_MASK(s
->aw_bits
);
2089 /* 2^(x+8) entries */
2090 s
->iq_size
= 1UL << ((iqa_val
& VTD_IQA_QS
) + 8 - (s
->iq_dw
? 1 : 0));
2091 s
->qi_enabled
= true;
2092 trace_vtd_inv_qi_setup(s
->iq
, s
->iq_size
);
2093 /* Ok - report back to driver */
2094 vtd_set_clear_mask_long(s
, DMAR_GSTS_REG
, 0, VTD_GSTS_QIES
);
2096 if (s
->iq_tail
!= 0) {
2098 * This is a spec violation but Windows guests are known to set up
2099 * Queued Invalidation this way so we allow the write and process
2100 * Invalidation Descriptors right away.
2102 trace_vtd_warn_invalid_qi_tail(s
->iq_tail
);
2103 if (!(vtd_get_long_raw(s
, DMAR_FSTS_REG
) & VTD_FSTS_IQE
)) {
2104 vtd_fetch_inv_desc(s
);
2108 if (vtd_queued_inv_disable_check(s
)) {
2109 /* disable Queued Invalidation */
2110 vtd_set_quad_raw(s
, DMAR_IQH_REG
, 0);
2112 s
->qi_enabled
= false;
2113 /* Ok - report back to driver */
2114 vtd_set_clear_mask_long(s
, DMAR_GSTS_REG
, VTD_GSTS_QIES
, 0);
2116 error_report_once("%s: detected improper state when disable QI "
2117 "(head=0x%x, tail=0x%x, last_type=%d)",
2119 s
->iq_head
, s
->iq_tail
, s
->iq_last_desc_type
);
2124 /* Set Root Table Pointer */
2125 static void vtd_handle_gcmd_srtp(IntelIOMMUState
*s
)
2127 vtd_root_table_setup(s
);
2128 /* Ok - report back to driver */
2129 vtd_set_clear_mask_long(s
, DMAR_GSTS_REG
, 0, VTD_GSTS_RTPS
);
2130 vtd_reset_caches(s
);
2131 vtd_address_space_refresh_all(s
);
2134 /* Set Interrupt Remap Table Pointer */
2135 static void vtd_handle_gcmd_sirtp(IntelIOMMUState
*s
)
2137 vtd_interrupt_remap_table_setup(s
);
2138 /* Ok - report back to driver */
2139 vtd_set_clear_mask_long(s
, DMAR_GSTS_REG
, 0, VTD_GSTS_IRTPS
);
2142 /* Handle Translation Enable/Disable */
2143 static void vtd_handle_gcmd_te(IntelIOMMUState
*s
, bool en
)
2145 if (s
->dmar_enabled
== en
) {
2149 trace_vtd_dmar_enable(en
);
2152 s
->dmar_enabled
= true;
2153 /* Ok - report back to driver */
2154 vtd_set_clear_mask_long(s
, DMAR_GSTS_REG
, 0, VTD_GSTS_TES
);
2156 s
->dmar_enabled
= false;
2158 /* Clear the index of Fault Recording Register */
2159 s
->next_frcd_reg
= 0;
2160 /* Ok - report back to driver */
2161 vtd_set_clear_mask_long(s
, DMAR_GSTS_REG
, VTD_GSTS_TES
, 0);
2164 vtd_reset_caches(s
);
2165 vtd_address_space_refresh_all(s
);
2168 /* Handle Interrupt Remap Enable/Disable */
2169 static void vtd_handle_gcmd_ire(IntelIOMMUState
*s
, bool en
)
2171 trace_vtd_ir_enable(en
);
2174 s
->intr_enabled
= true;
2175 /* Ok - report back to driver */
2176 vtd_set_clear_mask_long(s
, DMAR_GSTS_REG
, 0, VTD_GSTS_IRES
);
2178 s
->intr_enabled
= false;
2179 /* Ok - report back to driver */
2180 vtd_set_clear_mask_long(s
, DMAR_GSTS_REG
, VTD_GSTS_IRES
, 0);
2184 /* Handle write to Global Command Register */
2185 static void vtd_handle_gcmd_write(IntelIOMMUState
*s
)
2187 uint32_t status
= vtd_get_long_raw(s
, DMAR_GSTS_REG
);
2188 uint32_t val
= vtd_get_long_raw(s
, DMAR_GCMD_REG
);
2189 uint32_t changed
= status
^ val
;
2191 trace_vtd_reg_write_gcmd(status
, val
);
2192 if (changed
& VTD_GCMD_TE
) {
2193 /* Translation enable/disable */
2194 vtd_handle_gcmd_te(s
, val
& VTD_GCMD_TE
);
2196 if (val
& VTD_GCMD_SRTP
) {
2197 /* Set/update the root-table pointer */
2198 vtd_handle_gcmd_srtp(s
);
2200 if (changed
& VTD_GCMD_QIE
) {
2201 /* Queued Invalidation Enable */
2202 vtd_handle_gcmd_qie(s
, val
& VTD_GCMD_QIE
);
2204 if (val
& VTD_GCMD_SIRTP
) {
2205 /* Set/update the interrupt remapping root-table pointer */
2206 vtd_handle_gcmd_sirtp(s
);
2208 if (changed
& VTD_GCMD_IRE
) {
2209 /* Interrupt remap enable/disable */
2210 vtd_handle_gcmd_ire(s
, val
& VTD_GCMD_IRE
);
2214 /* Handle write to Context Command Register */
2215 static void vtd_handle_ccmd_write(IntelIOMMUState
*s
)
2218 uint64_t val
= vtd_get_quad_raw(s
, DMAR_CCMD_REG
);
2220 /* Context-cache invalidation request */
2221 if (val
& VTD_CCMD_ICC
) {
2222 if (s
->qi_enabled
) {
2223 error_report_once("Queued Invalidation enabled, "
2224 "should not use register-based invalidation");
2227 ret
= vtd_context_cache_invalidate(s
, val
);
2228 /* Invalidation completed. Change something to show */
2229 vtd_set_clear_mask_quad(s
, DMAR_CCMD_REG
, VTD_CCMD_ICC
, 0ULL);
2230 ret
= vtd_set_clear_mask_quad(s
, DMAR_CCMD_REG
, VTD_CCMD_CAIG_MASK
,
2235 /* Handle write to IOTLB Invalidation Register */
2236 static void vtd_handle_iotlb_write(IntelIOMMUState
*s
)
2239 uint64_t val
= vtd_get_quad_raw(s
, DMAR_IOTLB_REG
);
2241 /* IOTLB invalidation request */
2242 if (val
& VTD_TLB_IVT
) {
2243 if (s
->qi_enabled
) {
2244 error_report_once("Queued Invalidation enabled, "
2245 "should not use register-based invalidation");
2248 ret
= vtd_iotlb_flush(s
, val
);
2249 /* Invalidation completed. Change something to show */
2250 vtd_set_clear_mask_quad(s
, DMAR_IOTLB_REG
, VTD_TLB_IVT
, 0ULL);
2251 ret
= vtd_set_clear_mask_quad(s
, DMAR_IOTLB_REG
,
2252 VTD_TLB_FLUSH_GRANU_MASK_A
, ret
);
2256 /* Fetch an Invalidation Descriptor from the Invalidation Queue */
2257 static bool vtd_get_inv_desc(IntelIOMMUState
*s
,
2258 VTDInvDesc
*inv_desc
)
2260 dma_addr_t base_addr
= s
->iq
;
2261 uint32_t offset
= s
->iq_head
;
2262 uint32_t dw
= s
->iq_dw
? 32 : 16;
2263 dma_addr_t addr
= base_addr
+ offset
* dw
;
2265 if (dma_memory_read(&address_space_memory
, addr
, inv_desc
, dw
)) {
2266 error_report_once("Read INV DESC failed.");
2269 inv_desc
->lo
= le64_to_cpu(inv_desc
->lo
);
2270 inv_desc
->hi
= le64_to_cpu(inv_desc
->hi
);
2272 inv_desc
->val
[2] = le64_to_cpu(inv_desc
->val
[2]);
2273 inv_desc
->val
[3] = le64_to_cpu(inv_desc
->val
[3]);
2278 static bool vtd_process_wait_desc(IntelIOMMUState
*s
, VTDInvDesc
*inv_desc
)
2280 if ((inv_desc
->hi
& VTD_INV_DESC_WAIT_RSVD_HI
) ||
2281 (inv_desc
->lo
& VTD_INV_DESC_WAIT_RSVD_LO
)) {
2282 error_report_once("%s: invalid wait desc: hi=%"PRIx64
", lo=%"PRIx64
2283 " (reserved nonzero)", __func__
, inv_desc
->hi
,
2287 if (inv_desc
->lo
& VTD_INV_DESC_WAIT_SW
) {
2289 uint32_t status_data
= (uint32_t)(inv_desc
->lo
>>
2290 VTD_INV_DESC_WAIT_DATA_SHIFT
);
2292 assert(!(inv_desc
->lo
& VTD_INV_DESC_WAIT_IF
));
2294 /* FIXME: need to be masked with HAW? */
2295 dma_addr_t status_addr
= inv_desc
->hi
;
2296 trace_vtd_inv_desc_wait_sw(status_addr
, status_data
);
2297 status_data
= cpu_to_le32(status_data
);
2298 if (dma_memory_write(&address_space_memory
, status_addr
, &status_data
,
2299 sizeof(status_data
))) {
2300 trace_vtd_inv_desc_wait_write_fail(inv_desc
->hi
, inv_desc
->lo
);
2303 } else if (inv_desc
->lo
& VTD_INV_DESC_WAIT_IF
) {
2304 /* Interrupt flag */
2305 vtd_generate_completion_event(s
);
2307 error_report_once("%s: invalid wait desc: hi=%"PRIx64
", lo=%"PRIx64
2308 " (unknown type)", __func__
, inv_desc
->hi
,
2315 static bool vtd_process_context_cache_desc(IntelIOMMUState
*s
,
2316 VTDInvDesc
*inv_desc
)
2318 uint16_t sid
, fmask
;
2320 if ((inv_desc
->lo
& VTD_INV_DESC_CC_RSVD
) || inv_desc
->hi
) {
2321 error_report_once("%s: invalid cc inv desc: hi=%"PRIx64
", lo=%"PRIx64
2322 " (reserved nonzero)", __func__
, inv_desc
->hi
,
2326 switch (inv_desc
->lo
& VTD_INV_DESC_CC_G
) {
2327 case VTD_INV_DESC_CC_DOMAIN
:
2328 trace_vtd_inv_desc_cc_domain(
2329 (uint16_t)VTD_INV_DESC_CC_DID(inv_desc
->lo
));
2331 case VTD_INV_DESC_CC_GLOBAL
:
2332 vtd_context_global_invalidate(s
);
2335 case VTD_INV_DESC_CC_DEVICE
:
2336 sid
= VTD_INV_DESC_CC_SID(inv_desc
->lo
);
2337 fmask
= VTD_INV_DESC_CC_FM(inv_desc
->lo
);
2338 vtd_context_device_invalidate(s
, sid
, fmask
);
2342 error_report_once("%s: invalid cc inv desc: hi=%"PRIx64
", lo=%"PRIx64
2343 " (invalid type)", __func__
, inv_desc
->hi
,
2350 static bool vtd_process_iotlb_desc(IntelIOMMUState
*s
, VTDInvDesc
*inv_desc
)
2356 if ((inv_desc
->lo
& VTD_INV_DESC_IOTLB_RSVD_LO
) ||
2357 (inv_desc
->hi
& VTD_INV_DESC_IOTLB_RSVD_HI
)) {
2358 error_report_once("%s: invalid iotlb inv desc: hi=0x%"PRIx64
2359 ", lo=0x%"PRIx64
" (reserved bits unzero)",
2360 __func__
, inv_desc
->hi
, inv_desc
->lo
);
2364 switch (inv_desc
->lo
& VTD_INV_DESC_IOTLB_G
) {
2365 case VTD_INV_DESC_IOTLB_GLOBAL
:
2366 vtd_iotlb_global_invalidate(s
);
2369 case VTD_INV_DESC_IOTLB_DOMAIN
:
2370 domain_id
= VTD_INV_DESC_IOTLB_DID(inv_desc
->lo
);
2371 vtd_iotlb_domain_invalidate(s
, domain_id
);
2374 case VTD_INV_DESC_IOTLB_PAGE
:
2375 domain_id
= VTD_INV_DESC_IOTLB_DID(inv_desc
->lo
);
2376 addr
= VTD_INV_DESC_IOTLB_ADDR(inv_desc
->hi
);
2377 am
= VTD_INV_DESC_IOTLB_AM(inv_desc
->hi
);
2378 if (am
> VTD_MAMV
) {
2379 error_report_once("%s: invalid iotlb inv desc: hi=0x%"PRIx64
2380 ", lo=0x%"PRIx64
" (am=%u > VTD_MAMV=%u)",
2381 __func__
, inv_desc
->hi
, inv_desc
->lo
,
2382 am
, (unsigned)VTD_MAMV
);
2385 vtd_iotlb_page_invalidate(s
, domain_id
, addr
, am
);
2389 error_report_once("%s: invalid iotlb inv desc: hi=0x%"PRIx64
2390 ", lo=0x%"PRIx64
" (type mismatch: 0x%llx)",
2391 __func__
, inv_desc
->hi
, inv_desc
->lo
,
2392 inv_desc
->lo
& VTD_INV_DESC_IOTLB_G
);
2398 static bool vtd_process_inv_iec_desc(IntelIOMMUState
*s
,
2399 VTDInvDesc
*inv_desc
)
2401 trace_vtd_inv_desc_iec(inv_desc
->iec
.granularity
,
2402 inv_desc
->iec
.index
,
2403 inv_desc
->iec
.index_mask
);
2405 vtd_iec_notify_all(s
, !inv_desc
->iec
.granularity
,
2406 inv_desc
->iec
.index
,
2407 inv_desc
->iec
.index_mask
);
2411 static bool vtd_process_device_iotlb_desc(IntelIOMMUState
*s
,
2412 VTDInvDesc
*inv_desc
)
2414 VTDAddressSpace
*vtd_dev_as
;
2415 IOMMUTLBEntry entry
;
2416 struct VTDBus
*vtd_bus
;
2424 addr
= VTD_INV_DESC_DEVICE_IOTLB_ADDR(inv_desc
->hi
);
2425 sid
= VTD_INV_DESC_DEVICE_IOTLB_SID(inv_desc
->lo
);
2428 size
= VTD_INV_DESC_DEVICE_IOTLB_SIZE(inv_desc
->hi
);
2430 if ((inv_desc
->lo
& VTD_INV_DESC_DEVICE_IOTLB_RSVD_LO
) ||
2431 (inv_desc
->hi
& VTD_INV_DESC_DEVICE_IOTLB_RSVD_HI
)) {
2432 error_report_once("%s: invalid dev-iotlb inv desc: hi=%"PRIx64
2433 ", lo=%"PRIx64
" (reserved nonzero)", __func__
,
2434 inv_desc
->hi
, inv_desc
->lo
);
2438 vtd_bus
= vtd_find_as_from_bus_num(s
, bus_num
);
2443 vtd_dev_as
= vtd_bus
->dev_as
[devfn
];
2448 /* According to ATS spec table 2.4:
2449 * S = 0, bits 15:12 = xxxx range size: 4K
2450 * S = 1, bits 15:12 = xxx0 range size: 8K
2451 * S = 1, bits 15:12 = xx01 range size: 16K
2452 * S = 1, bits 15:12 = x011 range size: 32K
2453 * S = 1, bits 15:12 = 0111 range size: 64K
2457 sz
= (VTD_PAGE_SIZE
* 2) << cto64(addr
>> VTD_PAGE_SHIFT
);
2463 entry
.target_as
= &vtd_dev_as
->as
;
2464 entry
.addr_mask
= sz
- 1;
2466 entry
.perm
= IOMMU_NONE
;
2467 entry
.translated_addr
= 0;
2468 memory_region_notify_iommu(&vtd_dev_as
->iommu
, 0, entry
);
2474 static bool vtd_process_inv_desc(IntelIOMMUState
*s
)
2476 VTDInvDesc inv_desc
;
2479 trace_vtd_inv_qi_head(s
->iq_head
);
2480 if (!vtd_get_inv_desc(s
, &inv_desc
)) {
2481 s
->iq_last_desc_type
= VTD_INV_DESC_NONE
;
2485 desc_type
= inv_desc
.lo
& VTD_INV_DESC_TYPE
;
2486 /* FIXME: should update at first or at last? */
2487 s
->iq_last_desc_type
= desc_type
;
2489 switch (desc_type
) {
2490 case VTD_INV_DESC_CC
:
2491 trace_vtd_inv_desc("context-cache", inv_desc
.hi
, inv_desc
.lo
);
2492 if (!vtd_process_context_cache_desc(s
, &inv_desc
)) {
2497 case VTD_INV_DESC_IOTLB
:
2498 trace_vtd_inv_desc("iotlb", inv_desc
.hi
, inv_desc
.lo
);
2499 if (!vtd_process_iotlb_desc(s
, &inv_desc
)) {
2505 * TODO: the entity of below two cases will be implemented in future series.
2506 * To make guest (which integrates scalable mode support patch set in
2507 * iommu driver) work, just return true is enough so far.
2509 case VTD_INV_DESC_PC
:
2512 case VTD_INV_DESC_PIOTLB
:
2515 case VTD_INV_DESC_WAIT
:
2516 trace_vtd_inv_desc("wait", inv_desc
.hi
, inv_desc
.lo
);
2517 if (!vtd_process_wait_desc(s
, &inv_desc
)) {
2522 case VTD_INV_DESC_IEC
:
2523 trace_vtd_inv_desc("iec", inv_desc
.hi
, inv_desc
.lo
);
2524 if (!vtd_process_inv_iec_desc(s
, &inv_desc
)) {
2529 case VTD_INV_DESC_DEVICE
:
2530 trace_vtd_inv_desc("device", inv_desc
.hi
, inv_desc
.lo
);
2531 if (!vtd_process_device_iotlb_desc(s
, &inv_desc
)) {
2537 error_report_once("%s: invalid inv desc: hi=%"PRIx64
", lo=%"PRIx64
2538 " (unknown type)", __func__
, inv_desc
.hi
,
2543 if (s
->iq_head
== s
->iq_size
) {
2549 /* Try to fetch and process more Invalidation Descriptors */
2550 static void vtd_fetch_inv_desc(IntelIOMMUState
*s
)
2554 /* Refer to 10.4.23 of VT-d spec 3.0 */
2555 qi_shift
= s
->iq_dw
? VTD_IQH_QH_SHIFT_5
: VTD_IQH_QH_SHIFT_4
;
2557 trace_vtd_inv_qi_fetch();
2559 if (s
->iq_tail
>= s
->iq_size
) {
2560 /* Detects an invalid Tail pointer */
2561 error_report_once("%s: detected invalid QI tail "
2562 "(tail=0x%x, size=0x%x)",
2563 __func__
, s
->iq_tail
, s
->iq_size
);
2564 vtd_handle_inv_queue_error(s
);
2567 while (s
->iq_head
!= s
->iq_tail
) {
2568 if (!vtd_process_inv_desc(s
)) {
2569 /* Invalidation Queue Errors */
2570 vtd_handle_inv_queue_error(s
);
2573 /* Must update the IQH_REG in time */
2574 vtd_set_quad_raw(s
, DMAR_IQH_REG
,
2575 (((uint64_t)(s
->iq_head
)) << qi_shift
) &
2580 /* Handle write to Invalidation Queue Tail Register */
2581 static void vtd_handle_iqt_write(IntelIOMMUState
*s
)
2583 uint64_t val
= vtd_get_quad_raw(s
, DMAR_IQT_REG
);
2585 if (s
->iq_dw
&& (val
& VTD_IQT_QT_256_RSV_BIT
)) {
2586 error_report_once("%s: RSV bit is set: val=0x%"PRIx64
,
2590 s
->iq_tail
= VTD_IQT_QT(s
->iq_dw
, val
);
2591 trace_vtd_inv_qi_tail(s
->iq_tail
);
2593 if (s
->qi_enabled
&& !(vtd_get_long_raw(s
, DMAR_FSTS_REG
) & VTD_FSTS_IQE
)) {
2594 /* Process Invalidation Queue here */
2595 vtd_fetch_inv_desc(s
);
2599 static void vtd_handle_fsts_write(IntelIOMMUState
*s
)
2601 uint32_t fsts_reg
= vtd_get_long_raw(s
, DMAR_FSTS_REG
);
2602 uint32_t fectl_reg
= vtd_get_long_raw(s
, DMAR_FECTL_REG
);
2603 uint32_t status_fields
= VTD_FSTS_PFO
| VTD_FSTS_PPF
| VTD_FSTS_IQE
;
2605 if ((fectl_reg
& VTD_FECTL_IP
) && !(fsts_reg
& status_fields
)) {
2606 vtd_set_clear_mask_long(s
, DMAR_FECTL_REG
, VTD_FECTL_IP
, 0);
2607 trace_vtd_fsts_clear_ip();
2609 /* FIXME: when IQE is Clear, should we try to fetch some Invalidation
2610 * Descriptors if there are any when Queued Invalidation is enabled?
2614 static void vtd_handle_fectl_write(IntelIOMMUState
*s
)
2617 /* FIXME: when software clears the IM field, check the IP field. But do we
2618 * need to compare the old value and the new value to conclude that
2619 * software clears the IM field? Or just check if the IM field is zero?
2621 fectl_reg
= vtd_get_long_raw(s
, DMAR_FECTL_REG
);
2623 trace_vtd_reg_write_fectl(fectl_reg
);
2625 if ((fectl_reg
& VTD_FECTL_IP
) && !(fectl_reg
& VTD_FECTL_IM
)) {
2626 vtd_generate_interrupt(s
, DMAR_FEADDR_REG
, DMAR_FEDATA_REG
);
2627 vtd_set_clear_mask_long(s
, DMAR_FECTL_REG
, VTD_FECTL_IP
, 0);
2631 static void vtd_handle_ics_write(IntelIOMMUState
*s
)
2633 uint32_t ics_reg
= vtd_get_long_raw(s
, DMAR_ICS_REG
);
2634 uint32_t iectl_reg
= vtd_get_long_raw(s
, DMAR_IECTL_REG
);
2636 if ((iectl_reg
& VTD_IECTL_IP
) && !(ics_reg
& VTD_ICS_IWC
)) {
2637 trace_vtd_reg_ics_clear_ip();
2638 vtd_set_clear_mask_long(s
, DMAR_IECTL_REG
, VTD_IECTL_IP
, 0);
2642 static void vtd_handle_iectl_write(IntelIOMMUState
*s
)
2645 /* FIXME: when software clears the IM field, check the IP field. But do we
2646 * need to compare the old value and the new value to conclude that
2647 * software clears the IM field? Or just check if the IM field is zero?
2649 iectl_reg
= vtd_get_long_raw(s
, DMAR_IECTL_REG
);
2651 trace_vtd_reg_write_iectl(iectl_reg
);
2653 if ((iectl_reg
& VTD_IECTL_IP
) && !(iectl_reg
& VTD_IECTL_IM
)) {
2654 vtd_generate_interrupt(s
, DMAR_IEADDR_REG
, DMAR_IEDATA_REG
);
2655 vtd_set_clear_mask_long(s
, DMAR_IECTL_REG
, VTD_IECTL_IP
, 0);
2659 static uint64_t vtd_mem_read(void *opaque
, hwaddr addr
, unsigned size
)
2661 IntelIOMMUState
*s
= opaque
;
2664 trace_vtd_reg_read(addr
, size
);
2666 if (addr
+ size
> DMAR_REG_SIZE
) {
2667 error_report_once("%s: MMIO over range: addr=0x%" PRIx64
2668 " size=0x%u", __func__
, addr
, size
);
2669 return (uint64_t)-1;
2673 /* Root Table Address Register, 64-bit */
2674 case DMAR_RTADDR_REG
:
2675 val
= vtd_get_quad_raw(s
, DMAR_RTADDR_REG
);
2677 val
= val
& ((1ULL << 32) - 1);
2681 case DMAR_RTADDR_REG_HI
:
2683 val
= vtd_get_quad_raw(s
, DMAR_RTADDR_REG
) >> 32;
2686 /* Invalidation Queue Address Register, 64-bit */
2688 val
= s
->iq
| (vtd_get_quad(s
, DMAR_IQA_REG
) & VTD_IQA_QS
);
2690 val
= val
& ((1ULL << 32) - 1);
2694 case DMAR_IQA_REG_HI
:
2701 val
= vtd_get_long(s
, addr
);
2703 val
= vtd_get_quad(s
, addr
);
2710 static void vtd_mem_write(void *opaque
, hwaddr addr
,
2711 uint64_t val
, unsigned size
)
2713 IntelIOMMUState
*s
= opaque
;
2715 trace_vtd_reg_write(addr
, size
, val
);
2717 if (addr
+ size
> DMAR_REG_SIZE
) {
2718 error_report_once("%s: MMIO over range: addr=0x%" PRIx64
2719 " size=0x%u", __func__
, addr
, size
);
2724 /* Global Command Register, 32-bit */
2726 vtd_set_long(s
, addr
, val
);
2727 vtd_handle_gcmd_write(s
);
2730 /* Context Command Register, 64-bit */
2733 vtd_set_long(s
, addr
, val
);
2735 vtd_set_quad(s
, addr
, val
);
2736 vtd_handle_ccmd_write(s
);
2740 case DMAR_CCMD_REG_HI
:
2742 vtd_set_long(s
, addr
, val
);
2743 vtd_handle_ccmd_write(s
);
2746 /* IOTLB Invalidation Register, 64-bit */
2747 case DMAR_IOTLB_REG
:
2749 vtd_set_long(s
, addr
, val
);
2751 vtd_set_quad(s
, addr
, val
);
2752 vtd_handle_iotlb_write(s
);
2756 case DMAR_IOTLB_REG_HI
:
2758 vtd_set_long(s
, addr
, val
);
2759 vtd_handle_iotlb_write(s
);
2762 /* Invalidate Address Register, 64-bit */
2765 vtd_set_long(s
, addr
, val
);
2767 vtd_set_quad(s
, addr
, val
);
2771 case DMAR_IVA_REG_HI
:
2773 vtd_set_long(s
, addr
, val
);
2776 /* Fault Status Register, 32-bit */
2779 vtd_set_long(s
, addr
, val
);
2780 vtd_handle_fsts_write(s
);
2783 /* Fault Event Control Register, 32-bit */
2784 case DMAR_FECTL_REG
:
2786 vtd_set_long(s
, addr
, val
);
2787 vtd_handle_fectl_write(s
);
2790 /* Fault Event Data Register, 32-bit */
2791 case DMAR_FEDATA_REG
:
2793 vtd_set_long(s
, addr
, val
);
2796 /* Fault Event Address Register, 32-bit */
2797 case DMAR_FEADDR_REG
:
2799 vtd_set_long(s
, addr
, val
);
2802 * While the register is 32-bit only, some guests (Xen...) write to
2805 vtd_set_quad(s
, addr
, val
);
2809 /* Fault Event Upper Address Register, 32-bit */
2810 case DMAR_FEUADDR_REG
:
2812 vtd_set_long(s
, addr
, val
);
2815 /* Protected Memory Enable Register, 32-bit */
2818 vtd_set_long(s
, addr
, val
);
2821 /* Root Table Address Register, 64-bit */
2822 case DMAR_RTADDR_REG
:
2824 vtd_set_long(s
, addr
, val
);
2826 vtd_set_quad(s
, addr
, val
);
2830 case DMAR_RTADDR_REG_HI
:
2832 vtd_set_long(s
, addr
, val
);
2835 /* Invalidation Queue Tail Register, 64-bit */
2838 vtd_set_long(s
, addr
, val
);
2840 vtd_set_quad(s
, addr
, val
);
2842 vtd_handle_iqt_write(s
);
2845 case DMAR_IQT_REG_HI
:
2847 vtd_set_long(s
, addr
, val
);
2848 /* 19:63 of IQT_REG is RsvdZ, do nothing here */
2851 /* Invalidation Queue Address Register, 64-bit */
2854 vtd_set_long(s
, addr
, val
);
2856 vtd_set_quad(s
, addr
, val
);
2858 if (s
->ecap
& VTD_ECAP_SMTS
&&
2859 val
& VTD_IQA_DW_MASK
) {
2866 case DMAR_IQA_REG_HI
:
2868 vtd_set_long(s
, addr
, val
);
2871 /* Invalidation Completion Status Register, 32-bit */
2874 vtd_set_long(s
, addr
, val
);
2875 vtd_handle_ics_write(s
);
2878 /* Invalidation Event Control Register, 32-bit */
2879 case DMAR_IECTL_REG
:
2881 vtd_set_long(s
, addr
, val
);
2882 vtd_handle_iectl_write(s
);
2885 /* Invalidation Event Data Register, 32-bit */
2886 case DMAR_IEDATA_REG
:
2888 vtd_set_long(s
, addr
, val
);
2891 /* Invalidation Event Address Register, 32-bit */
2892 case DMAR_IEADDR_REG
:
2894 vtd_set_long(s
, addr
, val
);
2897 /* Invalidation Event Upper Address Register, 32-bit */
2898 case DMAR_IEUADDR_REG
:
2900 vtd_set_long(s
, addr
, val
);
2903 /* Fault Recording Registers, 128-bit */
2904 case DMAR_FRCD_REG_0_0
:
2906 vtd_set_long(s
, addr
, val
);
2908 vtd_set_quad(s
, addr
, val
);
2912 case DMAR_FRCD_REG_0_1
:
2914 vtd_set_long(s
, addr
, val
);
2917 case DMAR_FRCD_REG_0_2
:
2919 vtd_set_long(s
, addr
, val
);
2921 vtd_set_quad(s
, addr
, val
);
2922 /* May clear bit 127 (Fault), update PPF */
2923 vtd_update_fsts_ppf(s
);
2927 case DMAR_FRCD_REG_0_3
:
2929 vtd_set_long(s
, addr
, val
);
2930 /* May clear bit 127 (Fault), update PPF */
2931 vtd_update_fsts_ppf(s
);
2936 vtd_set_long(s
, addr
, val
);
2938 vtd_set_quad(s
, addr
, val
);
2942 case DMAR_IRTA_REG_HI
:
2944 vtd_set_long(s
, addr
, val
);
2949 vtd_set_long(s
, addr
, val
);
2951 vtd_set_quad(s
, addr
, val
);
2956 static IOMMUTLBEntry
vtd_iommu_translate(IOMMUMemoryRegion
*iommu
, hwaddr addr
,
2957 IOMMUAccessFlags flag
, int iommu_idx
)
2959 VTDAddressSpace
*vtd_as
= container_of(iommu
, VTDAddressSpace
, iommu
);
2960 IntelIOMMUState
*s
= vtd_as
->iommu_state
;
2961 IOMMUTLBEntry iotlb
= {
2962 /* We'll fill in the rest later. */
2963 .target_as
= &address_space_memory
,
2967 if (likely(s
->dmar_enabled
)) {
2968 success
= vtd_do_iommu_translate(vtd_as
, vtd_as
->bus
, vtd_as
->devfn
,
2969 addr
, flag
& IOMMU_WO
, &iotlb
);
2971 /* DMAR disabled, passthrough, use 4k-page*/
2972 iotlb
.iova
= addr
& VTD_PAGE_MASK_4K
;
2973 iotlb
.translated_addr
= addr
& VTD_PAGE_MASK_4K
;
2974 iotlb
.addr_mask
= ~VTD_PAGE_MASK_4K
;
2975 iotlb
.perm
= IOMMU_RW
;
2979 if (likely(success
)) {
2980 trace_vtd_dmar_translate(pci_bus_num(vtd_as
->bus
),
2981 VTD_PCI_SLOT(vtd_as
->devfn
),
2982 VTD_PCI_FUNC(vtd_as
->devfn
),
2983 iotlb
.iova
, iotlb
.translated_addr
,
2986 error_report_once("%s: detected translation failure "
2987 "(dev=%02x:%02x:%02x, iova=0x%" PRIx64
")",
2988 __func__
, pci_bus_num(vtd_as
->bus
),
2989 VTD_PCI_SLOT(vtd_as
->devfn
),
2990 VTD_PCI_FUNC(vtd_as
->devfn
),
2997 static int vtd_iommu_notify_flag_changed(IOMMUMemoryRegion
*iommu
,
2998 IOMMUNotifierFlag old
,
2999 IOMMUNotifierFlag
new,
3002 VTDAddressSpace
*vtd_as
= container_of(iommu
, VTDAddressSpace
, iommu
);
3003 IntelIOMMUState
*s
= vtd_as
->iommu_state
;
3005 /* Update per-address-space notifier flags */
3006 vtd_as
->notifier_flags
= new;
3008 if (old
== IOMMU_NOTIFIER_NONE
) {
3009 QLIST_INSERT_HEAD(&s
->vtd_as_with_notifiers
, vtd_as
, next
);
3010 } else if (new == IOMMU_NOTIFIER_NONE
) {
3011 QLIST_REMOVE(vtd_as
, next
);
3016 static int vtd_post_load(void *opaque
, int version_id
)
3018 IntelIOMMUState
*iommu
= opaque
;
3021 * Memory regions are dynamically turned on/off depending on
3022 * context entry configurations from the guest. After migration,
3023 * we need to make sure the memory regions are still correct.
3025 vtd_switch_address_space_all(iommu
);
3028 * We don't need to migrate the root_scalable because we can
3029 * simply do the calculation after the loading is complete. We
3030 * can actually do similar things with root, dmar_enabled, etc.
3031 * however since we've had them already so we'd better keep them
3032 * for compatibility of migration.
3034 vtd_update_scalable_state(iommu
);
3039 static const VMStateDescription vtd_vmstate
= {
3040 .name
= "iommu-intel",
3042 .minimum_version_id
= 1,
3043 .priority
= MIG_PRI_IOMMU
,
3044 .post_load
= vtd_post_load
,
3045 .fields
= (VMStateField
[]) {
3046 VMSTATE_UINT64(root
, IntelIOMMUState
),
3047 VMSTATE_UINT64(intr_root
, IntelIOMMUState
),
3048 VMSTATE_UINT64(iq
, IntelIOMMUState
),
3049 VMSTATE_UINT32(intr_size
, IntelIOMMUState
),
3050 VMSTATE_UINT16(iq_head
, IntelIOMMUState
),
3051 VMSTATE_UINT16(iq_tail
, IntelIOMMUState
),
3052 VMSTATE_UINT16(iq_size
, IntelIOMMUState
),
3053 VMSTATE_UINT16(next_frcd_reg
, IntelIOMMUState
),
3054 VMSTATE_UINT8_ARRAY(csr
, IntelIOMMUState
, DMAR_REG_SIZE
),
3055 VMSTATE_UINT8(iq_last_desc_type
, IntelIOMMUState
),
3056 VMSTATE_UNUSED(1), /* bool root_extended is obsolete by VT-d */
3057 VMSTATE_BOOL(dmar_enabled
, IntelIOMMUState
),
3058 VMSTATE_BOOL(qi_enabled
, IntelIOMMUState
),
3059 VMSTATE_BOOL(intr_enabled
, IntelIOMMUState
),
3060 VMSTATE_BOOL(intr_eime
, IntelIOMMUState
),
3061 VMSTATE_END_OF_LIST()
3065 static const MemoryRegionOps vtd_mem_ops
= {
3066 .read
= vtd_mem_read
,
3067 .write
= vtd_mem_write
,
3068 .endianness
= DEVICE_LITTLE_ENDIAN
,
3070 .min_access_size
= 4,
3071 .max_access_size
= 8,
3074 .min_access_size
= 4,
3075 .max_access_size
= 8,
3079 static Property vtd_properties
[] = {
3080 DEFINE_PROP_UINT32("version", IntelIOMMUState
, version
, 0),
3081 DEFINE_PROP_ON_OFF_AUTO("eim", IntelIOMMUState
, intr_eim
,
3083 DEFINE_PROP_BOOL("x-buggy-eim", IntelIOMMUState
, buggy_eim
, false),
3084 DEFINE_PROP_UINT8("aw-bits", IntelIOMMUState
, aw_bits
,
3085 VTD_HOST_ADDRESS_WIDTH
),
3086 DEFINE_PROP_BOOL("caching-mode", IntelIOMMUState
, caching_mode
, FALSE
),
3087 DEFINE_PROP_BOOL("x-scalable-mode", IntelIOMMUState
, scalable_mode
, FALSE
),
3088 DEFINE_PROP_BOOL("dma-drain", IntelIOMMUState
, dma_drain
, true),
3089 DEFINE_PROP_END_OF_LIST(),
3092 /* Read IRTE entry with specific index */
3093 static int vtd_irte_get(IntelIOMMUState
*iommu
, uint16_t index
,
3094 VTD_IR_TableEntry
*entry
, uint16_t sid
)
3096 static const uint16_t vtd_svt_mask
[VTD_SQ_MAX
] = \
3097 {0xffff, 0xfffb, 0xfff9, 0xfff8};
3098 dma_addr_t addr
= 0x00;
3099 uint16_t mask
, source_id
;
3100 uint8_t bus
, bus_max
, bus_min
;
3102 if (index
>= iommu
->intr_size
) {
3103 error_report_once("%s: index too large: ind=0x%x",
3105 return -VTD_FR_IR_INDEX_OVER
;
3108 addr
= iommu
->intr_root
+ index
* sizeof(*entry
);
3109 if (dma_memory_read(&address_space_memory
, addr
, entry
,
3111 error_report_once("%s: read failed: ind=0x%x addr=0x%" PRIx64
,
3112 __func__
, index
, addr
);
3113 return -VTD_FR_IR_ROOT_INVAL
;
3116 trace_vtd_ir_irte_get(index
, le64_to_cpu(entry
->data
[1]),
3117 le64_to_cpu(entry
->data
[0]));
3119 if (!entry
->irte
.present
) {
3120 error_report_once("%s: detected non-present IRTE "
3121 "(index=%u, high=0x%" PRIx64
", low=0x%" PRIx64
")",
3122 __func__
, index
, le64_to_cpu(entry
->data
[1]),
3123 le64_to_cpu(entry
->data
[0]));
3124 return -VTD_FR_IR_ENTRY_P
;
3127 if (entry
->irte
.__reserved_0
|| entry
->irte
.__reserved_1
||
3128 entry
->irte
.__reserved_2
) {
3129 error_report_once("%s: detected non-zero reserved IRTE "
3130 "(index=%u, high=0x%" PRIx64
", low=0x%" PRIx64
")",
3131 __func__
, index
, le64_to_cpu(entry
->data
[1]),
3132 le64_to_cpu(entry
->data
[0]));
3133 return -VTD_FR_IR_IRTE_RSVD
;
3136 if (sid
!= X86_IOMMU_SID_INVALID
) {
3137 /* Validate IRTE SID */
3138 source_id
= le32_to_cpu(entry
->irte
.source_id
);
3139 switch (entry
->irte
.sid_vtype
) {
3144 mask
= vtd_svt_mask
[entry
->irte
.sid_q
];
3145 if ((source_id
& mask
) != (sid
& mask
)) {
3146 error_report_once("%s: invalid IRTE SID "
3147 "(index=%u, sid=%u, source_id=%u)",
3148 __func__
, index
, sid
, source_id
);
3149 return -VTD_FR_IR_SID_ERR
;
3154 bus_max
= source_id
>> 8;
3155 bus_min
= source_id
& 0xff;
3157 if (bus
> bus_max
|| bus
< bus_min
) {
3158 error_report_once("%s: invalid SVT_BUS "
3159 "(index=%u, bus=%u, min=%u, max=%u)",
3160 __func__
, index
, bus
, bus_min
, bus_max
);
3161 return -VTD_FR_IR_SID_ERR
;
3166 error_report_once("%s: detected invalid IRTE SVT "
3167 "(index=%u, type=%d)", __func__
,
3168 index
, entry
->irte
.sid_vtype
);
3169 /* Take this as verification failure. */
3170 return -VTD_FR_IR_SID_ERR
;
3177 /* Fetch IRQ information of specific IR index */
3178 static int vtd_remap_irq_get(IntelIOMMUState
*iommu
, uint16_t index
,
3179 X86IOMMUIrq
*irq
, uint16_t sid
)
3181 VTD_IR_TableEntry irte
= {};
3184 ret
= vtd_irte_get(iommu
, index
, &irte
, sid
);
3189 irq
->trigger_mode
= irte
.irte
.trigger_mode
;
3190 irq
->vector
= irte
.irte
.vector
;
3191 irq
->delivery_mode
= irte
.irte
.delivery_mode
;
3192 irq
->dest
= le32_to_cpu(irte
.irte
.dest_id
);
3193 if (!iommu
->intr_eime
) {
3194 #define VTD_IR_APIC_DEST_MASK (0xff00ULL)
3195 #define VTD_IR_APIC_DEST_SHIFT (8)
3196 irq
->dest
= (irq
->dest
& VTD_IR_APIC_DEST_MASK
) >>
3197 VTD_IR_APIC_DEST_SHIFT
;
3199 irq
->dest_mode
= irte
.irte
.dest_mode
;
3200 irq
->redir_hint
= irte
.irte
.redir_hint
;
3202 trace_vtd_ir_remap(index
, irq
->trigger_mode
, irq
->vector
,
3203 irq
->delivery_mode
, irq
->dest
, irq
->dest_mode
);
3208 /* Interrupt remapping for MSI/MSI-X entry */
3209 static int vtd_interrupt_remap_msi(IntelIOMMUState
*iommu
,
3211 MSIMessage
*translated
,
3215 VTD_IR_MSIAddress addr
;
3217 X86IOMMUIrq irq
= {};
3219 assert(origin
&& translated
);
3221 trace_vtd_ir_remap_msi_req(origin
->address
, origin
->data
);
3223 if (!iommu
|| !iommu
->intr_enabled
) {
3224 memcpy(translated
, origin
, sizeof(*origin
));
3228 if (origin
->address
& VTD_MSI_ADDR_HI_MASK
) {
3229 error_report_once("%s: MSI address high 32 bits non-zero detected: "
3230 "address=0x%" PRIx64
, __func__
, origin
->address
);
3231 return -VTD_FR_IR_REQ_RSVD
;
3234 addr
.data
= origin
->address
& VTD_MSI_ADDR_LO_MASK
;
3235 if (addr
.addr
.__head
!= 0xfee) {
3236 error_report_once("%s: MSI address low 32 bit invalid: 0x%" PRIx32
,
3237 __func__
, addr
.data
);
3238 return -VTD_FR_IR_REQ_RSVD
;
3241 /* This is compatible mode. */
3242 if (addr
.addr
.int_mode
!= VTD_IR_INT_FORMAT_REMAP
) {
3243 memcpy(translated
, origin
, sizeof(*origin
));
3247 index
= addr
.addr
.index_h
<< 15 | le16_to_cpu(addr
.addr
.index_l
);
3249 #define VTD_IR_MSI_DATA_SUBHANDLE (0x0000ffff)
3250 #define VTD_IR_MSI_DATA_RESERVED (0xffff0000)
3252 if (addr
.addr
.sub_valid
) {
3253 /* See VT-d spec 5.1.2.2 and 5.1.3 on subhandle */
3254 index
+= origin
->data
& VTD_IR_MSI_DATA_SUBHANDLE
;
3257 ret
= vtd_remap_irq_get(iommu
, index
, &irq
, sid
);
3262 if (addr
.addr
.sub_valid
) {
3263 trace_vtd_ir_remap_type("MSI");
3264 if (origin
->data
& VTD_IR_MSI_DATA_RESERVED
) {
3265 error_report_once("%s: invalid IR MSI "
3266 "(sid=%u, address=0x%" PRIx64
3267 ", data=0x%" PRIx32
")",
3268 __func__
, sid
, origin
->address
, origin
->data
);
3269 return -VTD_FR_IR_REQ_RSVD
;
3272 uint8_t vector
= origin
->data
& 0xff;
3273 uint8_t trigger_mode
= (origin
->data
>> MSI_DATA_TRIGGER_SHIFT
) & 0x1;
3275 trace_vtd_ir_remap_type("IOAPIC");
3276 /* IOAPIC entry vector should be aligned with IRTE vector
3277 * (see vt-d spec 5.1.5.1). */
3278 if (vector
!= irq
.vector
) {
3279 trace_vtd_warn_ir_vector(sid
, index
, vector
, irq
.vector
);
3282 /* The Trigger Mode field must match the Trigger Mode in the IRTE.
3283 * (see vt-d spec 5.1.5.1). */
3284 if (trigger_mode
!= irq
.trigger_mode
) {
3285 trace_vtd_warn_ir_trigger(sid
, index
, trigger_mode
,
3291 * We'd better keep the last two bits, assuming that guest OS
3292 * might modify it. Keep it does not hurt after all.
3294 irq
.msi_addr_last_bits
= addr
.addr
.__not_care
;
3296 /* Translate X86IOMMUIrq to MSI message */
3297 x86_iommu_irq_to_msi_message(&irq
, translated
);
3300 trace_vtd_ir_remap_msi(origin
->address
, origin
->data
,
3301 translated
->address
, translated
->data
);
3305 static int vtd_int_remap(X86IOMMUState
*iommu
, MSIMessage
*src
,
3306 MSIMessage
*dst
, uint16_t sid
)
3308 return vtd_interrupt_remap_msi(INTEL_IOMMU_DEVICE(iommu
),
3312 static MemTxResult
vtd_mem_ir_read(void *opaque
, hwaddr addr
,
3313 uint64_t *data
, unsigned size
,
3319 static MemTxResult
vtd_mem_ir_write(void *opaque
, hwaddr addr
,
3320 uint64_t value
, unsigned size
,
3324 MSIMessage from
= {}, to
= {};
3325 uint16_t sid
= X86_IOMMU_SID_INVALID
;
3327 from
.address
= (uint64_t) addr
+ VTD_INTERRUPT_ADDR_FIRST
;
3328 from
.data
= (uint32_t) value
;
3330 if (!attrs
.unspecified
) {
3331 /* We have explicit Source ID */
3332 sid
= attrs
.requester_id
;
3335 ret
= vtd_interrupt_remap_msi(opaque
, &from
, &to
, sid
);
3337 /* TODO: report error */
3338 /* Drop this interrupt */
3342 apic_get_class()->send_msi(&to
);
3347 static const MemoryRegionOps vtd_mem_ir_ops
= {
3348 .read_with_attrs
= vtd_mem_ir_read
,
3349 .write_with_attrs
= vtd_mem_ir_write
,
3350 .endianness
= DEVICE_LITTLE_ENDIAN
,
3352 .min_access_size
= 4,
3353 .max_access_size
= 4,
3356 .min_access_size
= 4,
3357 .max_access_size
= 4,
3361 VTDAddressSpace
*vtd_find_add_as(IntelIOMMUState
*s
, PCIBus
*bus
, int devfn
)
3363 uintptr_t key
= (uintptr_t)bus
;
3364 VTDBus
*vtd_bus
= g_hash_table_lookup(s
->vtd_as_by_busptr
, &key
);
3365 VTDAddressSpace
*vtd_dev_as
;
3369 uintptr_t *new_key
= g_malloc(sizeof(*new_key
));
3370 *new_key
= (uintptr_t)bus
;
3371 /* No corresponding free() */
3372 vtd_bus
= g_malloc0(sizeof(VTDBus
) + sizeof(VTDAddressSpace
*) * \
3375 g_hash_table_insert(s
->vtd_as_by_busptr
, new_key
, vtd_bus
);
3378 vtd_dev_as
= vtd_bus
->dev_as
[devfn
];
3381 snprintf(name
, sizeof(name
), "vtd-%02x.%x", PCI_SLOT(devfn
),
3383 vtd_bus
->dev_as
[devfn
] = vtd_dev_as
= g_malloc0(sizeof(VTDAddressSpace
));
3385 vtd_dev_as
->bus
= bus
;
3386 vtd_dev_as
->devfn
= (uint8_t)devfn
;
3387 vtd_dev_as
->iommu_state
= s
;
3388 vtd_dev_as
->context_cache_entry
.context_cache_gen
= 0;
3389 vtd_dev_as
->iova_tree
= iova_tree_new();
3391 memory_region_init(&vtd_dev_as
->root
, OBJECT(s
), name
, UINT64_MAX
);
3392 address_space_init(&vtd_dev_as
->as
, &vtd_dev_as
->root
, "vtd-root");
3395 * Build the DMAR-disabled container with aliases to the
3396 * shared MRs. Note that aliasing to a shared memory region
3397 * could help the memory API to detect same FlatViews so we
3398 * can have devices to share the same FlatView when DMAR is
3399 * disabled (either by not providing "intel_iommu=on" or with
3400 * "iommu=pt"). It will greatly reduce the total number of
3401 * FlatViews of the system hence VM runs faster.
3403 memory_region_init_alias(&vtd_dev_as
->nodmar
, OBJECT(s
),
3404 "vtd-nodmar", &s
->mr_nodmar
, 0,
3405 memory_region_size(&s
->mr_nodmar
));
3408 * Build the per-device DMAR-enabled container.
3410 * TODO: currently we have per-device IOMMU memory region only
3411 * because we have per-device IOMMU notifiers for devices. If
3412 * one day we can abstract the IOMMU notifiers out of the
3413 * memory regions then we can also share the same memory
3414 * region here just like what we've done above with the nodmar
3417 strcat(name
, "-dmar");
3418 memory_region_init_iommu(&vtd_dev_as
->iommu
, sizeof(vtd_dev_as
->iommu
),
3419 TYPE_INTEL_IOMMU_MEMORY_REGION
, OBJECT(s
),
3421 memory_region_init_alias(&vtd_dev_as
->iommu_ir
, OBJECT(s
), "vtd-ir",
3422 &s
->mr_ir
, 0, memory_region_size(&s
->mr_ir
));
3423 memory_region_add_subregion_overlap(MEMORY_REGION(&vtd_dev_as
->iommu
),
3424 VTD_INTERRUPT_ADDR_FIRST
,
3425 &vtd_dev_as
->iommu_ir
, 1);
3428 * Hook both the containers under the root container, we
3429 * switch between DMAR & noDMAR by enable/disable
3430 * corresponding sub-containers
3432 memory_region_add_subregion_overlap(&vtd_dev_as
->root
, 0,
3433 MEMORY_REGION(&vtd_dev_as
->iommu
),
3435 memory_region_add_subregion_overlap(&vtd_dev_as
->root
, 0,
3436 &vtd_dev_as
->nodmar
, 0);
3438 vtd_switch_address_space(vtd_dev_as
);
3443 static uint64_t get_naturally_aligned_size(uint64_t start
,
3444 uint64_t size
, int gaw
)
3446 uint64_t max_mask
= 1ULL << gaw
;
3447 uint64_t alignment
= start
? start
& -start
: max_mask
;
3449 alignment
= MIN(alignment
, max_mask
);
3450 size
= MIN(size
, max_mask
);
3452 if (alignment
<= size
) {
3453 /* Increase the alignment of start */
3456 /* Find the largest page mask from size */
3457 return 1ULL << (63 - clz64(size
));
3461 /* Unmap the whole range in the notifier's scope. */
3462 static void vtd_address_space_unmap(VTDAddressSpace
*as
, IOMMUNotifier
*n
)
3464 hwaddr size
, remain
;
3465 hwaddr start
= n
->start
;
3466 hwaddr end
= n
->end
;
3467 IntelIOMMUState
*s
= as
->iommu_state
;
3471 * Note: all the codes in this function has a assumption that IOVA
3472 * bits are no more than VTD_MGAW bits (which is restricted by
3473 * VT-d spec), otherwise we need to consider overflow of 64 bits.
3476 if (end
> VTD_ADDRESS_SIZE(s
->aw_bits
) - 1) {
3478 * Don't need to unmap regions that is bigger than the whole
3479 * VT-d supported address space size
3481 end
= VTD_ADDRESS_SIZE(s
->aw_bits
) - 1;
3484 assert(start
<= end
);
3485 size
= remain
= end
- start
+ 1;
3487 while (remain
>= VTD_PAGE_SIZE
) {
3488 IOMMUTLBEntry entry
;
3489 uint64_t mask
= get_naturally_aligned_size(start
, remain
, s
->aw_bits
);
3494 entry
.addr_mask
= mask
- 1;
3495 entry
.target_as
= &address_space_memory
;
3496 entry
.perm
= IOMMU_NONE
;
3497 /* This field is meaningless for unmap */
3498 entry
.translated_addr
= 0;
3500 memory_region_notify_one(n
, &entry
);
3508 trace_vtd_as_unmap_whole(pci_bus_num(as
->bus
),
3509 VTD_PCI_SLOT(as
->devfn
),
3510 VTD_PCI_FUNC(as
->devfn
),
3513 map
.iova
= n
->start
;
3515 iova_tree_remove(as
->iova_tree
, &map
);
3518 static void vtd_address_space_unmap_all(IntelIOMMUState
*s
)
3520 VTDAddressSpace
*vtd_as
;
3523 QLIST_FOREACH(vtd_as
, &s
->vtd_as_with_notifiers
, next
) {
3524 IOMMU_NOTIFIER_FOREACH(n
, &vtd_as
->iommu
) {
3525 vtd_address_space_unmap(vtd_as
, n
);
3530 static void vtd_address_space_refresh_all(IntelIOMMUState
*s
)
3532 vtd_address_space_unmap_all(s
);
3533 vtd_switch_address_space_all(s
);
3536 static int vtd_replay_hook(IOMMUTLBEntry
*entry
, void *private)
3538 memory_region_notify_one((IOMMUNotifier
*)private, entry
);
3542 static void vtd_iommu_replay(IOMMUMemoryRegion
*iommu_mr
, IOMMUNotifier
*n
)
3544 VTDAddressSpace
*vtd_as
= container_of(iommu_mr
, VTDAddressSpace
, iommu
);
3545 IntelIOMMUState
*s
= vtd_as
->iommu_state
;
3546 uint8_t bus_n
= pci_bus_num(vtd_as
->bus
);
3550 * The replay can be triggered by either a invalidation or a newly
3551 * created entry. No matter what, we release existing mappings
3552 * (it means flushing caches for UNMAP-only registers).
3554 vtd_address_space_unmap(vtd_as
, n
);
3556 if (vtd_dev_to_context_entry(s
, bus_n
, vtd_as
->devfn
, &ce
) == 0) {
3557 trace_vtd_replay_ce_valid(s
->root_scalable
? "scalable mode" :
3559 bus_n
, PCI_SLOT(vtd_as
->devfn
),
3560 PCI_FUNC(vtd_as
->devfn
),
3561 vtd_get_domain_id(s
, &ce
),
3563 if (vtd_as_has_map_notifier(vtd_as
)) {
3564 /* This is required only for MAP typed notifiers */
3565 vtd_page_walk_info info
= {
3566 .hook_fn
= vtd_replay_hook
,
3567 .private = (void *)n
,
3568 .notify_unmap
= false,
3571 .domain_id
= vtd_get_domain_id(s
, &ce
),
3574 vtd_page_walk(s
, &ce
, 0, ~0ULL, &info
);
3577 trace_vtd_replay_ce_invalid(bus_n
, PCI_SLOT(vtd_as
->devfn
),
3578 PCI_FUNC(vtd_as
->devfn
));
3584 /* Do the initialization. It will also be called when reset, so pay
3585 * attention when adding new initialization stuff.
3587 static void vtd_init(IntelIOMMUState
*s
)
3589 X86IOMMUState
*x86_iommu
= X86_IOMMU_DEVICE(s
);
3591 memset(s
->csr
, 0, DMAR_REG_SIZE
);
3592 memset(s
->wmask
, 0, DMAR_REG_SIZE
);
3593 memset(s
->w1cmask
, 0, DMAR_REG_SIZE
);
3594 memset(s
->womask
, 0, DMAR_REG_SIZE
);
3597 s
->root_scalable
= false;
3598 s
->dmar_enabled
= false;
3599 s
->intr_enabled
= false;
3604 s
->qi_enabled
= false;
3605 s
->iq_last_desc_type
= VTD_INV_DESC_NONE
;
3607 s
->next_frcd_reg
= 0;
3608 s
->cap
= VTD_CAP_FRO
| VTD_CAP_NFR
| VTD_CAP_ND
|
3609 VTD_CAP_MAMV
| VTD_CAP_PSI
| VTD_CAP_SLLPS
|
3610 VTD_CAP_SAGAW_39bit
| VTD_CAP_MGAW(s
->aw_bits
);
3612 s
->cap
|= VTD_CAP_DRAIN
;
3614 if (s
->aw_bits
== VTD_HOST_AW_48BIT
) {
3615 s
->cap
|= VTD_CAP_SAGAW_48bit
;
3617 s
->ecap
= VTD_ECAP_QI
| VTD_ECAP_IRO
;
3620 * Rsvd field masks for spte
3622 vtd_spte_rsvd
[0] = ~0ULL;
3623 vtd_spte_rsvd
[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s
->aw_bits
,
3624 x86_iommu
->dt_supported
);
3625 vtd_spte_rsvd
[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s
->aw_bits
);
3626 vtd_spte_rsvd
[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s
->aw_bits
);
3627 vtd_spte_rsvd
[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s
->aw_bits
);
3629 vtd_spte_rsvd_large
[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s
->aw_bits
,
3630 x86_iommu
->dt_supported
);
3631 vtd_spte_rsvd_large
[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s
->aw_bits
,
3632 x86_iommu
->dt_supported
);
3634 if (x86_iommu_ir_supported(x86_iommu
)) {
3635 s
->ecap
|= VTD_ECAP_IR
| VTD_ECAP_MHMV
;
3636 if (s
->intr_eim
== ON_OFF_AUTO_ON
) {
3637 s
->ecap
|= VTD_ECAP_EIM
;
3639 assert(s
->intr_eim
!= ON_OFF_AUTO_AUTO
);
3642 if (x86_iommu
->dt_supported
) {
3643 s
->ecap
|= VTD_ECAP_DT
;
3646 if (x86_iommu
->pt_supported
) {
3647 s
->ecap
|= VTD_ECAP_PT
;
3650 if (s
->caching_mode
) {
3651 s
->cap
|= VTD_CAP_CM
;
3654 /* TODO: read cap/ecap from host to decide which cap to be exposed. */
3655 if (s
->scalable_mode
) {
3656 s
->ecap
|= VTD_ECAP_SMTS
| VTD_ECAP_SRS
| VTD_ECAP_SLTS
;
3659 vtd_reset_caches(s
);
3661 /* Define registers with default values and bit semantics */
3662 vtd_define_long(s
, DMAR_VER_REG
, 0x10UL
, 0, 0);
3663 vtd_define_quad(s
, DMAR_CAP_REG
, s
->cap
, 0, 0);
3664 vtd_define_quad(s
, DMAR_ECAP_REG
, s
->ecap
, 0, 0);
3665 vtd_define_long(s
, DMAR_GCMD_REG
, 0, 0xff800000UL
, 0);
3666 vtd_define_long_wo(s
, DMAR_GCMD_REG
, 0xff800000UL
);
3667 vtd_define_long(s
, DMAR_GSTS_REG
, 0, 0, 0);
3668 vtd_define_quad(s
, DMAR_RTADDR_REG
, 0, 0xfffffffffffffc00ULL
, 0);
3669 vtd_define_quad(s
, DMAR_CCMD_REG
, 0, 0xe0000003ffffffffULL
, 0);
3670 vtd_define_quad_wo(s
, DMAR_CCMD_REG
, 0x3ffff0000ULL
);
3672 /* Advanced Fault Logging not supported */
3673 vtd_define_long(s
, DMAR_FSTS_REG
, 0, 0, 0x11UL
);
3674 vtd_define_long(s
, DMAR_FECTL_REG
, 0x80000000UL
, 0x80000000UL
, 0);
3675 vtd_define_long(s
, DMAR_FEDATA_REG
, 0, 0x0000ffffUL
, 0);
3676 vtd_define_long(s
, DMAR_FEADDR_REG
, 0, 0xfffffffcUL
, 0);
3678 /* Treated as RsvdZ when EIM in ECAP_REG is not supported
3679 * vtd_define_long(s, DMAR_FEUADDR_REG, 0, 0xffffffffUL, 0);
3681 vtd_define_long(s
, DMAR_FEUADDR_REG
, 0, 0, 0);
3683 /* Treated as RO for implementations that PLMR and PHMR fields reported
3684 * as Clear in the CAP_REG.
3685 * vtd_define_long(s, DMAR_PMEN_REG, 0, 0x80000000UL, 0);
3687 vtd_define_long(s
, DMAR_PMEN_REG
, 0, 0, 0);
3689 vtd_define_quad(s
, DMAR_IQH_REG
, 0, 0, 0);
3690 vtd_define_quad(s
, DMAR_IQT_REG
, 0, 0x7fff0ULL
, 0);
3691 vtd_define_quad(s
, DMAR_IQA_REG
, 0, 0xfffffffffffff807ULL
, 0);
3692 vtd_define_long(s
, DMAR_ICS_REG
, 0, 0, 0x1UL
);
3693 vtd_define_long(s
, DMAR_IECTL_REG
, 0x80000000UL
, 0x80000000UL
, 0);
3694 vtd_define_long(s
, DMAR_IEDATA_REG
, 0, 0xffffffffUL
, 0);
3695 vtd_define_long(s
, DMAR_IEADDR_REG
, 0, 0xfffffffcUL
, 0);
3696 /* Treadted as RsvdZ when EIM in ECAP_REG is not supported */
3697 vtd_define_long(s
, DMAR_IEUADDR_REG
, 0, 0, 0);
3699 /* IOTLB registers */
3700 vtd_define_quad(s
, DMAR_IOTLB_REG
, 0, 0Xb003ffff00000000ULL
, 0);
3701 vtd_define_quad(s
, DMAR_IVA_REG
, 0, 0xfffffffffffff07fULL
, 0);
3702 vtd_define_quad_wo(s
, DMAR_IVA_REG
, 0xfffffffffffff07fULL
);
3704 /* Fault Recording Registers, 128-bit */
3705 vtd_define_quad(s
, DMAR_FRCD_REG_0_0
, 0, 0, 0);
3706 vtd_define_quad(s
, DMAR_FRCD_REG_0_2
, 0, 0, 0x8000000000000000ULL
);
3709 * Interrupt remapping registers.
3711 vtd_define_quad(s
, DMAR_IRTA_REG
, 0, 0xfffffffffffff80fULL
, 0);
3714 /* Should not reset address_spaces when reset because devices will still use
3715 * the address space they got at first (won't ask the bus again).
3717 static void vtd_reset(DeviceState
*dev
)
3719 IntelIOMMUState
*s
= INTEL_IOMMU_DEVICE(dev
);
3722 vtd_address_space_refresh_all(s
);
3725 static AddressSpace
*vtd_host_dma_iommu(PCIBus
*bus
, void *opaque
, int devfn
)
3727 IntelIOMMUState
*s
= opaque
;
3728 VTDAddressSpace
*vtd_as
;
3730 assert(0 <= devfn
&& devfn
< PCI_DEVFN_MAX
);
3732 vtd_as
= vtd_find_add_as(s
, bus
, devfn
);
3736 static bool vtd_decide_config(IntelIOMMUState
*s
, Error
**errp
)
3738 X86IOMMUState
*x86_iommu
= X86_IOMMU_DEVICE(s
);
3740 if (s
->intr_eim
== ON_OFF_AUTO_ON
&& !x86_iommu_ir_supported(x86_iommu
)) {
3741 error_setg(errp
, "eim=on cannot be selected without intremap=on");
3745 if (s
->intr_eim
== ON_OFF_AUTO_AUTO
) {
3746 s
->intr_eim
= (kvm_irqchip_in_kernel() || s
->buggy_eim
)
3747 && x86_iommu_ir_supported(x86_iommu
) ?
3748 ON_OFF_AUTO_ON
: ON_OFF_AUTO_OFF
;
3750 if (s
->intr_eim
== ON_OFF_AUTO_ON
&& !s
->buggy_eim
) {
3751 if (!kvm_irqchip_in_kernel()) {
3752 error_setg(errp
, "eim=on requires accel=kvm,kernel-irqchip=split");
3755 if (!kvm_enable_x2apic()) {
3756 error_setg(errp
, "eim=on requires support on the KVM side"
3757 "(X2APIC_API, first shipped in v4.7)");
3762 /* Currently only address widths supported are 39 and 48 bits */
3763 if ((s
->aw_bits
!= VTD_HOST_AW_39BIT
) &&
3764 (s
->aw_bits
!= VTD_HOST_AW_48BIT
)) {
3765 error_setg(errp
, "Supported values for aw-bits are: %d, %d",
3766 VTD_HOST_AW_39BIT
, VTD_HOST_AW_48BIT
);
3770 if (s
->scalable_mode
&& !s
->dma_drain
) {
3771 error_setg(errp
, "Need to set dma_drain for scalable mode");
3778 static int vtd_machine_done_notify_one(Object
*child
, void *unused
)
3780 IntelIOMMUState
*iommu
= INTEL_IOMMU_DEVICE(x86_iommu_get_default());
3783 * We hard-coded here because vfio-pci is the only special case
3784 * here. Let's be more elegant in the future when we can, but so
3785 * far there seems to be no better way.
3787 if (object_dynamic_cast(child
, "vfio-pci") && !iommu
->caching_mode
) {
3788 vtd_panic_require_caching_mode();
3794 static void vtd_machine_done_hook(Notifier
*notifier
, void *unused
)
3796 object_child_foreach_recursive(object_get_root(),
3797 vtd_machine_done_notify_one
, NULL
);
3800 static Notifier vtd_machine_done_notify
= {
3801 .notify
= vtd_machine_done_hook
,
3804 static void vtd_realize(DeviceState
*dev
, Error
**errp
)
3806 MachineState
*ms
= MACHINE(qdev_get_machine());
3807 PCMachineState
*pcms
= PC_MACHINE(ms
);
3808 X86MachineState
*x86ms
= X86_MACHINE(ms
);
3809 PCIBus
*bus
= pcms
->bus
;
3810 IntelIOMMUState
*s
= INTEL_IOMMU_DEVICE(dev
);
3811 X86IOMMUState
*x86_iommu
= X86_IOMMU_DEVICE(dev
);
3813 x86_iommu
->type
= TYPE_INTEL
;
3815 if (!vtd_decide_config(s
, errp
)) {
3819 QLIST_INIT(&s
->vtd_as_with_notifiers
);
3820 qemu_mutex_init(&s
->iommu_lock
);
3821 memset(s
->vtd_as_by_bus_num
, 0, sizeof(s
->vtd_as_by_bus_num
));
3822 memory_region_init_io(&s
->csrmem
, OBJECT(s
), &vtd_mem_ops
, s
,
3823 "intel_iommu", DMAR_REG_SIZE
);
3825 /* Create the shared memory regions by all devices */
3826 memory_region_init(&s
->mr_nodmar
, OBJECT(s
), "vtd-nodmar",
3828 memory_region_init_io(&s
->mr_ir
, OBJECT(s
), &vtd_mem_ir_ops
,
3829 s
, "vtd-ir", VTD_INTERRUPT_ADDR_SIZE
);
3830 memory_region_init_alias(&s
->mr_sys_alias
, OBJECT(s
),
3831 "vtd-sys-alias", get_system_memory(), 0,
3832 memory_region_size(get_system_memory()));
3833 memory_region_add_subregion_overlap(&s
->mr_nodmar
, 0,
3834 &s
->mr_sys_alias
, 0);
3835 memory_region_add_subregion_overlap(&s
->mr_nodmar
,
3836 VTD_INTERRUPT_ADDR_FIRST
,
3839 sysbus_init_mmio(SYS_BUS_DEVICE(s
), &s
->csrmem
);
3840 /* No corresponding destroy */
3841 s
->iotlb
= g_hash_table_new_full(vtd_uint64_hash
, vtd_uint64_equal
,
3843 s
->vtd_as_by_busptr
= g_hash_table_new_full(vtd_uint64_hash
, vtd_uint64_equal
,
3846 sysbus_mmio_map(SYS_BUS_DEVICE(s
), 0, Q35_HOST_BRIDGE_IOMMU_ADDR
);
3847 pci_setup_iommu(bus
, vtd_host_dma_iommu
, dev
);
3848 /* Pseudo address space under root PCI bus. */
3849 x86ms
->ioapic_as
= vtd_host_dma_iommu(bus
, s
, Q35_PSEUDO_DEVFN_IOAPIC
);
3850 qemu_add_machine_init_done_notifier(&vtd_machine_done_notify
);
3853 static void vtd_class_init(ObjectClass
*klass
, void *data
)
3855 DeviceClass
*dc
= DEVICE_CLASS(klass
);
3856 X86IOMMUClass
*x86_class
= X86_IOMMU_DEVICE_CLASS(klass
);
3858 dc
->reset
= vtd_reset
;
3859 dc
->vmsd
= &vtd_vmstate
;
3860 device_class_set_props(dc
, vtd_properties
);
3861 dc
->hotpluggable
= false;
3862 x86_class
->realize
= vtd_realize
;
3863 x86_class
->int_remap
= vtd_int_remap
;
3864 /* Supported by the pc-q35-* machine types */
3865 dc
->user_creatable
= true;
3866 set_bit(DEVICE_CATEGORY_MISC
, dc
->categories
);
3867 dc
->desc
= "Intel IOMMU (VT-d) DMA Remapping device";
3870 static const TypeInfo vtd_info
= {
3871 .name
= TYPE_INTEL_IOMMU_DEVICE
,
3872 .parent
= TYPE_X86_IOMMU_DEVICE
,
3873 .instance_size
= sizeof(IntelIOMMUState
),
3874 .class_init
= vtd_class_init
,
3877 static void vtd_iommu_memory_region_class_init(ObjectClass
*klass
,
3880 IOMMUMemoryRegionClass
*imrc
= IOMMU_MEMORY_REGION_CLASS(klass
);
3882 imrc
->translate
= vtd_iommu_translate
;
3883 imrc
->notify_flag_changed
= vtd_iommu_notify_flag_changed
;
3884 imrc
->replay
= vtd_iommu_replay
;
3887 static const TypeInfo vtd_iommu_memory_region_info
= {
3888 .parent
= TYPE_IOMMU_MEMORY_REGION
,
3889 .name
= TYPE_INTEL_IOMMU_MEMORY_REGION
,
3890 .class_init
= vtd_iommu_memory_region_class_init
,
3893 static void vtd_register_types(void)
3895 type_register_static(&vtd_info
);
3896 type_register_static(&vtd_iommu_memory_region_info
);
3899 type_init(vtd_register_types
)