hw/net/dp8393x.c

   1 /*
   2  * QEMU NS SONIC DP8393x netcard
   3  *
   4  * Copyright (c) 2008-2009 Herve Poussineau
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along
  17  * with this program; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "hw/irq.h"
  22 #include "hw/qdev-properties.h"
  23 #include "hw/sysbus.h"
  24 #include "migration/vmstate.h"
  25 #include "net/net.h"
  26 #include "qapi/error.h"
  27 #include "qemu/module.h"
  28 #include "qemu/timer.h"
  29 #include <zlib.h>
  30
  31 //#define DEBUG_SONIC
  32
  33 #define SONIC_PROM_SIZE 0x1000
  34
  35 #ifdef DEBUG_SONIC
  36 #define DPRINTF(fmt, ...) \
  37 do { printf("sonic: " fmt , ##  __VA_ARGS__); } while (0)
  38 static const char* reg_names[] = {
  39     "CR", "DCR", "RCR", "TCR", "IMR", "ISR", "UTDA", "CTDA",
  40     "TPS", "TFC", "TSA0", "TSA1", "TFS", "URDA", "CRDA", "CRBA0",
  41     "CRBA1", "RBWC0", "RBWC1", "EOBC", "URRA", "RSA", "REA", "RRP",
  42     "RWP", "TRBA0", "TRBA1", "0x1b", "0x1c", "0x1d", "0x1e", "LLFA",
  43     "TTDA", "CEP", "CAP2", "CAP1", "CAP0", "CE", "CDP", "CDC",
  44     "SR", "WT0", "WT1", "RSC", "CRCT", "FAET", "MPT", "MDT",
  45     "0x30", "0x31", "0x32", "0x33", "0x34", "0x35", "0x36", "0x37",
  46     "0x38", "0x39", "0x3a", "0x3b", "0x3c", "0x3d", "0x3e", "DCR2" };
  47 #else
  48 #define DPRINTF(fmt, ...) do {} while (0)
  49 #endif
  50
  51 #define SONIC_ERROR(fmt, ...) \
  52 do { printf("sonic ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
  53
  54 #define SONIC_CR     0x00
  55 #define SONIC_DCR    0x01
  56 #define SONIC_RCR    0x02
  57 #define SONIC_TCR    0x03
  58 #define SONIC_IMR    0x04
  59 #define SONIC_ISR    0x05
  60 #define SONIC_UTDA   0x06
  61 #define SONIC_CTDA   0x07
  62 #define SONIC_TPS    0x08
  63 #define SONIC_TFC    0x09
  64 #define SONIC_TSA0   0x0a
  65 #define SONIC_TSA1   0x0b
  66 #define SONIC_TFS    0x0c
  67 #define SONIC_URDA   0x0d
  68 #define SONIC_CRDA   0x0e
  69 #define SONIC_CRBA0  0x0f
  70 #define SONIC_CRBA1  0x10
  71 #define SONIC_RBWC0  0x11
  72 #define SONIC_RBWC1  0x12
  73 #define SONIC_EOBC   0x13
  74 #define SONIC_URRA   0x14
  75 #define SONIC_RSA    0x15
  76 #define SONIC_REA    0x16
  77 #define SONIC_RRP    0x17
  78 #define SONIC_RWP    0x18
  79 #define SONIC_TRBA0  0x19
  80 #define SONIC_TRBA1  0x1a
  81 #define SONIC_LLFA   0x1f
  82 #define SONIC_TTDA   0x20
  83 #define SONIC_CEP    0x21
  84 #define SONIC_CAP2   0x22
  85 #define SONIC_CAP1   0x23
  86 #define SONIC_CAP0   0x24
  87 #define SONIC_CE     0x25
  88 #define SONIC_CDP    0x26
  89 #define SONIC_CDC    0x27
  90 #define SONIC_SR     0x28
  91 #define SONIC_WT0    0x29
  92 #define SONIC_WT1    0x2a
  93 #define SONIC_RSC    0x2b
  94 #define SONIC_CRCT   0x2c
  95 #define SONIC_FAET   0x2d
  96 #define SONIC_MPT    0x2e
  97 #define SONIC_MDT    0x2f
  98 #define SONIC_DCR2   0x3f
  99
 100 #define SONIC_CR_HTX     0x0001
 101 #define SONIC_CR_TXP     0x0002
 102 #define SONIC_CR_RXDIS   0x0004
 103 #define SONIC_CR_RXEN    0x0008
 104 #define SONIC_CR_STP     0x0010
 105 #define SONIC_CR_ST      0x0020
 106 #define SONIC_CR_RST     0x0080
 107 #define SONIC_CR_RRRA    0x0100
 108 #define SONIC_CR_LCAM    0x0200
 109 #define SONIC_CR_MASK    0x03bf
 110
 111 #define SONIC_DCR_DW     0x0020
 112 #define SONIC_DCR_LBR    0x2000
 113 #define SONIC_DCR_EXBUS  0x8000
 114
 115 #define SONIC_RCR_PRX    0x0001
 116 #define SONIC_RCR_LBK    0x0002
 117 #define SONIC_RCR_FAER   0x0004
 118 #define SONIC_RCR_CRCR   0x0008
 119 #define SONIC_RCR_CRS    0x0020
 120 #define SONIC_RCR_LPKT   0x0040
 121 #define SONIC_RCR_BC     0x0080
 122 #define SONIC_RCR_MC     0x0100
 123 #define SONIC_RCR_LB0    0x0200
 124 #define SONIC_RCR_LB1    0x0400
 125 #define SONIC_RCR_AMC    0x0800
 126 #define SONIC_RCR_PRO    0x1000
 127 #define SONIC_RCR_BRD    0x2000
 128 #define SONIC_RCR_RNT    0x4000
 129
 130 #define SONIC_TCR_PTX    0x0001
 131 #define SONIC_TCR_BCM    0x0002
 132 #define SONIC_TCR_FU     0x0004
 133 #define SONIC_TCR_EXC    0x0040
 134 #define SONIC_TCR_CRSL   0x0080
 135 #define SONIC_TCR_NCRS   0x0100
 136 #define SONIC_TCR_EXD    0x0400
 137 #define SONIC_TCR_CRCI   0x2000
 138 #define SONIC_TCR_PINT   0x8000
 139
 140 #define SONIC_ISR_RBE    0x0020
 141 #define SONIC_ISR_RDE    0x0040
 142 #define SONIC_ISR_TC     0x0080
 143 #define SONIC_ISR_TXDN   0x0200
 144 #define SONIC_ISR_PKTRX  0x0400
 145 #define SONIC_ISR_PINT   0x0800
 146 #define SONIC_ISR_LCD    0x1000
 147
 148 #define TYPE_DP8393X "dp8393x"
 149 #define DP8393X(obj) OBJECT_CHECK(dp8393xState, (obj), TYPE_DP8393X)
 150
 151 typedef struct dp8393xState {
 152     SysBusDevice parent_obj;
 153
 154     /* Hardware */
 155     uint8_t it_shift;
 156     bool big_endian;
 157     qemu_irq irq;
 158 #ifdef DEBUG_SONIC
 159     int irq_level;
 160 #endif
 161     QEMUTimer *watchdog;
 162     int64_t wt_last_update;
 163     NICConf conf;
 164     NICState *nic;
 165     MemoryRegion mmio;
 166     MemoryRegion prom;
 167
 168     /* Registers */
 169     uint8_t cam[16][6];
 170     uint16_t regs[0x40];
 171
 172     /* Temporaries */
 173     uint8_t tx_buffer[0x10000];
 174     int loopback_packet;
 175
 176     /* Memory access */
 177     void *dma_mr;
 178     AddressSpace as;
 179 } dp8393xState;
 180
 181 /* Accessor functions for values which are formed by
 182  * concatenating two 16 bit device registers. By putting these
 183  * in their own functions with a uint32_t return type we avoid the
 184  * pitfall of implicit sign extension where ((x << 16) | y) is a
 185  * signed 32 bit integer that might get sign-extended to a 64 bit integer.
 186  */
 187 static uint32_t dp8393x_cdp(dp8393xState *s)
 188 {
 189     return (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_CDP];
 190 }
 191
 192 static uint32_t dp8393x_crba(dp8393xState *s)
 193 {
 194     return (s->regs[SONIC_CRBA1] << 16) | s->regs[SONIC_CRBA0];
 195 }
 196
 197 static uint32_t dp8393x_crda(dp8393xState *s)
 198 {
 199     return (s->regs[SONIC_URDA] << 16) | s->regs[SONIC_CRDA];
 200 }
 201
 202 static uint32_t dp8393x_rbwc(dp8393xState *s)
 203 {
 204     return (s->regs[SONIC_RBWC1] << 16) | s->regs[SONIC_RBWC0];
 205 }
 206
 207 static uint32_t dp8393x_rrp(dp8393xState *s)
 208 {
 209     return (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_RRP];
 210 }
 211
 212 static uint32_t dp8393x_tsa(dp8393xState *s)
 213 {
 214     return (s->regs[SONIC_TSA1] << 16) | s->regs[SONIC_TSA0];
 215 }
 216
 217 static uint32_t dp8393x_ttda(dp8393xState *s)
 218 {
 219     return (s->regs[SONIC_UTDA] << 16) | s->regs[SONIC_TTDA];
 220 }
 221
 222 static uint32_t dp8393x_wt(dp8393xState *s)
 223 {
 224     return s->regs[SONIC_WT1] << 16 | s->regs[SONIC_WT0];
 225 }
 226
 227 static uint16_t dp8393x_get(dp8393xState *s, int width, uint16_t *base,
 228                             int offset)
 229 {
 230     uint16_t val;
 231
 232     if (s->big_endian) {
 233         val = be16_to_cpu(base[offset * width + width - 1]);
 234     } else {
 235         val = le16_to_cpu(base[offset * width]);
 236     }
 237     return val;
 238 }
 239
 240 static void dp8393x_put(dp8393xState *s, int width, uint16_t *base, int offset,
 241                         uint16_t val)
 242 {
 243     if (s->big_endian) {
 244         base[offset * width + width - 1] = cpu_to_be16(val);
 245     } else {
 246         base[offset * width] = cpu_to_le16(val);
 247     }
 248 }
 249
 250 static void dp8393x_update_irq(dp8393xState *s)
 251 {
 252     int level = (s->regs[SONIC_IMR] & s->regs[SONIC_ISR]) ? 1 : 0;
 253
 254 #ifdef DEBUG_SONIC
 255     if (level != s->irq_level) {
 256         s->irq_level = level;
 257         if (level) {
 258             DPRINTF("raise irq, isr is 0x%04x\n", s->regs[SONIC_ISR]);
 259         } else {
 260             DPRINTF("lower irq\n");
 261         }
 262     }
 263 #endif
 264
 265     qemu_set_irq(s->irq, level);
 266 }
 267
 268 static void dp8393x_do_load_cam(dp8393xState *s)
 269 {
 270     uint16_t data[8];
 271     int width, size;
 272     uint16_t index = 0;
 273
 274     width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
 275     size = sizeof(uint16_t) * 4 * width;
 276
 277     while (s->regs[SONIC_CDC] & 0x1f) {
 278         /* Fill current entry */
 279         address_space_rw(&s->as, dp8393x_cdp(s),
 280             MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
 281         s->cam[index][0] = dp8393x_get(s, width, data, 1) & 0xff;
 282         s->cam[index][1] = dp8393x_get(s, width, data, 1) >> 8;
 283         s->cam[index][2] = dp8393x_get(s, width, data, 2) & 0xff;
 284         s->cam[index][3] = dp8393x_get(s, width, data, 2) >> 8;
 285         s->cam[index][4] = dp8393x_get(s, width, data, 3) & 0xff;
 286         s->cam[index][5] = dp8393x_get(s, width, data, 3) >> 8;
 287         DPRINTF("load cam[%d] with %02x%02x%02x%02x%02x%02x\n", index,
 288             s->cam[index][0], s->cam[index][1], s->cam[index][2],
 289             s->cam[index][3], s->cam[index][4], s->cam[index][5]);
 290         /* Move to next entry */
 291         s->regs[SONIC_CDC]--;
 292         s->regs[SONIC_CDP] += size;
 293         index++;
 294     }
 295
 296     /* Read CAM enable */
 297     address_space_rw(&s->as, dp8393x_cdp(s),
 298         MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
 299     s->regs[SONIC_CE] = dp8393x_get(s, width, data, 0);
 300     DPRINTF("load cam done. cam enable mask 0x%04x\n", s->regs[SONIC_CE]);
 301
 302     /* Done */
 303     s->regs[SONIC_CR] &= ~SONIC_CR_LCAM;
 304     s->regs[SONIC_ISR] |= SONIC_ISR_LCD;
 305     dp8393x_update_irq(s);
 306 }
 307
 308 static void dp8393x_do_read_rra(dp8393xState *s)
 309 {
 310     uint16_t data[8];
 311     int width, size;
 312
 313     /* Read memory */
 314     width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
 315     size = sizeof(uint16_t) * 4 * width;
 316     address_space_rw(&s->as, dp8393x_rrp(s),
 317         MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
 318
 319     /* Update SONIC registers */
 320     s->regs[SONIC_CRBA0] = dp8393x_get(s, width, data, 0);
 321     s->regs[SONIC_CRBA1] = dp8393x_get(s, width, data, 1);
 322     s->regs[SONIC_RBWC0] = dp8393x_get(s, width, data, 2);
 323     s->regs[SONIC_RBWC1] = dp8393x_get(s, width, data, 3);
 324     DPRINTF("CRBA0/1: 0x%04x/0x%04x, RBWC0/1: 0x%04x/0x%04x\n",
 325         s->regs[SONIC_CRBA0], s->regs[SONIC_CRBA1],
 326         s->regs[SONIC_RBWC0], s->regs[SONIC_RBWC1]);
 327
 328     /* Go to next entry */
 329     s->regs[SONIC_RRP] += size;
 330
 331     /* Handle wrap */
 332     if (s->regs[SONIC_RRP] == s->regs[SONIC_REA]) {
 333         s->regs[SONIC_RRP] = s->regs[SONIC_RSA];
 334     }
 335
 336     /* Check resource exhaustion */
 337     if (s->regs[SONIC_RRP] == s->regs[SONIC_RWP])
 338     {
 339         s->regs[SONIC_ISR] |= SONIC_ISR_RBE;
 340         dp8393x_update_irq(s);
 341     }
 342
 343     /* Done */
 344     s->regs[SONIC_CR] &= ~SONIC_CR_RRRA;
 345 }
 346
 347 static void dp8393x_do_software_reset(dp8393xState *s)
 348 {
 349     timer_del(s->watchdog);
 350
 351     s->regs[SONIC_CR] &= ~(SONIC_CR_LCAM | SONIC_CR_RRRA | SONIC_CR_TXP | SONIC_CR_HTX);
 352     s->regs[SONIC_CR] |= SONIC_CR_RST | SONIC_CR_RXDIS;
 353 }
 354
 355 static void dp8393x_set_next_tick(dp8393xState *s)
 356 {
 357     uint32_t ticks;
 358     int64_t delay;
 359
 360     if (s->regs[SONIC_CR] & SONIC_CR_STP) {
 361         timer_del(s->watchdog);
 362         return;
 363     }
 364
 365     ticks = dp8393x_wt(s);
 366     s->wt_last_update = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 367     delay = NANOSECONDS_PER_SECOND * ticks / 5000000;
 368     timer_mod(s->watchdog, s->wt_last_update + delay);
 369 }
 370
 371 static void dp8393x_update_wt_regs(dp8393xState *s)
 372 {
 373     int64_t elapsed;
 374     uint32_t val;
 375
 376     if (s->regs[SONIC_CR] & SONIC_CR_STP) {
 377         timer_del(s->watchdog);
 378         return;
 379     }
 380
 381     elapsed = s->wt_last_update - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 382     val = dp8393x_wt(s);
 383     val -= elapsed / 5000000;
 384     s->regs[SONIC_WT1] = (val >> 16) & 0xffff;
 385     s->regs[SONIC_WT0] = (val >> 0)  & 0xffff;
 386     dp8393x_set_next_tick(s);
 387
 388 }
 389
 390 static void dp8393x_do_start_timer(dp8393xState *s)
 391 {
 392     s->regs[SONIC_CR] &= ~SONIC_CR_STP;
 393     dp8393x_set_next_tick(s);
 394 }
 395
 396 static void dp8393x_do_stop_timer(dp8393xState *s)
 397 {
 398     s->regs[SONIC_CR] &= ~SONIC_CR_ST;
 399     dp8393x_update_wt_regs(s);
 400 }
 401
 402 static int dp8393x_can_receive(NetClientState *nc);
 403
 404 static void dp8393x_do_receiver_enable(dp8393xState *s)
 405 {
 406     s->regs[SONIC_CR] &= ~SONIC_CR_RXDIS;
 407     if (dp8393x_can_receive(s->nic->ncs)) {
 408         qemu_flush_queued_packets(qemu_get_queue(s->nic));
 409     }
 410 }
 411
 412 static void dp8393x_do_receiver_disable(dp8393xState *s)
 413 {
 414     s->regs[SONIC_CR] &= ~SONIC_CR_RXEN;
 415 }
 416
 417 static void dp8393x_do_transmit_packets(dp8393xState *s)
 418 {
 419     NetClientState *nc = qemu_get_queue(s->nic);
 420     uint16_t data[12];
 421     int width, size;
 422     int tx_len, len;
 423     uint16_t i;
 424
 425     width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
 426
 427     while (1) {
 428         /* Read memory */
 429         size = sizeof(uint16_t) * 6 * width;
 430         s->regs[SONIC_TTDA] = s->regs[SONIC_CTDA];
 431         DPRINTF("Transmit packet at %08x\n", dp8393x_ttda(s));
 432         address_space_rw(&s->as,
 433             dp8393x_ttda(s) + sizeof(uint16_t) * width,
 434             MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
 435         tx_len = 0;
 436
 437         /* Update registers */
 438         s->regs[SONIC_TCR] = dp8393x_get(s, width, data, 0) & 0xf000;
 439         s->regs[SONIC_TPS] = dp8393x_get(s, width, data, 1);
 440         s->regs[SONIC_TFC] = dp8393x_get(s, width, data, 2);
 441         s->regs[SONIC_TSA0] = dp8393x_get(s, width, data, 3);
 442         s->regs[SONIC_TSA1] = dp8393x_get(s, width, data, 4);
 443         s->regs[SONIC_TFS] = dp8393x_get(s, width, data, 5);
 444
 445         /* Handle programmable interrupt */
 446         if (s->regs[SONIC_TCR] & SONIC_TCR_PINT) {
 447             s->regs[SONIC_ISR] |= SONIC_ISR_PINT;
 448         } else {
 449             s->regs[SONIC_ISR] &= ~SONIC_ISR_PINT;
 450         }
 451
 452         for (i = 0; i < s->regs[SONIC_TFC]; ) {
 453             /* Append fragment */
 454             len = s->regs[SONIC_TFS];
 455             if (tx_len + len > sizeof(s->tx_buffer)) {
 456                 len = sizeof(s->tx_buffer) - tx_len;
 457             }
 458             address_space_rw(&s->as, dp8393x_tsa(s),
 459                 MEMTXATTRS_UNSPECIFIED, &s->tx_buffer[tx_len], len, 0);
 460             tx_len += len;
 461
 462             i++;
 463             if (i != s->regs[SONIC_TFC]) {
 464                 /* Read next fragment details */
 465                 size = sizeof(uint16_t) * 3 * width;
 466                 address_space_rw(&s->as,
 467                     dp8393x_ttda(s) + sizeof(uint16_t) * (4 + 3 * i) * width,
 468                     MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
 469                 s->regs[SONIC_TSA0] = dp8393x_get(s, width, data, 0);
 470                 s->regs[SONIC_TSA1] = dp8393x_get(s, width, data, 1);
 471                 s->regs[SONIC_TFS] = dp8393x_get(s, width, data, 2);
 472             }
 473         }
 474
 475         /* Handle Ethernet checksum */
 476         if (!(s->regs[SONIC_TCR] & SONIC_TCR_CRCI)) {
 477             /* Don't append FCS there, to look like slirp packets
 478              * which don't have one */
 479         } else {
 480             /* Remove existing FCS */
 481             tx_len -= 4;
 482         }
 483
 484         if (s->regs[SONIC_RCR] & (SONIC_RCR_LB1 | SONIC_RCR_LB0)) {
 485             /* Loopback */
 486             s->regs[SONIC_TCR] |= SONIC_TCR_CRSL;
 487             if (nc->info->can_receive(nc)) {
 488                 s->loopback_packet = 1;
 489                 nc->info->receive(nc, s->tx_buffer, tx_len);
 490             }
 491         } else {
 492             /* Transmit packet */
 493             qemu_send_packet(nc, s->tx_buffer, tx_len);
 494         }
 495         s->regs[SONIC_TCR] |= SONIC_TCR_PTX;
 496
 497         /* Write status */
 498         dp8393x_put(s, width, data, 0,
 499                     s->regs[SONIC_TCR] & 0x0fff); /* status */
 500         size = sizeof(uint16_t) * width;
 501         address_space_rw(&s->as,
 502             dp8393x_ttda(s),
 503             MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 1);
 504
 505         if (!(s->regs[SONIC_CR] & SONIC_CR_HTX)) {
 506             /* Read footer of packet */
 507             size = sizeof(uint16_t) * width;
 508             address_space_rw(&s->as,
 509                 dp8393x_ttda(s) +
 510                              sizeof(uint16_t) *
 511                              (4 + 3 * s->regs[SONIC_TFC]) * width,
 512                 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
 513             s->regs[SONIC_CTDA] = dp8393x_get(s, width, data, 0) & ~0x1;
 514             if (dp8393x_get(s, width, data, 0) & 0x1) {
 515                 /* EOL detected */
 516                 break;
 517             }
 518         }
 519     }
 520
 521     /* Done */
 522     s->regs[SONIC_CR] &= ~SONIC_CR_TXP;
 523     s->regs[SONIC_ISR] |= SONIC_ISR_TXDN;
 524     dp8393x_update_irq(s);
 525 }
 526
 527 static void dp8393x_do_halt_transmission(dp8393xState *s)
 528 {
 529     /* Nothing to do */
 530 }
 531
 532 static void dp8393x_do_command(dp8393xState *s, uint16_t command)
 533 {
 534     if ((s->regs[SONIC_CR] & SONIC_CR_RST) && !(command & SONIC_CR_RST)) {
 535         s->regs[SONIC_CR] &= ~SONIC_CR_RST;
 536         return;
 537     }
 538
 539     s->regs[SONIC_CR] |= (command & SONIC_CR_MASK);
 540
 541     if (command & SONIC_CR_HTX)
 542         dp8393x_do_halt_transmission(s);
 543     if (command & SONIC_CR_TXP)
 544         dp8393x_do_transmit_packets(s);
 545     if (command & SONIC_CR_RXDIS)
 546         dp8393x_do_receiver_disable(s);
 547     if (command & SONIC_CR_RXEN)
 548         dp8393x_do_receiver_enable(s);
 549     if (command & SONIC_CR_STP)
 550         dp8393x_do_stop_timer(s);
 551     if (command & SONIC_CR_ST)
 552         dp8393x_do_start_timer(s);
 553     if (command & SONIC_CR_RST)
 554         dp8393x_do_software_reset(s);
 555     if (command & SONIC_CR_RRRA)
 556         dp8393x_do_read_rra(s);
 557     if (command & SONIC_CR_LCAM)
 558         dp8393x_do_load_cam(s);
 559 }
 560
 561 static uint64_t dp8393x_read(void *opaque, hwaddr addr, unsigned int size)
 562 {
 563     dp8393xState *s = opaque;
 564     int reg = addr >> s->it_shift;
 565     uint16_t val = 0;
 566
 567     switch (reg) {
 568         /* Update data before reading it */
 569         case SONIC_WT0:
 570         case SONIC_WT1:
 571             dp8393x_update_wt_regs(s);
 572             val = s->regs[reg];
 573             break;
 574         /* Accept read to some registers only when in reset mode */
 575         case SONIC_CAP2:
 576         case SONIC_CAP1:
 577         case SONIC_CAP0:
 578             if (s->regs[SONIC_CR] & SONIC_CR_RST) {
 579                 val = s->cam[s->regs[SONIC_CEP] & 0xf][2* (SONIC_CAP0 - reg) + 1] << 8;
 580                 val |= s->cam[s->regs[SONIC_CEP] & 0xf][2* (SONIC_CAP0 - reg)];
 581             }
 582             break;
 583         /* All other registers have no special contrainst */
 584         default:
 585             val = s->regs[reg];
 586     }
 587
 588     DPRINTF("read 0x%04x from reg %s\n", val, reg_names[reg]);
 589
 590     return val;
 591 }
 592
 593 static void dp8393x_write(void *opaque, hwaddr addr, uint64_t data,
 594                           unsigned int size)
 595 {
 596     dp8393xState *s = opaque;
 597     int reg = addr >> s->it_shift;
 598
 599     DPRINTF("write 0x%04x to reg %s\n", (uint16_t)data, reg_names[reg]);
 600
 601     switch (reg) {
 602         /* Command register */
 603         case SONIC_CR:
 604             dp8393x_do_command(s, data);
 605             break;
 606         /* Prevent write to read-only registers */
 607         case SONIC_CAP2:
 608         case SONIC_CAP1:
 609         case SONIC_CAP0:
 610         case SONIC_SR:
 611         case SONIC_MDT:
 612             DPRINTF("writing to reg %d invalid\n", reg);
 613             break;
 614         /* Accept write to some registers only when in reset mode */
 615         case SONIC_DCR:
 616             if (s->regs[SONIC_CR] & SONIC_CR_RST) {
 617                 s->regs[reg] = data & 0xbfff;
 618             } else {
 619                 DPRINTF("writing to DCR invalid\n");
 620             }
 621             break;
 622         case SONIC_DCR2:
 623             if (s->regs[SONIC_CR] & SONIC_CR_RST) {
 624                 s->regs[reg] = data & 0xf017;
 625             } else {
 626                 DPRINTF("writing to DCR2 invalid\n");
 627             }
 628             break;
 629         /* 12 lower bytes are Read Only */
 630         case SONIC_TCR:
 631             s->regs[reg] = data & 0xf000;
 632             break;
 633         /* 9 lower bytes are Read Only */
 634         case SONIC_RCR:
 635             s->regs[reg] = data & 0xffe0;
 636             break;
 637         /* Ignore most significant bit */
 638         case SONIC_IMR:
 639             s->regs[reg] = data & 0x7fff;
 640             dp8393x_update_irq(s);
 641             break;
 642         /* Clear bits by writing 1 to them */
 643         case SONIC_ISR:
 644             data &= s->regs[reg];
 645             s->regs[reg] &= ~data;
 646             if (data & SONIC_ISR_RBE) {
 647                 dp8393x_do_read_rra(s);
 648             }
 649             dp8393x_update_irq(s);
 650             if (dp8393x_can_receive(s->nic->ncs)) {
 651                 qemu_flush_queued_packets(qemu_get_queue(s->nic));
 652             }
 653             break;
 654         /* Ignore least significant bit */
 655         case SONIC_RSA:
 656         case SONIC_REA:
 657         case SONIC_RRP:
 658         case SONIC_RWP:
 659             s->regs[reg] = data & 0xfffe;
 660             break;
 661         /* Invert written value for some registers */
 662         case SONIC_CRCT:
 663         case SONIC_FAET:
 664         case SONIC_MPT:
 665             s->regs[reg] = data ^ 0xffff;
 666             break;
 667         /* All other registers have no special contrainst */
 668         default:
 669             s->regs[reg] = data;
 670     }
 671
 672     if (reg == SONIC_WT0 || reg == SONIC_WT1) {
 673         dp8393x_set_next_tick(s);
 674     }
 675 }
 676
 677 static const MemoryRegionOps dp8393x_ops = {
 678     .read = dp8393x_read,
 679     .write = dp8393x_write,
 680     .impl.min_access_size = 2,
 681     .impl.max_access_size = 2,
 682     .endianness = DEVICE_NATIVE_ENDIAN,
 683 };
 684
 685 static void dp8393x_watchdog(void *opaque)
 686 {
 687     dp8393xState *s = opaque;
 688
 689     if (s->regs[SONIC_CR] & SONIC_CR_STP) {
 690         return;
 691     }
 692
 693     s->regs[SONIC_WT1] = 0xffff;
 694     s->regs[SONIC_WT0] = 0xffff;
 695     dp8393x_set_next_tick(s);
 696
 697     /* Signal underflow */
 698     s->regs[SONIC_ISR] |= SONIC_ISR_TC;
 699     dp8393x_update_irq(s);
 700 }
 701
 702 static int dp8393x_can_receive(NetClientState *nc)
 703 {
 704     dp8393xState *s = qemu_get_nic_opaque(nc);
 705
 706     if (!(s->regs[SONIC_CR] & SONIC_CR_RXEN))
 707         return 0;
 708     if (s->regs[SONIC_ISR] & SONIC_ISR_RBE)
 709         return 0;
 710     return 1;
 711 }
 712
 713 static int dp8393x_receive_filter(dp8393xState *s, const uint8_t * buf,
 714                                   int size)
 715 {
 716     static const uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
 717     int i;
 718
 719     /* Check promiscuous mode */
 720     if ((s->regs[SONIC_RCR] & SONIC_RCR_PRO) && (buf[0] & 1) == 0) {
 721         return 0;
 722     }
 723
 724     /* Check multicast packets */
 725     if ((s->regs[SONIC_RCR] & SONIC_RCR_AMC) && (buf[0] & 1) == 1) {
 726         return SONIC_RCR_MC;
 727     }
 728
 729     /* Check broadcast */
 730     if ((s->regs[SONIC_RCR] & SONIC_RCR_BRD) && !memcmp(buf, bcast, sizeof(bcast))) {
 731         return SONIC_RCR_BC;
 732     }
 733
 734     /* Check CAM */
 735     for (i = 0; i < 16; i++) {
 736         if (s->regs[SONIC_CE] & (1 << i)) {
 737              /* Entry enabled */
 738              if (!memcmp(buf, s->cam[i], sizeof(s->cam[i]))) {
 739                  return 0;
 740              }
 741         }
 742     }
 743
 744     return -1;
 745 }
 746
 747 static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
 748                                size_t size)
 749 {
 750     dp8393xState *s = qemu_get_nic_opaque(nc);
 751     uint16_t data[10];
 752     int packet_type;
 753     uint32_t available, address;
 754     int width, rx_len = size;
 755     uint32_t checksum;
 756
 757     width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
 758
 759     s->regs[SONIC_RCR] &= ~(SONIC_RCR_PRX | SONIC_RCR_LBK | SONIC_RCR_FAER |
 760         SONIC_RCR_CRCR | SONIC_RCR_LPKT | SONIC_RCR_BC | SONIC_RCR_MC);
 761
 762     packet_type = dp8393x_receive_filter(s, buf, size);
 763     if (packet_type < 0) {
 764         DPRINTF("packet not for netcard\n");
 765         return -1;
 766     }
 767
 768     /* XXX: Check byte ordering */
 769
 770     /* Check for EOL */
 771     if (s->regs[SONIC_LLFA] & 0x1) {
 772         /* Are we still in resource exhaustion? */
 773         size = sizeof(uint16_t) * 1 * width;
 774         address = dp8393x_crda(s) + sizeof(uint16_t) * 5 * width;
 775         address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED,
 776                          (uint8_t *)data, size, 0);
 777         if (dp8393x_get(s, width, data, 0) & 0x1) {
 778             /* Still EOL ; stop reception */
 779             return -1;
 780         } else {
 781             s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA];
 782         }
 783     }
 784
 785     /* Save current position */
 786     s->regs[SONIC_TRBA1] = s->regs[SONIC_CRBA1];
 787     s->regs[SONIC_TRBA0] = s->regs[SONIC_CRBA0];
 788
 789     /* Calculate the ethernet checksum */
 790     checksum = cpu_to_le32(crc32(0, buf, rx_len));
 791
 792     /* Put packet into RBA */
 793     DPRINTF("Receive packet at %08x\n", dp8393x_crba(s));
 794     address = dp8393x_crba(s);
 795     address_space_rw(&s->as, address,
 796         MEMTXATTRS_UNSPECIFIED, (uint8_t *)buf, rx_len, 1);
 797     address += rx_len;
 798     address_space_rw(&s->as, address,
 799         MEMTXATTRS_UNSPECIFIED, (uint8_t *)&checksum, 4, 1);
 800     rx_len += 4;
 801     s->regs[SONIC_CRBA1] = address >> 16;
 802     s->regs[SONIC_CRBA0] = address & 0xffff;
 803     available = dp8393x_rbwc(s);
 804     available -= rx_len / 2;
 805     s->regs[SONIC_RBWC1] = available >> 16;
 806     s->regs[SONIC_RBWC0] = available & 0xffff;
 807
 808     /* Update status */
 809     if (dp8393x_rbwc(s) < s->regs[SONIC_EOBC]) {
 810         s->regs[SONIC_RCR] |= SONIC_RCR_LPKT;
 811     }
 812     s->regs[SONIC_RCR] |= packet_type;
 813     s->regs[SONIC_RCR] |= SONIC_RCR_PRX;
 814     if (s->loopback_packet) {
 815         s->regs[SONIC_RCR] |= SONIC_RCR_LBK;
 816         s->loopback_packet = 0;
 817     }
 818
 819     /* Write status to memory */
 820     DPRINTF("Write status at %08x\n", dp8393x_crda(s));
 821     dp8393x_put(s, width, data, 0, s->regs[SONIC_RCR]); /* status */
 822     dp8393x_put(s, width, data, 1, rx_len); /* byte count */
 823     dp8393x_put(s, width, data, 2, s->regs[SONIC_TRBA0]); /* pkt_ptr0 */
 824     dp8393x_put(s, width, data, 3, s->regs[SONIC_TRBA1]); /* pkt_ptr1 */
 825     dp8393x_put(s, width, data, 4, s->regs[SONIC_RSC]); /* seq_no */
 826     size = sizeof(uint16_t) * 5 * width;
 827     address_space_rw(&s->as, dp8393x_crda(s),
 828         MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 1);
 829
 830     /* Move to next descriptor */
 831     size = sizeof(uint16_t) * width;
 832     address_space_rw(&s->as, dp8393x_crda(s) + sizeof(uint16_t) * 5 * width,
 833         MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
 834     s->regs[SONIC_LLFA] = dp8393x_get(s, width, data, 0);
 835     if (s->regs[SONIC_LLFA] & 0x1) {
 836         /* EOL detected */
 837         s->regs[SONIC_ISR] |= SONIC_ISR_RDE;
 838     } else {
 839         dp8393x_put(s, width, data, 0, 0); /* in_use */
 840         address_space_rw(&s->as, dp8393x_crda(s) + sizeof(uint16_t) * 6 * width,
 841             MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, sizeof(uint16_t), 1);
 842         s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA];
 843         s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX;
 844         s->regs[SONIC_RSC] = (s->regs[SONIC_RSC] & 0xff00) | (((s->regs[SONIC_RSC] & 0x00ff) + 1) & 0x00ff);
 845
 846         if (s->regs[SONIC_RCR] & SONIC_RCR_LPKT) {
 847             /* Read next RRA */
 848             dp8393x_do_read_rra(s);
 849         }
 850     }
 851
 852     /* Done */
 853     dp8393x_update_irq(s);
 854
 855     return size;
 856 }
 857
 858 static void dp8393x_reset(DeviceState *dev)
 859 {
 860     dp8393xState *s = DP8393X(dev);
 861     timer_del(s->watchdog);
 862
 863     memset(s->regs, 0, sizeof(s->regs));
 864     s->regs[SONIC_CR] = SONIC_CR_RST | SONIC_CR_STP | SONIC_CR_RXDIS;
 865     s->regs[SONIC_DCR] &= ~(SONIC_DCR_EXBUS | SONIC_DCR_LBR);
 866     s->regs[SONIC_RCR] &= ~(SONIC_RCR_LB0 | SONIC_RCR_LB1 | SONIC_RCR_BRD | SONIC_RCR_RNT);
 867     s->regs[SONIC_TCR] |= SONIC_TCR_NCRS | SONIC_TCR_PTX;
 868     s->regs[SONIC_TCR] &= ~SONIC_TCR_BCM;
 869     s->regs[SONIC_IMR] = 0;
 870     s->regs[SONIC_ISR] = 0;
 871     s->regs[SONIC_DCR2] = 0;
 872     s->regs[SONIC_EOBC] = 0x02F8;
 873     s->regs[SONIC_RSC] = 0;
 874     s->regs[SONIC_CE] = 0;
 875     s->regs[SONIC_RSC] = 0;
 876
 877     /* Network cable is connected */
 878     s->regs[SONIC_RCR] |= SONIC_RCR_CRS;
 879
 880     dp8393x_update_irq(s);
 881 }
 882
 883 static NetClientInfo net_dp83932_info = {
 884     .type = NET_CLIENT_DRIVER_NIC,
 885     .size = sizeof(NICState),
 886     .can_receive = dp8393x_can_receive,
 887     .receive = dp8393x_receive,
 888 };
 889
 890 static void dp8393x_instance_init(Object *obj)
 891 {
 892     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 893     dp8393xState *s = DP8393X(obj);
 894
 895     sysbus_init_mmio(sbd, &s->mmio);
 896     sysbus_init_mmio(sbd, &s->prom);
 897     sysbus_init_irq(sbd, &s->irq);
 898 }
 899
 900 static void dp8393x_realize(DeviceState *dev, Error **errp)
 901 {
 902     dp8393xState *s = DP8393X(dev);
 903     int i, checksum;
 904     uint8_t *prom;
 905     Error *local_err = NULL;
 906
 907     address_space_init(&s->as, s->dma_mr, "dp8393x");
 908     memory_region_init_io(&s->mmio, OBJECT(dev), &dp8393x_ops, s,
 909                           "dp8393x-regs", 0x40 << s->it_shift);
 910
 911     s->nic = qemu_new_nic(&net_dp83932_info, &s->conf,
 912                           object_get_typename(OBJECT(dev)), dev->id, s);
 913     qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
 914
 915     s->watchdog = timer_new_ns(QEMU_CLOCK_VIRTUAL, dp8393x_watchdog, s);
 916     s->regs[SONIC_SR] = 0x0004; /* only revision recognized by Linux */
 917
 918     memory_region_init_ram(&s->prom, OBJECT(dev),
 919                            "dp8393x-prom", SONIC_PROM_SIZE, &local_err);
 920     if (local_err) {
 921         error_propagate(errp, local_err);
 922         return;
 923     }
 924     memory_region_set_readonly(&s->prom, true);
 925     prom = memory_region_get_ram_ptr(&s->prom);
 926     checksum = 0;
 927     for (i = 0; i < 6; i++) {
 928         prom[i] = s->conf.macaddr.a[i];
 929         checksum += prom[i];
 930         if (checksum > 0xff) {
 931             checksum = (checksum + 1) & 0xff;
 932         }
 933     }
 934     prom[7] = 0xff - checksum;
 935 }
 936
 937 static const VMStateDescription vmstate_dp8393x = {
 938     .name = "dp8393x",
 939     .version_id = 0,
 940     .minimum_version_id = 0,
 941     .fields = (VMStateField []) {
 942         VMSTATE_BUFFER_UNSAFE(cam, dp8393xState, 0, 16 * 6),
 943         VMSTATE_UINT16_ARRAY(regs, dp8393xState, 0x40),
 944         VMSTATE_END_OF_LIST()
 945     }
 946 };
 947
 948 static Property dp8393x_properties[] = {
 949     DEFINE_NIC_PROPERTIES(dp8393xState, conf),
 950     DEFINE_PROP_PTR("dma_mr", dp8393xState, dma_mr),
 951     DEFINE_PROP_UINT8("it_shift", dp8393xState, it_shift, 0),
 952     DEFINE_PROP_BOOL("big_endian", dp8393xState, big_endian, false),
 953     DEFINE_PROP_END_OF_LIST(),
 954 };
 955
 956 static void dp8393x_class_init(ObjectClass *klass, void *data)
 957 {
 958     DeviceClass *dc = DEVICE_CLASS(klass);
 959
 960     set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
 961     dc->realize = dp8393x_realize;
 962     dc->reset = dp8393x_reset;
 963     dc->vmsd = &vmstate_dp8393x;
 964     dc->props = dp8393x_properties;
 965     /* Reason: dma_mr property can't be set */
 966     dc->user_creatable = false;
 967 }
 968
 969 static const TypeInfo dp8393x_info = {
 970     .name          = TYPE_DP8393X,
 971     .parent        = TYPE_SYS_BUS_DEVICE,
 972     .instance_size = sizeof(dp8393xState),
 973     .instance_init = dp8393x_instance_init,
 974     .class_init    = dp8393x_class_init,
 975 };
 976
 977 static void dp8393x_register_types(void)
 978 {
 979     type_register_static(&dp8393x_info);
 980 }
 981
 982 type_init(dp8393x_register_types)