target/sh4/helper.c

   1 /*
   2  *  SH4 emulation
   3  *
   4  *  Copyright (c) 2005 Samuel Tardieu
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "qemu/osdep.h"
  20
  21 #include "cpu.h"
  22 #include "exec/exec-all.h"
  23 #include "exec/log.h"
  24 #include "sysemu/sysemu.h"
  25
  26 #if !defined(CONFIG_USER_ONLY)
  27 #include "hw/sh4/sh_intc.h"
  28 #endif
  29
  30 #define MMU_OK                   0
  31 #define MMU_ITLB_MISS            (-1)
  32 #define MMU_ITLB_MULTIPLE        (-2)
  33 #define MMU_ITLB_VIOLATION       (-3)
  34 #define MMU_DTLB_MISS_READ       (-4)
  35 #define MMU_DTLB_MISS_WRITE      (-5)
  36 #define MMU_DTLB_INITIAL_WRITE   (-6)
  37 #define MMU_DTLB_VIOLATION_READ  (-7)
  38 #define MMU_DTLB_VIOLATION_WRITE (-8)
  39 #define MMU_DTLB_MULTIPLE        (-9)
  40 #define MMU_DTLB_MISS            (-10)
  41 #define MMU_IADDR_ERROR          (-11)
  42 #define MMU_DADDR_ERROR_READ     (-12)
  43 #define MMU_DADDR_ERROR_WRITE    (-13)
  44
  45 #if defined(CONFIG_USER_ONLY)
  46
  47 void superh_cpu_do_interrupt(CPUState *cs)
  48 {
  49     cs->exception_index = -1;
  50 }
  51
  52 int cpu_sh4_is_cached(CPUSH4State *env, target_ulong addr)
  53 {
  54     /* For user mode, only U0 area is cacheable. */
  55     return !(addr & 0x80000000);
  56 }
  57
  58 #else /* !CONFIG_USER_ONLY */
  59
  60 void superh_cpu_do_interrupt(CPUState *cs)
  61 {
  62     SuperHCPU *cpu = SUPERH_CPU(cs);
  63     CPUSH4State *env = &cpu->env;
  64     int do_irq = cs->interrupt_request & CPU_INTERRUPT_HARD;
  65     int do_exp, irq_vector = cs->exception_index;
  66
  67     /* prioritize exceptions over interrupts */
  68
  69     do_exp = cs->exception_index != -1;
  70     do_irq = do_irq && (cs->exception_index == -1);
  71
  72     if (env->sr & (1u << SR_BL)) {
  73         if (do_exp && cs->exception_index != 0x1e0) {
  74             /* In theory a masked exception generates a reset exception,
  75                which in turn jumps to the reset vector. However this only
  76                works when using a bootloader. When using a kernel and an
  77                initrd, they need to be reloaded and the program counter
  78                should be loaded with the kernel entry point.
  79                qemu_system_reset_request takes care of that.  */
  80             qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
  81             return;
  82         }
  83         if (do_irq && !env->in_sleep) {
  84             return; /* masked */
  85         }
  86     }
  87     env->in_sleep = 0;
  88
  89     if (do_irq) {
  90         irq_vector = sh_intc_get_pending_vector(env->intc_handle,
  91                                                 (env->sr >> 4) & 0xf);
  92         if (irq_vector == -1) {
  93             return; /* masked */
  94         }
  95     }
  96
  97     if (qemu_loglevel_mask(CPU_LOG_INT)) {
  98         const char *expname;
  99         switch (cs->exception_index) {
 100         case 0x0e0:
 101             expname = "addr_error";
 102             break;
 103         case 0x040:
 104             expname = "tlb_miss";
 105             break;
 106         case 0x0a0:
 107             expname = "tlb_violation";
 108             break;
 109         case 0x180:
 110             expname = "illegal_instruction";
 111             break;
 112         case 0x1a0:
 113             expname = "slot_illegal_instruction";
 114             break;
 115         case 0x800:
 116             expname = "fpu_disable";
 117             break;
 118         case 0x820:
 119             expname = "slot_fpu";
 120             break;
 121         case 0x100:
 122             expname = "data_write";
 123             break;
 124         case 0x060:
 125             expname = "dtlb_miss_write";
 126             break;
 127         case 0x0c0:
 128             expname = "dtlb_violation_write";
 129             break;
 130         case 0x120:
 131             expname = "fpu_exception";
 132             break;
 133         case 0x080:
 134             expname = "initial_page_write";
 135             break;
 136         case 0x160:
 137             expname = "trapa";
 138             break;
 139         default:
 140             expname = do_irq ? "interrupt" : "???";
 141             break;
 142         }
 143         qemu_log("exception 0x%03x [%s] raised\n",
 144                   irq_vector, expname);
 145         log_cpu_state(cs, 0);
 146     }
 147
 148     env->ssr = cpu_read_sr(env);
 149     env->spc = env->pc;
 150     env->sgr = env->gregs[15];
 151     env->sr |= (1u << SR_BL) | (1u << SR_MD) | (1u << SR_RB);
 152     env->lock_addr = -1;
 153
 154     if (env->flags & DELAY_SLOT_MASK) {
 155         /* Branch instruction should be executed again before delay slot. */
 156         env->spc -= 2;
 157         /* Clear flags for exception/interrupt routine. */
 158         env->flags &= ~DELAY_SLOT_MASK;
 159     }
 160
 161     if (do_exp) {
 162         env->expevt = cs->exception_index;
 163         switch (cs->exception_index) {
 164         case 0x000:
 165         case 0x020:
 166         case 0x140:
 167             env->sr &= ~(1u << SR_FD);
 168             env->sr |= 0xf << 4; /* IMASK */
 169             env->pc = 0xa0000000;
 170             break;
 171         case 0x040:
 172         case 0x060:
 173             env->pc = env->vbr + 0x400;
 174             break;
 175         case 0x160:
 176             env->spc += 2; /* special case for TRAPA */
 177             /* fall through */
 178         default:
 179             env->pc = env->vbr + 0x100;
 180             break;
 181         }
 182         return;
 183     }
 184
 185     if (do_irq) {
 186         env->intevt = irq_vector;
 187         env->pc = env->vbr + 0x600;
 188         return;
 189     }
 190 }
 191
 192 static void update_itlb_use(CPUSH4State * env, int itlbnb)
 193 {
 194     uint8_t or_mask = 0, and_mask = (uint8_t) - 1;
 195
 196     switch (itlbnb) {
 197     case 0:
 198         and_mask = 0x1f;
 199         break;
 200     case 1:
 201         and_mask = 0xe7;
 202         or_mask = 0x80;
 203         break;
 204     case 2:
 205         and_mask = 0xfb;
 206         or_mask = 0x50;
 207         break;
 208     case 3:
 209         or_mask = 0x2c;
 210         break;
 211     }
 212
 213     env->mmucr &= (and_mask << 24) | 0x00ffffff;
 214     env->mmucr |= (or_mask << 24);
 215 }
 216
 217 static int itlb_replacement(CPUSH4State * env)
 218 {
 219     if ((env->mmucr & 0xe0000000) == 0xe0000000) {
 220         return 0;
 221     }
 222     if ((env->mmucr & 0x98000000) == 0x18000000) {
 223         return 1;
 224     }
 225     if ((env->mmucr & 0x54000000) == 0x04000000) {
 226         return 2;
 227     }
 228     if ((env->mmucr & 0x2c000000) == 0x00000000) {
 229         return 3;
 230     }
 231     cpu_abort(env_cpu(env), "Unhandled itlb_replacement");
 232 }
 233
 234 /* Find the corresponding entry in the right TLB
 235    Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
 236 */
 237 static int find_tlb_entry(CPUSH4State * env, target_ulong address,
 238                           tlb_t * entries, uint8_t nbtlb, int use_asid)
 239 {
 240     int match = MMU_DTLB_MISS;
 241     uint32_t start, end;
 242     uint8_t asid;
 243     int i;
 244
 245     asid = env->pteh & 0xff;
 246
 247     for (i = 0; i < nbtlb; i++) {
 248         if (!entries[i].v)
 249             continue;           /* Invalid entry */
 250         if (!entries[i].sh && use_asid && entries[i].asid != asid)
 251             continue;           /* Bad ASID */
 252         start = (entries[i].vpn << 10) & ~(entries[i].size - 1);
 253         end = start + entries[i].size - 1;
 254         if (address >= start && address <= end) {       /* Match */
 255             if (match != MMU_DTLB_MISS)
 256                 return MMU_DTLB_MULTIPLE;       /* Multiple match */
 257             match = i;
 258         }
 259     }
 260     return match;
 261 }
 262
 263 static void increment_urc(CPUSH4State * env)
 264 {
 265     uint8_t urb, urc;
 266
 267     /* Increment URC */
 268     urb = ((env->mmucr) >> 18) & 0x3f;
 269     urc = ((env->mmucr) >> 10) & 0x3f;
 270     urc++;
 271     if ((urb > 0 && urc > urb) || urc > (UTLB_SIZE - 1))
 272         urc = 0;
 273     env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10);
 274 }
 275
 276 /* Copy and utlb entry into itlb
 277    Return entry
 278 */
 279 static int copy_utlb_entry_itlb(CPUSH4State *env, int utlb)
 280 {
 281     int itlb;
 282
 283     tlb_t * ientry;
 284     itlb = itlb_replacement(env);
 285     ientry = &env->itlb[itlb];
 286     if (ientry->v) {
 287         tlb_flush_page(env_cpu(env), ientry->vpn << 10);
 288     }
 289     *ientry = env->utlb[utlb];
 290     update_itlb_use(env, itlb);
 291     return itlb;
 292 }
 293
 294 /* Find itlb entry
 295    Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
 296 */
 297 static int find_itlb_entry(CPUSH4State * env, target_ulong address,
 298                            int use_asid)
 299 {
 300     int e;
 301
 302     e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid);
 303     if (e == MMU_DTLB_MULTIPLE) {
 304         e = MMU_ITLB_MULTIPLE;
 305     } else if (e == MMU_DTLB_MISS) {
 306         e = MMU_ITLB_MISS;
 307     } else if (e >= 0) {
 308         update_itlb_use(env, e);
 309     }
 310     return e;
 311 }
 312
 313 /* Find utlb entry
 314    Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
 315 static int find_utlb_entry(CPUSH4State * env, target_ulong address, int use_asid)
 316 {
 317     /* per utlb access */
 318     increment_urc(env);
 319
 320     /* Return entry */
 321     return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
 322 }
 323
 324 /* Match address against MMU
 325    Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE,
 326    MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ,
 327    MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS,
 328    MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION,
 329    MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE.
 330 */
 331 static int get_mmu_address(CPUSH4State * env, target_ulong * physical,
 332                            int *prot, target_ulong address,
 333                            int rw, int access_type)
 334 {
 335     int use_asid, n;
 336     tlb_t *matching = NULL;
 337
 338     use_asid = !(env->mmucr & MMUCR_SV) || !(env->sr & (1u << SR_MD));
 339
 340     if (rw == 2) {
 341         n = find_itlb_entry(env, address, use_asid);
 342         if (n >= 0) {
 343             matching = &env->itlb[n];
 344             if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) {
 345                 n = MMU_ITLB_VIOLATION;
 346             } else {
 347                 *prot = PAGE_EXEC;
 348             }
 349         } else {
 350             n = find_utlb_entry(env, address, use_asid);
 351             if (n >= 0) {
 352                 n = copy_utlb_entry_itlb(env, n);
 353                 matching = &env->itlb[n];
 354                 if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) {
 355                     n = MMU_ITLB_VIOLATION;
 356                 } else {
 357                     *prot = PAGE_READ | PAGE_EXEC;
 358                     if ((matching->pr & 1) && matching->d) {
 359                         *prot |= PAGE_WRITE;
 360                     }
 361                 }
 362             } else if (n == MMU_DTLB_MULTIPLE) {
 363                 n = MMU_ITLB_MULTIPLE;
 364             } else if (n == MMU_DTLB_MISS) {
 365                 n = MMU_ITLB_MISS;
 366             }
 367         }
 368     } else {
 369         n = find_utlb_entry(env, address, use_asid);
 370         if (n >= 0) {
 371             matching = &env->utlb[n];
 372             if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) {
 373                 n = (rw == 1) ? MMU_DTLB_VIOLATION_WRITE :
 374                     MMU_DTLB_VIOLATION_READ;
 375             } else if ((rw == 1) && !(matching->pr & 1)) {
 376                 n = MMU_DTLB_VIOLATION_WRITE;
 377             } else if ((rw == 1) && !matching->d) {
 378                 n = MMU_DTLB_INITIAL_WRITE;
 379             } else {
 380                 *prot = PAGE_READ;
 381                 if ((matching->pr & 1) && matching->d) {
 382                     *prot |= PAGE_WRITE;
 383                 }
 384             }
 385         } else if (n == MMU_DTLB_MISS) {
 386             n = (rw == 1) ? MMU_DTLB_MISS_WRITE :
 387                 MMU_DTLB_MISS_READ;
 388         }
 389     }
 390     if (n >= 0) {
 391         n = MMU_OK;
 392         *physical = ((matching->ppn << 10) & ~(matching->size - 1)) |
 393             (address & (matching->size - 1));
 394     }
 395     return n;
 396 }
 397
 398 static int get_physical_address(CPUSH4State * env, target_ulong * physical,
 399                                 int *prot, target_ulong address,
 400                                 int rw, int access_type)
 401 {
 402     /* P1, P2 and P4 areas do not use translation */
 403     if ((address >= 0x80000000 && address < 0xc0000000) ||
 404         address >= 0xe0000000) {
 405         if (!(env->sr & (1u << SR_MD))
 406             && (address < 0xe0000000 || address >= 0xe4000000)) {
 407             /* Unauthorized access in user mode (only store queues are available) */
 408             qemu_log_mask(LOG_GUEST_ERROR, "Unauthorized access\n");
 409             if (rw == 0)
 410                 return MMU_DADDR_ERROR_READ;
 411             else if (rw == 1)
 412                 return MMU_DADDR_ERROR_WRITE;
 413             else
 414                 return MMU_IADDR_ERROR;
 415         }
 416         if (address >= 0x80000000 && address < 0xc0000000) {
 417             /* Mask upper 3 bits for P1 and P2 areas */
 418             *physical = address & 0x1fffffff;
 419         } else {
 420             *physical = address;
 421         }
 422         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 423         return MMU_OK;
 424     }
 425
 426     /* If MMU is disabled, return the corresponding physical page */
 427     if (!(env->mmucr & MMUCR_AT)) {
 428         *physical = address & 0x1FFFFFFF;
 429         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 430         return MMU_OK;
 431     }
 432
 433     /* We need to resort to the MMU */
 434     return get_mmu_address(env, physical, prot, address, rw, access_type);
 435 }
 436
 437 hwaddr superh_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 438 {
 439     SuperHCPU *cpu = SUPERH_CPU(cs);
 440     target_ulong physical;
 441     int prot;
 442
 443     get_physical_address(&cpu->env, &physical, &prot, addr, 0, 0);
 444     return physical;
 445 }
 446
 447 void cpu_load_tlb(CPUSH4State * env)
 448 {
 449     CPUState *cs = env_cpu(env);
 450     int n = cpu_mmucr_urc(env->mmucr);
 451     tlb_t * entry = &env->utlb[n];
 452
 453     if (entry->v) {
 454         /* Overwriting valid entry in utlb. */
 455         target_ulong address = entry->vpn << 10;
 456         tlb_flush_page(cs, address);
 457     }
 458
 459     /* Take values into cpu status from registers. */
 460     entry->asid = (uint8_t)cpu_pteh_asid(env->pteh);
 461     entry->vpn  = cpu_pteh_vpn(env->pteh);
 462     entry->v    = (uint8_t)cpu_ptel_v(env->ptel);
 463     entry->ppn  = cpu_ptel_ppn(env->ptel);
 464     entry->sz   = (uint8_t)cpu_ptel_sz(env->ptel);
 465     switch (entry->sz) {
 466     case 0: /* 00 */
 467         entry->size = 1024; /* 1K */
 468         break;
 469     case 1: /* 01 */
 470         entry->size = 1024 * 4; /* 4K */
 471         break;
 472     case 2: /* 10 */
 473         entry->size = 1024 * 64; /* 64K */
 474         break;
 475     case 3: /* 11 */
 476         entry->size = 1024 * 1024; /* 1M */
 477         break;
 478     default:
 479         cpu_abort(cs, "Unhandled load_tlb");
 480         break;
 481     }
 482     entry->sh   = (uint8_t)cpu_ptel_sh(env->ptel);
 483     entry->c    = (uint8_t)cpu_ptel_c(env->ptel);
 484     entry->pr   = (uint8_t)cpu_ptel_pr(env->ptel);
 485     entry->d    = (uint8_t)cpu_ptel_d(env->ptel);
 486     entry->wt   = (uint8_t)cpu_ptel_wt(env->ptel);
 487     entry->sa   = (uint8_t)cpu_ptea_sa(env->ptea);
 488     entry->tc   = (uint8_t)cpu_ptea_tc(env->ptea);
 489 }
 490
 491  void cpu_sh4_invalidate_tlb(CPUSH4State *s)
 492 {
 493     int i;
 494
 495     /* UTLB */
 496     for (i = 0; i < UTLB_SIZE; i++) {
 497         tlb_t * entry = &s->utlb[i];
 498         entry->v = 0;
 499     }
 500     /* ITLB */
 501     for (i = 0; i < ITLB_SIZE; i++) {
 502         tlb_t * entry = &s->itlb[i];
 503         entry->v = 0;
 504     }
 505
 506     tlb_flush(env_cpu(s));
 507 }
 508
 509 uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
 510                                        hwaddr addr)
 511 {
 512     int index = (addr & 0x00000300) >> 8;
 513     tlb_t * entry = &s->itlb[index];
 514
 515     return (entry->vpn  << 10) |
 516            (entry->v    <<  8) |
 517            (entry->asid);
 518 }
 519
 520 void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr,
 521                                     uint32_t mem_value)
 522 {
 523     uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
 524     uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
 525     uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
 526
 527     int index = (addr & 0x00000300) >> 8;
 528     tlb_t * entry = &s->itlb[index];
 529     if (entry->v) {
 530         /* Overwriting valid entry in itlb. */
 531         target_ulong address = entry->vpn << 10;
 532         tlb_flush_page(env_cpu(s), address);
 533     }
 534     entry->asid = asid;
 535     entry->vpn = vpn;
 536     entry->v = v;
 537 }
 538
 539 uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s,
 540                                        hwaddr addr)
 541 {
 542     int array = (addr & 0x00800000) >> 23;
 543     int index = (addr & 0x00000300) >> 8;
 544     tlb_t * entry = &s->itlb[index];
 545
 546     if (array == 0) {
 547         /* ITLB Data Array 1 */
 548         return (entry->ppn << 10) |
 549                (entry->v   <<  8) |
 550                (entry->pr  <<  5) |
 551                ((entry->sz & 1) <<  6) |
 552                ((entry->sz & 2) <<  4) |
 553                (entry->c   <<  3) |
 554                (entry->sh  <<  1);
 555     } else {
 556         /* ITLB Data Array 2 */
 557         return (entry->tc << 1) |
 558                (entry->sa);
 559     }
 560 }
 561
 562 void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr,
 563                                     uint32_t mem_value)
 564 {
 565     int array = (addr & 0x00800000) >> 23;
 566     int index = (addr & 0x00000300) >> 8;
 567     tlb_t * entry = &s->itlb[index];
 568
 569     if (array == 0) {
 570         /* ITLB Data Array 1 */
 571         if (entry->v) {
 572             /* Overwriting valid entry in utlb. */
 573             target_ulong address = entry->vpn << 10;
 574             tlb_flush_page(env_cpu(s), address);
 575         }
 576         entry->ppn = (mem_value & 0x1ffffc00) >> 10;
 577         entry->v   = (mem_value & 0x00000100) >> 8;
 578         entry->sz  = (mem_value & 0x00000080) >> 6 |
 579                      (mem_value & 0x00000010) >> 4;
 580         entry->pr  = (mem_value & 0x00000040) >> 5;
 581         entry->c   = (mem_value & 0x00000008) >> 3;
 582         entry->sh  = (mem_value & 0x00000002) >> 1;
 583     } else {
 584         /* ITLB Data Array 2 */
 585         entry->tc  = (mem_value & 0x00000008) >> 3;
 586         entry->sa  = (mem_value & 0x00000007);
 587     }
 588 }
 589
 590 uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s,
 591                                        hwaddr addr)
 592 {
 593     int index = (addr & 0x00003f00) >> 8;
 594     tlb_t * entry = &s->utlb[index];
 595
 596     increment_urc(s); /* per utlb access */
 597
 598     return (entry->vpn  << 10) |
 599            (entry->v    <<  8) |
 600            (entry->asid);
 601 }
 602
 603 void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
 604                                     uint32_t mem_value)
 605 {
 606     int associate = addr & 0x0000080;
 607     uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
 608     uint8_t d = (uint8_t)((mem_value & 0x00000200) >> 9);
 609     uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
 610     uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
 611     int use_asid = !(s->mmucr & MMUCR_SV) || !(s->sr & (1u << SR_MD));
 612
 613     if (associate) {
 614         int i;
 615         tlb_t * utlb_match_entry = NULL;
 616         int needs_tlb_flush = 0;
 617
 618         /* search UTLB */
 619         for (i = 0; i < UTLB_SIZE; i++) {
 620             tlb_t * entry = &s->utlb[i];
 621             if (!entry->v)
 622                 continue;
 623
 624             if (entry->vpn == vpn
 625                 && (!use_asid || entry->asid == asid || entry->sh)) {
 626                 if (utlb_match_entry) {
 627                     CPUState *cs = env_cpu(s);
 628
 629                     /* Multiple TLB Exception */
 630                     cs->exception_index = 0x140;
 631                     s->tea = addr;
 632                     break;
 633                 }
 634                 if (entry->v && !v)
 635                     needs_tlb_flush = 1;
 636                 entry->v = v;
 637                 entry->d = d;
 638                 utlb_match_entry = entry;
 639             }
 640             increment_urc(s); /* per utlb access */
 641         }
 642
 643         /* search ITLB */
 644         for (i = 0; i < ITLB_SIZE; i++) {
 645             tlb_t * entry = &s->itlb[i];
 646             if (entry->vpn == vpn
 647                 && (!use_asid || entry->asid == asid || entry->sh)) {
 648                 if (entry->v && !v)
 649                     needs_tlb_flush = 1;
 650                 if (utlb_match_entry)
 651                     *entry = *utlb_match_entry;
 652                 else
 653                     entry->v = v;
 654                 break;
 655             }
 656         }
 657
 658         if (needs_tlb_flush) {
 659             tlb_flush_page(env_cpu(s), vpn << 10);
 660         }
 661     } else {
 662         int index = (addr & 0x00003f00) >> 8;
 663         tlb_t * entry = &s->utlb[index];
 664         if (entry->v) {
 665             CPUState *cs = env_cpu(s);
 666
 667             /* Overwriting valid entry in utlb. */
 668             target_ulong address = entry->vpn << 10;
 669             tlb_flush_page(cs, address);
 670         }
 671         entry->asid = asid;
 672         entry->vpn = vpn;
 673         entry->d = d;
 674         entry->v = v;
 675         increment_urc(s);
 676     }
 677 }
 678
 679 uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s,
 680                                        hwaddr addr)
 681 {
 682     int array = (addr & 0x00800000) >> 23;
 683     int index = (addr & 0x00003f00) >> 8;
 684     tlb_t * entry = &s->utlb[index];
 685
 686     increment_urc(s); /* per utlb access */
 687
 688     if (array == 0) {
 689         /* ITLB Data Array 1 */
 690         return (entry->ppn << 10) |
 691                (entry->v   <<  8) |
 692                (entry->pr  <<  5) |
 693                ((entry->sz & 1) <<  6) |
 694                ((entry->sz & 2) <<  4) |
 695                (entry->c   <<  3) |
 696                (entry->d   <<  2) |
 697                (entry->sh  <<  1) |
 698                (entry->wt);
 699     } else {
 700         /* ITLB Data Array 2 */
 701         return (entry->tc << 1) |
 702                (entry->sa);
 703     }
 704 }
 705
 706 void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr,
 707                                     uint32_t mem_value)
 708 {
 709     int array = (addr & 0x00800000) >> 23;
 710     int index = (addr & 0x00003f00) >> 8;
 711     tlb_t * entry = &s->utlb[index];
 712
 713     increment_urc(s); /* per utlb access */
 714
 715     if (array == 0) {
 716         /* UTLB Data Array 1 */
 717         if (entry->v) {
 718             /* Overwriting valid entry in utlb. */
 719             target_ulong address = entry->vpn << 10;
 720             tlb_flush_page(env_cpu(s), address);
 721         }
 722         entry->ppn = (mem_value & 0x1ffffc00) >> 10;
 723         entry->v   = (mem_value & 0x00000100) >> 8;
 724         entry->sz  = (mem_value & 0x00000080) >> 6 |
 725                      (mem_value & 0x00000010) >> 4;
 726         entry->pr  = (mem_value & 0x00000060) >> 5;
 727         entry->c   = (mem_value & 0x00000008) >> 3;
 728         entry->d   = (mem_value & 0x00000004) >> 2;
 729         entry->sh  = (mem_value & 0x00000002) >> 1;
 730         entry->wt  = (mem_value & 0x00000001);
 731     } else {
 732         /* UTLB Data Array 2 */
 733         entry->tc = (mem_value & 0x00000008) >> 3;
 734         entry->sa = (mem_value & 0x00000007);
 735     }
 736 }
 737
 738 int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
 739 {
 740     int n;
 741     int use_asid = !(env->mmucr & MMUCR_SV) || !(env->sr & (1u << SR_MD));
 742
 743     /* check area */
 744     if (env->sr & (1u << SR_MD)) {
 745         /* For privileged mode, P2 and P4 area is not cacheable. */
 746         if ((0xA0000000 <= addr && addr < 0xC0000000) || 0xE0000000 <= addr)
 747             return 0;
 748     } else {
 749         /* For user mode, only U0 area is cacheable. */
 750         if (0x80000000 <= addr)
 751             return 0;
 752     }
 753
 754     /*
 755      * TODO : Evaluate CCR and check if the cache is on or off.
 756      *        Now CCR is not in CPUSH4State, but in SH7750State.
 757      *        When you move the ccr into CPUSH4State, the code will be
 758      *        as follows.
 759      */
 760 #if 0
 761     /* check if operand cache is enabled or not. */
 762     if (!(env->ccr & 1))
 763         return 0;
 764 #endif
 765
 766     /* if MMU is off, no check for TLB. */
 767     if (env->mmucr & MMUCR_AT)
 768         return 1;
 769
 770     /* check TLB */
 771     n = find_tlb_entry(env, addr, env->itlb, ITLB_SIZE, use_asid);
 772     if (n >= 0)
 773         return env->itlb[n].c;
 774
 775     n = find_tlb_entry(env, addr, env->utlb, UTLB_SIZE, use_asid);
 776     if (n >= 0)
 777         return env->utlb[n].c;
 778
 779     return 0;
 780 }
 781
 782 #endif
 783
 784 bool superh_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 785 {
 786     if (interrupt_request & CPU_INTERRUPT_HARD) {
 787         SuperHCPU *cpu = SUPERH_CPU(cs);
 788         CPUSH4State *env = &cpu->env;
 789
 790         /* Delay slots are indivisible, ignore interrupts */
 791         if (env->flags & DELAY_SLOT_MASK) {
 792             return false;
 793         } else {
 794             superh_cpu_do_interrupt(cs);
 795             return true;
 796         }
 797     }
 798     return false;
 799 }
 800
 801 bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 802                          MMUAccessType access_type, int mmu_idx,
 803                          bool probe, uintptr_t retaddr)
 804 {
 805     SuperHCPU *cpu = SUPERH_CPU(cs);
 806     CPUSH4State *env = &cpu->env;
 807     int ret;
 808
 809 #ifdef CONFIG_USER_ONLY
 810     ret = (access_type == MMU_DATA_STORE ? MMU_DTLB_VIOLATION_WRITE :
 811            access_type == MMU_INST_FETCH ? MMU_ITLB_VIOLATION :
 812            MMU_DTLB_VIOLATION_READ);
 813 #else
 814     target_ulong physical;
 815     int prot, sh_access_type;
 816
 817     sh_access_type = ACCESS_INT;
 818     ret = get_physical_address(env, &physical, &prot, address,
 819                                access_type, sh_access_type);
 820
 821     if (ret == MMU_OK) {
 822         address &= TARGET_PAGE_MASK;
 823         physical &= TARGET_PAGE_MASK;
 824         tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE);
 825         return true;
 826     }
 827     if (probe) {
 828         return false;
 829     }
 830
 831     if (ret != MMU_DTLB_MULTIPLE && ret != MMU_ITLB_MULTIPLE) {
 832         env->pteh = (env->pteh & PTEH_ASID_MASK) | (address & PTEH_VPN_MASK);
 833     }
 834 #endif
 835
 836     env->tea = address;
 837     switch (ret) {
 838     case MMU_ITLB_MISS:
 839     case MMU_DTLB_MISS_READ:
 840         cs->exception_index = 0x040;
 841         break;
 842     case MMU_DTLB_MULTIPLE:
 843     case MMU_ITLB_MULTIPLE:
 844         cs->exception_index = 0x140;
 845         break;
 846     case MMU_ITLB_VIOLATION:
 847         cs->exception_index = 0x0a0;
 848         break;
 849     case MMU_DTLB_MISS_WRITE:
 850         cs->exception_index = 0x060;
 851         break;
 852     case MMU_DTLB_INITIAL_WRITE:
 853         cs->exception_index = 0x080;
 854         break;
 855     case MMU_DTLB_VIOLATION_READ:
 856         cs->exception_index = 0x0a0;
 857         break;
 858     case MMU_DTLB_VIOLATION_WRITE:
 859         cs->exception_index = 0x0c0;
 860         break;
 861     case MMU_IADDR_ERROR:
 862     case MMU_DADDR_ERROR_READ:
 863         cs->exception_index = 0x0e0;
 864         break;
 865     case MMU_DADDR_ERROR_WRITE:
 866         cs->exception_index = 0x100;
 867         break;
 868     default:
 869         cpu_abort(cs, "Unhandled MMU fault");
 870     }
 871     cpu_loop_exit_restore(cs, retaddr);
 872 }