hw/arm/allwinner-a10.c

   1 /*
   2  * Allwinner A10 SoC emulation
   3  *
   4  * Copyright (C) 2013 Li Guang
   5  * Written by Li Guang <lig.fnst@cn.fujitsu.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  15  * for more details.
  16  */
  17
  18 #include "qemu/osdep.h"
  19 #include "qapi/error.h"
  20 #include "qemu/module.h"
  21 #include "cpu.h"
  22 #include "hw/sysbus.h"
  23 #include "hw/arm/allwinner-a10.h"
  24 #include "hw/misc/unimp.h"
  25
  26 static void aw_a10_init(Object *obj)
  27 {
  28     AwA10State *s = AW_A10(obj);
  29
  30     object_initialize_child(obj, "cpu", &s->cpu, sizeof(s->cpu),
  31                             "cortex-a8-" TYPE_ARM_CPU, &error_abort, NULL);
  32
  33     sysbus_init_child_obj(obj, "intc", &s->intc, sizeof(s->intc),
  34                           TYPE_AW_A10_PIC);
  35
  36     sysbus_init_child_obj(obj, "timer", &s->timer, sizeof(s->timer),
  37                           TYPE_AW_A10_PIT);
  38
  39     sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac), TYPE_AW_EMAC);
  40
  41     sysbus_init_child_obj(obj, "sata", &s->sata, sizeof(s->sata),
  42                           TYPE_ALLWINNER_AHCI);
  43 }
  44
  45 static void aw_a10_realize(DeviceState *dev, Error **errp)
  46 {
  47     AwA10State *s = AW_A10(dev);
  48     SysBusDevice *sysbusdev;
  49     uint8_t i;
  50     qemu_irq fiq, irq;
  51     Error *err = NULL;
  52
  53     object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
  54     if (err != NULL) {
  55         error_propagate(errp, err);
  56         return;
  57     }
  58     irq = qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ);
  59     fiq = qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ);
  60
  61     object_property_set_bool(OBJECT(&s->intc), true, "realized", &err);
  62     if (err != NULL) {
  63         error_propagate(errp, err);
  64         return;
  65     }
  66     sysbusdev = SYS_BUS_DEVICE(&s->intc);
  67     sysbus_mmio_map(sysbusdev, 0, AW_A10_PIC_REG_BASE);
  68     sysbus_connect_irq(sysbusdev, 0, irq);
  69     sysbus_connect_irq(sysbusdev, 1, fiq);
  70     for (i = 0; i < AW_A10_PIC_INT_NR; i++) {
  71         s->irq[i] = qdev_get_gpio_in(DEVICE(&s->intc), i);
  72     }
  73
  74     object_property_set_bool(OBJECT(&s->timer), true, "realized", &err);
  75     if (err != NULL) {
  76         error_propagate(errp, err);
  77         return;
  78     }
  79     sysbusdev = SYS_BUS_DEVICE(&s->timer);
  80     sysbus_mmio_map(sysbusdev, 0, AW_A10_PIT_REG_BASE);
  81     sysbus_connect_irq(sysbusdev, 0, s->irq[22]);
  82     sysbus_connect_irq(sysbusdev, 1, s->irq[23]);
  83     sysbus_connect_irq(sysbusdev, 2, s->irq[24]);
  84     sysbus_connect_irq(sysbusdev, 3, s->irq[25]);
  85     sysbus_connect_irq(sysbusdev, 4, s->irq[67]);
  86     sysbus_connect_irq(sysbusdev, 5, s->irq[68]);
  87
  88     memory_region_init_ram(&s->sram_a, OBJECT(dev), "sram A", 48 * KiB,
  89                            &error_fatal);
  90     memory_region_add_subregion(get_system_memory(), 0x00000000, &s->sram_a);
  91     create_unimplemented_device("a10-sram-ctrl", 0x01c00000, 4 * KiB);
  92
  93     /* FIXME use qdev NIC properties instead of nd_table[] */
  94     if (nd_table[0].used) {
  95         qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC);
  96         qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
  97     }
  98     object_property_set_bool(OBJECT(&s->emac), true, "realized", &err);
  99     if (err != NULL) {
 100         error_propagate(errp, err);
 101         return;
 102     }
 103     sysbusdev = SYS_BUS_DEVICE(&s->emac);
 104     sysbus_mmio_map(sysbusdev, 0, AW_A10_EMAC_BASE);
 105     sysbus_connect_irq(sysbusdev, 0, s->irq[55]);
 106
 107     object_property_set_bool(OBJECT(&s->sata), true, "realized", &err);
 108     if (err) {
 109         error_propagate(errp, err);
 110         return;
 111     }
 112     sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, AW_A10_SATA_BASE);
 113     sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, s->irq[56]);
 114
 115     /* FIXME use a qdev chardev prop instead of serial_hd() */
 116     serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2, s->irq[1],
 117                    115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
 118 }
 119
 120 static void aw_a10_class_init(ObjectClass *oc, void *data)
 121 {
 122     DeviceClass *dc = DEVICE_CLASS(oc);
 123
 124     dc->realize = aw_a10_realize;
 125     /* Reason: Uses serial_hds and nd_table in realize function */
 126     dc->user_creatable = false;
 127 }
 128
 129 static const TypeInfo aw_a10_type_info = {
 130     .name = TYPE_AW_A10,
 131     .parent = TYPE_DEVICE,
 132     .instance_size = sizeof(AwA10State),
 133     .instance_init = aw_a10_init,
 134     .class_init = aw_a10_class_init,
 135 };
 136
 137 static void aw_a10_register_types(void)
 138 {
 139     type_register_static(&aw_a10_type_info);
 140 }
 141
 142 type_init(aw_a10_register_types)