2 * PowerPC gdb server stub
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 * Copyright (c) 2013 SUSE LINUX Products GmbH
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
22 #include "exec/gdbstub.h"
23 #include "gdbstub/helpers.h"
26 static int ppc_gdb_register_len_apple(int n
)
37 case 64 + 32: /* nip */
38 case 65 + 32: /* msr */
39 case 67 + 32: /* lr */
40 case 68 + 32: /* ctr */
41 case 70 + 32: /* fpscr */
43 case 66 + 32: /* cr */
44 case 69 + 32: /* xer */
51 static int ppc_gdb_register_len(int n
)
56 return sizeof(target_ulong
);
70 return sizeof(target_ulong
);
77 * We need to present the registers to gdb in the "current" memory
78 * ordering. For user-only mode we get this for free;
79 * TARGET_BIG_ENDIAN is set to the proper ordering for the
80 * binary, and cannot be changed. For system mode,
81 * TARGET_BIG_ENDIAN is always set, and we must check the current
82 * mode of the chip to see if we're running in little-endian.
84 void ppc_maybe_bswap_register(CPUPPCState
*env
, uint8_t *mem_buf
, int len
)
86 #ifndef CONFIG_USER_ONLY
87 if (!FIELD_EX64(env
->msr
, MSR
, LE
)) {
89 } else if (len
== 4) {
90 bswap32s((uint32_t *)mem_buf
);
91 } else if (len
== 8) {
92 bswap64s((uint64_t *)mem_buf
);
93 } else if (len
== 16) {
94 bswap128s((Int128
*)mem_buf
);
96 g_assert_not_reached();
102 * Old gdb always expects FP registers. Newer (xml-aware) gdb only
103 * expects whatever the target description contains. Due to a
104 * historical mishap the FP registers appear in between core integer
105 * regs and PC, MSR, CR, and so forth. We hack round this by giving
106 * the FP regs zero size when talking to a newer gdb.
109 int ppc_cpu_gdb_read_register(CPUState
*cs
, GByteArray
*buf
, int n
)
111 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
112 CPUPPCState
*env
= &cpu
->env
;
114 int r
= ppc_gdb_register_len(n
);
122 gdb_get_regl(buf
, env
->gpr
[n
]);
126 gdb_get_regl(buf
, env
->nip
);
129 gdb_get_regl(buf
, env
->msr
);
133 uint32_t cr
= ppc_get_cr(env
);
134 gdb_get_reg32(buf
, cr
);
138 gdb_get_regl(buf
, env
->lr
);
141 gdb_get_regl(buf
, env
->ctr
);
144 gdb_get_reg32(buf
, cpu_read_xer(env
));
148 mem_buf
= buf
->data
+ buf
->len
- r
;
149 ppc_maybe_bswap_register(env
, mem_buf
, r
);
153 int ppc_cpu_gdb_read_register_apple(CPUState
*cs
, GByteArray
*buf
, int n
)
155 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
156 CPUPPCState
*env
= &cpu
->env
;
158 int r
= ppc_gdb_register_len_apple(n
);
166 gdb_get_reg64(buf
, env
->gpr
[n
]);
169 gdb_get_reg64(buf
, *cpu_fpr_ptr(env
, n
- 32));
172 gdb_get_reg64(buf
, n
- 64);
173 gdb_get_reg64(buf
, 0);
177 gdb_get_reg64(buf
, env
->nip
);
180 gdb_get_reg64(buf
, env
->msr
);
184 uint32_t cr
= ppc_get_cr(env
);
185 gdb_get_reg32(buf
, cr
);
189 gdb_get_reg64(buf
, env
->lr
);
192 gdb_get_reg64(buf
, env
->ctr
);
195 gdb_get_reg32(buf
, cpu_read_xer(env
));
198 gdb_get_reg64(buf
, env
->fpscr
);
202 mem_buf
= buf
->data
+ buf
->len
- r
;
203 ppc_maybe_bswap_register(env
, mem_buf
, r
);
207 int ppc_cpu_gdb_write_register(CPUState
*cs
, uint8_t *mem_buf
, int n
)
209 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
210 CPUPPCState
*env
= &cpu
->env
;
211 int r
= ppc_gdb_register_len(n
);
216 ppc_maybe_bswap_register(env
, mem_buf
, r
);
219 env
->gpr
[n
] = ldtul_p(mem_buf
);
222 *cpu_fpr_ptr(env
, n
- 32) = ldq_p(mem_buf
);
226 env
->nip
= ldtul_p(mem_buf
);
229 ppc_store_msr(env
, ldtul_p(mem_buf
));
233 uint32_t cr
= ldl_p(mem_buf
);
238 env
->lr
= ldtul_p(mem_buf
);
241 env
->ctr
= ldtul_p(mem_buf
);
244 cpu_write_xer(env
, ldl_p(mem_buf
));
248 ppc_store_fpscr(env
, ldtul_p(mem_buf
));
254 int ppc_cpu_gdb_write_register_apple(CPUState
*cs
, uint8_t *mem_buf
, int n
)
256 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
257 CPUPPCState
*env
= &cpu
->env
;
258 int r
= ppc_gdb_register_len_apple(n
);
263 ppc_maybe_bswap_register(env
, mem_buf
, r
);
266 env
->gpr
[n
] = ldq_p(mem_buf
);
269 *cpu_fpr_ptr(env
, n
- 32) = ldq_p(mem_buf
);
273 env
->nip
= ldq_p(mem_buf
);
276 ppc_store_msr(env
, ldq_p(mem_buf
));
280 uint32_t cr
= ldl_p(mem_buf
);
285 env
->lr
= ldq_p(mem_buf
);
288 env
->ctr
= ldq_p(mem_buf
);
291 cpu_write_xer(env
, ldl_p(mem_buf
));
295 ppc_store_fpscr(env
, ldq_p(mem_buf
));
302 #ifndef CONFIG_USER_ONLY
303 static void gdb_gen_spr_feature(CPUState
*cs
)
305 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cs
);
306 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
307 CPUPPCState
*env
= &cpu
->env
;
308 GDBFeatureBuilder builder
;
309 unsigned int num_regs
= 0;
312 if (pcc
->gdb_spr
.xml
) {
316 gdb_feature_builder_init(&builder
, &pcc
->gdb_spr
,
317 "org.qemu.power.spr", "power-spr.xml",
320 for (i
= 0; i
< ARRAY_SIZE(env
->spr_cb
); i
++) {
321 ppc_spr_t
*spr
= &env
->spr_cb
[i
];
328 * GDB identifies registers based on the order they are
329 * presented in the XML. These ids will not match QEMU's
330 * representation (which follows the PowerISA).
332 * Store the position of the current register description so
333 * we can make the correspondence later.
335 spr
->gdb_id
= num_regs
;
338 gdb_feature_builder_append_reg(&builder
, g_ascii_strdown(spr
->name
, -1),
339 TARGET_LONG_BITS
, num_regs
,
343 gdb_feature_builder_end(&builder
);
347 #if !defined(CONFIG_USER_ONLY)
348 static int gdb_find_spr_idx(CPUPPCState
*env
, int n
)
352 for (i
= 0; i
< ARRAY_SIZE(env
->spr_cb
); i
++) {
353 ppc_spr_t
*spr
= &env
->spr_cb
[i
];
355 if (spr
->name
&& spr
->gdb_id
== n
) {
362 static int gdb_get_spr_reg(CPUState
*cs
, GByteArray
*buf
, int n
)
364 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
365 CPUPPCState
*env
= &cpu
->env
;
369 reg
= gdb_find_spr_idx(env
, n
);
374 len
= TARGET_LONG_SIZE
;
376 /* Handle those SPRs that are not part of the env->spr[] array */
379 #if defined(TARGET_PPC64)
385 val
= cpu_ppc_load_hdecr(env
);
388 val
= cpu_ppc_load_tbl(env
);
391 val
= cpu_ppc_load_tbu(env
);
394 val
= cpu_ppc_load_decr(env
);
399 gdb_get_regl(buf
, val
);
401 ppc_maybe_bswap_register(env
, gdb_get_reg_ptr(buf
, len
), len
);
405 static int gdb_set_spr_reg(CPUState
*cs
, uint8_t *mem_buf
, int n
)
407 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
408 CPUPPCState
*env
= &cpu
->env
;
412 reg
= gdb_find_spr_idx(env
, n
);
417 len
= TARGET_LONG_SIZE
;
418 ppc_maybe_bswap_register(env
, mem_buf
, len
);
420 /* Handle those SPRs that are not part of the env->spr[] array */
421 target_ulong val
= ldn_p(mem_buf
, len
);
423 #if defined(TARGET_PPC64)
436 static int gdb_get_float_reg(CPUState
*cs
, GByteArray
*buf
, int n
)
438 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
439 CPUPPCState
*env
= &cpu
->env
;
442 gdb_get_reg64(buf
, *cpu_fpr_ptr(env
, n
));
443 mem_buf
= gdb_get_reg_ptr(buf
, 8);
444 ppc_maybe_bswap_register(env
, mem_buf
, 8);
448 gdb_get_reg32(buf
, env
->fpscr
);
449 mem_buf
= gdb_get_reg_ptr(buf
, 4);
450 ppc_maybe_bswap_register(env
, mem_buf
, 4);
456 static int gdb_set_float_reg(CPUState
*cs
, uint8_t *mem_buf
, int n
)
458 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
459 CPUPPCState
*env
= &cpu
->env
;
462 ppc_maybe_bswap_register(env
, mem_buf
, 8);
463 *cpu_fpr_ptr(env
, n
) = ldq_p(mem_buf
);
467 ppc_maybe_bswap_register(env
, mem_buf
, 4);
468 ppc_store_fpscr(env
, ldl_p(mem_buf
));
474 static int gdb_get_avr_reg(CPUState
*cs
, GByteArray
*buf
, int n
)
476 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
477 CPUPPCState
*env
= &cpu
->env
;
481 ppc_avr_t
*avr
= cpu_avr_ptr(env
, n
);
482 gdb_get_reg128(buf
, avr
->VsrD(0), avr
->VsrD(1));
483 mem_buf
= gdb_get_reg_ptr(buf
, 16);
484 ppc_maybe_bswap_register(env
, mem_buf
, 16);
488 gdb_get_reg32(buf
, ppc_get_vscr(env
));
489 mem_buf
= gdb_get_reg_ptr(buf
, 4);
490 ppc_maybe_bswap_register(env
, mem_buf
, 4);
494 gdb_get_reg32(buf
, (uint32_t)env
->spr
[SPR_VRSAVE
]);
495 mem_buf
= gdb_get_reg_ptr(buf
, 4);
496 ppc_maybe_bswap_register(env
, mem_buf
, 4);
502 static int gdb_set_avr_reg(CPUState
*cs
, uint8_t *mem_buf
, int n
)
504 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
505 CPUPPCState
*env
= &cpu
->env
;
508 ppc_avr_t
*avr
= cpu_avr_ptr(env
, n
);
509 ppc_maybe_bswap_register(env
, mem_buf
, 16);
510 avr
->VsrD(0) = ldq_p(mem_buf
);
511 avr
->VsrD(1) = ldq_p(mem_buf
+ 8);
515 ppc_maybe_bswap_register(env
, mem_buf
, 4);
516 ppc_store_vscr(env
, ldl_p(mem_buf
));
520 ppc_maybe_bswap_register(env
, mem_buf
, 4);
521 env
->spr
[SPR_VRSAVE
] = (target_ulong
)ldl_p(mem_buf
);
527 static int gdb_get_spe_reg(CPUState
*cs
, GByteArray
*buf
, int n
)
529 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
530 CPUPPCState
*env
= &cpu
->env
;
533 #if defined(TARGET_PPC64)
534 gdb_get_reg32(buf
, env
->gpr
[n
] >> 32);
535 ppc_maybe_bswap_register(env
, gdb_get_reg_ptr(buf
, 4), 4);
537 gdb_get_reg32(buf
, env
->gprh
[n
]);
542 gdb_get_reg64(buf
, env
->spe_acc
);
543 ppc_maybe_bswap_register(env
, gdb_get_reg_ptr(buf
, 8), 8);
547 gdb_get_reg32(buf
, env
->spe_fscr
);
548 ppc_maybe_bswap_register(env
, gdb_get_reg_ptr(buf
, 4), 4);
554 static int gdb_set_spe_reg(CPUState
*cs
, uint8_t *mem_buf
, int n
)
556 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
557 CPUPPCState
*env
= &cpu
->env
;
560 #if defined(TARGET_PPC64)
561 target_ulong lo
= (uint32_t)env
->gpr
[n
];
564 ppc_maybe_bswap_register(env
, mem_buf
, 4);
566 hi
= (target_ulong
)ldl_p(mem_buf
) << 32;
567 env
->gpr
[n
] = lo
| hi
;
569 env
->gprh
[n
] = ldl_p(mem_buf
);
574 ppc_maybe_bswap_register(env
, mem_buf
, 8);
575 env
->spe_acc
= ldq_p(mem_buf
);
579 ppc_maybe_bswap_register(env
, mem_buf
, 4);
580 env
->spe_fscr
= ldl_p(mem_buf
);
586 static int gdb_get_vsx_reg(CPUState
*cs
, GByteArray
*buf
, int n
)
588 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
589 CPUPPCState
*env
= &cpu
->env
;
592 gdb_get_reg64(buf
, *cpu_vsrl_ptr(env
, n
));
593 ppc_maybe_bswap_register(env
, gdb_get_reg_ptr(buf
, 8), 8);
599 static int gdb_set_vsx_reg(CPUState
*cs
, uint8_t *mem_buf
, int n
)
601 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
602 CPUPPCState
*env
= &cpu
->env
;
605 ppc_maybe_bswap_register(env
, mem_buf
, 8);
606 *cpu_vsrl_ptr(env
, n
) = ldq_p(mem_buf
);
612 const gchar
*ppc_gdb_arch_name(CPUState
*cs
)
614 #if defined(TARGET_PPC64)
615 return "powerpc:common64";
617 return "powerpc:common";
621 void ppc_gdb_init(CPUState
*cs
, PowerPCCPUClass
*pcc
)
623 if (pcc
->insns_flags
& PPC_FLOAT
) {
624 gdb_register_coprocessor(cs
, gdb_get_float_reg
, gdb_set_float_reg
,
625 gdb_find_static_feature("power-fpu.xml"), 0);
627 if (pcc
->insns_flags
& PPC_ALTIVEC
) {
628 gdb_register_coprocessor(cs
, gdb_get_avr_reg
, gdb_set_avr_reg
,
629 gdb_find_static_feature("power-altivec.xml"),
632 if (pcc
->insns_flags
& PPC_SPE
) {
633 gdb_register_coprocessor(cs
, gdb_get_spe_reg
, gdb_set_spe_reg
,
634 gdb_find_static_feature("power-spe.xml"), 0);
636 if (pcc
->insns_flags2
& PPC2_VSX
) {
637 gdb_register_coprocessor(cs
, gdb_get_vsx_reg
, gdb_set_vsx_reg
,
638 gdb_find_static_feature("power-vsx.xml"), 0);
640 #ifndef CONFIG_USER_ONLY
641 gdb_gen_spr_feature(cs
);
642 gdb_register_coprocessor(cs
, gdb_get_spr_reg
, gdb_set_spr_reg
,