2 * Xilinx Zynq MPSoC emulation
4 * Copyright (C) 2015 Xilinx Inc
5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 #include "hw/arm/xlnx-zynqmp.h"
19 #include "hw/intc/arm_gic_common.h"
20 #include "exec/address-spaces.h"
22 #define GIC_NUM_SPI_INTR 160
24 #define ARM_PHYS_TIMER_PPI 30
25 #define ARM_VIRT_TIMER_PPI 27
27 #define GIC_BASE_ADDR 0xf9000000
28 #define GIC_DIST_ADDR 0xf9010000
29 #define GIC_CPU_ADDR 0xf9020000
32 #define SATA_ADDR 0xFD0C0000
33 #define SATA_NUM_PORTS 2
35 static const uint64_t gem_addr
[XLNX_ZYNQMP_NUM_GEMS
] = {
36 0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
39 static const int gem_intr
[XLNX_ZYNQMP_NUM_GEMS
] = {
43 static const uint64_t uart_addr
[XLNX_ZYNQMP_NUM_UARTS
] = {
44 0xFF000000, 0xFF010000,
47 static const int uart_intr
[XLNX_ZYNQMP_NUM_UARTS
] = {
51 static const uint64_t sdhci_addr
[XLNX_ZYNQMP_NUM_SDHCI
] = {
52 0xFF160000, 0xFF170000,
55 static const int sdhci_intr
[XLNX_ZYNQMP_NUM_SDHCI
] = {
59 typedef struct XlnxZynqMPGICRegion
{
62 } XlnxZynqMPGICRegion
;
64 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions
[] = {
65 { .region_index
= 0, .address
= GIC_DIST_ADDR
, },
66 { .region_index
= 1, .address
= GIC_CPU_ADDR
, },
69 static inline int arm_gic_ppi_index(int cpu_nr
, int ppi_index
)
71 return GIC_NUM_SPI_INTR
+ cpu_nr
* GIC_INTERNAL
+ ppi_index
;
74 static void xlnx_zynqmp_init(Object
*obj
)
76 XlnxZynqMPState
*s
= XLNX_ZYNQMP(obj
);
79 for (i
= 0; i
< XLNX_ZYNQMP_NUM_APU_CPUS
; i
++) {
80 object_initialize(&s
->apu_cpu
[i
], sizeof(s
->apu_cpu
[i
]),
81 "cortex-a53-" TYPE_ARM_CPU
);
82 object_property_add_child(obj
, "apu-cpu[*]", OBJECT(&s
->apu_cpu
[i
]),
86 for (i
= 0; i
< XLNX_ZYNQMP_NUM_RPU_CPUS
; i
++) {
87 object_initialize(&s
->rpu_cpu
[i
], sizeof(s
->rpu_cpu
[i
]),
88 "cortex-r5-" TYPE_ARM_CPU
);
89 object_property_add_child(obj
, "rpu-cpu[*]", OBJECT(&s
->rpu_cpu
[i
]),
93 object_property_add_link(obj
, "ddr-ram", TYPE_MEMORY_REGION
,
94 (Object
**)&s
->ddr_ram
,
95 qdev_prop_allow_set_link_before_realize
,
96 OBJ_PROP_LINK_UNREF_ON_RELEASE
, &error_abort
);
98 object_initialize(&s
->gic
, sizeof(s
->gic
), TYPE_ARM_GIC
);
99 qdev_set_parent_bus(DEVICE(&s
->gic
), sysbus_get_default());
101 for (i
= 0; i
< XLNX_ZYNQMP_NUM_GEMS
; i
++) {
102 object_initialize(&s
->gem
[i
], sizeof(s
->gem
[i
]), TYPE_CADENCE_GEM
);
103 qdev_set_parent_bus(DEVICE(&s
->gem
[i
]), sysbus_get_default());
106 for (i
= 0; i
< XLNX_ZYNQMP_NUM_UARTS
; i
++) {
107 object_initialize(&s
->uart
[i
], sizeof(s
->uart
[i
]), TYPE_CADENCE_UART
);
108 qdev_set_parent_bus(DEVICE(&s
->uart
[i
]), sysbus_get_default());
111 object_initialize(&s
->sata
, sizeof(s
->sata
), TYPE_SYSBUS_AHCI
);
112 qdev_set_parent_bus(DEVICE(&s
->sata
), sysbus_get_default());
114 for (i
= 0; i
< XLNX_ZYNQMP_NUM_SDHCI
; i
++) {
115 object_initialize(&s
->sdhci
[i
], sizeof(s
->sdhci
[i
]),
117 qdev_set_parent_bus(DEVICE(&s
->sdhci
[i
]),
118 sysbus_get_default());
122 static void xlnx_zynqmp_realize(DeviceState
*dev
, Error
**errp
)
124 XlnxZynqMPState
*s
= XLNX_ZYNQMP(dev
);
125 MemoryRegion
*system_memory
= get_system_memory();
128 const char *boot_cpu
= s
->boot_cpu
? s
->boot_cpu
: "apu-cpu[0]";
129 ram_addr_t ddr_low_size
, ddr_high_size
;
130 qemu_irq gic_spi
[GIC_NUM_SPI_INTR
];
133 ram_size
= memory_region_size(s
->ddr_ram
);
135 /* Create the DDR Memory Regions. User friendly checks should happen at
138 if (ram_size
> XLNX_ZYNQMP_MAX_LOW_RAM_SIZE
) {
139 /* The RAM size is above the maximum available for the low DDR.
140 * Create the high DDR memory region as well.
142 assert(ram_size
<= XLNX_ZYNQMP_MAX_RAM_SIZE
);
143 ddr_low_size
= XLNX_ZYNQMP_MAX_LOW_RAM_SIZE
;
144 ddr_high_size
= ram_size
- XLNX_ZYNQMP_MAX_LOW_RAM_SIZE
;
146 memory_region_init_alias(&s
->ddr_ram_high
, NULL
,
147 "ddr-ram-high", s
->ddr_ram
,
148 ddr_low_size
, ddr_high_size
);
149 memory_region_add_subregion(get_system_memory(),
150 XLNX_ZYNQMP_HIGH_RAM_START
,
153 /* RAM must be non-zero */
155 ddr_low_size
= ram_size
;
158 memory_region_init_alias(&s
->ddr_ram_low
, NULL
,
159 "ddr-ram-low", s
->ddr_ram
,
161 memory_region_add_subregion(get_system_memory(), 0, &s
->ddr_ram_low
);
163 /* Create the four OCM banks */
164 for (i
= 0; i
< XLNX_ZYNQMP_NUM_OCM_BANKS
; i
++) {
165 char *ocm_name
= g_strdup_printf("zynqmp.ocm_ram_bank_%d", i
);
167 memory_region_init_ram(&s
->ocm_ram
[i
], NULL
, ocm_name
,
168 XLNX_ZYNQMP_OCM_RAM_SIZE
, &error_fatal
);
169 vmstate_register_ram_global(&s
->ocm_ram
[i
]);
170 memory_region_add_subregion(get_system_memory(),
171 XLNX_ZYNQMP_OCM_RAM_0_ADDRESS
+
172 i
* XLNX_ZYNQMP_OCM_RAM_SIZE
,
178 qdev_prop_set_uint32(DEVICE(&s
->gic
), "num-irq", GIC_NUM_SPI_INTR
+ 32);
179 qdev_prop_set_uint32(DEVICE(&s
->gic
), "revision", 2);
180 qdev_prop_set_uint32(DEVICE(&s
->gic
), "num-cpu", XLNX_ZYNQMP_NUM_APU_CPUS
);
181 object_property_set_bool(OBJECT(&s
->gic
), true, "realized", &err
);
183 error_propagate(errp
, err
);
186 assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions
) == XLNX_ZYNQMP_GIC_REGIONS
);
187 for (i
= 0; i
< XLNX_ZYNQMP_GIC_REGIONS
; i
++) {
188 SysBusDevice
*gic
= SYS_BUS_DEVICE(&s
->gic
);
189 const XlnxZynqMPGICRegion
*r
= &xlnx_zynqmp_gic_regions
[i
];
190 MemoryRegion
*mr
= sysbus_mmio_get_region(gic
, r
->region_index
);
191 uint32_t addr
= r
->address
;
194 sysbus_mmio_map(gic
, r
->region_index
, addr
);
196 for (j
= 0; j
< XLNX_ZYNQMP_GIC_ALIASES
; j
++) {
197 MemoryRegion
*alias
= &s
->gic_mr
[i
][j
];
199 addr
+= XLNX_ZYNQMP_GIC_REGION_SIZE
;
200 memory_region_init_alias(alias
, OBJECT(s
), "zynqmp-gic-alias", mr
,
201 0, XLNX_ZYNQMP_GIC_REGION_SIZE
);
202 memory_region_add_subregion(system_memory
, addr
, alias
);
206 for (i
= 0; i
< XLNX_ZYNQMP_NUM_APU_CPUS
; i
++) {
210 object_property_set_int(OBJECT(&s
->apu_cpu
[i
]), QEMU_PSCI_CONDUIT_SMC
,
211 "psci-conduit", &error_abort
);
213 name
= object_get_canonical_path_component(OBJECT(&s
->apu_cpu
[i
]));
214 if (strcmp(name
, boot_cpu
)) {
215 /* Secondary CPUs start in PSCI powered-down state */
216 object_property_set_bool(OBJECT(&s
->apu_cpu
[i
]), true,
217 "start-powered-off", &error_abort
);
219 s
->boot_cpu_ptr
= &s
->apu_cpu
[i
];
223 object_property_set_int(OBJECT(&s
->apu_cpu
[i
]), GIC_BASE_ADDR
,
224 "reset-cbar", &error_abort
);
225 object_property_set_bool(OBJECT(&s
->apu_cpu
[i
]), true, "realized",
228 error_propagate(errp
, err
);
232 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gic
), i
,
233 qdev_get_gpio_in(DEVICE(&s
->apu_cpu
[i
]),
235 irq
= qdev_get_gpio_in(DEVICE(&s
->gic
),
236 arm_gic_ppi_index(i
, ARM_PHYS_TIMER_PPI
));
237 qdev_connect_gpio_out(DEVICE(&s
->apu_cpu
[i
]), 0, irq
);
238 irq
= qdev_get_gpio_in(DEVICE(&s
->gic
),
239 arm_gic_ppi_index(i
, ARM_VIRT_TIMER_PPI
));
240 qdev_connect_gpio_out(DEVICE(&s
->apu_cpu
[i
]), 1, irq
);
243 for (i
= 0; i
< XLNX_ZYNQMP_NUM_RPU_CPUS
; i
++) {
246 name
= object_get_canonical_path_component(OBJECT(&s
->rpu_cpu
[i
]));
247 if (strcmp(name
, boot_cpu
)) {
248 /* Secondary CPUs start in PSCI powered-down state */
249 object_property_set_bool(OBJECT(&s
->rpu_cpu
[i
]), true,
250 "start-powered-off", &error_abort
);
252 s
->boot_cpu_ptr
= &s
->rpu_cpu
[i
];
256 object_property_set_bool(OBJECT(&s
->rpu_cpu
[i
]), true, "reset-hivecs",
258 object_property_set_bool(OBJECT(&s
->rpu_cpu
[i
]), true, "realized",
261 error_propagate(errp
, err
);
266 if (!s
->boot_cpu_ptr
) {
267 error_setg(errp
, "ZynqMP Boot cpu %s not found", boot_cpu
);
271 for (i
= 0; i
< GIC_NUM_SPI_INTR
; i
++) {
272 gic_spi
[i
] = qdev_get_gpio_in(DEVICE(&s
->gic
), i
);
275 for (i
= 0; i
< XLNX_ZYNQMP_NUM_GEMS
; i
++) {
276 NICInfo
*nd
= &nd_table
[i
];
279 qemu_check_nic_model(nd
, TYPE_CADENCE_GEM
);
280 qdev_set_nic_properties(DEVICE(&s
->gem
[i
]), nd
);
282 object_property_set_bool(OBJECT(&s
->gem
[i
]), true, "realized", &err
);
284 error_propagate(errp
, err
);
287 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->gem
[i
]), 0, gem_addr
[i
]);
288 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gem
[i
]), 0,
289 gic_spi
[gem_intr
[i
]]);
292 for (i
= 0; i
< XLNX_ZYNQMP_NUM_UARTS
; i
++) {
293 object_property_set_bool(OBJECT(&s
->uart
[i
]), true, "realized", &err
);
295 error_propagate(errp
, err
);
298 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->uart
[i
]), 0, uart_addr
[i
]);
299 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->uart
[i
]), 0,
300 gic_spi
[uart_intr
[i
]]);
303 object_property_set_int(OBJECT(&s
->sata
), SATA_NUM_PORTS
, "num-ports",
305 object_property_set_bool(OBJECT(&s
->sata
), true, "realized", &err
);
307 error_propagate(errp
, err
);
311 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->sata
), 0, SATA_ADDR
);
312 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->sata
), 0, gic_spi
[SATA_INTR
]);
314 for (i
= 0; i
< XLNX_ZYNQMP_NUM_SDHCI
; i
++) {
315 object_property_set_bool(OBJECT(&s
->sdhci
[i
]), true,
318 error_propagate(errp
, err
);
321 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->sdhci
[i
]), 0,
323 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->sdhci
[i
]), 0,
324 gic_spi
[sdhci_intr
[i
]]);
328 static Property xlnx_zynqmp_props
[] = {
329 DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState
, boot_cpu
),
330 DEFINE_PROP_END_OF_LIST()
333 static void xlnx_zynqmp_class_init(ObjectClass
*oc
, void *data
)
335 DeviceClass
*dc
= DEVICE_CLASS(oc
);
337 dc
->props
= xlnx_zynqmp_props
;
338 dc
->realize
= xlnx_zynqmp_realize
;
341 * Reason: creates an ARM CPU, thus use after free(), see
342 * arm_cpu_class_init()
344 dc
->cannot_destroy_with_object_finalize_yet
= true;
347 static const TypeInfo xlnx_zynqmp_type_info
= {
348 .name
= TYPE_XLNX_ZYNQMP
,
349 .parent
= TYPE_DEVICE
,
350 .instance_size
= sizeof(XlnxZynqMPState
),
351 .instance_init
= xlnx_zynqmp_init
,
352 .class_init
= xlnx_zynqmp_class_init
,
355 static void xlnx_zynqmp_register_types(void)
357 type_register_static(&xlnx_zynqmp_type_info
);
360 type_init(xlnx_zynqmp_register_types
)