2 * Helpers for loads and stores
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
23 #include "exec/helper-proto.h"
24 #include "exec/exec-all.h"
25 #include "exec/cpu_ldst.h"
30 //#define DEBUG_UNALIGNED
31 //#define DEBUG_UNASSIGNED
33 //#define DEBUG_CACHE_CONTROL
36 #define DPRINTF_MMU(fmt, ...) \
37 do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0)
39 #define DPRINTF_MMU(fmt, ...) do {} while (0)
43 #define DPRINTF_MXCC(fmt, ...) \
44 do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0)
46 #define DPRINTF_MXCC(fmt, ...) do {} while (0)
50 #define DPRINTF_ASI(fmt, ...) \
51 do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0)
54 #ifdef DEBUG_CACHE_CONTROL
55 #define DPRINTF_CACHE_CONTROL(fmt, ...) \
56 do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0)
58 #define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0)
63 #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
65 #define AM_CHECK(env1) (1)
69 #define QT0 (env->qt0)
70 #define QT1 (env->qt1)
72 #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
73 /* Calculates TSB pointer value for fault page size
74 * UltraSPARC IIi has fixed sizes (8k or 64k) for the page pointers
75 * UA2005 holds the page size configuration in mmu_ctx registers */
76 static uint64_t ultrasparc_tsb_pointer(CPUSPARCState
*env
,
77 const SparcV9MMU
*mmu
, const int idx
)
79 uint64_t tsb_register
;
81 if (cpu_has_hypervisor(env
)) {
83 int ctx
= mmu
->tag_access
& 0x1fffULL
;
84 uint64_t ctx_register
= mmu
->sun4v_ctx_config
[ctx
? 1 : 0];
86 tsb_index
|= ctx
? 2 : 0;
87 page_size
= idx
? ctx_register
>> 8 : ctx_register
;
89 tsb_register
= mmu
->sun4v_tsb_pointers
[tsb_index
];
92 tsb_register
= mmu
->tsb
;
94 int tsb_split
= (tsb_register
& 0x1000ULL
) ? 1 : 0;
95 int tsb_size
= tsb_register
& 0xf;
97 uint64_t tsb_base_mask
= (~0x1fffULL
) << tsb_size
;
99 /* move va bits to correct position,
100 * the context bits will be masked out later */
101 uint64_t va
= mmu
->tag_access
>> (3 * page_size
+ 9);
103 /* calculate tsb_base mask and adjust va if split is in use */
106 va
&= ~(1ULL << (13 + tsb_size
));
108 va
|= (1ULL << (13 + tsb_size
));
113 return ((tsb_register
& tsb_base_mask
) | (va
& ~tsb_base_mask
)) & ~0xfULL
;
116 /* Calculates tag target register value by reordering bits
117 in tag access register */
118 static uint64_t ultrasparc_tag_target(uint64_t tag_access_register
)
120 return ((tag_access_register
& 0x1fff) << 48) | (tag_access_register
>> 22);
123 static void replace_tlb_entry(SparcTLBEntry
*tlb
,
124 uint64_t tlb_tag
, uint64_t tlb_tte
,
127 target_ulong mask
, size
, va
, offset
;
129 /* flush page range if translation is valid */
130 if (TTE_IS_VALID(tlb
->tte
)) {
131 CPUState
*cs
= env_cpu(env
);
133 size
= 8192ULL << 3 * TTE_PGSIZE(tlb
->tte
);
136 va
= tlb
->tag
& mask
;
138 for (offset
= 0; offset
< size
; offset
+= TARGET_PAGE_SIZE
) {
139 tlb_flush_page(cs
, va
+ offset
);
147 static void demap_tlb(SparcTLBEntry
*tlb
, target_ulong demap_addr
,
148 const char *strmmu
, CPUSPARCState
*env1
)
154 int is_demap_context
= (demap_addr
>> 6) & 1;
157 switch ((demap_addr
>> 4) & 3) {
158 case 0: /* primary */
159 context
= env1
->dmmu
.mmu_primary_context
;
161 case 1: /* secondary */
162 context
= env1
->dmmu
.mmu_secondary_context
;
164 case 2: /* nucleus */
167 case 3: /* reserved */
172 for (i
= 0; i
< 64; i
++) {
173 if (TTE_IS_VALID(tlb
[i
].tte
)) {
175 if (is_demap_context
) {
176 /* will remove non-global entries matching context value */
177 if (TTE_IS_GLOBAL(tlb
[i
].tte
) ||
178 !tlb_compare_context(&tlb
[i
], context
)) {
183 will remove any entry matching VA */
184 mask
= 0xffffffffffffe000ULL
;
185 mask
<<= 3 * ((tlb
[i
].tte
>> 61) & 3);
187 if (!compare_masked(demap_addr
, tlb
[i
].tag
, mask
)) {
191 /* entry should be global or matching context value */
192 if (!TTE_IS_GLOBAL(tlb
[i
].tte
) &&
193 !tlb_compare_context(&tlb
[i
], context
)) {
198 replace_tlb_entry(&tlb
[i
], 0, 0, env1
);
200 DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu
, i
);
207 static uint64_t sun4v_tte_to_sun4u(CPUSPARCState
*env
, uint64_t tag
,
211 if (!(cpu_has_hypervisor(env
) && (tag
& TLB_UST1_IS_SUN4V_BIT
))) {
212 /* is already in the sun4u format */
215 sun4u_tte
= TTE_PA(sun4v_tte
) | (sun4v_tte
& TTE_VALID_BIT
);
216 sun4u_tte
|= (sun4v_tte
& 3ULL) << 61; /* TTE_PGSIZE */
217 sun4u_tte
|= CONVERT_BIT(sun4v_tte
, TTE_NFO_BIT_UA2005
, TTE_NFO_BIT
);
218 sun4u_tte
|= CONVERT_BIT(sun4v_tte
, TTE_USED_BIT_UA2005
, TTE_USED_BIT
);
219 sun4u_tte
|= CONVERT_BIT(sun4v_tte
, TTE_W_OK_BIT_UA2005
, TTE_W_OK_BIT
);
220 sun4u_tte
|= CONVERT_BIT(sun4v_tte
, TTE_SIDEEFFECT_BIT_UA2005
,
222 sun4u_tte
|= CONVERT_BIT(sun4v_tte
, TTE_PRIV_BIT_UA2005
, TTE_PRIV_BIT
);
223 sun4u_tte
|= CONVERT_BIT(sun4v_tte
, TTE_LOCKED_BIT_UA2005
, TTE_LOCKED_BIT
);
227 static void replace_tlb_1bit_lru(SparcTLBEntry
*tlb
,
228 uint64_t tlb_tag
, uint64_t tlb_tte
,
229 const char *strmmu
, CPUSPARCState
*env1
,
232 unsigned int i
, replace_used
;
234 tlb_tte
= sun4v_tte_to_sun4u(env1
, addr
, tlb_tte
);
235 if (cpu_has_hypervisor(env1
)) {
236 uint64_t new_vaddr
= tlb_tag
& ~0x1fffULL
;
237 uint64_t new_size
= 8192ULL << 3 * TTE_PGSIZE(tlb_tte
);
238 uint32_t new_ctx
= tlb_tag
& 0x1fffU
;
239 for (i
= 0; i
< 64; i
++) {
240 uint32_t ctx
= tlb
[i
].tag
& 0x1fffU
;
241 /* check if new mapping overlaps an existing one */
242 if (new_ctx
== ctx
) {
243 uint64_t vaddr
= tlb
[i
].tag
& ~0x1fffULL
;
244 uint64_t size
= 8192ULL << 3 * TTE_PGSIZE(tlb
[i
].tte
);
245 if (new_vaddr
== vaddr
246 || (new_vaddr
< vaddr
+ size
247 && vaddr
< new_vaddr
+ new_size
)) {
248 DPRINTF_MMU("auto demap entry [%d] %lx->%lx\n", i
, vaddr
,
250 replace_tlb_entry(&tlb
[i
], tlb_tag
, tlb_tte
, env1
);
257 /* Try replacing invalid entry */
258 for (i
= 0; i
< 64; i
++) {
259 if (!TTE_IS_VALID(tlb
[i
].tte
)) {
260 replace_tlb_entry(&tlb
[i
], tlb_tag
, tlb_tte
, env1
);
262 DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu
, i
);
269 /* All entries are valid, try replacing unlocked entry */
271 for (replace_used
= 0; replace_used
< 2; ++replace_used
) {
273 /* Used entries are not replaced on first pass */
275 for (i
= 0; i
< 64; i
++) {
276 if (!TTE_IS_LOCKED(tlb
[i
].tte
) && !TTE_IS_USED(tlb
[i
].tte
)) {
278 replace_tlb_entry(&tlb
[i
], tlb_tag
, tlb_tte
, env1
);
280 DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n",
281 strmmu
, (replace_used
? "used" : "unused"), i
);
288 /* Now reset used bit and search for unused entries again */
290 for (i
= 0; i
< 64; i
++) {
291 TTE_SET_UNUSED(tlb
[i
].tte
);
296 DPRINTF_MMU("%s lru replacement: no free entries available, "
297 "replacing the last one\n", strmmu
);
299 /* corner case: the last entry is replaced anyway */
300 replace_tlb_entry(&tlb
[63], tlb_tag
, tlb_tte
, env1
);
305 #ifdef TARGET_SPARC64
306 /* returns true if access using this ASI is to have address translated by MMU
307 otherwise access is to raw physical address */
308 /* TODO: check sparc32 bits */
309 static inline int is_translating_asi(int asi
)
311 /* Ultrasparc IIi translating asi
312 - note this list is defined by cpu implementation
329 static inline target_ulong
address_mask(CPUSPARCState
*env1
, target_ulong addr
)
331 if (AM_CHECK(env1
)) {
332 addr
&= 0xffffffffULL
;
337 static inline target_ulong
asi_address_mask(CPUSPARCState
*env
,
338 int asi
, target_ulong addr
)
340 if (is_translating_asi(asi
)) {
341 addr
= address_mask(env
, addr
);
346 #ifndef CONFIG_USER_ONLY
347 static inline void do_check_asi(CPUSPARCState
*env
, int asi
, uintptr_t ra
)
349 /* ASIs >= 0x80 are user mode.
350 * ASIs >= 0x30 are hyper mode (or super if hyper is not available).
351 * ASIs <= 0x2f are super mode.
354 && !cpu_hypervisor_mode(env
)
355 && (!cpu_supervisor_mode(env
)
356 || (asi
>= 0x30 && cpu_has_hypervisor(env
)))) {
357 cpu_raise_exception_ra(env
, TT_PRIV_ACT
, ra
);
360 #endif /* !CONFIG_USER_ONLY */
363 static void do_check_align(CPUSPARCState
*env
, target_ulong addr
,
364 uint32_t align
, uintptr_t ra
)
367 #ifdef DEBUG_UNALIGNED
368 printf("Unaligned access to 0x" TARGET_FMT_lx
" from 0x" TARGET_FMT_lx
369 "\n", addr
, env
->pc
);
371 cpu_raise_exception_ra(env
, TT_UNALIGNED
, ra
);
375 void helper_check_align(CPUSPARCState
*env
, target_ulong addr
, uint32_t align
)
377 do_check_align(env
, addr
, align
, GETPC());
380 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
382 static void dump_mxcc(CPUSPARCState
*env
)
384 printf("mxccdata: %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
386 env
->mxccdata
[0], env
->mxccdata
[1],
387 env
->mxccdata
[2], env
->mxccdata
[3]);
388 printf("mxccregs: %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
390 " %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
392 env
->mxccregs
[0], env
->mxccregs
[1],
393 env
->mxccregs
[2], env
->mxccregs
[3],
394 env
->mxccregs
[4], env
->mxccregs
[5],
395 env
->mxccregs
[6], env
->mxccregs
[7]);
399 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
400 && defined(DEBUG_ASI)
401 static void dump_asi(const char *txt
, target_ulong addr
, int asi
, int size
,
406 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %02" PRIx64
"\n", txt
,
407 addr
, asi
, r1
& 0xff);
410 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %04" PRIx64
"\n", txt
,
411 addr
, asi
, r1
& 0xffff);
414 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %08" PRIx64
"\n", txt
,
415 addr
, asi
, r1
& 0xffffffff);
418 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %016" PRIx64
"\n", txt
,
425 #ifndef CONFIG_USER_ONLY
426 #ifndef TARGET_SPARC64
427 static void sparc_raise_mmu_fault(CPUState
*cs
, hwaddr addr
,
428 bool is_write
, bool is_exec
, int is_asi
,
429 unsigned size
, uintptr_t retaddr
)
431 SPARCCPU
*cpu
= SPARC_CPU(cs
);
432 CPUSPARCState
*env
= &cpu
->env
;
435 #ifdef DEBUG_UNASSIGNED
437 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
438 " asi 0x%02x from " TARGET_FMT_lx
"\n",
439 is_exec
? "exec" : is_write
? "write" : "read", size
,
440 size
== 1 ? "" : "s", addr
, is_asi
, env
->pc
);
442 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
443 " from " TARGET_FMT_lx
"\n",
444 is_exec
? "exec" : is_write
? "write" : "read", size
,
445 size
== 1 ? "" : "s", addr
, env
->pc
);
448 /* Don't overwrite translation and access faults */
449 fault_type
= (env
->mmuregs
[3] & 0x1c) >> 2;
450 if ((fault_type
> 4) || (fault_type
== 0)) {
451 env
->mmuregs
[3] = 0; /* Fault status register */
453 env
->mmuregs
[3] |= 1 << 16;
456 env
->mmuregs
[3] |= 1 << 5;
459 env
->mmuregs
[3] |= 1 << 6;
462 env
->mmuregs
[3] |= 1 << 7;
464 env
->mmuregs
[3] |= (5 << 2) | 2;
465 /* SuperSPARC will never place instruction fault addresses in the FAR */
467 env
->mmuregs
[4] = addr
; /* Fault address register */
470 /* overflow (same type fault was not read before another fault) */
471 if (fault_type
== ((env
->mmuregs
[3] & 0x1c)) >> 2) {
472 env
->mmuregs
[3] |= 1;
475 if ((env
->mmuregs
[0] & MMU_E
) && !(env
->mmuregs
[0] & MMU_NF
)) {
476 int tt
= is_exec
? TT_CODE_ACCESS
: TT_DATA_ACCESS
;
477 cpu_raise_exception_ra(env
, tt
, retaddr
);
481 * flush neverland mappings created during no-fault mode,
482 * so the sequential MMU faults report proper fault types
484 if (env
->mmuregs
[0] & MMU_NF
) {
489 static void sparc_raise_mmu_fault(CPUState
*cs
, hwaddr addr
,
490 bool is_write
, bool is_exec
, int is_asi
,
491 unsigned size
, uintptr_t retaddr
)
493 SPARCCPU
*cpu
= SPARC_CPU(cs
);
494 CPUSPARCState
*env
= &cpu
->env
;
496 #ifdef DEBUG_UNASSIGNED
497 printf("Unassigned mem access to " TARGET_FMT_plx
" from " TARGET_FMT_lx
498 "\n", addr
, env
->pc
);
501 if (is_exec
) { /* XXX has_hypervisor */
502 if (env
->lsu
& (IMMU_E
)) {
503 cpu_raise_exception_ra(env
, TT_CODE_ACCESS
, retaddr
);
504 } else if (cpu_has_hypervisor(env
) && !(env
->hpstate
& HS_PRIV
)) {
505 cpu_raise_exception_ra(env
, TT_INSN_REAL_TRANSLATION_MISS
, retaddr
);
508 if (env
->lsu
& (DMMU_E
)) {
509 cpu_raise_exception_ra(env
, TT_DATA_ACCESS
, retaddr
);
510 } else if (cpu_has_hypervisor(env
) && !(env
->hpstate
& HS_PRIV
)) {
511 cpu_raise_exception_ra(env
, TT_DATA_REAL_TRANSLATION_MISS
, retaddr
);
518 #ifndef TARGET_SPARC64
519 #ifndef CONFIG_USER_ONLY
522 /* Leon3 cache control */
524 static void leon3_cache_control_st(CPUSPARCState
*env
, target_ulong addr
,
525 uint64_t val
, int size
)
527 DPRINTF_CACHE_CONTROL("st addr:%08x, val:%" PRIx64
", size:%d\n",
531 DPRINTF_CACHE_CONTROL("32bits only\n");
536 case 0x00: /* Cache control */
538 /* These values must always be read as zeros */
539 val
&= ~CACHE_CTRL_FD
;
540 val
&= ~CACHE_CTRL_FI
;
541 val
&= ~CACHE_CTRL_IB
;
542 val
&= ~CACHE_CTRL_IP
;
543 val
&= ~CACHE_CTRL_DP
;
545 env
->cache_control
= val
;
547 case 0x04: /* Instruction cache configuration */
548 case 0x08: /* Data cache configuration */
552 DPRINTF_CACHE_CONTROL("write unknown register %08x\n", addr
);
557 static uint64_t leon3_cache_control_ld(CPUSPARCState
*env
, target_ulong addr
,
563 DPRINTF_CACHE_CONTROL("32bits only\n");
568 case 0x00: /* Cache control */
569 ret
= env
->cache_control
;
572 /* Configuration registers are read and only always keep those
575 case 0x04: /* Instruction cache configuration */
578 case 0x08: /* Data cache configuration */
582 DPRINTF_CACHE_CONTROL("read unknown register %08x\n", addr
);
585 DPRINTF_CACHE_CONTROL("ld addr:%08x, ret:0x%" PRIx64
", size:%d\n",
590 uint64_t helper_ld_asi(CPUSPARCState
*env
, target_ulong addr
,
591 int asi
, uint32_t memop
)
593 int size
= 1 << (memop
& MO_SIZE
);
594 int sign
= memop
& MO_SIGN
;
595 CPUState
*cs
= env_cpu(env
);
597 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
598 uint32_t last_addr
= addr
;
601 do_check_align(env
, addr
, size
- 1, GETPC());
603 case ASI_M_MXCC
: /* SuperSparc MXCC registers, or... */
604 /* case ASI_LEON_CACHEREGS: Leon3 cache control */
606 case 0x00: /* Leon3 Cache Control */
607 case 0x08: /* Leon3 Instruction Cache config */
608 case 0x0C: /* Leon3 Date Cache config */
609 if (env
->def
.features
& CPU_FEATURE_CACHE_CTRL
) {
610 ret
= leon3_cache_control_ld(env
, addr
, size
);
613 case 0x01c00a00: /* MXCC control register */
615 ret
= env
->mxccregs
[3];
617 qemu_log_mask(LOG_UNIMP
,
618 "%08x: unimplemented access size: %d\n", addr
,
622 case 0x01c00a04: /* MXCC control register */
624 ret
= env
->mxccregs
[3];
626 qemu_log_mask(LOG_UNIMP
,
627 "%08x: unimplemented access size: %d\n", addr
,
631 case 0x01c00c00: /* Module reset register */
633 ret
= env
->mxccregs
[5];
634 /* should we do something here? */
636 qemu_log_mask(LOG_UNIMP
,
637 "%08x: unimplemented access size: %d\n", addr
,
641 case 0x01c00f00: /* MBus port address register */
643 ret
= env
->mxccregs
[7];
645 qemu_log_mask(LOG_UNIMP
,
646 "%08x: unimplemented access size: %d\n", addr
,
651 qemu_log_mask(LOG_UNIMP
,
652 "%08x: unimplemented address, size: %d\n", addr
,
656 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
657 "addr = %08x -> ret = %" PRIx64
","
658 "addr = %08x\n", asi
, size
, sign
, last_addr
, ret
, addr
);
663 case ASI_M_FLUSH_PROBE
: /* SuperSparc MMU probe */
664 case ASI_LEON_MMUFLUSH
: /* LEON3 MMU probe */
668 mmulev
= (addr
>> 8) & 15;
672 ret
= mmu_probe(env
, addr
, mmulev
);
674 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64
"\n",
678 case ASI_M_MMUREGS
: /* SuperSparc MMU regs */
679 case ASI_LEON_MMUREGS
: /* LEON3 MMU regs */
681 int reg
= (addr
>> 8) & 0x1f;
683 ret
= env
->mmuregs
[reg
];
684 if (reg
== 3) { /* Fault status cleared on read */
686 } else if (reg
== 0x13) { /* Fault status read */
687 ret
= env
->mmuregs
[3];
688 } else if (reg
== 0x14) { /* Fault address read */
689 ret
= env
->mmuregs
[4];
691 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64
"\n", reg
, ret
);
694 case ASI_M_TLBDIAG
: /* Turbosparc ITLB Diagnostic */
695 case ASI_M_DIAGS
: /* Turbosparc DTLB Diagnostic */
696 case ASI_M_IODIAG
: /* Turbosparc IOTLB Diagnostic */
698 case ASI_KERNELTXT
: /* Supervisor code access */
701 ret
= cpu_ldub_code(env
, addr
);
704 ret
= cpu_lduw_code(env
, addr
);
708 ret
= cpu_ldl_code(env
, addr
);
711 ret
= cpu_ldq_code(env
, addr
);
715 case ASI_M_TXTC_TAG
: /* SparcStation 5 I-cache tag */
716 case ASI_M_TXTC_DATA
: /* SparcStation 5 I-cache data */
717 case ASI_M_DATAC_TAG
: /* SparcStation 5 D-cache tag */
718 case ASI_M_DATAC_DATA
: /* SparcStation 5 D-cache data */
720 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
723 hwaddr access_addr
= (hwaddr
)addr
| ((hwaddr
)(asi
& 0xf) << 32);
727 ret
= address_space_ldub(cs
->as
, access_addr
,
728 MEMTXATTRS_UNSPECIFIED
, &result
);
731 ret
= address_space_lduw(cs
->as
, access_addr
,
732 MEMTXATTRS_UNSPECIFIED
, &result
);
736 ret
= address_space_ldl(cs
->as
, access_addr
,
737 MEMTXATTRS_UNSPECIFIED
, &result
);
740 ret
= address_space_ldq(cs
->as
, access_addr
,
741 MEMTXATTRS_UNSPECIFIED
, &result
);
745 if (result
!= MEMTX_OK
) {
746 sparc_raise_mmu_fault(cs
, access_addr
, false, false, false,
751 case 0x30: /* Turbosparc secondary cache diagnostic */
752 case 0x31: /* Turbosparc RAM snoop */
753 case 0x32: /* Turbosparc page table descriptor diagnostic */
754 case 0x39: /* data cache diagnostic register */
757 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
759 int reg
= (addr
>> 8) & 3;
762 case 0: /* Breakpoint Value (Addr) */
763 ret
= env
->mmubpregs
[reg
];
765 case 1: /* Breakpoint Mask */
766 ret
= env
->mmubpregs
[reg
];
768 case 2: /* Breakpoint Control */
769 ret
= env
->mmubpregs
[reg
];
771 case 3: /* Breakpoint Status */
772 ret
= env
->mmubpregs
[reg
];
773 env
->mmubpregs
[reg
] = 0ULL;
776 DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64
"\n", reg
,
780 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
781 ret
= env
->mmubpctrv
;
783 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
784 ret
= env
->mmubpctrc
;
786 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
787 ret
= env
->mmubpctrs
;
789 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
790 ret
= env
->mmubpaction
;
792 case ASI_USERTXT
: /* User code access, XXX */
794 sparc_raise_mmu_fault(cs
, addr
, false, false, asi
, size
, GETPC());
798 case ASI_USERDATA
: /* User data access */
799 case ASI_KERNELDATA
: /* Supervisor data access */
800 case ASI_P
: /* Implicit primary context data access (v9 only?) */
801 case ASI_M_BYPASS
: /* MMU passthrough */
802 case ASI_LEON_BYPASS
: /* LEON MMU passthrough */
803 /* These are always handled inline. */
804 g_assert_not_reached();
822 dump_asi("read ", last_addr
, asi
, size
, ret
);
827 void helper_st_asi(CPUSPARCState
*env
, target_ulong addr
, uint64_t val
,
828 int asi
, uint32_t memop
)
830 int size
= 1 << (memop
& MO_SIZE
);
831 CPUState
*cs
= env_cpu(env
);
833 do_check_align(env
, addr
, size
- 1, GETPC());
835 case ASI_M_MXCC
: /* SuperSparc MXCC registers, or... */
836 /* case ASI_LEON_CACHEREGS: Leon3 cache control */
838 case 0x00: /* Leon3 Cache Control */
839 case 0x08: /* Leon3 Instruction Cache config */
840 case 0x0C: /* Leon3 Date Cache config */
841 if (env
->def
.features
& CPU_FEATURE_CACHE_CTRL
) {
842 leon3_cache_control_st(env
, addr
, val
, size
);
846 case 0x01c00000: /* MXCC stream data register 0 */
848 env
->mxccdata
[0] = val
;
850 qemu_log_mask(LOG_UNIMP
,
851 "%08x: unimplemented access size: %d\n", addr
,
855 case 0x01c00008: /* MXCC stream data register 1 */
857 env
->mxccdata
[1] = val
;
859 qemu_log_mask(LOG_UNIMP
,
860 "%08x: unimplemented access size: %d\n", addr
,
864 case 0x01c00010: /* MXCC stream data register 2 */
866 env
->mxccdata
[2] = val
;
868 qemu_log_mask(LOG_UNIMP
,
869 "%08x: unimplemented access size: %d\n", addr
,
873 case 0x01c00018: /* MXCC stream data register 3 */
875 env
->mxccdata
[3] = val
;
877 qemu_log_mask(LOG_UNIMP
,
878 "%08x: unimplemented access size: %d\n", addr
,
882 case 0x01c00100: /* MXCC stream source */
887 env
->mxccregs
[0] = val
;
889 qemu_log_mask(LOG_UNIMP
,
890 "%08x: unimplemented access size: %d\n", addr
,
894 for (i
= 0; i
< 4; i
++) {
896 hwaddr access_addr
= (env
->mxccregs
[0] & 0xffffffffULL
) + 8 * i
;
898 env
->mxccdata
[i
] = address_space_ldq(cs
->as
,
900 MEMTXATTRS_UNSPECIFIED
,
902 if (result
!= MEMTX_OK
) {
903 /* TODO: investigate whether this is the right behaviour */
904 sparc_raise_mmu_fault(cs
, access_addr
, false, false,
905 false, size
, GETPC());
910 case 0x01c00200: /* MXCC stream destination */
915 env
->mxccregs
[1] = val
;
917 qemu_log_mask(LOG_UNIMP
,
918 "%08x: unimplemented access size: %d\n", addr
,
922 for (i
= 0; i
< 4; i
++) {
924 hwaddr access_addr
= (env
->mxccregs
[1] & 0xffffffffULL
) + 8 * i
;
926 address_space_stq(cs
->as
, access_addr
, env
->mxccdata
[i
],
927 MEMTXATTRS_UNSPECIFIED
, &result
);
929 if (result
!= MEMTX_OK
) {
930 /* TODO: investigate whether this is the right behaviour */
931 sparc_raise_mmu_fault(cs
, access_addr
, true, false,
932 false, size
, GETPC());
937 case 0x01c00a00: /* MXCC control register */
939 env
->mxccregs
[3] = val
;
941 qemu_log_mask(LOG_UNIMP
,
942 "%08x: unimplemented access size: %d\n", addr
,
946 case 0x01c00a04: /* MXCC control register */
948 env
->mxccregs
[3] = (env
->mxccregs
[3] & 0xffffffff00000000ULL
)
951 qemu_log_mask(LOG_UNIMP
,
952 "%08x: unimplemented access size: %d\n", addr
,
956 case 0x01c00e00: /* MXCC error register */
957 /* writing a 1 bit clears the error */
959 env
->mxccregs
[6] &= ~val
;
961 qemu_log_mask(LOG_UNIMP
,
962 "%08x: unimplemented access size: %d\n", addr
,
966 case 0x01c00f00: /* MBus port address register */
968 env
->mxccregs
[7] = val
;
970 qemu_log_mask(LOG_UNIMP
,
971 "%08x: unimplemented access size: %d\n", addr
,
976 qemu_log_mask(LOG_UNIMP
,
977 "%08x: unimplemented address, size: %d\n", addr
,
981 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64
"\n",
982 asi
, size
, addr
, val
);
987 case ASI_M_FLUSH_PROBE
: /* SuperSparc MMU flush */
988 case ASI_LEON_MMUFLUSH
: /* LEON3 MMU flush */
992 mmulev
= (addr
>> 8) & 15;
993 DPRINTF_MMU("mmu flush level %d\n", mmulev
);
995 case 0: /* flush page */
996 tlb_flush_page(cs
, addr
& 0xfffff000);
998 case 1: /* flush segment (256k) */
999 case 2: /* flush region (16M) */
1000 case 3: /* flush context (4G) */
1001 case 4: /* flush entire */
1012 case ASI_M_MMUREGS
: /* write MMU regs */
1013 case ASI_LEON_MMUREGS
: /* LEON3 write MMU regs */
1015 int reg
= (addr
>> 8) & 0x1f;
1018 oldreg
= env
->mmuregs
[reg
];
1020 case 0: /* Control Register */
1021 env
->mmuregs
[reg
] = (env
->mmuregs
[reg
] & 0xff000000) |
1023 /* Mappings generated during no-fault mode
1024 are invalid in normal mode. */
1025 if ((oldreg
^ env
->mmuregs
[reg
])
1026 & (MMU_NF
| env
->def
.mmu_bm
)) {
1030 case 1: /* Context Table Pointer Register */
1031 env
->mmuregs
[reg
] = val
& env
->def
.mmu_ctpr_mask
;
1033 case 2: /* Context Register */
1034 env
->mmuregs
[reg
] = val
& env
->def
.mmu_cxr_mask
;
1035 if (oldreg
!= env
->mmuregs
[reg
]) {
1036 /* we flush when the MMU context changes because
1037 QEMU has no MMU context support */
1041 case 3: /* Synchronous Fault Status Register with Clear */
1042 case 4: /* Synchronous Fault Address Register */
1044 case 0x10: /* TLB Replacement Control Register */
1045 env
->mmuregs
[reg
] = val
& env
->def
.mmu_trcr_mask
;
1047 case 0x13: /* Synchronous Fault Status Register with Read
1049 env
->mmuregs
[3] = val
& env
->def
.mmu_sfsr_mask
;
1051 case 0x14: /* Synchronous Fault Address Register */
1052 env
->mmuregs
[4] = val
;
1055 env
->mmuregs
[reg
] = val
;
1058 if (oldreg
!= env
->mmuregs
[reg
]) {
1059 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
1060 reg
, oldreg
, env
->mmuregs
[reg
]);
1067 case ASI_M_TLBDIAG
: /* Turbosparc ITLB Diagnostic */
1068 case ASI_M_DIAGS
: /* Turbosparc DTLB Diagnostic */
1069 case ASI_M_IODIAG
: /* Turbosparc IOTLB Diagnostic */
1071 case ASI_M_TXTC_TAG
: /* I-cache tag */
1072 case ASI_M_TXTC_DATA
: /* I-cache data */
1073 case ASI_M_DATAC_TAG
: /* D-cache tag */
1074 case ASI_M_DATAC_DATA
: /* D-cache data */
1075 case ASI_M_FLUSH_PAGE
: /* I/D-cache flush page */
1076 case ASI_M_FLUSH_SEG
: /* I/D-cache flush segment */
1077 case ASI_M_FLUSH_REGION
: /* I/D-cache flush region */
1078 case ASI_M_FLUSH_CTX
: /* I/D-cache flush context */
1079 case ASI_M_FLUSH_USER
: /* I/D-cache flush user */
1081 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1084 hwaddr access_addr
= (hwaddr
)addr
| ((hwaddr
)(asi
& 0xf) << 32);
1088 address_space_stb(cs
->as
, access_addr
, val
,
1089 MEMTXATTRS_UNSPECIFIED
, &result
);
1092 address_space_stw(cs
->as
, access_addr
, val
,
1093 MEMTXATTRS_UNSPECIFIED
, &result
);
1097 address_space_stl(cs
->as
, access_addr
, val
,
1098 MEMTXATTRS_UNSPECIFIED
, &result
);
1101 address_space_stq(cs
->as
, access_addr
, val
,
1102 MEMTXATTRS_UNSPECIFIED
, &result
);
1105 if (result
!= MEMTX_OK
) {
1106 sparc_raise_mmu_fault(cs
, access_addr
, true, false, false,
1111 case 0x30: /* store buffer tags or Turbosparc secondary cache diagnostic */
1112 case 0x31: /* store buffer data, Ross RT620 I-cache flush or
1113 Turbosparc snoop RAM */
1114 case 0x32: /* store buffer control or Turbosparc page table
1115 descriptor diagnostic */
1116 case 0x36: /* I-cache flash clear */
1117 case 0x37: /* D-cache flash clear */
1119 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
1121 int reg
= (addr
>> 8) & 3;
1124 case 0: /* Breakpoint Value (Addr) */
1125 env
->mmubpregs
[reg
] = (val
& 0xfffffffffULL
);
1127 case 1: /* Breakpoint Mask */
1128 env
->mmubpregs
[reg
] = (val
& 0xfffffffffULL
);
1130 case 2: /* Breakpoint Control */
1131 env
->mmubpregs
[reg
] = (val
& 0x7fULL
);
1133 case 3: /* Breakpoint Status */
1134 env
->mmubpregs
[reg
] = (val
& 0xfULL
);
1137 DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg
,
1141 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
1142 env
->mmubpctrv
= val
& 0xffffffff;
1144 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
1145 env
->mmubpctrc
= val
& 0x3;
1147 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
1148 env
->mmubpctrs
= val
& 0x3;
1150 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
1151 env
->mmubpaction
= val
& 0x1fff;
1153 case ASI_USERTXT
: /* User code access, XXX */
1154 case ASI_KERNELTXT
: /* Supervisor code access, XXX */
1156 sparc_raise_mmu_fault(cs
, addr
, true, false, asi
, size
, GETPC());
1159 case ASI_USERDATA
: /* User data access */
1160 case ASI_KERNELDATA
: /* Supervisor data access */
1162 case ASI_M_BYPASS
: /* MMU passthrough */
1163 case ASI_LEON_BYPASS
: /* LEON MMU passthrough */
1164 case ASI_M_BCOPY
: /* Block copy, sta access */
1165 case ASI_M_BFILL
: /* Block fill, stda access */
1166 /* These are always handled inline. */
1167 g_assert_not_reached();
1170 dump_asi("write", addr
, asi
, size
, val
);
1174 #endif /* CONFIG_USER_ONLY */
1175 #else /* TARGET_SPARC64 */
1177 #ifdef CONFIG_USER_ONLY
1178 uint64_t helper_ld_asi(CPUSPARCState
*env
, target_ulong addr
,
1179 int asi
, uint32_t memop
)
1181 int size
= 1 << (memop
& MO_SIZE
);
1182 int sign
= memop
& MO_SIGN
;
1186 cpu_raise_exception_ra(env
, TT_PRIV_ACT
, GETPC());
1188 do_check_align(env
, addr
, size
- 1, GETPC());
1189 addr
= asi_address_mask(env
, asi
, addr
);
1192 case ASI_PNF
: /* Primary no-fault */
1193 case ASI_PNFL
: /* Primary no-fault LE */
1194 case ASI_SNF
: /* Secondary no-fault */
1195 case ASI_SNFL
: /* Secondary no-fault LE */
1196 if (page_check_range(addr
, size
, PAGE_READ
) == -1) {
1202 ret
= cpu_ldub_data(env
, addr
);
1205 ret
= cpu_lduw_data(env
, addr
);
1208 ret
= cpu_ldl_data(env
, addr
);
1211 ret
= cpu_ldq_data(env
, addr
);
1214 g_assert_not_reached();
1219 case ASI_P
: /* Primary */
1220 case ASI_PL
: /* Primary LE */
1221 case ASI_S
: /* Secondary */
1222 case ASI_SL
: /* Secondary LE */
1223 /* These are always handled inline. */
1224 g_assert_not_reached();
1227 cpu_raise_exception_ra(env
, TT_DATA_ACCESS
, GETPC());
1230 /* Convert from little endian */
1232 case ASI_PNFL
: /* Primary no-fault LE */
1233 case ASI_SNFL
: /* Secondary no-fault LE */
1247 /* Convert to signed number */
1254 ret
= (int16_t) ret
;
1257 ret
= (int32_t) ret
;
1262 dump_asi("read", addr
, asi
, size
, ret
);
1267 void helper_st_asi(CPUSPARCState
*env
, target_ulong addr
, target_ulong val
,
1268 int asi
, uint32_t memop
)
1270 int size
= 1 << (memop
& MO_SIZE
);
1272 dump_asi("write", addr
, asi
, size
, val
);
1275 cpu_raise_exception_ra(env
, TT_PRIV_ACT
, GETPC());
1277 do_check_align(env
, addr
, size
- 1, GETPC());
1280 case ASI_P
: /* Primary */
1281 case ASI_PL
: /* Primary LE */
1282 case ASI_S
: /* Secondary */
1283 case ASI_SL
: /* Secondary LE */
1284 /* These are always handled inline. */
1285 g_assert_not_reached();
1287 case ASI_PNF
: /* Primary no-fault, RO */
1288 case ASI_SNF
: /* Secondary no-fault, RO */
1289 case ASI_PNFL
: /* Primary no-fault LE, RO */
1290 case ASI_SNFL
: /* Secondary no-fault LE, RO */
1292 cpu_raise_exception_ra(env
, TT_DATA_ACCESS
, GETPC());
1296 #else /* CONFIG_USER_ONLY */
1298 uint64_t helper_ld_asi(CPUSPARCState
*env
, target_ulong addr
,
1299 int asi
, uint32_t memop
)
1301 int size
= 1 << (memop
& MO_SIZE
);
1302 int sign
= memop
& MO_SIGN
;
1303 CPUState
*cs
= env_cpu(env
);
1305 #if defined(DEBUG_ASI)
1306 target_ulong last_addr
= addr
;
1311 do_check_asi(env
, asi
, GETPC());
1312 do_check_align(env
, addr
, size
- 1, GETPC());
1313 addr
= asi_address_mask(env
, asi
, addr
);
1322 int idx
= (env
->pstate
& PS_PRIV
1323 ? (asi
& 1 ? MMU_KERNEL_SECONDARY_IDX
: MMU_KERNEL_IDX
)
1324 : (asi
& 1 ? MMU_USER_SECONDARY_IDX
: MMU_USER_IDX
));
1326 if (cpu_get_phys_page_nofault(env
, addr
, idx
) == -1ULL) {
1328 dump_asi("read ", last_addr
, asi
, size
, ret
);
1330 /* exception_index is set in get_physical_address_data. */
1331 cpu_raise_exception_ra(env
, cs
->exception_index
, GETPC());
1333 oi
= make_memop_idx(memop
, idx
);
1336 ret
= helper_ret_ldub_mmu(env
, addr
, oi
, GETPC());
1340 ret
= helper_le_lduw_mmu(env
, addr
, oi
, GETPC());
1342 ret
= helper_be_lduw_mmu(env
, addr
, oi
, GETPC());
1347 ret
= helper_le_ldul_mmu(env
, addr
, oi
, GETPC());
1349 ret
= helper_be_ldul_mmu(env
, addr
, oi
, GETPC());
1354 ret
= helper_le_ldq_mmu(env
, addr
, oi
, GETPC());
1356 ret
= helper_be_ldq_mmu(env
, addr
, oi
, GETPC());
1360 g_assert_not_reached();
1365 case ASI_AIUP
: /* As if user primary */
1366 case ASI_AIUS
: /* As if user secondary */
1367 case ASI_AIUPL
: /* As if user primary LE */
1368 case ASI_AIUSL
: /* As if user secondary LE */
1369 case ASI_P
: /* Primary */
1370 case ASI_S
: /* Secondary */
1371 case ASI_PL
: /* Primary LE */
1372 case ASI_SL
: /* Secondary LE */
1373 case ASI_REAL
: /* Bypass */
1374 case ASI_REAL_IO
: /* Bypass, non-cacheable */
1375 case ASI_REAL_L
: /* Bypass LE */
1376 case ASI_REAL_IO_L
: /* Bypass, non-cacheable LE */
1377 case ASI_N
: /* Nucleus */
1378 case ASI_NL
: /* Nucleus Little Endian (LE) */
1379 case ASI_NUCLEUS_QUAD_LDD
: /* Nucleus quad LDD 128 bit atomic */
1380 case ASI_NUCLEUS_QUAD_LDD_L
: /* Nucleus quad LDD 128 bit atomic LE */
1381 case ASI_TWINX_AIUP
: /* As if user primary, twinx */
1382 case ASI_TWINX_AIUS
: /* As if user secondary, twinx */
1383 case ASI_TWINX_REAL
: /* Real address, twinx */
1384 case ASI_TWINX_AIUP_L
: /* As if user primary, twinx, LE */
1385 case ASI_TWINX_AIUS_L
: /* As if user secondary, twinx, LE */
1386 case ASI_TWINX_REAL_L
: /* Real address, twinx, LE */
1387 case ASI_TWINX_N
: /* Nucleus, twinx */
1388 case ASI_TWINX_NL
: /* Nucleus, twinx, LE */
1389 /* ??? From the UA2011 document; overlaps BLK_INIT_QUAD_LDD_* */
1390 case ASI_TWINX_P
: /* Primary, twinx */
1391 case ASI_TWINX_PL
: /* Primary, twinx, LE */
1392 case ASI_TWINX_S
: /* Secondary, twinx */
1393 case ASI_TWINX_SL
: /* Secondary, twinx, LE */
1394 /* These are always handled inline. */
1395 g_assert_not_reached();
1397 case ASI_UPA_CONFIG
: /* UPA config */
1400 case ASI_LSU_CONTROL
: /* LSU */
1403 case ASI_IMMU
: /* I-MMU regs */
1405 int reg
= (addr
>> 3) & 0xf;
1408 /* 0x00 I-TSB Tag Target register */
1409 ret
= ultrasparc_tag_target(env
->immu
.tag_access
);
1412 ret
= env
->immu
.sfsr
;
1414 case 5: /* TSB access */
1415 ret
= env
->immu
.tsb
;
1418 /* 0x30 I-TSB Tag Access register */
1419 ret
= env
->immu
.tag_access
;
1422 sparc_raise_mmu_fault(cs
, addr
, false, false, 1, size
, GETPC());
1427 case ASI_IMMU_TSB_8KB_PTR
: /* I-MMU 8k TSB pointer */
1429 /* env->immuregs[5] holds I-MMU TSB register value
1430 env->immuregs[6] holds I-MMU Tag Access register value */
1431 ret
= ultrasparc_tsb_pointer(env
, &env
->immu
, 0);
1434 case ASI_IMMU_TSB_64KB_PTR
: /* I-MMU 64k TSB pointer */
1436 /* env->immuregs[5] holds I-MMU TSB register value
1437 env->immuregs[6] holds I-MMU Tag Access register value */
1438 ret
= ultrasparc_tsb_pointer(env
, &env
->immu
, 1);
1441 case ASI_ITLB_DATA_ACCESS
: /* I-MMU data access */
1443 int reg
= (addr
>> 3) & 0x3f;
1445 ret
= env
->itlb
[reg
].tte
;
1448 case ASI_ITLB_TAG_READ
: /* I-MMU tag read */
1450 int reg
= (addr
>> 3) & 0x3f;
1452 ret
= env
->itlb
[reg
].tag
;
1455 case ASI_DMMU
: /* D-MMU regs */
1457 int reg
= (addr
>> 3) & 0xf;
1460 /* 0x00 D-TSB Tag Target register */
1461 ret
= ultrasparc_tag_target(env
->dmmu
.tag_access
);
1463 case 1: /* 0x08 Primary Context */
1464 ret
= env
->dmmu
.mmu_primary_context
;
1466 case 2: /* 0x10 Secondary Context */
1467 ret
= env
->dmmu
.mmu_secondary_context
;
1470 ret
= env
->dmmu
.sfsr
;
1472 case 4: /* 0x20 SFAR */
1473 ret
= env
->dmmu
.sfar
;
1475 case 5: /* 0x28 TSB access */
1476 ret
= env
->dmmu
.tsb
;
1478 case 6: /* 0x30 D-TSB Tag Access register */
1479 ret
= env
->dmmu
.tag_access
;
1482 ret
= env
->dmmu
.virtual_watchpoint
;
1485 ret
= env
->dmmu
.physical_watchpoint
;
1488 sparc_raise_mmu_fault(cs
, addr
, false, false, 1, size
, GETPC());
1493 case ASI_DMMU_TSB_8KB_PTR
: /* D-MMU 8k TSB pointer */
1495 /* env->dmmuregs[5] holds D-MMU TSB register value
1496 env->dmmuregs[6] holds D-MMU Tag Access register value */
1497 ret
= ultrasparc_tsb_pointer(env
, &env
->dmmu
, 0);
1500 case ASI_DMMU_TSB_64KB_PTR
: /* D-MMU 64k TSB pointer */
1502 /* env->dmmuregs[5] holds D-MMU TSB register value
1503 env->dmmuregs[6] holds D-MMU Tag Access register value */
1504 ret
= ultrasparc_tsb_pointer(env
, &env
->dmmu
, 1);
1507 case ASI_DTLB_DATA_ACCESS
: /* D-MMU data access */
1509 int reg
= (addr
>> 3) & 0x3f;
1511 ret
= env
->dtlb
[reg
].tte
;
1514 case ASI_DTLB_TAG_READ
: /* D-MMU tag read */
1516 int reg
= (addr
>> 3) & 0x3f;
1518 ret
= env
->dtlb
[reg
].tag
;
1521 case ASI_INTR_DISPATCH_STAT
: /* Interrupt dispatch, RO */
1523 case ASI_INTR_RECEIVE
: /* Interrupt data receive */
1524 ret
= env
->ivec_status
;
1526 case ASI_INTR_R
: /* Incoming interrupt vector, RO */
1528 int reg
= (addr
>> 4) & 0x3;
1530 ret
= env
->ivec_data
[reg
];
1534 case ASI_SCRATCHPAD
: /* UA2005 privileged scratchpad */
1535 if (unlikely((addr
>= 0x20) && (addr
< 0x30))) {
1536 /* Hyperprivileged access only */
1537 sparc_raise_mmu_fault(cs
, addr
, false, false, 1, size
, GETPC());
1540 case ASI_HYP_SCRATCHPAD
: /* UA2005 hyperprivileged scratchpad */
1542 unsigned int i
= (addr
>> 3) & 0x7;
1543 ret
= env
->scratch
[i
];
1546 case ASI_MMU
: /* UA2005 Context ID registers */
1547 switch ((addr
>> 3) & 0x3) {
1549 ret
= env
->dmmu
.mmu_primary_context
;
1552 ret
= env
->dmmu
.mmu_secondary_context
;
1555 sparc_raise_mmu_fault(cs
, addr
, true, false, 1, size
, GETPC());
1558 case ASI_DCACHE_DATA
: /* D-cache data */
1559 case ASI_DCACHE_TAG
: /* D-cache tag access */
1560 case ASI_ESTATE_ERROR_EN
: /* E-cache error enable */
1561 case ASI_AFSR
: /* E-cache asynchronous fault status */
1562 case ASI_AFAR
: /* E-cache asynchronous fault address */
1563 case ASI_EC_TAG_DATA
: /* E-cache tag data */
1564 case ASI_IC_INSTR
: /* I-cache instruction access */
1565 case ASI_IC_TAG
: /* I-cache tag access */
1566 case ASI_IC_PRE_DECODE
: /* I-cache predecode */
1567 case ASI_IC_NEXT_FIELD
: /* I-cache LRU etc. */
1568 case ASI_EC_W
: /* E-cache tag */
1569 case ASI_EC_R
: /* E-cache tag */
1571 case ASI_DMMU_TSB_DIRECT_PTR
: /* D-MMU data pointer */
1572 case ASI_ITLB_DATA_IN
: /* I-MMU data in, WO */
1573 case ASI_IMMU_DEMAP
: /* I-MMU demap, WO */
1574 case ASI_DTLB_DATA_IN
: /* D-MMU data in, WO */
1575 case ASI_DMMU_DEMAP
: /* D-MMU demap, WO */
1576 case ASI_INTR_W
: /* Interrupt vector, WO */
1578 sparc_raise_mmu_fault(cs
, addr
, false, false, 1, size
, GETPC());
1583 /* Convert to signed number */
1590 ret
= (int16_t) ret
;
1593 ret
= (int32_t) ret
;
1600 dump_asi("read ", last_addr
, asi
, size
, ret
);
1605 void helper_st_asi(CPUSPARCState
*env
, target_ulong addr
, target_ulong val
,
1606 int asi
, uint32_t memop
)
1608 int size
= 1 << (memop
& MO_SIZE
);
1609 CPUState
*cs
= env_cpu(env
);
1612 dump_asi("write", addr
, asi
, size
, val
);
1617 do_check_asi(env
, asi
, GETPC());
1618 do_check_align(env
, addr
, size
- 1, GETPC());
1619 addr
= asi_address_mask(env
, asi
, addr
);
1622 case ASI_AIUP
: /* As if user primary */
1623 case ASI_AIUS
: /* As if user secondary */
1624 case ASI_AIUPL
: /* As if user primary LE */
1625 case ASI_AIUSL
: /* As if user secondary LE */
1626 case ASI_P
: /* Primary */
1627 case ASI_S
: /* Secondary */
1628 case ASI_PL
: /* Primary LE */
1629 case ASI_SL
: /* Secondary LE */
1630 case ASI_REAL
: /* Bypass */
1631 case ASI_REAL_IO
: /* Bypass, non-cacheable */
1632 case ASI_REAL_L
: /* Bypass LE */
1633 case ASI_REAL_IO_L
: /* Bypass, non-cacheable LE */
1634 case ASI_N
: /* Nucleus */
1635 case ASI_NL
: /* Nucleus Little Endian (LE) */
1636 case ASI_NUCLEUS_QUAD_LDD
: /* Nucleus quad LDD 128 bit atomic */
1637 case ASI_NUCLEUS_QUAD_LDD_L
: /* Nucleus quad LDD 128 bit atomic LE */
1638 case ASI_TWINX_AIUP
: /* As if user primary, twinx */
1639 case ASI_TWINX_AIUS
: /* As if user secondary, twinx */
1640 case ASI_TWINX_REAL
: /* Real address, twinx */
1641 case ASI_TWINX_AIUP_L
: /* As if user primary, twinx, LE */
1642 case ASI_TWINX_AIUS_L
: /* As if user secondary, twinx, LE */
1643 case ASI_TWINX_REAL_L
: /* Real address, twinx, LE */
1644 case ASI_TWINX_N
: /* Nucleus, twinx */
1645 case ASI_TWINX_NL
: /* Nucleus, twinx, LE */
1646 /* ??? From the UA2011 document; overlaps BLK_INIT_QUAD_LDD_* */
1647 case ASI_TWINX_P
: /* Primary, twinx */
1648 case ASI_TWINX_PL
: /* Primary, twinx, LE */
1649 case ASI_TWINX_S
: /* Secondary, twinx */
1650 case ASI_TWINX_SL
: /* Secondary, twinx, LE */
1651 /* These are always handled inline. */
1652 g_assert_not_reached();
1653 /* these ASIs have different functions on UltraSPARC-IIIi
1654 * and UA2005 CPUs. Use the explicit numbers to avoid confusion
1660 if (cpu_has_hypervisor(env
)) {
1662 * ASI_DMMU_CTX_ZERO_TSB_BASE_PS0
1663 * ASI_DMMU_CTX_ZERO_TSB_BASE_PS1
1664 * ASI_DMMU_CTX_NONZERO_TSB_BASE_PS0
1665 * ASI_DMMU_CTX_NONZERO_TSB_BASE_PS1
1667 int idx
= ((asi
& 2) >> 1) | ((asi
& 8) >> 2);
1668 env
->dmmu
.sun4v_tsb_pointers
[idx
] = val
;
1670 helper_raise_exception(env
, TT_ILL_INSN
);
1675 if (cpu_has_hypervisor(env
)) {
1677 * ASI_DMMU_CTX_ZERO_CONFIG
1678 * ASI_DMMU_CTX_NONZERO_CONFIG
1680 env
->dmmu
.sun4v_ctx_config
[(asi
& 8) >> 3] = val
;
1682 helper_raise_exception(env
, TT_ILL_INSN
);
1689 if (cpu_has_hypervisor(env
)) {
1691 * ASI_IMMU_CTX_ZERO_TSB_BASE_PS0
1692 * ASI_IMMU_CTX_ZERO_TSB_BASE_PS1
1693 * ASI_IMMU_CTX_NONZERO_TSB_BASE_PS0
1694 * ASI_IMMU_CTX_NONZERO_TSB_BASE_PS1
1696 int idx
= ((asi
& 2) >> 1) | ((asi
& 8) >> 2);
1697 env
->immu
.sun4v_tsb_pointers
[idx
] = val
;
1699 helper_raise_exception(env
, TT_ILL_INSN
);
1704 if (cpu_has_hypervisor(env
)) {
1706 * ASI_IMMU_CTX_ZERO_CONFIG
1707 * ASI_IMMU_CTX_NONZERO_CONFIG
1709 env
->immu
.sun4v_ctx_config
[(asi
& 8) >> 3] = val
;
1711 helper_raise_exception(env
, TT_ILL_INSN
);
1714 case ASI_UPA_CONFIG
: /* UPA config */
1717 case ASI_LSU_CONTROL
: /* LSU */
1718 env
->lsu
= val
& (DMMU_E
| IMMU_E
);
1720 case ASI_IMMU
: /* I-MMU regs */
1722 int reg
= (addr
>> 3) & 0xf;
1725 oldreg
= env
->immu
.mmuregs
[reg
];
1729 case 1: /* Not in I-MMU */
1733 if ((val
& 1) == 0) {
1734 val
= 0; /* Clear SFSR */
1736 env
->immu
.sfsr
= val
;
1740 case 5: /* TSB access */
1741 DPRINTF_MMU("immu TSB write: 0x%016" PRIx64
" -> 0x%016"
1742 PRIx64
"\n", env
->immu
.tsb
, val
);
1743 env
->immu
.tsb
= val
;
1745 case 6: /* Tag access */
1746 env
->immu
.tag_access
= val
;
1752 sparc_raise_mmu_fault(cs
, addr
, true, false, 1, size
, GETPC());
1756 if (oldreg
!= env
->immu
.mmuregs
[reg
]) {
1757 DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64
" -> 0x%016"
1758 PRIx64
"\n", reg
, oldreg
, env
->immuregs
[reg
]);
1765 case ASI_ITLB_DATA_IN
: /* I-MMU data in */
1766 /* ignore real translation entries */
1767 if (!(addr
& TLB_UST1_IS_REAL_BIT
)) {
1768 replace_tlb_1bit_lru(env
->itlb
, env
->immu
.tag_access
,
1769 val
, "immu", env
, addr
);
1772 case ASI_ITLB_DATA_ACCESS
: /* I-MMU data access */
1774 /* TODO: auto demap */
1776 unsigned int i
= (addr
>> 3) & 0x3f;
1778 /* ignore real translation entries */
1779 if (!(addr
& TLB_UST1_IS_REAL_BIT
)) {
1780 replace_tlb_entry(&env
->itlb
[i
], env
->immu
.tag_access
,
1781 sun4v_tte_to_sun4u(env
, addr
, val
), env
);
1784 DPRINTF_MMU("immu data access replaced entry [%i]\n", i
);
1789 case ASI_IMMU_DEMAP
: /* I-MMU demap */
1790 demap_tlb(env
->itlb
, addr
, "immu", env
);
1792 case ASI_DMMU
: /* D-MMU regs */
1794 int reg
= (addr
>> 3) & 0xf;
1797 oldreg
= env
->dmmu
.mmuregs
[reg
];
1803 if ((val
& 1) == 0) {
1804 val
= 0; /* Clear SFSR, Fault address */
1807 env
->dmmu
.sfsr
= val
;
1809 case 1: /* Primary context */
1810 env
->dmmu
.mmu_primary_context
= val
;
1811 /* can be optimized to only flush MMU_USER_IDX
1812 and MMU_KERNEL_IDX entries */
1815 case 2: /* Secondary context */
1816 env
->dmmu
.mmu_secondary_context
= val
;
1817 /* can be optimized to only flush MMU_USER_SECONDARY_IDX
1818 and MMU_KERNEL_SECONDARY_IDX entries */
1821 case 5: /* TSB access */
1822 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64
" -> 0x%016"
1823 PRIx64
"\n", env
->dmmu
.tsb
, val
);
1824 env
->dmmu
.tsb
= val
;
1826 case 6: /* Tag access */
1827 env
->dmmu
.tag_access
= val
;
1829 case 7: /* Virtual Watchpoint */
1830 env
->dmmu
.virtual_watchpoint
= val
;
1832 case 8: /* Physical Watchpoint */
1833 env
->dmmu
.physical_watchpoint
= val
;
1836 sparc_raise_mmu_fault(cs
, addr
, true, false, 1, size
, GETPC());
1840 if (oldreg
!= env
->dmmu
.mmuregs
[reg
]) {
1841 DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64
" -> 0x%016"
1842 PRIx64
"\n", reg
, oldreg
, env
->dmmuregs
[reg
]);
1849 case ASI_DTLB_DATA_IN
: /* D-MMU data in */
1850 /* ignore real translation entries */
1851 if (!(addr
& TLB_UST1_IS_REAL_BIT
)) {
1852 replace_tlb_1bit_lru(env
->dtlb
, env
->dmmu
.tag_access
,
1853 val
, "dmmu", env
, addr
);
1856 case ASI_DTLB_DATA_ACCESS
: /* D-MMU data access */
1858 unsigned int i
= (addr
>> 3) & 0x3f;
1860 /* ignore real translation entries */
1861 if (!(addr
& TLB_UST1_IS_REAL_BIT
)) {
1862 replace_tlb_entry(&env
->dtlb
[i
], env
->dmmu
.tag_access
,
1863 sun4v_tte_to_sun4u(env
, addr
, val
), env
);
1866 DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i
);
1871 case ASI_DMMU_DEMAP
: /* D-MMU demap */
1872 demap_tlb(env
->dtlb
, addr
, "dmmu", env
);
1874 case ASI_INTR_RECEIVE
: /* Interrupt data receive */
1875 env
->ivec_status
= val
& 0x20;
1877 case ASI_SCRATCHPAD
: /* UA2005 privileged scratchpad */
1878 if (unlikely((addr
>= 0x20) && (addr
< 0x30))) {
1879 /* Hyperprivileged access only */
1880 sparc_raise_mmu_fault(cs
, addr
, true, false, 1, size
, GETPC());
1883 case ASI_HYP_SCRATCHPAD
: /* UA2005 hyperprivileged scratchpad */
1885 unsigned int i
= (addr
>> 3) & 0x7;
1886 env
->scratch
[i
] = val
;
1889 case ASI_MMU
: /* UA2005 Context ID registers */
1891 switch ((addr
>> 3) & 0x3) {
1893 env
->dmmu
.mmu_primary_context
= val
;
1894 env
->immu
.mmu_primary_context
= val
;
1895 tlb_flush_by_mmuidx(cs
,
1896 (1 << MMU_USER_IDX
) | (1 << MMU_KERNEL_IDX
));
1899 env
->dmmu
.mmu_secondary_context
= val
;
1900 env
->immu
.mmu_secondary_context
= val
;
1901 tlb_flush_by_mmuidx(cs
,
1902 (1 << MMU_USER_SECONDARY_IDX
) |
1903 (1 << MMU_KERNEL_SECONDARY_IDX
));
1906 sparc_raise_mmu_fault(cs
, addr
, true, false, 1, size
, GETPC());
1910 case ASI_QUEUE
: /* UA2005 CPU mondo queue */
1911 case ASI_DCACHE_DATA
: /* D-cache data */
1912 case ASI_DCACHE_TAG
: /* D-cache tag access */
1913 case ASI_ESTATE_ERROR_EN
: /* E-cache error enable */
1914 case ASI_AFSR
: /* E-cache asynchronous fault status */
1915 case ASI_AFAR
: /* E-cache asynchronous fault address */
1916 case ASI_EC_TAG_DATA
: /* E-cache tag data */
1917 case ASI_IC_INSTR
: /* I-cache instruction access */
1918 case ASI_IC_TAG
: /* I-cache tag access */
1919 case ASI_IC_PRE_DECODE
: /* I-cache predecode */
1920 case ASI_IC_NEXT_FIELD
: /* I-cache LRU etc. */
1921 case ASI_EC_W
: /* E-cache tag */
1922 case ASI_EC_R
: /* E-cache tag */
1924 case ASI_IMMU_TSB_8KB_PTR
: /* I-MMU 8k TSB pointer, RO */
1925 case ASI_IMMU_TSB_64KB_PTR
: /* I-MMU 64k TSB pointer, RO */
1926 case ASI_ITLB_TAG_READ
: /* I-MMU tag read, RO */
1927 case ASI_DMMU_TSB_8KB_PTR
: /* D-MMU 8k TSB pointer, RO */
1928 case ASI_DMMU_TSB_64KB_PTR
: /* D-MMU 64k TSB pointer, RO */
1929 case ASI_DMMU_TSB_DIRECT_PTR
: /* D-MMU data pointer, RO */
1930 case ASI_DTLB_TAG_READ
: /* D-MMU tag read, RO */
1931 case ASI_INTR_DISPATCH_STAT
: /* Interrupt dispatch, RO */
1932 case ASI_INTR_R
: /* Incoming interrupt vector, RO */
1933 case ASI_PNF
: /* Primary no-fault, RO */
1934 case ASI_SNF
: /* Secondary no-fault, RO */
1935 case ASI_PNFL
: /* Primary no-fault LE, RO */
1936 case ASI_SNFL
: /* Secondary no-fault LE, RO */
1938 sparc_raise_mmu_fault(cs
, addr
, true, false, 1, size
, GETPC());
1942 #endif /* CONFIG_USER_ONLY */
1943 #endif /* TARGET_SPARC64 */
1945 #if !defined(CONFIG_USER_ONLY)
1947 void sparc_cpu_do_transaction_failed(CPUState
*cs
, hwaddr physaddr
,
1948 vaddr addr
, unsigned size
,
1949 MMUAccessType access_type
,
1950 int mmu_idx
, MemTxAttrs attrs
,
1951 MemTxResult response
, uintptr_t retaddr
)
1953 bool is_write
= access_type
== MMU_DATA_STORE
;
1954 bool is_exec
= access_type
== MMU_INST_FETCH
;
1955 bool is_asi
= false;
1957 sparc_raise_mmu_fault(cs
, physaddr
, is_write
, is_exec
,
1958 is_asi
, size
, retaddr
);
1962 #if !defined(CONFIG_USER_ONLY)
1963 void QEMU_NORETURN
sparc_cpu_do_unaligned_access(CPUState
*cs
, vaddr addr
,
1964 MMUAccessType access_type
,
1968 SPARCCPU
*cpu
= SPARC_CPU(cs
);
1969 CPUSPARCState
*env
= &cpu
->env
;
1971 #ifdef DEBUG_UNALIGNED
1972 printf("Unaligned access to 0x" TARGET_FMT_lx
" from 0x" TARGET_FMT_lx
1973 "\n", addr
, env
->pc
);
1975 cpu_raise_exception_ra(env
, TT_UNALIGNED
, retaddr
);