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Merge remote-tracking branch 'qemu-project/master'
[qemu/ar7.git] / target / sparc / ldst_helper.c
blob2d48e98bf468e5b7df72a96a72dab78001d3c70a
1 /*
2 * Helpers for loads and stores
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu/log.h"
22 #include "cpu.h"
23 #include "tcg/tcg.h"
24 #include "exec/helper-proto.h"
25 #include "exec/exec-all.h"
26 #include "exec/page-protection.h"
27 #include "exec/cpu_ldst.h"
28 #include "asi.h"
29
30 //#define DEBUG_MMU
31 //#define DEBUG_MXCC
32 //#define DEBUG_UNASSIGNED
33 //#define DEBUG_ASI
34 //#define DEBUG_CACHE_CONTROL
35
36 #ifdef DEBUG_MMU
37 #define DPRINTF_MMU(fmt, ...) \
38 do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0)
39 #else
40 #define DPRINTF_MMU(fmt, ...) do {} while (0)
41 #endif
42
43 #ifdef DEBUG_MXCC
44 #define DPRINTF_MXCC(fmt, ...) \
45 do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0)
46 #else
47 #define DPRINTF_MXCC(fmt, ...) do {} while (0)
48 #endif
49
50 #ifdef DEBUG_ASI
51 #define DPRINTF_ASI(fmt, ...) \
52 do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0)
53 #endif
54
55 #ifdef DEBUG_CACHE_CONTROL
56 #define DPRINTF_CACHE_CONTROL(fmt, ...) \
57 do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0)
58 #else
59 #define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0)
60 #endif
61
62 #ifdef TARGET_SPARC64
63 #ifndef TARGET_ABI32
64 #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
65 #else
66 #define AM_CHECK(env1) (1)
67 #endif
68 #endif
69
70 #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
71 /* Calculates TSB pointer value for fault page size
72 * UltraSPARC IIi has fixed sizes (8k or 64k) for the page pointers
73 * UA2005 holds the page size configuration in mmu_ctx registers */
74 static uint64_t ultrasparc_tsb_pointer(CPUSPARCState *env,
75 const SparcV9MMU *mmu, const int idx)
76 {
77 uint64_t tsb_register;
78 int page_size;
79 if (cpu_has_hypervisor(env)) {
80 int tsb_index = 0;
81 int ctx = mmu->tag_access & 0x1fffULL;
82 uint64_t ctx_register = mmu->sun4v_ctx_config[ctx ? 1 : 0];
83 tsb_index = idx;
84 tsb_index |= ctx ? 2 : 0;
85 page_size = idx ? ctx_register >> 8 : ctx_register;
86 page_size &= 7;
87 tsb_register = mmu->sun4v_tsb_pointers[tsb_index];
88 } else {
89 page_size = idx;
90 tsb_register = mmu->tsb;
91 }
92 int tsb_split = (tsb_register & 0x1000ULL) ? 1 : 0;
93 int tsb_size = tsb_register & 0xf;
94
95 uint64_t tsb_base_mask = (~0x1fffULL) << tsb_size;
96
97 /* move va bits to correct position,
98 * the context bits will be masked out later */
99 uint64_t va = mmu->tag_access >> (3 * page_size + 9);
100
101 /* calculate tsb_base mask and adjust va if split is in use */
102 if (tsb_split) {
103 if (idx == 0) {
104 va &= ~(1ULL << (13 + tsb_size));
105 } else {
106 va |= (1ULL << (13 + tsb_size));
107 }
108 tsb_base_mask <<= 1;
109 }
110
111 return ((tsb_register & tsb_base_mask) | (va & ~tsb_base_mask)) & ~0xfULL;
112 }
113
114 /* Calculates tag target register value by reordering bits
115 in tag access register */
116 static uint64_t ultrasparc_tag_target(uint64_t tag_access_register)
117 {
118 return ((tag_access_register & 0x1fff) << 48) | (tag_access_register >> 22);
119 }
120
121 static void replace_tlb_entry(SparcTLBEntry *tlb,
122 uint64_t tlb_tag, uint64_t tlb_tte,
123 CPUSPARCState *env)
124 {
125 target_ulong mask, size, va, offset;
126
127 /* flush page range if translation is valid */
128 if (TTE_IS_VALID(tlb->tte)) {
129 CPUState *cs = env_cpu(env);
130
131 size = 8192ULL << 3 * TTE_PGSIZE(tlb->tte);
132 mask = 1ULL + ~size;
133
134 va = tlb->tag & mask;
135
136 for (offset = 0; offset < size; offset += TARGET_PAGE_SIZE) {
137 tlb_flush_page(cs, va + offset);
138 }
139 }
140
141 tlb->tag = tlb_tag;
142 tlb->tte = tlb_tte;
143 }
144
145 static void demap_tlb(SparcTLBEntry *tlb, target_ulong demap_addr,
146 const char *strmmu, CPUSPARCState *env1)
147 {
148 unsigned int i;
149 target_ulong mask;
150 uint64_t context;
151
152 int is_demap_context = (demap_addr >> 6) & 1;
153
154 /* demap context */
155 switch ((demap_addr >> 4) & 3) {
156 case 0: /* primary */
157 context = env1->dmmu.mmu_primary_context;
158 break;
159 case 1: /* secondary */
160 context = env1->dmmu.mmu_secondary_context;
161 break;
162 case 2: /* nucleus */
163 context = 0;
164 break;
165 case 3: /* reserved */
166 default:
167 return;
168 }
169
170 for (i = 0; i < 64; i++) {
171 if (TTE_IS_VALID(tlb[i].tte)) {
172
173 if (is_demap_context) {
174 /* will remove non-global entries matching context value */
175 if (TTE_IS_GLOBAL(tlb[i].tte) ||
176 !tlb_compare_context(&tlb[i], context)) {
177 continue;
178 }
179 } else {
180 /* demap page
181 will remove any entry matching VA */
182 mask = 0xffffffffffffe000ULL;
183 mask <<= 3 * ((tlb[i].tte >> 61) & 3);
184
185 if (!compare_masked(demap_addr, tlb[i].tag, mask)) {
186 continue;
187 }
188
189 /* entry should be global or matching context value */
190 if (!TTE_IS_GLOBAL(tlb[i].tte) &&
191 !tlb_compare_context(&tlb[i], context)) {
192 continue;
193 }
194 }
195
196 replace_tlb_entry(&tlb[i], 0, 0, env1);
197 #ifdef DEBUG_MMU
198 DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu, i);
199 dump_mmu(env1);
200 #endif
201 }
202 }
203 }
204
205 static uint64_t sun4v_tte_to_sun4u(CPUSPARCState *env, uint64_t tag,
206 uint64_t sun4v_tte)
207 {
208 uint64_t sun4u_tte;
209 if (!(cpu_has_hypervisor(env) && (tag & TLB_UST1_IS_SUN4V_BIT))) {
210 /* is already in the sun4u format */
211 return sun4v_tte;
212 }
213 sun4u_tte = TTE_PA(sun4v_tte) | (sun4v_tte & TTE_VALID_BIT);
214 sun4u_tte |= (sun4v_tte & 3ULL) << 61; /* TTE_PGSIZE */
215 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_NFO_BIT_UA2005, TTE_NFO_BIT);
216 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_USED_BIT_UA2005, TTE_USED_BIT);
217 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_W_OK_BIT_UA2005, TTE_W_OK_BIT);
218 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_SIDEEFFECT_BIT_UA2005,
219 TTE_SIDEEFFECT_BIT);
220 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_PRIV_BIT_UA2005, TTE_PRIV_BIT);
221 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_LOCKED_BIT_UA2005, TTE_LOCKED_BIT);
222 return sun4u_tte;
223 }
224
225 static void replace_tlb_1bit_lru(SparcTLBEntry *tlb,
226 uint64_t tlb_tag, uint64_t tlb_tte,
227 const char *strmmu, CPUSPARCState *env1,
228 uint64_t addr)
229 {
230 unsigned int i, replace_used;
231
232 tlb_tte = sun4v_tte_to_sun4u(env1, addr, tlb_tte);
233 if (cpu_has_hypervisor(env1)) {
234 uint64_t new_vaddr = tlb_tag & ~0x1fffULL;
235 uint64_t new_size = 8192ULL << 3 * TTE_PGSIZE(tlb_tte);
236 uint32_t new_ctx = tlb_tag & 0x1fffU;
237 for (i = 0; i < 64; i++) {
238 uint32_t ctx = tlb[i].tag & 0x1fffU;
239 /* check if new mapping overlaps an existing one */
240 if (new_ctx == ctx) {
241 uint64_t vaddr = tlb[i].tag & ~0x1fffULL;
242 uint64_t size = 8192ULL << 3 * TTE_PGSIZE(tlb[i].tte);
243 if (new_vaddr == vaddr
244 || (new_vaddr < vaddr + size
245 && vaddr < new_vaddr + new_size)) {
246 DPRINTF_MMU("auto demap entry [%d] %lx->%lx\n", i, vaddr,
247 new_vaddr);
248 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
249 return;
250 }
251 }
252
253 }
254 }
255 /* Try replacing invalid entry */
256 for (i = 0; i < 64; i++) {
257 if (!TTE_IS_VALID(tlb[i].tte)) {
258 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
259 #ifdef DEBUG_MMU
260 DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu, i);
261 dump_mmu(env1);
262 #endif
263 return;
264 }
265 }
266
267 /* All entries are valid, try replacing unlocked entry */
268
269 for (replace_used = 0; replace_used < 2; ++replace_used) {
270
271 /* Used entries are not replaced on first pass */
272
273 for (i = 0; i < 64; i++) {
274 if (!TTE_IS_LOCKED(tlb[i].tte) && !TTE_IS_USED(tlb[i].tte)) {
275
276 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
277 #ifdef DEBUG_MMU
278 DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n",
279 strmmu, (replace_used ? "used" : "unused"), i);
280 dump_mmu(env1);
281 #endif
282 return;
283 }
284 }
285
286 /* Now reset used bit and search for unused entries again */
287
288 for (i = 0; i < 64; i++) {
289 TTE_SET_UNUSED(tlb[i].tte);
290 }
291 }
292
293 #ifdef DEBUG_MMU
294 DPRINTF_MMU("%s lru replacement: no free entries available, "
295 "replacing the last one\n", strmmu);
296 #endif
297 /* corner case: the last entry is replaced anyway */
298 replace_tlb_entry(&tlb[63], tlb_tag, tlb_tte, env1);
299 }
300
301 #endif
302
303 #ifdef TARGET_SPARC64
304 /* returns true if access using this ASI is to have address translated by MMU
305 otherwise access is to raw physical address */
306 /* TODO: check sparc32 bits */
307 static inline int is_translating_asi(int asi)
308 {
309 /* Ultrasparc IIi translating asi
310 - note this list is defined by cpu implementation
311 */
312 switch (asi) {
313 case 0x04 ... 0x11:
314 case 0x16 ... 0x19:
315 case 0x1E ... 0x1F:
316 case 0x24 ... 0x2C:
317 case 0x70 ... 0x73:
318 case 0x78 ... 0x79:
319 case 0x80 ... 0xFF:
320 return 1;
321
322 default:
323 return 0;
324 }
325 }
326
327 static inline target_ulong address_mask(CPUSPARCState *env1, target_ulong addr)
328 {
329 if (AM_CHECK(env1)) {
330 addr &= 0xffffffffULL;
331 }
332 return addr;
333 }
334
335 static inline target_ulong asi_address_mask(CPUSPARCState *env,
336 int asi, target_ulong addr)
337 {
338 if (is_translating_asi(asi)) {
339 addr = address_mask(env, addr);
340 }
341 return addr;
342 }
343
344 #ifndef CONFIG_USER_ONLY
345 static inline void do_check_asi(CPUSPARCState *env, int asi, uintptr_t ra)
346 {
347 /* ASIs >= 0x80 are user mode.
348 * ASIs >= 0x30 are hyper mode (or super if hyper is not available).
349 * ASIs <= 0x2f are super mode.
350 */
351 if (asi < 0x80
352 && !cpu_hypervisor_mode(env)
353 && (!cpu_supervisor_mode(env)
354 || (asi >= 0x30 && cpu_has_hypervisor(env)))) {
355 cpu_raise_exception_ra(env, TT_PRIV_ACT, ra);
356 }
357 }
358 #endif /* !CONFIG_USER_ONLY */
359 #endif
360
361 #if defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)
362 static void do_check_align(CPUSPARCState *env, target_ulong addr,
363 uint32_t align, uintptr_t ra)
364 {
365 if (addr & align) {
366 cpu_raise_exception_ra(env, TT_UNALIGNED, ra);
367 }
368 }
369 #endif
370
371 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
372 defined(DEBUG_MXCC)
373 static void dump_mxcc(CPUSPARCState *env)
374 {
375 printf("mxccdata: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
376 "\n",
377 env->mxccdata[0], env->mxccdata[1],
378 env->mxccdata[2], env->mxccdata[3]);
379 printf("mxccregs: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
380 "\n"
381 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
382 "\n",
383 env->mxccregs[0], env->mxccregs[1],
384 env->mxccregs[2], env->mxccregs[3],
385 env->mxccregs[4], env->mxccregs[5],
386 env->mxccregs[6], env->mxccregs[7]);
387 }
388 #endif
389
390 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
391 && defined(DEBUG_ASI)
392 static void dump_asi(const char *txt, target_ulong addr, int asi, int size,
393 uint64_t r1)
394 {
395 switch (size) {
396 case 1:
397 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt,
398 addr, asi, r1 & 0xff);
399 break;
400 case 2:
401 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt,
402 addr, asi, r1 & 0xffff);
403 break;
404 case 4:
405 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt,
406 addr, asi, r1 & 0xffffffff);
407 break;
408 case 8:
409 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt,
410 addr, asi, r1);
411 break;
412 }
413 }
414 #endif
415
416 #ifndef CONFIG_USER_ONLY
417 #ifndef TARGET_SPARC64
418 static void sparc_raise_mmu_fault(CPUState *cs, hwaddr addr,
419 bool is_write, bool is_exec, int is_asi,
420 unsigned size, uintptr_t retaddr)
421 {
422 CPUSPARCState *env = cpu_env(cs);
423 int fault_type;
424
425 #ifdef DEBUG_UNASSIGNED
426 if (is_asi) {
427 printf("Unassigned mem %s access of %d byte%s to " HWADDR_FMT_plx
428 " asi 0x%02x from " TARGET_FMT_lx "\n",
429 is_exec ? "exec" : is_write ? "write" : "read", size,
430 size == 1 ? "" : "s", addr, is_asi, env->pc);
431 } else {
432 printf("Unassigned mem %s access of %d byte%s to " HWADDR_FMT_plx
433 " from " TARGET_FMT_lx "\n",
434 is_exec ? "exec" : is_write ? "write" : "read", size,
435 size == 1 ? "" : "s", addr, env->pc);
436 }
437 #endif
438 /* Don't overwrite translation and access faults */
439 fault_type = (env->mmuregs[3] & 0x1c) >> 2;
440 if ((fault_type > 4) || (fault_type == 0)) {
441 env->mmuregs[3] = 0; /* Fault status register */
442 if (is_asi) {
443 env->mmuregs[3] |= 1 << 16;
444 }
445 if (env->psrs) {
446 env->mmuregs[3] |= 1 << 5;
447 }
448 if (is_exec) {
449 env->mmuregs[3] |= 1 << 6;
450 }
451 if (is_write) {
452 env->mmuregs[3] |= 1 << 7;
453 }
454 env->mmuregs[3] |= (5 << 2) | 2;
455 /* SuperSPARC will never place instruction fault addresses in the FAR */
456 if (!is_exec) {
457 env->mmuregs[4] = addr; /* Fault address register */
458 }
459 }
460 /* overflow (same type fault was not read before another fault) */
461 if (fault_type == ((env->mmuregs[3] & 0x1c)) >> 2) {
462 env->mmuregs[3] |= 1;
463 }
464
465 if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) {
466 int tt = is_exec ? TT_CODE_ACCESS : TT_DATA_ACCESS;
467 cpu_raise_exception_ra(env, tt, retaddr);
468 }
469
470 /*
471 * flush neverland mappings created during no-fault mode,
472 * so the sequential MMU faults report proper fault types
473 */
474 if (env->mmuregs[0] & MMU_NF) {
475 tlb_flush(cs);
476 }
477 }
478 #else
479 static void sparc_raise_mmu_fault(CPUState *cs, hwaddr addr,
480 bool is_write, bool is_exec, int is_asi,
481 unsigned size, uintptr_t retaddr)
482 {
483 CPUSPARCState *env = cpu_env(cs);
484
485 #ifdef DEBUG_UNASSIGNED
486 printf("Unassigned mem access to " HWADDR_FMT_plx " from " TARGET_FMT_lx
487 "\n", addr, env->pc);
488 #endif
489
490 if (is_exec) { /* XXX has_hypervisor */
491 if (env->lsu & (IMMU_E)) {
492 cpu_raise_exception_ra(env, TT_CODE_ACCESS, retaddr);
493 } else if (cpu_has_hypervisor(env) && !(env->hpstate & HS_PRIV)) {
494 cpu_raise_exception_ra(env, TT_INSN_REAL_TRANSLATION_MISS, retaddr);
495 }
496 } else {
497 if (env->lsu & (DMMU_E)) {
498 cpu_raise_exception_ra(env, TT_DATA_ACCESS, retaddr);
499 } else if (cpu_has_hypervisor(env) && !(env->hpstate & HS_PRIV)) {
500 cpu_raise_exception_ra(env, TT_DATA_REAL_TRANSLATION_MISS, retaddr);
501 }
502 }
503 }
504 #endif
505 #endif
506
507 #ifndef TARGET_SPARC64
508 #ifndef CONFIG_USER_ONLY
509
510
511 /* Leon3 cache control */
512
513 static void leon3_cache_control_st(CPUSPARCState *env, target_ulong addr,
514 uint64_t val, int size)
515 {
516 DPRINTF_CACHE_CONTROL("st addr:%08x, val:%" PRIx64 ", size:%d\n",
517 addr, val, size);
518
519 if (size != 4) {
520 DPRINTF_CACHE_CONTROL("32bits only\n");
521 return;
522 }
523
524 switch (addr) {
525 case 0x00: /* Cache control */
526
527 /* These values must always be read as zeros */
528 val &= ~CACHE_CTRL_FD;
529 val &= ~CACHE_CTRL_FI;
530 val &= ~CACHE_CTRL_IB;
531 val &= ~CACHE_CTRL_IP;
532 val &= ~CACHE_CTRL_DP;
533
534 env->cache_control = val;
535 break;
536 case 0x04: /* Instruction cache configuration */
537 case 0x08: /* Data cache configuration */
538 /* Read Only */
539 break;
540 default:
541 DPRINTF_CACHE_CONTROL("write unknown register %08x\n", addr);
542 break;
543 };
544 }
545
546 static uint64_t leon3_cache_control_ld(CPUSPARCState *env, target_ulong addr,
547 int size)
548 {
549 uint64_t ret = 0;
550
551 if (size != 4) {
552 DPRINTF_CACHE_CONTROL("32bits only\n");
553 return 0;
554 }
555
556 switch (addr) {
557 case 0x00: /* Cache control */
558 ret = env->cache_control;
559 break;
560
561 /* Configuration registers are read and only always keep those
562 predefined values */
563
564 case 0x04: /* Instruction cache configuration */
565 ret = 0x10220000;
566 break;
567 case 0x08: /* Data cache configuration */
568 ret = 0x18220000;
569 break;
570 default:
571 DPRINTF_CACHE_CONTROL("read unknown register %08x\n", addr);
572 break;
573 };
574 DPRINTF_CACHE_CONTROL("ld addr:%08x, ret:0x%" PRIx64 ", size:%d\n",
575 addr, ret, size);
576 return ret;
577 }
578
579 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr,
580 int asi, uint32_t memop)
581 {
582 int size = 1 << (memop & MO_SIZE);
583 int sign = memop & MO_SIGN;
584 CPUState *cs = env_cpu(env);
585 uint64_t ret = 0;
586 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
587 uint32_t last_addr = addr;
588 #endif
589
590 do_check_align(env, addr, size - 1, GETPC());
591 switch (asi) {
592 case ASI_M_MXCC: /* SuperSparc MXCC registers, or... */
593 /* case ASI_LEON_CACHEREGS: Leon3 cache control */
594 switch (addr) {
595 case 0x00: /* Leon3 Cache Control */
596 case 0x08: /* Leon3 Instruction Cache config */
597 case 0x0C: /* Leon3 Date Cache config */
598 if (env->def.features & CPU_FEATURE_CACHE_CTRL) {
599 ret = leon3_cache_control_ld(env, addr, size);
600 }
601 break;
602 case 0x01c00a00: /* MXCC control register */
603 if (size == 8) {
604 ret = env->mxccregs[3];
605 } else {
606 qemu_log_mask(LOG_UNIMP,
607 "%08x: unimplemented access size: %d\n", addr,
608 size);
609 }
610 break;
611 case 0x01c00a04: /* MXCC control register */
612 if (size == 4) {
613 ret = env->mxccregs[3];
614 } else {
615 qemu_log_mask(LOG_UNIMP,
616 "%08x: unimplemented access size: %d\n", addr,
617 size);
618 }
619 break;
620 case 0x01c00c00: /* Module reset register */
621 if (size == 8) {
622 ret = env->mxccregs[5];
623 /* should we do something here? */
624 } else {
625 qemu_log_mask(LOG_UNIMP,
626 "%08x: unimplemented access size: %d\n", addr,
627 size);
628 }
629 break;
630 case 0x01c00f00: /* MBus port address register */
631 if (size == 8) {
632 ret = env->mxccregs[7];
633 } else {
634 qemu_log_mask(LOG_UNIMP,
635 "%08x: unimplemented access size: %d\n", addr,
636 size);
637 }
638 break;
639 default:
640 qemu_log_mask(LOG_UNIMP,
641 "%08x: unimplemented address, size: %d\n", addr,
642 size);
643 break;
644 }
645 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
646 "addr = %08x -> ret = %" PRIx64 ","
647 "addr = %08x\n", asi, size, sign, last_addr, ret, addr);
648 #ifdef DEBUG_MXCC
649 dump_mxcc(env);
650 #endif
651 break;
652 case ASI_M_FLUSH_PROBE: /* SuperSparc MMU probe */
653 case ASI_LEON_MMUFLUSH: /* LEON3 MMU probe */
654 {
655 int mmulev;
656
657 mmulev = (addr >> 8) & 15;
658 if (mmulev > 4) {
659 ret = 0;
660 } else {
661 ret = mmu_probe(env, addr, mmulev);
662 }
663 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n",
664 addr, mmulev, ret);
665 }
666 break;
667 case ASI_M_MMUREGS: /* SuperSparc MMU regs */
668 case ASI_LEON_MMUREGS: /* LEON3 MMU regs */
669 {
670 int reg = (addr >> 8) & 0x1f;
671
672 ret = env->mmuregs[reg];
673 if (reg == 3) { /* Fault status cleared on read */
674 env->mmuregs[3] = 0;
675 } else if (reg == 0x13) { /* Fault status read */
676 ret = env->mmuregs[3];
677 } else if (reg == 0x14) { /* Fault address read */
678 ret = env->mmuregs[4];
679 }
680 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret);
681 }
682 break;
683 case ASI_M_TLBDIAG: /* Turbosparc ITLB Diagnostic */
684 case ASI_M_DIAGS: /* Turbosparc DTLB Diagnostic */
685 case ASI_M_IODIAG: /* Turbosparc IOTLB Diagnostic */
686 break;
687 case ASI_M_TXTC_TAG: /* SparcStation 5 I-cache tag */
688 case ASI_M_TXTC_DATA: /* SparcStation 5 I-cache data */
689 case ASI_M_DATAC_TAG: /* SparcStation 5 D-cache tag */
690 case ASI_M_DATAC_DATA: /* SparcStation 5 D-cache data */
691 break;
692 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
693 {
694 MemTxResult result;
695 hwaddr access_addr = (hwaddr)addr | ((hwaddr)(asi & 0xf) << 32);
696
697 switch (size) {
698 case 1:
699 ret = address_space_ldub(cs->as, access_addr,
700 MEMTXATTRS_UNSPECIFIED, &result);
701 break;
702 case 2:
703 ret = address_space_lduw(cs->as, access_addr,
704 MEMTXATTRS_UNSPECIFIED, &result);
705 break;
706 default:
707 case 4:
708 ret = address_space_ldl(cs->as, access_addr,
709 MEMTXATTRS_UNSPECIFIED, &result);
710 break;
711 case 8:
712 ret = address_space_ldq(cs->as, access_addr,
713 MEMTXATTRS_UNSPECIFIED, &result);
714 break;
715 }
716
717 if (result != MEMTX_OK) {
718 sparc_raise_mmu_fault(cs, access_addr, false, false, false,
719 size, GETPC());
720 }
721 break;
722 }
723 case 0x30: /* Turbosparc secondary cache diagnostic */
724 case 0x31: /* Turbosparc RAM snoop */
725 case 0x32: /* Turbosparc page table descriptor diagnostic */
726 case 0x39: /* data cache diagnostic register */
727 ret = 0;
728 break;
729 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
730 {
731 int reg = (addr >> 8) & 3;
732
733 switch (reg) {
734 case 0: /* Breakpoint Value (Addr) */
735 ret = env->mmubpregs[reg];
736 break;
737 case 1: /* Breakpoint Mask */
738 ret = env->mmubpregs[reg];
739 break;
740 case 2: /* Breakpoint Control */
741 ret = env->mmubpregs[reg];
742 break;
743 case 3: /* Breakpoint Status */
744 ret = env->mmubpregs[reg];
745 env->mmubpregs[reg] = 0ULL;
746 break;
747 }
748 DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64 "\n", reg,
749 ret);
750 }
751 break;
752 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
753 ret = env->mmubpctrv;
754 break;
755 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
756 ret = env->mmubpctrc;
757 break;
758 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
759 ret = env->mmubpctrs;
760 break;
761 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
762 ret = env->mmubpaction;
763 break;
764 default:
765 sparc_raise_mmu_fault(cs, addr, false, false, asi, size, GETPC());
766 ret = 0;
767 break;
768
769 case ASI_USERDATA: /* User data access */
770 case ASI_KERNELDATA: /* Supervisor data access */
771 case ASI_USERTXT: /* User code access */
772 case ASI_KERNELTXT: /* Supervisor code access */
773 case ASI_P: /* Implicit primary context data access (v9 only?) */
774 case ASI_M_BYPASS: /* MMU passthrough */
775 case ASI_LEON_BYPASS: /* LEON MMU passthrough */
776 /* These are always handled inline. */
777 g_assert_not_reached();
778 }
779 if (sign) {
780 switch (size) {
781 case 1:
782 ret = (int8_t) ret;
783 break;
784 case 2:
785 ret = (int16_t) ret;
786 break;
787 case 4:
788 ret = (int32_t) ret;
789 break;
790 default:
791 break;
792 }
793 }
794 #ifdef DEBUG_ASI
795 dump_asi("read ", last_addr, asi, size, ret);
796 #endif
797 return ret;
798 }
799
800 void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val,
801 int asi, uint32_t memop)
802 {
803 int size = 1 << (memop & MO_SIZE);
804 CPUState *cs = env_cpu(env);
805
806 do_check_align(env, addr, size - 1, GETPC());
807 switch (asi) {
808 case ASI_M_MXCC: /* SuperSparc MXCC registers, or... */
809 /* case ASI_LEON_CACHEREGS: Leon3 cache control */
810 switch (addr) {
811 case 0x00: /* Leon3 Cache Control */
812 case 0x08: /* Leon3 Instruction Cache config */
813 case 0x0C: /* Leon3 Date Cache config */
814 if (env->def.features & CPU_FEATURE_CACHE_CTRL) {
815 leon3_cache_control_st(env, addr, val, size);
816 }
817 break;
818
819 case 0x01c00000: /* MXCC stream data register 0 */
820 if (size == 8) {
821 env->mxccdata[0] = val;
822 } else {
823 qemu_log_mask(LOG_UNIMP,
824 "%08x: unimplemented access size: %d\n", addr,
825 size);
826 }
827 break;
828 case 0x01c00008: /* MXCC stream data register 1 */
829 if (size == 8) {
830 env->mxccdata[1] = val;
831 } else {
832 qemu_log_mask(LOG_UNIMP,
833 "%08x: unimplemented access size: %d\n", addr,
834 size);
835 }
836 break;
837 case 0x01c00010: /* MXCC stream data register 2 */
838 if (size == 8) {
839 env->mxccdata[2] = val;
840 } else {
841 qemu_log_mask(LOG_UNIMP,
842 "%08x: unimplemented access size: %d\n", addr,
843 size);
844 }
845 break;
846 case 0x01c00018: /* MXCC stream data register 3 */
847 if (size == 8) {
848 env->mxccdata[3] = val;
849 } else {
850 qemu_log_mask(LOG_UNIMP,
851 "%08x: unimplemented access size: %d\n", addr,
852 size);
853 }
854 break;
855 case 0x01c00100: /* MXCC stream source */
856 {
857 int i;
858
859 if (size == 8) {
860 env->mxccregs[0] = val;
861 } else {
862 qemu_log_mask(LOG_UNIMP,
863 "%08x: unimplemented access size: %d\n", addr,
864 size);
865 }
866
867 for (i = 0; i < 4; i++) {
868 MemTxResult result;
869 hwaddr access_addr = (env->mxccregs[0] & 0xffffffffULL) + 8 * i;
870
871 env->mxccdata[i] = address_space_ldq(cs->as,
872 access_addr,
873 MEMTXATTRS_UNSPECIFIED,
874 &result);
875 if (result != MEMTX_OK) {
876 /* TODO: investigate whether this is the right behaviour */
877 sparc_raise_mmu_fault(cs, access_addr, false, false,
878 false, size, GETPC());
879 }
880 }
881 break;
882 }
883 case 0x01c00200: /* MXCC stream destination */
884 {
885 int i;
886
887 if (size == 8) {
888 env->mxccregs[1] = val;
889 } else {
890 qemu_log_mask(LOG_UNIMP,
891 "%08x: unimplemented access size: %d\n", addr,
892 size);
893 }
894
895 for (i = 0; i < 4; i++) {
896 MemTxResult result;
897 hwaddr access_addr = (env->mxccregs[1] & 0xffffffffULL) + 8 * i;
898
899 address_space_stq(cs->as, access_addr, env->mxccdata[i],
900 MEMTXATTRS_UNSPECIFIED, &result);
901
902 if (result != MEMTX_OK) {
903 /* TODO: investigate whether this is the right behaviour */
904 sparc_raise_mmu_fault(cs, access_addr, true, false,
905 false, size, GETPC());
906 }
907 }
908 break;
909 }
910 case 0x01c00a00: /* MXCC control register */
911 if (size == 8) {
912 env->mxccregs[3] = val;
913 } else {
914 qemu_log_mask(LOG_UNIMP,
915 "%08x: unimplemented access size: %d\n", addr,
916 size);
917 }
918 break;
919 case 0x01c00a04: /* MXCC control register */
920 if (size == 4) {
921 env->mxccregs[3] = (env->mxccregs[3] & 0xffffffff00000000ULL)
922 | val;
923 } else {
924 qemu_log_mask(LOG_UNIMP,
925 "%08x: unimplemented access size: %d\n", addr,
926 size);
927 }
928 break;
929 case 0x01c00e00: /* MXCC error register */
930 /* writing a 1 bit clears the error */
931 if (size == 8) {
932 env->mxccregs[6] &= ~val;
933 } else {
934 qemu_log_mask(LOG_UNIMP,
935 "%08x: unimplemented access size: %d\n", addr,
936 size);
937 }
938 break;
939 case 0x01c00f00: /* MBus port address register */
940 if (size == 8) {
941 env->mxccregs[7] = val;
942 } else {
943 qemu_log_mask(LOG_UNIMP,
944 "%08x: unimplemented access size: %d\n", addr,
945 size);
946 }
947 break;
948 default:
949 qemu_log_mask(LOG_UNIMP,
950 "%08x: unimplemented address, size: %d\n", addr,
951 size);
952 break;
953 }
954 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64 "\n",
955 asi, size, addr, val);
956 #ifdef DEBUG_MXCC
957 dump_mxcc(env);
958 #endif
959 break;
960 case ASI_M_FLUSH_PROBE: /* SuperSparc MMU flush */
961 case ASI_LEON_MMUFLUSH: /* LEON3 MMU flush */
962 {
963 int mmulev;
964
965 mmulev = (addr >> 8) & 15;
966 DPRINTF_MMU("mmu flush level %d\n", mmulev);
967 switch (mmulev) {
968 case 0: /* flush page */
969 tlb_flush_page(cs, addr & 0xfffff000);
970 break;
971 case 1: /* flush segment (256k) */
972 case 2: /* flush region (16M) */
973 case 3: /* flush context (4G) */
974 case 4: /* flush entire */
975 tlb_flush(cs);
976 break;
977 default:
978 break;
979 }
980 #ifdef DEBUG_MMU
981 dump_mmu(env);
982 #endif
983 }
984 break;
985 case ASI_M_MMUREGS: /* write MMU regs */
986 case ASI_LEON_MMUREGS: /* LEON3 write MMU regs */
987 {
988 int reg = (addr >> 8) & 0x1f;
989 uint32_t oldreg;
990
991 oldreg = env->mmuregs[reg];
992 switch (reg) {
993 case 0: /* Control Register */
994 env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |
995 (val & 0x00ffffff);
996 /* Mappings generated during no-fault mode
997 are invalid in normal mode. */
998 if ((oldreg ^ env->mmuregs[reg])
999 & (MMU_NF | env->def.mmu_bm)) {
1000 tlb_flush(cs);
1001 }
1002 break;
1003 case 1: /* Context Table Pointer Register */
1004 env->mmuregs[reg] = val & env->def.mmu_ctpr_mask;
1005 break;
1006 case 2: /* Context Register */
1007 env->mmuregs[reg] = val & env->def.mmu_cxr_mask;
1008 if (oldreg != env->mmuregs[reg]) {
1009 /* we flush when the MMU context changes because
1010 QEMU has no MMU context support */
1011 tlb_flush(cs);
1012 }
1013 break;
1014 case 3: /* Synchronous Fault Status Register with Clear */
1015 case 4: /* Synchronous Fault Address Register */
1016 break;
1017 case 0x10: /* TLB Replacement Control Register */
1018 env->mmuregs[reg] = val & env->def.mmu_trcr_mask;
1019 break;
1020 case 0x13: /* Synchronous Fault Status Register with Read
1021 and Clear */
1022 env->mmuregs[3] = val & env->def.mmu_sfsr_mask;
1023 break;
1024 case 0x14: /* Synchronous Fault Address Register */
1025 env->mmuregs[4] = val;
1026 break;
1027 default:
1028 env->mmuregs[reg] = val;
1029 break;
1030 }
1031 if (oldreg != env->mmuregs[reg]) {
1032 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
1033 reg, oldreg, env->mmuregs[reg]);
1034 }
1035 #ifdef DEBUG_MMU
1036 dump_mmu(env);
1037 #endif
1038 }
1039 break;
1040 case ASI_M_TLBDIAG: /* Turbosparc ITLB Diagnostic */
1041 case ASI_M_DIAGS: /* Turbosparc DTLB Diagnostic */
1042 case ASI_M_IODIAG: /* Turbosparc IOTLB Diagnostic */
1043 break;
1044 case ASI_M_TXTC_TAG: /* I-cache tag */
1045 case ASI_M_TXTC_DATA: /* I-cache data */
1046 case ASI_M_DATAC_TAG: /* D-cache tag */
1047 case ASI_M_DATAC_DATA: /* D-cache data */
1048 case ASI_M_FLUSH_PAGE: /* I/D-cache flush page */
1049 case ASI_M_FLUSH_SEG: /* I/D-cache flush segment */
1050 case ASI_M_FLUSH_REGION: /* I/D-cache flush region */
1051 case ASI_M_FLUSH_CTX: /* I/D-cache flush context */
1052 case ASI_M_FLUSH_USER: /* I/D-cache flush user */
1053 break;
1054 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1055 {
1056 MemTxResult result;
1057 hwaddr access_addr = (hwaddr)addr | ((hwaddr)(asi & 0xf) << 32);
1058
1059 switch (size) {
1060 case 1:
1061 address_space_stb(cs->as, access_addr, val,
1062 MEMTXATTRS_UNSPECIFIED, &result);
1063 break;
1064 case 2:
1065 address_space_stw(cs->as, access_addr, val,
1066 MEMTXATTRS_UNSPECIFIED, &result);
1067 break;
1068 case 4:
1069 default:
1070 address_space_stl(cs->as, access_addr, val,
1071 MEMTXATTRS_UNSPECIFIED, &result);
1072 break;
1073 case 8:
1074 address_space_stq(cs->as, access_addr, val,
1075 MEMTXATTRS_UNSPECIFIED, &result);
1076 break;
1077 }
1078 if (result != MEMTX_OK) {
1079 sparc_raise_mmu_fault(cs, access_addr, true, false, false,
1080 size, GETPC());
1081 }
1082 }
1083 break;
1084 case 0x30: /* store buffer tags or Turbosparc secondary cache diagnostic */
1085 case 0x31: /* store buffer data, Ross RT620 I-cache flush or
1086 Turbosparc snoop RAM */
1087 case 0x32: /* store buffer control or Turbosparc page table
1088 descriptor diagnostic */
1089 case 0x36: /* I-cache flash clear */
1090 case 0x37: /* D-cache flash clear */
1091 break;
1092 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
1093 {
1094 int reg = (addr >> 8) & 3;
1095
1096 switch (reg) {
1097 case 0: /* Breakpoint Value (Addr) */
1098 env->mmubpregs[reg] = (val & 0xfffffffffULL);
1099 break;
1100 case 1: /* Breakpoint Mask */
1101 env->mmubpregs[reg] = (val & 0xfffffffffULL);
1102 break;
1103 case 2: /* Breakpoint Control */
1104 env->mmubpregs[reg] = (val & 0x7fULL);
1105 break;
1106 case 3: /* Breakpoint Status */
1107 env->mmubpregs[reg] = (val & 0xfULL);
1108 break;
1109 }
1110 DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg,
1111 env->mmuregs[reg]);
1112 }
1113 break;
1114 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
1115 env->mmubpctrv = val & 0xffffffff;
1116 break;
1117 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
1118 env->mmubpctrc = val & 0x3;
1119 break;
1120 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
1121 env->mmubpctrs = val & 0x3;
1122 break;
1123 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
1124 env->mmubpaction = val & 0x1fff;
1125 break;
1126 case ASI_USERTXT: /* User code access, XXX */
1127 case ASI_KERNELTXT: /* Supervisor code access, XXX */
1128 default:
1129 sparc_raise_mmu_fault(cs, addr, true, false, asi, size, GETPC());
1130 break;
1131
1132 case ASI_USERDATA: /* User data access */
1133 case ASI_KERNELDATA: /* Supervisor data access */
1134 case ASI_P:
1135 case ASI_M_BYPASS: /* MMU passthrough */
1136 case ASI_LEON_BYPASS: /* LEON MMU passthrough */
1137 case ASI_M_BCOPY: /* Block copy, sta access */
1138 case ASI_M_BFILL: /* Block fill, stda access */
1139 /* These are always handled inline. */
1140 g_assert_not_reached();
1141 }
1142 #ifdef DEBUG_ASI
1143 dump_asi("write", addr, asi, size, val);
1144 #endif
1145 }
1146
1147 uint64_t helper_ld_code(CPUSPARCState *env, target_ulong addr, uint32_t oi)
1148 {
1149 MemOp mop = get_memop(oi);
1150 uintptr_t ra = GETPC();
1151 uint64_t ret;
1152
1153 switch (mop & MO_SIZE) {
1154 case MO_8:
1155 ret = cpu_ldb_code_mmu(env, addr, oi, ra);
1156 if (mop & MO_SIGN) {
1157 ret = (int8_t)ret;
1158 }
1159 break;
1160 case MO_16:
1161 ret = cpu_ldw_code_mmu(env, addr, oi, ra);
1162 if ((mop & MO_BSWAP) != MO_TE) {
1163 ret = bswap16(ret);
1164 }
1165 if (mop & MO_SIGN) {
1166 ret = (int16_t)ret;
1167 }
1168 break;
1169 case MO_32:
1170 ret = cpu_ldl_code_mmu(env, addr, oi, ra);
1171 if ((mop & MO_BSWAP) != MO_TE) {
1172 ret = bswap32(ret);
1173 }
1174 if (mop & MO_SIGN) {
1175 ret = (int32_t)ret;
1176 }
1177 break;
1178 case MO_64:
1179 ret = cpu_ldq_code_mmu(env, addr, oi, ra);
1180 if ((mop & MO_BSWAP) != MO_TE) {
1181 ret = bswap64(ret);
1182 }
1183 break;
1184 default:
1185 g_assert_not_reached();
1186 }
1187 return ret;
1188 }
1189
1190 #endif /* CONFIG_USER_ONLY */
1191 #else /* TARGET_SPARC64 */
1192
1193 #ifdef CONFIG_USER_ONLY
1194 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr,
1195 int asi, uint32_t memop)
1196 {
1197 int size = 1 << (memop & MO_SIZE);
1198 int sign = memop & MO_SIGN;
1199 uint64_t ret = 0;
1200
1201 if (asi < 0x80) {
1202 cpu_raise_exception_ra(env, TT_PRIV_ACT, GETPC());
1203 }
1204 do_check_align(env, addr, size - 1, GETPC());
1205 addr = asi_address_mask(env, asi, addr);
1206
1207 switch (asi) {
1208 case ASI_PNF: /* Primary no-fault */
1209 case ASI_PNFL: /* Primary no-fault LE */
1210 case ASI_SNF: /* Secondary no-fault */
1211 case ASI_SNFL: /* Secondary no-fault LE */
1212 if (!page_check_range(addr, size, PAGE_READ)) {
1213 ret = 0;
1214 break;
1215 }
1216 switch (size) {
1217 case 1:
1218 ret = cpu_ldub_data(env, addr);
1219 break;
1220 case 2:
1221 ret = cpu_lduw_data(env, addr);
1222 break;
1223 case 4:
1224 ret = cpu_ldl_data(env, addr);
1225 break;
1226 case 8:
1227 ret = cpu_ldq_data(env, addr);
1228 break;
1229 default:
1230 g_assert_not_reached();
1231 }
1232 break;
1233 break;
1234
1235 case ASI_P: /* Primary */
1236 case ASI_PL: /* Primary LE */
1237 case ASI_S: /* Secondary */
1238 case ASI_SL: /* Secondary LE */
1239 /* These are always handled inline. */
1240 g_assert_not_reached();
1241
1242 default:
1243 cpu_raise_exception_ra(env, TT_DATA_ACCESS, GETPC());
1244 }
1245
1246 /* Convert from little endian */
1247 switch (asi) {
1248 case ASI_PNFL: /* Primary no-fault LE */
1249 case ASI_SNFL: /* Secondary no-fault LE */
1250 switch (size) {
1251 case 2:
1252 ret = bswap16(ret);
1253 break;
1254 case 4:
1255 ret = bswap32(ret);
1256 break;
1257 case 8:
1258 ret = bswap64(ret);
1259 break;
1260 }
1261 }
1262
1263 /* Convert to signed number */
1264 if (sign) {
1265 switch (size) {
1266 case 1:
1267 ret = (int8_t) ret;
1268 break;
1269 case 2:
1270 ret = (int16_t) ret;
1271 break;
1272 case 4:
1273 ret = (int32_t) ret;
1274 break;
1275 }
1276 }
1277 #ifdef DEBUG_ASI
1278 dump_asi("read", addr, asi, size, ret);
1279 #endif
1280 return ret;
1281 }
1282
1283 void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
1284 int asi, uint32_t memop)
1285 {
1286 int size = 1 << (memop & MO_SIZE);
1287 #ifdef DEBUG_ASI
1288 dump_asi("write", addr, asi, size, val);
1289 #endif
1290 if (asi < 0x80) {
1291 cpu_raise_exception_ra(env, TT_PRIV_ACT, GETPC());
1292 }
1293 do_check_align(env, addr, size - 1, GETPC());
1294
1295 switch (asi) {
1296 case ASI_P: /* Primary */
1297 case ASI_PL: /* Primary LE */
1298 case ASI_S: /* Secondary */
1299 case ASI_SL: /* Secondary LE */
1300 /* These are always handled inline. */
1301 g_assert_not_reached();
1302
1303 case ASI_PNF: /* Primary no-fault, RO */
1304 case ASI_SNF: /* Secondary no-fault, RO */
1305 case ASI_PNFL: /* Primary no-fault LE, RO */
1306 case ASI_SNFL: /* Secondary no-fault LE, RO */
1307 default:
1308 cpu_raise_exception_ra(env, TT_DATA_ACCESS, GETPC());
1309 }
1310 }
1311
1312 #else /* CONFIG_USER_ONLY */
1313
1314 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr,
1315 int asi, uint32_t memop)
1316 {
1317 int size = 1 << (memop & MO_SIZE);
1318 int sign = memop & MO_SIGN;
1319 CPUState *cs = env_cpu(env);
1320 uint64_t ret = 0;
1321 #if defined(DEBUG_ASI)
1322 target_ulong last_addr = addr;
1323 #endif
1324
1325 asi &= 0xff;
1326
1327 do_check_asi(env, asi, GETPC());
1328 do_check_align(env, addr, size - 1, GETPC());
1329 addr = asi_address_mask(env, asi, addr);
1330
1331 switch (asi) {
1332 case ASI_PNF:
1333 case ASI_PNFL:
1334 case ASI_SNF:
1335 case ASI_SNFL:
1336 {
1337 MemOpIdx oi;
1338 int idx = (env->pstate & PS_PRIV
1339 ? (asi & 1 ? MMU_KERNEL_SECONDARY_IDX : MMU_KERNEL_IDX)
1340 : (asi & 1 ? MMU_USER_SECONDARY_IDX : MMU_USER_IDX));
1341
1342 if (cpu_get_phys_page_nofault(env, addr, idx) == -1ULL) {
1343 #ifdef DEBUG_ASI
1344 dump_asi("read ", last_addr, asi, size, ret);
1345 #endif
1346 /* exception_index is set in get_physical_address_data. */
1347 cpu_raise_exception_ra(env, cs->exception_index, GETPC());
1348 }
1349 oi = make_memop_idx(memop, idx);
1350 switch (size) {
1351 case 1:
1352 ret = cpu_ldb_mmu(env, addr, oi, GETPC());
1353 break;
1354 case 2:
1355 ret = cpu_ldw_mmu(env, addr, oi, GETPC());
1356 break;
1357 case 4:
1358 ret = cpu_ldl_mmu(env, addr, oi, GETPC());
1359 break;
1360 case 8:
1361 ret = cpu_ldq_mmu(env, addr, oi, GETPC());
1362 break;
1363 default:
1364 g_assert_not_reached();
1365 }
1366 }
1367 break;
1368
1369 case ASI_AIUP: /* As if user primary */
1370 case ASI_AIUS: /* As if user secondary */
1371 case ASI_AIUPL: /* As if user primary LE */
1372 case ASI_AIUSL: /* As if user secondary LE */
1373 case ASI_P: /* Primary */
1374 case ASI_S: /* Secondary */
1375 case ASI_PL: /* Primary LE */
1376 case ASI_SL: /* Secondary LE */
1377 case ASI_REAL: /* Bypass */
1378 case ASI_REAL_IO: /* Bypass, non-cacheable */
1379 case ASI_REAL_L: /* Bypass LE */
1380 case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */
1381 case ASI_N: /* Nucleus */
1382 case ASI_NL: /* Nucleus Little Endian (LE) */
1383 case ASI_NUCLEUS_QUAD_LDD: /* Nucleus quad LDD 128 bit atomic */
1384 case ASI_NUCLEUS_QUAD_LDD_L: /* Nucleus quad LDD 128 bit atomic LE */
1385 case ASI_TWINX_AIUP: /* As if user primary, twinx */
1386 case ASI_TWINX_AIUS: /* As if user secondary, twinx */
1387 case ASI_TWINX_REAL: /* Real address, twinx */
1388 case ASI_TWINX_AIUP_L: /* As if user primary, twinx, LE */
1389 case ASI_TWINX_AIUS_L: /* As if user secondary, twinx, LE */
1390 case ASI_TWINX_REAL_L: /* Real address, twinx, LE */
1391 case ASI_TWINX_N: /* Nucleus, twinx */
1392 case ASI_TWINX_NL: /* Nucleus, twinx, LE */
1393 /* ??? From the UA2011 document; overlaps BLK_INIT_QUAD_LDD_* */
1394 case ASI_TWINX_P: /* Primary, twinx */
1395 case ASI_TWINX_PL: /* Primary, twinx, LE */
1396 case ASI_TWINX_S: /* Secondary, twinx */
1397 case ASI_TWINX_SL: /* Secondary, twinx, LE */
1398 case ASI_MON_P:
1399 case ASI_MON_S:
1400 case ASI_MON_AIUP:
1401 case ASI_MON_AIUS:
1402 /* These are always handled inline. */
1403 g_assert_not_reached();
1404
1405 case ASI_UPA_CONFIG: /* UPA config */
1406 /* XXX */
1407 break;
1408 case ASI_LSU_CONTROL: /* LSU */
1409 ret = env->lsu;
1410 break;
1411 case ASI_IMMU: /* I-MMU regs */
1412 {
1413 int reg = (addr >> 3) & 0xf;
1414 switch (reg) {
1415 case 0:
1416 /* 0x00 I-TSB Tag Target register */
1417 ret = ultrasparc_tag_target(env->immu.tag_access);
1418 break;
1419 case 3: /* SFSR */
1420 ret = env->immu.sfsr;
1421 break;
1422 case 5: /* TSB access */
1423 ret = env->immu.tsb;
1424 break;
1425 case 6:
1426 /* 0x30 I-TSB Tag Access register */
1427 ret = env->immu.tag_access;
1428 break;
1429 default:
1430 sparc_raise_mmu_fault(cs, addr, false, false, 1, size, GETPC());
1431 ret = 0;
1432 }
1433 break;
1434 }
1435 case ASI_IMMU_TSB_8KB_PTR: /* I-MMU 8k TSB pointer */
1436 {
1437 /* env->immuregs[5] holds I-MMU TSB register value
1438 env->immuregs[6] holds I-MMU Tag Access register value */
1439 ret = ultrasparc_tsb_pointer(env, &env->immu, 0);
1440 break;
1441 }
1442 case ASI_IMMU_TSB_64KB_PTR: /* I-MMU 64k TSB pointer */
1443 {
1444 /* env->immuregs[5] holds I-MMU TSB register value
1445 env->immuregs[6] holds I-MMU Tag Access register value */
1446 ret = ultrasparc_tsb_pointer(env, &env->immu, 1);
1447 break;
1448 }
1449 case ASI_ITLB_DATA_ACCESS: /* I-MMU data access */
1450 {
1451 int reg = (addr >> 3) & 0x3f;
1452
1453 ret = env->itlb[reg].tte;
1454 break;
1455 }
1456 case ASI_ITLB_TAG_READ: /* I-MMU tag read */
1457 {
1458 int reg = (addr >> 3) & 0x3f;
1459
1460 ret = env->itlb[reg].tag;
1461 break;
1462 }
1463 case ASI_DMMU: /* D-MMU regs */
1464 {
1465 int reg = (addr >> 3) & 0xf;
1466 switch (reg) {
1467 case 0:
1468 /* 0x00 D-TSB Tag Target register */
1469 ret = ultrasparc_tag_target(env->dmmu.tag_access);
1470 break;
1471 case 1: /* 0x08 Primary Context */
1472 ret = env->dmmu.mmu_primary_context;
1473 break;
1474 case 2: /* 0x10 Secondary Context */
1475 ret = env->dmmu.mmu_secondary_context;
1476 break;
1477 case 3: /* SFSR */
1478 ret = env->dmmu.sfsr;
1479 break;
1480 case 4: /* 0x20 SFAR */
1481 ret = env->dmmu.sfar;
1482 break;
1483 case 5: /* 0x28 TSB access */
1484 ret = env->dmmu.tsb;
1485 break;
1486 case 6: /* 0x30 D-TSB Tag Access register */
1487 ret = env->dmmu.tag_access;
1488 break;
1489 case 7:
1490 ret = env->dmmu.virtual_watchpoint;
1491 break;
1492 case 8:
1493 ret = env->dmmu.physical_watchpoint;
1494 break;
1495 default:
1496 sparc_raise_mmu_fault(cs, addr, false, false, 1, size, GETPC());
1497 ret = 0;
1498 }
1499 break;
1500 }
1501 case ASI_DMMU_TSB_8KB_PTR: /* D-MMU 8k TSB pointer */
1502 {
1503 /* env->dmmuregs[5] holds D-MMU TSB register value
1504 env->dmmuregs[6] holds D-MMU Tag Access register value */
1505 ret = ultrasparc_tsb_pointer(env, &env->dmmu, 0);
1506 break;
1507 }
1508 case ASI_DMMU_TSB_64KB_PTR: /* D-MMU 64k TSB pointer */
1509 {
1510 /* env->dmmuregs[5] holds D-MMU TSB register value
1511 env->dmmuregs[6] holds D-MMU Tag Access register value */
1512 ret = ultrasparc_tsb_pointer(env, &env->dmmu, 1);
1513 break;
1514 }
1515 case ASI_DTLB_DATA_ACCESS: /* D-MMU data access */
1516 {
1517 int reg = (addr >> 3) & 0x3f;
1518
1519 ret = env->dtlb[reg].tte;
1520 break;
1521 }
1522 case ASI_DTLB_TAG_READ: /* D-MMU tag read */
1523 {
1524 int reg = (addr >> 3) & 0x3f;
1525
1526 ret = env->dtlb[reg].tag;
1527 break;
1528 }
1529 case ASI_INTR_DISPATCH_STAT: /* Interrupt dispatch, RO */
1530 break;
1531 case ASI_INTR_RECEIVE: /* Interrupt data receive */
1532 ret = env->ivec_status;
1533 break;
1534 case ASI_INTR_R: /* Incoming interrupt vector, RO */
1535 {
1536 int reg = (addr >> 4) & 0x3;
1537 if (reg < 3) {
1538 ret = env->ivec_data[reg];
1539 }
1540 break;
1541 }
1542 case ASI_SCRATCHPAD: /* UA2005 privileged scratchpad */
1543 if (unlikely((addr >= 0x20) && (addr < 0x30))) {
1544 /* Hyperprivileged access only */
1545 sparc_raise_mmu_fault(cs, addr, false, false, 1, size, GETPC());
1546 }
1547 /* fall through */
1548 case ASI_HYP_SCRATCHPAD: /* UA2005 hyperprivileged scratchpad */
1549 {
1550 unsigned int i = (addr >> 3) & 0x7;
1551 ret = env->scratch[i];
1552 break;
1553 }
1554 case ASI_MMU: /* UA2005 Context ID registers */
1555 switch ((addr >> 3) & 0x3) {
1556 case 1:
1557 ret = env->dmmu.mmu_primary_context;
1558 break;
1559 case 2:
1560 ret = env->dmmu.mmu_secondary_context;
1561 break;
1562 default:
1563 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC());
1564 }
1565 break;
1566 case ASI_DCACHE_DATA: /* D-cache data */
1567 case ASI_DCACHE_TAG: /* D-cache tag access */
1568 case ASI_ESTATE_ERROR_EN: /* E-cache error enable */
1569 case ASI_AFSR: /* E-cache asynchronous fault status */
1570 case ASI_AFAR: /* E-cache asynchronous fault address */
1571 case ASI_EC_TAG_DATA: /* E-cache tag data */
1572 case ASI_IC_INSTR: /* I-cache instruction access */
1573 case ASI_IC_TAG: /* I-cache tag access */
1574 case ASI_IC_PRE_DECODE: /* I-cache predecode */
1575 case ASI_IC_NEXT_FIELD: /* I-cache LRU etc. */
1576 case ASI_EC_W: /* E-cache tag */
1577 case ASI_EC_R: /* E-cache tag */
1578 break;
1579 case ASI_DMMU_TSB_DIRECT_PTR: /* D-MMU data pointer */
1580 case ASI_ITLB_DATA_IN: /* I-MMU data in, WO */
1581 case ASI_IMMU_DEMAP: /* I-MMU demap, WO */
1582 case ASI_DTLB_DATA_IN: /* D-MMU data in, WO */
1583 case ASI_DMMU_DEMAP: /* D-MMU demap, WO */
1584 case ASI_INTR_W: /* Interrupt vector, WO */
1585 default:
1586 sparc_raise_mmu_fault(cs, addr, false, false, 1, size, GETPC());
1587 ret = 0;
1588 break;
1589 }
1590
1591 /* Convert to signed number */
1592 if (sign) {
1593 switch (size) {
1594 case 1:
1595 ret = (int8_t) ret;
1596 break;
1597 case 2:
1598 ret = (int16_t) ret;
1599 break;
1600 case 4:
1601 ret = (int32_t) ret;
1602 break;
1603 default:
1604 break;
1605 }
1606 }
1607 #ifdef DEBUG_ASI
1608 dump_asi("read ", last_addr, asi, size, ret);
1609 #endif
1610 return ret;
1611 }
1612
1613 void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
1614 int asi, uint32_t memop)
1615 {
1616 int size = 1 << (memop & MO_SIZE);
1617 CPUState *cs = env_cpu(env);
1618
1619 #ifdef DEBUG_ASI
1620 dump_asi("write", addr, asi, size, val);
1621 #endif
1622
1623 asi &= 0xff;
1624
1625 do_check_asi(env, asi, GETPC());
1626 do_check_align(env, addr, size - 1, GETPC());
1627 addr = asi_address_mask(env, asi, addr);
1628
1629 switch (asi) {
1630 case ASI_AIUP: /* As if user primary */
1631 case ASI_AIUS: /* As if user secondary */
1632 case ASI_AIUPL: /* As if user primary LE */
1633 case ASI_AIUSL: /* As if user secondary LE */
1634 case ASI_P: /* Primary */
1635 case ASI_S: /* Secondary */
1636 case ASI_PL: /* Primary LE */
1637 case ASI_SL: /* Secondary LE */
1638 case ASI_REAL: /* Bypass */
1639 case ASI_REAL_IO: /* Bypass, non-cacheable */
1640 case ASI_REAL_L: /* Bypass LE */
1641 case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */
1642 case ASI_N: /* Nucleus */
1643 case ASI_NL: /* Nucleus Little Endian (LE) */
1644 case ASI_NUCLEUS_QUAD_LDD: /* Nucleus quad LDD 128 bit atomic */
1645 case ASI_NUCLEUS_QUAD_LDD_L: /* Nucleus quad LDD 128 bit atomic LE */
1646 case ASI_TWINX_AIUP: /* As if user primary, twinx */
1647 case ASI_TWINX_AIUS: /* As if user secondary, twinx */
1648 case ASI_TWINX_REAL: /* Real address, twinx */
1649 case ASI_TWINX_AIUP_L: /* As if user primary, twinx, LE */
1650 case ASI_TWINX_AIUS_L: /* As if user secondary, twinx, LE */
1651 case ASI_TWINX_REAL_L: /* Real address, twinx, LE */
1652 case ASI_TWINX_N: /* Nucleus, twinx */
1653 case ASI_TWINX_NL: /* Nucleus, twinx, LE */
1654 /* ??? From the UA2011 document; overlaps BLK_INIT_QUAD_LDD_* */
1655 case ASI_TWINX_P: /* Primary, twinx */
1656 case ASI_TWINX_PL: /* Primary, twinx, LE */
1657 case ASI_TWINX_S: /* Secondary, twinx */
1658 case ASI_TWINX_SL: /* Secondary, twinx, LE */
1659 /* These are always handled inline. */
1660 g_assert_not_reached();
1661 /* these ASIs have different functions on UltraSPARC-IIIi
1662 * and UA2005 CPUs. Use the explicit numbers to avoid confusion
1663 */
1664 case 0x31:
1665 case 0x32:
1666 case 0x39:
1667 case 0x3a:
1668 if (cpu_has_hypervisor(env)) {
1669 /* UA2005
1670 * ASI_DMMU_CTX_ZERO_TSB_BASE_PS0
1671 * ASI_DMMU_CTX_ZERO_TSB_BASE_PS1
1672 * ASI_DMMU_CTX_NONZERO_TSB_BASE_PS0
1673 * ASI_DMMU_CTX_NONZERO_TSB_BASE_PS1
1674 */
1675 int idx = ((asi & 2) >> 1) | ((asi & 8) >> 2);
1676 env->dmmu.sun4v_tsb_pointers[idx] = val;
1677 } else {
1678 goto illegal_insn;
1679 }
1680 break;
1681 case 0x33:
1682 case 0x3b:
1683 if (cpu_has_hypervisor(env)) {
1684 /* UA2005
1685 * ASI_DMMU_CTX_ZERO_CONFIG
1686 * ASI_DMMU_CTX_NONZERO_CONFIG
1687 */
1688 env->dmmu.sun4v_ctx_config[(asi & 8) >> 3] = val;
1689 } else {
1690 goto illegal_insn;
1691 }
1692 break;
1693 case 0x35:
1694 case 0x36:
1695 case 0x3d:
1696 case 0x3e:
1697 if (cpu_has_hypervisor(env)) {
1698 /* UA2005
1699 * ASI_IMMU_CTX_ZERO_TSB_BASE_PS0
1700 * ASI_IMMU_CTX_ZERO_TSB_BASE_PS1
1701 * ASI_IMMU_CTX_NONZERO_TSB_BASE_PS0
1702 * ASI_IMMU_CTX_NONZERO_TSB_BASE_PS1
1703 */
1704 int idx = ((asi & 2) >> 1) | ((asi & 8) >> 2);
1705 env->immu.sun4v_tsb_pointers[idx] = val;
1706 } else {
1707 goto illegal_insn;
1708 }
1709 break;
1710 case 0x37:
1711 case 0x3f:
1712 if (cpu_has_hypervisor(env)) {
1713 /* UA2005
1714 * ASI_IMMU_CTX_ZERO_CONFIG
1715 * ASI_IMMU_CTX_NONZERO_CONFIG
1716 */
1717 env->immu.sun4v_ctx_config[(asi & 8) >> 3] = val;
1718 } else {
1719 goto illegal_insn;
1720 }
1721 break;
1722 case ASI_UPA_CONFIG: /* UPA config */
1723 /* XXX */
1724 return;
1725 case ASI_LSU_CONTROL: /* LSU */
1726 env->lsu = val & (DMMU_E | IMMU_E);
1727 return;
1728 case ASI_IMMU: /* I-MMU regs */
1729 {
1730 int reg = (addr >> 3) & 0xf;
1731 uint64_t oldreg;
1732
1733 oldreg = env->immu.mmuregs[reg];
1734 switch (reg) {
1735 case 0: /* RO */
1736 return;
1737 case 1: /* Not in I-MMU */
1738 case 2:
1739 return;
1740 case 3: /* SFSR */
1741 if ((val & 1) == 0) {
1742 val = 0; /* Clear SFSR */
1743 }
1744 env->immu.sfsr = val;
1745 break;
1746 case 4: /* RO */
1747 return;
1748 case 5: /* TSB access */
1749 DPRINTF_MMU("immu TSB write: 0x%016" PRIx64 " -> 0x%016"
1750 PRIx64 "\n", env->immu.tsb, val);
1751 env->immu.tsb = val;
1752 break;
1753 case 6: /* Tag access */
1754 env->immu.tag_access = val;
1755 break;
1756 case 7:
1757 case 8:
1758 return;
1759 default:
1760 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC());
1761 break;
1762 }
1763
1764 if (oldreg != env->immu.mmuregs[reg]) {
1765 DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
1766 PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
1767 }
1768 #ifdef DEBUG_MMU
1769 dump_mmu(env);
1770 #endif
1771 return;
1772 }
1773 case ASI_ITLB_DATA_IN: /* I-MMU data in */
1774 /* ignore real translation entries */
1775 if (!(addr & TLB_UST1_IS_REAL_BIT)) {
1776 replace_tlb_1bit_lru(env->itlb, env->immu.tag_access,
1777 val, "immu", env, addr);
1778 }
1779 return;
1780 case ASI_ITLB_DATA_ACCESS: /* I-MMU data access */
1781 {
1782 /* TODO: auto demap */
1783
1784 unsigned int i = (addr >> 3) & 0x3f;
1785
1786 /* ignore real translation entries */
1787 if (!(addr & TLB_UST1_IS_REAL_BIT)) {
1788 replace_tlb_entry(&env->itlb[i], env->immu.tag_access,
1789 sun4v_tte_to_sun4u(env, addr, val), env);
1790 }
1791 #ifdef DEBUG_MMU
1792 DPRINTF_MMU("immu data access replaced entry [%i]\n", i);
1793 dump_mmu(env);
1794 #endif
1795 return;
1796 }
1797 case ASI_IMMU_DEMAP: /* I-MMU demap */
1798 demap_tlb(env->itlb, addr, "immu", env);
1799 return;
1800 case ASI_DMMU: /* D-MMU regs */
1801 {
1802 int reg = (addr >> 3) & 0xf;
1803 uint64_t oldreg;
1804
1805 oldreg = env->dmmu.mmuregs[reg];
1806 switch (reg) {
1807 case 0: /* RO */
1808 case 4:
1809 return;
1810 case 3: /* SFSR */
1811 if ((val & 1) == 0) {
1812 val = 0; /* Clear SFSR, Fault address */
1813 env->dmmu.sfar = 0;
1814 }
1815 env->dmmu.sfsr = val;
1816 break;
1817 case 1: /* Primary context */
1818 env->dmmu.mmu_primary_context = val;
1819 /* can be optimized to only flush MMU_USER_IDX
1820 and MMU_KERNEL_IDX entries */
1821 tlb_flush(cs);
1822 break;
1823 case 2: /* Secondary context */
1824 env->dmmu.mmu_secondary_context = val;
1825 /* can be optimized to only flush MMU_USER_SECONDARY_IDX
1826 and MMU_KERNEL_SECONDARY_IDX entries */
1827 tlb_flush(cs);
1828 break;
1829 case 5: /* TSB access */
1830 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016"
1831 PRIx64 "\n", env->dmmu.tsb, val);
1832 env->dmmu.tsb = val;
1833 break;
1834 case 6: /* Tag access */
1835 env->dmmu.tag_access = val;
1836 break;
1837 case 7: /* Virtual Watchpoint */
1838 env->dmmu.virtual_watchpoint = val;
1839 break;
1840 case 8: /* Physical Watchpoint */
1841 env->dmmu.physical_watchpoint = val;
1842 break;
1843 default:
1844 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC());
1845 break;
1846 }
1847
1848 if (oldreg != env->dmmu.mmuregs[reg]) {
1849 DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
1850 PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
1851 }
1852 #ifdef DEBUG_MMU
1853 dump_mmu(env);
1854 #endif
1855 return;
1856 }
1857 case ASI_DTLB_DATA_IN: /* D-MMU data in */
1858 /* ignore real translation entries */
1859 if (!(addr & TLB_UST1_IS_REAL_BIT)) {
1860 replace_tlb_1bit_lru(env->dtlb, env->dmmu.tag_access,
1861 val, "dmmu", env, addr);
1862 }
1863 return;
1864 case ASI_DTLB_DATA_ACCESS: /* D-MMU data access */
1865 {
1866 unsigned int i = (addr >> 3) & 0x3f;
1867
1868 /* ignore real translation entries */
1869 if (!(addr & TLB_UST1_IS_REAL_BIT)) {
1870 replace_tlb_entry(&env->dtlb[i], env->dmmu.tag_access,
1871 sun4v_tte_to_sun4u(env, addr, val), env);
1872 }
1873 #ifdef DEBUG_MMU
1874 DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i);
1875 dump_mmu(env);
1876 #endif
1877 return;
1878 }
1879 case ASI_DMMU_DEMAP: /* D-MMU demap */
1880 demap_tlb(env->dtlb, addr, "dmmu", env);
1881 return;
1882 case ASI_INTR_RECEIVE: /* Interrupt data receive */
1883 env->ivec_status = val & 0x20;
1884 return;
1885 case ASI_SCRATCHPAD: /* UA2005 privileged scratchpad */
1886 if (unlikely((addr >= 0x20) && (addr < 0x30))) {
1887 /* Hyperprivileged access only */
1888 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC());
1889 }
1890 /* fall through */
1891 case ASI_HYP_SCRATCHPAD: /* UA2005 hyperprivileged scratchpad */
1892 {
1893 unsigned int i = (addr >> 3) & 0x7;
1894 env->scratch[i] = val;
1895 return;
1896 }
1897 case ASI_MMU: /* UA2005 Context ID registers */
1898 {
1899 switch ((addr >> 3) & 0x3) {
1900 case 1:
1901 env->dmmu.mmu_primary_context = val;
1902 env->immu.mmu_primary_context = val;
1903 tlb_flush_by_mmuidx(cs,
1904 (1 << MMU_USER_IDX) | (1 << MMU_KERNEL_IDX));
1905 break;
1906 case 2:
1907 env->dmmu.mmu_secondary_context = val;
1908 env->immu.mmu_secondary_context = val;
1909 tlb_flush_by_mmuidx(cs,
1910 (1 << MMU_USER_SECONDARY_IDX) |
1911 (1 << MMU_KERNEL_SECONDARY_IDX));
1912 break;
1913 default:
1914 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC());
1915 }
1916 }
1917 return;
1918 case ASI_QUEUE: /* UA2005 CPU mondo queue */
1919 case ASI_DCACHE_DATA: /* D-cache data */
1920 case ASI_DCACHE_TAG: /* D-cache tag access */
1921 case ASI_ESTATE_ERROR_EN: /* E-cache error enable */
1922 case ASI_AFSR: /* E-cache asynchronous fault status */
1923 case ASI_AFAR: /* E-cache asynchronous fault address */
1924 case ASI_EC_TAG_DATA: /* E-cache tag data */
1925 case ASI_IC_INSTR: /* I-cache instruction access */
1926 case ASI_IC_TAG: /* I-cache tag access */
1927 case ASI_IC_PRE_DECODE: /* I-cache predecode */
1928 case ASI_IC_NEXT_FIELD: /* I-cache LRU etc. */
1929 case ASI_EC_W: /* E-cache tag */
1930 case ASI_EC_R: /* E-cache tag */
1931 return;
1932 case ASI_IMMU_TSB_8KB_PTR: /* I-MMU 8k TSB pointer, RO */
1933 case ASI_IMMU_TSB_64KB_PTR: /* I-MMU 64k TSB pointer, RO */
1934 case ASI_ITLB_TAG_READ: /* I-MMU tag read, RO */
1935 case ASI_DMMU_TSB_8KB_PTR: /* D-MMU 8k TSB pointer, RO */
1936 case ASI_DMMU_TSB_64KB_PTR: /* D-MMU 64k TSB pointer, RO */
1937 case ASI_DMMU_TSB_DIRECT_PTR: /* D-MMU data pointer, RO */
1938 case ASI_DTLB_TAG_READ: /* D-MMU tag read, RO */
1939 case ASI_INTR_DISPATCH_STAT: /* Interrupt dispatch, RO */
1940 case ASI_INTR_R: /* Incoming interrupt vector, RO */
1941 case ASI_PNF: /* Primary no-fault, RO */
1942 case ASI_SNF: /* Secondary no-fault, RO */
1943 case ASI_PNFL: /* Primary no-fault LE, RO */
1944 case ASI_SNFL: /* Secondary no-fault LE, RO */
1945 default:
1946 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC());
1947 return;
1948 illegal_insn:
1949 cpu_raise_exception_ra(env, TT_ILL_INSN, GETPC());
1950 }
1951 }
1952 #endif /* CONFIG_USER_ONLY */
1953 #endif /* TARGET_SPARC64 */
1954
1955 #if !defined(CONFIG_USER_ONLY)
1956
1957 void sparc_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
1958 vaddr addr, unsigned size,
1959 MMUAccessType access_type,
1960 int mmu_idx, MemTxAttrs attrs,
1961 MemTxResult response, uintptr_t retaddr)
1962 {
1963 bool is_write = access_type == MMU_DATA_STORE;
1964 bool is_exec = access_type == MMU_INST_FETCH;
1965 bool is_asi = false;
1966
1967 sparc_raise_mmu_fault(cs, physaddr, is_write, is_exec,
1968 is_asi, size, retaddr);
1969 }
1970 #endif
AR7 emulation for QEMU