hw/arm/virt: fix max-cpus check
[qemu/ar7.git] / hw / intc / arm_gic.c
blob60ab9b858b15fbe39938a9ea1c8586e0641e4adb
1 /*
2 * ARM Generic/Distributed Interrupt Controller
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
8 */
10 /* This file contains implementation code for the RealView EB interrupt
11 * controller, MPCore distributed interrupt controller and ARMv7-M
12 * Nested Vectored Interrupt Controller.
13 * It is compiled in two ways:
14 * (1) as a standalone file to produce a sysbus device which is a GIC
15 * that can be used on the realview board and as one of the builtin
16 * private peripherals for the ARM MP CPUs (11MPCore, A9, etc)
17 * (2) by being directly #included into armv7m_nvic.c to produce the
18 * armv7m_nvic device.
21 #include "qemu/osdep.h"
22 #include "hw/sysbus.h"
23 #include "gic_internal.h"
24 #include "qom/cpu.h"
26 //#define DEBUG_GIC
28 #ifdef DEBUG_GIC
29 #define DPRINTF(fmt, ...) \
30 do { fprintf(stderr, "arm_gic: " fmt , ## __VA_ARGS__); } while (0)
31 #else
32 #define DPRINTF(fmt, ...) do {} while(0)
33 #endif
35 static const uint8_t gic_id_11mpcore[] = {
36 0x00, 0x00, 0x00, 0x00, 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1
39 static const uint8_t gic_id_gicv1[] = {
40 0x04, 0x00, 0x00, 0x00, 0x90, 0xb3, 0x1b, 0x00, 0x0d, 0xf0, 0x05, 0xb1
43 static const uint8_t gic_id_gicv2[] = {
44 0x04, 0x00, 0x00, 0x00, 0x90, 0xb4, 0x2b, 0x00, 0x0d, 0xf0, 0x05, 0xb1
47 static inline int gic_get_current_cpu(GICState *s)
49 if (s->num_cpu > 1) {
50 return current_cpu->cpu_index;
52 return 0;
55 /* Return true if this GIC config has interrupt groups, which is
56 * true if we're a GICv2, or a GICv1 with the security extensions.
58 static inline bool gic_has_groups(GICState *s)
60 return s->revision == 2 || s->security_extn;
63 /* TODO: Many places that call this routine could be optimized. */
64 /* Update interrupt status after enabled or pending bits have been changed. */
65 void gic_update(GICState *s)
67 int best_irq;
68 int best_prio;
69 int irq;
70 int irq_level, fiq_level;
71 int cpu;
72 int cm;
74 for (cpu = 0; cpu < s->num_cpu; cpu++) {
75 cm = 1 << cpu;
76 s->current_pending[cpu] = 1023;
77 if (!(s->ctlr & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1))
78 || !(s->cpu_ctlr[cpu] & (GICC_CTLR_EN_GRP0 | GICC_CTLR_EN_GRP1))) {
79 qemu_irq_lower(s->parent_irq[cpu]);
80 qemu_irq_lower(s->parent_fiq[cpu]);
81 continue;
83 best_prio = 0x100;
84 best_irq = 1023;
85 for (irq = 0; irq < s->num_irq; irq++) {
86 if (GIC_TEST_ENABLED(irq, cm) && gic_test_pending(s, irq, cm) &&
87 (irq < GIC_INTERNAL || GIC_TARGET(irq) & cm)) {
88 if (GIC_GET_PRIORITY(irq, cpu) < best_prio) {
89 best_prio = GIC_GET_PRIORITY(irq, cpu);
90 best_irq = irq;
95 irq_level = fiq_level = 0;
97 if (best_prio < s->priority_mask[cpu]) {
98 s->current_pending[cpu] = best_irq;
99 if (best_prio < s->running_priority[cpu]) {
100 int group = GIC_TEST_GROUP(best_irq, cm);
102 if (extract32(s->ctlr, group, 1) &&
103 extract32(s->cpu_ctlr[cpu], group, 1)) {
104 if (group == 0 && s->cpu_ctlr[cpu] & GICC_CTLR_FIQ_EN) {
105 DPRINTF("Raised pending FIQ %d (cpu %d)\n",
106 best_irq, cpu);
107 fiq_level = 1;
108 } else {
109 DPRINTF("Raised pending IRQ %d (cpu %d)\n",
110 best_irq, cpu);
111 irq_level = 1;
117 qemu_set_irq(s->parent_irq[cpu], irq_level);
118 qemu_set_irq(s->parent_fiq[cpu], fiq_level);
122 void gic_set_pending_private(GICState *s, int cpu, int irq)
124 int cm = 1 << cpu;
126 if (gic_test_pending(s, irq, cm)) {
127 return;
130 DPRINTF("Set %d pending cpu %d\n", irq, cpu);
131 GIC_SET_PENDING(irq, cm);
132 gic_update(s);
135 static void gic_set_irq_11mpcore(GICState *s, int irq, int level,
136 int cm, int target)
138 if (level) {
139 GIC_SET_LEVEL(irq, cm);
140 if (GIC_TEST_EDGE_TRIGGER(irq) || GIC_TEST_ENABLED(irq, cm)) {
141 DPRINTF("Set %d pending mask %x\n", irq, target);
142 GIC_SET_PENDING(irq, target);
144 } else {
145 GIC_CLEAR_LEVEL(irq, cm);
149 static void gic_set_irq_generic(GICState *s, int irq, int level,
150 int cm, int target)
152 if (level) {
153 GIC_SET_LEVEL(irq, cm);
154 DPRINTF("Set %d pending mask %x\n", irq, target);
155 if (GIC_TEST_EDGE_TRIGGER(irq)) {
156 GIC_SET_PENDING(irq, target);
158 } else {
159 GIC_CLEAR_LEVEL(irq, cm);
163 /* Process a change in an external IRQ input. */
164 static void gic_set_irq(void *opaque, int irq, int level)
166 /* Meaning of the 'irq' parameter:
167 * [0..N-1] : external interrupts
168 * [N..N+31] : PPI (internal) interrupts for CPU 0
169 * [N+32..N+63] : PPI (internal interrupts for CPU 1
170 * ...
172 GICState *s = (GICState *)opaque;
173 int cm, target;
174 if (irq < (s->num_irq - GIC_INTERNAL)) {
175 /* The first external input line is internal interrupt 32. */
176 cm = ALL_CPU_MASK;
177 irq += GIC_INTERNAL;
178 target = GIC_TARGET(irq);
179 } else {
180 int cpu;
181 irq -= (s->num_irq - GIC_INTERNAL);
182 cpu = irq / GIC_INTERNAL;
183 irq %= GIC_INTERNAL;
184 cm = 1 << cpu;
185 target = cm;
188 assert(irq >= GIC_NR_SGIS);
190 if (level == GIC_TEST_LEVEL(irq, cm)) {
191 return;
194 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) {
195 gic_set_irq_11mpcore(s, irq, level, cm, target);
196 } else {
197 gic_set_irq_generic(s, irq, level, cm, target);
200 gic_update(s);
203 static uint16_t gic_get_current_pending_irq(GICState *s, int cpu,
204 MemTxAttrs attrs)
206 uint16_t pending_irq = s->current_pending[cpu];
208 if (pending_irq < GIC_MAXIRQ && gic_has_groups(s)) {
209 int group = GIC_TEST_GROUP(pending_irq, (1 << cpu));
210 /* On a GIC without the security extensions, reading this register
211 * behaves in the same way as a secure access to a GIC with them.
213 bool secure = !s->security_extn || attrs.secure;
215 if (group == 0 && !secure) {
216 /* Group0 interrupts hidden from Non-secure access */
217 return 1023;
219 if (group == 1 && secure && !(s->cpu_ctlr[cpu] & GICC_CTLR_ACK_CTL)) {
220 /* Group1 interrupts only seen by Secure access if
221 * AckCtl bit set.
223 return 1022;
226 return pending_irq;
229 static int gic_get_group_priority(GICState *s, int cpu, int irq)
231 /* Return the group priority of the specified interrupt
232 * (which is the top bits of its priority, with the number
233 * of bits masked determined by the applicable binary point register).
235 int bpr;
236 uint32_t mask;
238 if (gic_has_groups(s) &&
239 !(s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) &&
240 GIC_TEST_GROUP(irq, (1 << cpu))) {
241 bpr = s->abpr[cpu];
242 } else {
243 bpr = s->bpr[cpu];
246 /* a BPR of 0 means the group priority bits are [7:1];
247 * a BPR of 1 means they are [7:2], and so on down to
248 * a BPR of 7 meaning no group priority bits at all.
250 mask = ~0U << ((bpr & 7) + 1);
252 return GIC_GET_PRIORITY(irq, cpu) & mask;
255 static void gic_activate_irq(GICState *s, int cpu, int irq)
257 /* Set the appropriate Active Priority Register bit for this IRQ,
258 * and update the running priority.
260 int prio = gic_get_group_priority(s, cpu, irq);
261 int preemption_level = prio >> (GIC_MIN_BPR + 1);
262 int regno = preemption_level / 32;
263 int bitno = preemption_level % 32;
265 if (gic_has_groups(s) && GIC_TEST_GROUP(irq, (1 << cpu))) {
266 s->nsapr[regno][cpu] |= (1 << bitno);
267 } else {
268 s->apr[regno][cpu] |= (1 << bitno);
271 s->running_priority[cpu] = prio;
272 GIC_SET_ACTIVE(irq, 1 << cpu);
275 static int gic_get_prio_from_apr_bits(GICState *s, int cpu)
277 /* Recalculate the current running priority for this CPU based
278 * on the set bits in the Active Priority Registers.
280 int i;
281 for (i = 0; i < GIC_NR_APRS; i++) {
282 uint32_t apr = s->apr[i][cpu] | s->nsapr[i][cpu];
283 if (!apr) {
284 continue;
286 return (i * 32 + ctz32(apr)) << (GIC_MIN_BPR + 1);
288 return 0x100;
291 static void gic_drop_prio(GICState *s, int cpu, int group)
293 /* Drop the priority of the currently active interrupt in the
294 * specified group.
296 * Note that we can guarantee (because of the requirement to nest
297 * GICC_IAR reads [which activate an interrupt and raise priority]
298 * with GICC_EOIR writes [which drop the priority for the interrupt])
299 * that the interrupt we're being called for is the highest priority
300 * active interrupt, meaning that it has the lowest set bit in the
301 * APR registers.
303 * If the guest does not honour the ordering constraints then the
304 * behaviour of the GIC is UNPREDICTABLE, which for us means that
305 * the values of the APR registers might become incorrect and the
306 * running priority will be wrong, so interrupts that should preempt
307 * might not do so, and interrupts that should not preempt might do so.
309 int i;
311 for (i = 0; i < GIC_NR_APRS; i++) {
312 uint32_t *papr = group ? &s->nsapr[i][cpu] : &s->apr[i][cpu];
313 if (!*papr) {
314 continue;
316 /* Clear lowest set bit */
317 *papr &= *papr - 1;
318 break;
321 s->running_priority[cpu] = gic_get_prio_from_apr_bits(s, cpu);
324 uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs)
326 int ret, irq, src;
327 int cm = 1 << cpu;
329 /* gic_get_current_pending_irq() will return 1022 or 1023 appropriately
330 * for the case where this GIC supports grouping and the pending interrupt
331 * is in the wrong group.
333 irq = gic_get_current_pending_irq(s, cpu, attrs);
335 if (irq >= GIC_MAXIRQ) {
336 DPRINTF("ACK, no pending interrupt or it is hidden: %d\n", irq);
337 return irq;
340 if (GIC_GET_PRIORITY(irq, cpu) >= s->running_priority[cpu]) {
341 DPRINTF("ACK, pending interrupt (%d) has insufficient priority\n", irq);
342 return 1023;
345 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) {
346 /* Clear pending flags for both level and edge triggered interrupts.
347 * Level triggered IRQs will be reasserted once they become inactive.
349 GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm);
350 ret = irq;
351 } else {
352 if (irq < GIC_NR_SGIS) {
353 /* Lookup the source CPU for the SGI and clear this in the
354 * sgi_pending map. Return the src and clear the overall pending
355 * state on this CPU if the SGI is not pending from any CPUs.
357 assert(s->sgi_pending[irq][cpu] != 0);
358 src = ctz32(s->sgi_pending[irq][cpu]);
359 s->sgi_pending[irq][cpu] &= ~(1 << src);
360 if (s->sgi_pending[irq][cpu] == 0) {
361 GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm);
363 ret = irq | ((src & 0x7) << 10);
364 } else {
365 /* Clear pending state for both level and edge triggered
366 * interrupts. (level triggered interrupts with an active line
367 * remain pending, see gic_test_pending)
369 GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm);
370 ret = irq;
374 gic_activate_irq(s, cpu, irq);
375 gic_update(s);
376 DPRINTF("ACK %d\n", irq);
377 return ret;
380 void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val,
381 MemTxAttrs attrs)
383 if (s->security_extn && !attrs.secure) {
384 if (!GIC_TEST_GROUP(irq, (1 << cpu))) {
385 return; /* Ignore Non-secure access of Group0 IRQ */
387 val = 0x80 | (val >> 1); /* Non-secure view */
390 if (irq < GIC_INTERNAL) {
391 s->priority1[irq][cpu] = val;
392 } else {
393 s->priority2[(irq) - GIC_INTERNAL] = val;
397 static uint32_t gic_get_priority(GICState *s, int cpu, int irq,
398 MemTxAttrs attrs)
400 uint32_t prio = GIC_GET_PRIORITY(irq, cpu);
402 if (s->security_extn && !attrs.secure) {
403 if (!GIC_TEST_GROUP(irq, (1 << cpu))) {
404 return 0; /* Non-secure access cannot read priority of Group0 IRQ */
406 prio = (prio << 1) & 0xff; /* Non-secure view */
408 return prio;
411 static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask,
412 MemTxAttrs attrs)
414 if (s->security_extn && !attrs.secure) {
415 if (s->priority_mask[cpu] & 0x80) {
416 /* Priority Mask in upper half */
417 pmask = 0x80 | (pmask >> 1);
418 } else {
419 /* Non-secure write ignored if priority mask is in lower half */
420 return;
423 s->priority_mask[cpu] = pmask;
426 static uint32_t gic_get_priority_mask(GICState *s, int cpu, MemTxAttrs attrs)
428 uint32_t pmask = s->priority_mask[cpu];
430 if (s->security_extn && !attrs.secure) {
431 if (pmask & 0x80) {
432 /* Priority Mask in upper half, return Non-secure view */
433 pmask = (pmask << 1) & 0xff;
434 } else {
435 /* Priority Mask in lower half, RAZ */
436 pmask = 0;
439 return pmask;
442 static uint32_t gic_get_cpu_control(GICState *s, int cpu, MemTxAttrs attrs)
444 uint32_t ret = s->cpu_ctlr[cpu];
446 if (s->security_extn && !attrs.secure) {
447 /* Construct the NS banked view of GICC_CTLR from the correct
448 * bits of the S banked view. We don't need to move the bypass
449 * control bits because we don't implement that (IMPDEF) part
450 * of the GIC architecture.
452 ret = (ret & (GICC_CTLR_EN_GRP1 | GICC_CTLR_EOIMODE_NS)) >> 1;
454 return ret;
457 static void gic_set_cpu_control(GICState *s, int cpu, uint32_t value,
458 MemTxAttrs attrs)
460 uint32_t mask;
462 if (s->security_extn && !attrs.secure) {
463 /* The NS view can only write certain bits in the register;
464 * the rest are unchanged
466 mask = GICC_CTLR_EN_GRP1;
467 if (s->revision == 2) {
468 mask |= GICC_CTLR_EOIMODE_NS;
470 s->cpu_ctlr[cpu] &= ~mask;
471 s->cpu_ctlr[cpu] |= (value << 1) & mask;
472 } else {
473 if (s->revision == 2) {
474 mask = s->security_extn ? GICC_CTLR_V2_S_MASK : GICC_CTLR_V2_MASK;
475 } else {
476 mask = s->security_extn ? GICC_CTLR_V1_S_MASK : GICC_CTLR_V1_MASK;
478 s->cpu_ctlr[cpu] = value & mask;
480 DPRINTF("CPU Interface %d: Group0 Interrupts %sabled, "
481 "Group1 Interrupts %sabled\n", cpu,
482 (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP0) ? "En" : "Dis",
483 (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP1) ? "En" : "Dis");
486 static uint8_t gic_get_running_priority(GICState *s, int cpu, MemTxAttrs attrs)
488 if (s->security_extn && !attrs.secure) {
489 if (s->running_priority[cpu] & 0x80) {
490 /* Running priority in upper half of range: return the Non-secure
491 * view of the priority.
493 return s->running_priority[cpu] << 1;
494 } else {
495 /* Running priority in lower half of range: RAZ */
496 return 0;
498 } else {
499 return s->running_priority[cpu];
503 void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
505 int cm = 1 << cpu;
506 int group;
508 DPRINTF("EOI %d\n", irq);
509 if (irq >= s->num_irq) {
510 /* This handles two cases:
511 * 1. If software writes the ID of a spurious interrupt [ie 1023]
512 * to the GICC_EOIR, the GIC ignores that write.
513 * 2. If software writes the number of a non-existent interrupt
514 * this must be a subcase of "value written does not match the last
515 * valid interrupt value read from the Interrupt Acknowledge
516 * register" and so this is UNPREDICTABLE. We choose to ignore it.
518 return;
520 if (s->running_priority[cpu] == 0x100) {
521 return; /* No active IRQ. */
524 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) {
525 /* Mark level triggered interrupts as pending if they are still
526 raised. */
527 if (!GIC_TEST_EDGE_TRIGGER(irq) && GIC_TEST_ENABLED(irq, cm)
528 && GIC_TEST_LEVEL(irq, cm) && (GIC_TARGET(irq) & cm) != 0) {
529 DPRINTF("Set %d pending mask %x\n", irq, cm);
530 GIC_SET_PENDING(irq, cm);
534 group = gic_has_groups(s) && GIC_TEST_GROUP(irq, cm);
536 if (s->security_extn && !attrs.secure && !group) {
537 DPRINTF("Non-secure EOI for Group0 interrupt %d ignored\n", irq);
538 return;
541 /* Secure EOI with GICC_CTLR.AckCtl == 0 when the IRQ is a Group 1
542 * interrupt is UNPREDICTABLE. We choose to handle it as if AckCtl == 1,
543 * i.e. go ahead and complete the irq anyway.
546 gic_drop_prio(s, cpu, group);
547 GIC_CLEAR_ACTIVE(irq, cm);
548 gic_update(s);
551 static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
553 GICState *s = (GICState *)opaque;
554 uint32_t res;
555 int irq;
556 int i;
557 int cpu;
558 int cm;
559 int mask;
561 cpu = gic_get_current_cpu(s);
562 cm = 1 << cpu;
563 if (offset < 0x100) {
564 if (offset == 0) { /* GICD_CTLR */
565 if (s->security_extn && !attrs.secure) {
566 /* The NS bank of this register is just an alias of the
567 * EnableGrp1 bit in the S bank version.
569 return extract32(s->ctlr, 1, 1);
570 } else {
571 return s->ctlr;
574 if (offset == 4)
575 /* Interrupt Controller Type Register */
576 return ((s->num_irq / 32) - 1)
577 | ((s->num_cpu - 1) << 5)
578 | (s->security_extn << 10);
579 if (offset < 0x08)
580 return 0;
581 if (offset >= 0x80) {
582 /* Interrupt Group Registers: these RAZ/WI if this is an NS
583 * access to a GIC with the security extensions, or if the GIC
584 * doesn't have groups at all.
586 res = 0;
587 if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) {
588 /* Every byte offset holds 8 group status bits */
589 irq = (offset - 0x080) * 8 + GIC_BASE_IRQ;
590 if (irq >= s->num_irq) {
591 goto bad_reg;
593 for (i = 0; i < 8; i++) {
594 if (GIC_TEST_GROUP(irq + i, cm)) {
595 res |= (1 << i);
599 return res;
601 goto bad_reg;
602 } else if (offset < 0x200) {
603 /* Interrupt Set/Clear Enable. */
604 if (offset < 0x180)
605 irq = (offset - 0x100) * 8;
606 else
607 irq = (offset - 0x180) * 8;
608 irq += GIC_BASE_IRQ;
609 if (irq >= s->num_irq)
610 goto bad_reg;
611 res = 0;
612 for (i = 0; i < 8; i++) {
613 if (GIC_TEST_ENABLED(irq + i, cm)) {
614 res |= (1 << i);
617 } else if (offset < 0x300) {
618 /* Interrupt Set/Clear Pending. */
619 if (offset < 0x280)
620 irq = (offset - 0x200) * 8;
621 else
622 irq = (offset - 0x280) * 8;
623 irq += GIC_BASE_IRQ;
624 if (irq >= s->num_irq)
625 goto bad_reg;
626 res = 0;
627 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK;
628 for (i = 0; i < 8; i++) {
629 if (gic_test_pending(s, irq + i, mask)) {
630 res |= (1 << i);
633 } else if (offset < 0x400) {
634 /* Interrupt Active. */
635 irq = (offset - 0x300) * 8 + GIC_BASE_IRQ;
636 if (irq >= s->num_irq)
637 goto bad_reg;
638 res = 0;
639 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK;
640 for (i = 0; i < 8; i++) {
641 if (GIC_TEST_ACTIVE(irq + i, mask)) {
642 res |= (1 << i);
645 } else if (offset < 0x800) {
646 /* Interrupt Priority. */
647 irq = (offset - 0x400) + GIC_BASE_IRQ;
648 if (irq >= s->num_irq)
649 goto bad_reg;
650 res = gic_get_priority(s, cpu, irq, attrs);
651 } else if (offset < 0xc00) {
652 /* Interrupt CPU Target. */
653 if (s->num_cpu == 1 && s->revision != REV_11MPCORE) {
654 /* For uniprocessor GICs these RAZ/WI */
655 res = 0;
656 } else {
657 irq = (offset - 0x800) + GIC_BASE_IRQ;
658 if (irq >= s->num_irq) {
659 goto bad_reg;
661 if (irq >= 29 && irq <= 31) {
662 res = cm;
663 } else {
664 res = GIC_TARGET(irq);
667 } else if (offset < 0xf00) {
668 /* Interrupt Configuration. */
669 irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ;
670 if (irq >= s->num_irq)
671 goto bad_reg;
672 res = 0;
673 for (i = 0; i < 4; i++) {
674 if (GIC_TEST_MODEL(irq + i))
675 res |= (1 << (i * 2));
676 if (GIC_TEST_EDGE_TRIGGER(irq + i))
677 res |= (2 << (i * 2));
679 } else if (offset < 0xf10) {
680 goto bad_reg;
681 } else if (offset < 0xf30) {
682 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) {
683 goto bad_reg;
686 if (offset < 0xf20) {
687 /* GICD_CPENDSGIRn */
688 irq = (offset - 0xf10);
689 } else {
690 irq = (offset - 0xf20);
691 /* GICD_SPENDSGIRn */
694 res = s->sgi_pending[irq][cpu];
695 } else if (offset < 0xfd0) {
696 goto bad_reg;
697 } else if (offset < 0x1000) {
698 if (offset & 3) {
699 res = 0;
700 } else {
701 switch (s->revision) {
702 case REV_11MPCORE:
703 res = gic_id_11mpcore[(offset - 0xfd0) >> 2];
704 break;
705 case 1:
706 res = gic_id_gicv1[(offset - 0xfd0) >> 2];
707 break;
708 case 2:
709 res = gic_id_gicv2[(offset - 0xfd0) >> 2];
710 break;
711 case REV_NVIC:
712 /* Shouldn't be able to get here */
713 abort();
714 default:
715 res = 0;
718 } else {
719 g_assert_not_reached();
721 return res;
722 bad_reg:
723 qemu_log_mask(LOG_GUEST_ERROR,
724 "gic_dist_readb: Bad offset %x\n", (int)offset);
725 return 0;
728 static MemTxResult gic_dist_read(void *opaque, hwaddr offset, uint64_t *data,
729 unsigned size, MemTxAttrs attrs)
731 switch (size) {
732 case 1:
733 *data = gic_dist_readb(opaque, offset, attrs);
734 return MEMTX_OK;
735 case 2:
736 *data = gic_dist_readb(opaque, offset, attrs);
737 *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8;
738 return MEMTX_OK;
739 case 4:
740 *data = gic_dist_readb(opaque, offset, attrs);
741 *data |= gic_dist_readb(opaque, offset + 1, attrs) << 8;
742 *data |= gic_dist_readb(opaque, offset + 2, attrs) << 16;
743 *data |= gic_dist_readb(opaque, offset + 3, attrs) << 24;
744 return MEMTX_OK;
745 default:
746 return MEMTX_ERROR;
750 static void gic_dist_writeb(void *opaque, hwaddr offset,
751 uint32_t value, MemTxAttrs attrs)
753 GICState *s = (GICState *)opaque;
754 int irq;
755 int i;
756 int cpu;
758 cpu = gic_get_current_cpu(s);
759 if (offset < 0x100) {
760 if (offset == 0) {
761 if (s->security_extn && !attrs.secure) {
762 /* NS version is just an alias of the S version's bit 1 */
763 s->ctlr = deposit32(s->ctlr, 1, 1, value);
764 } else if (gic_has_groups(s)) {
765 s->ctlr = value & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1);
766 } else {
767 s->ctlr = value & GICD_CTLR_EN_GRP0;
769 DPRINTF("Distributor: Group0 %sabled; Group 1 %sabled\n",
770 s->ctlr & GICD_CTLR_EN_GRP0 ? "En" : "Dis",
771 s->ctlr & GICD_CTLR_EN_GRP1 ? "En" : "Dis");
772 } else if (offset < 4) {
773 /* ignored. */
774 } else if (offset >= 0x80) {
775 /* Interrupt Group Registers: RAZ/WI for NS access to secure
776 * GIC, or for GICs without groups.
778 if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) {
779 /* Every byte offset holds 8 group status bits */
780 irq = (offset - 0x80) * 8 + GIC_BASE_IRQ;
781 if (irq >= s->num_irq) {
782 goto bad_reg;
784 for (i = 0; i < 8; i++) {
785 /* Group bits are banked for private interrupts */
786 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
787 if (value & (1 << i)) {
788 /* Group1 (Non-secure) */
789 GIC_SET_GROUP(irq + i, cm);
790 } else {
791 /* Group0 (Secure) */
792 GIC_CLEAR_GROUP(irq + i, cm);
796 } else {
797 goto bad_reg;
799 } else if (offset < 0x180) {
800 /* Interrupt Set Enable. */
801 irq = (offset - 0x100) * 8 + GIC_BASE_IRQ;
802 if (irq >= s->num_irq)
803 goto bad_reg;
804 if (irq < GIC_NR_SGIS) {
805 value = 0xff;
808 for (i = 0; i < 8; i++) {
809 if (value & (1 << i)) {
810 int mask =
811 (irq < GIC_INTERNAL) ? (1 << cpu) : GIC_TARGET(irq + i);
812 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
814 if (!GIC_TEST_ENABLED(irq + i, cm)) {
815 DPRINTF("Enabled IRQ %d\n", irq + i);
817 GIC_SET_ENABLED(irq + i, cm);
818 /* If a raised level triggered IRQ enabled then mark
819 is as pending. */
820 if (GIC_TEST_LEVEL(irq + i, mask)
821 && !GIC_TEST_EDGE_TRIGGER(irq + i)) {
822 DPRINTF("Set %d pending mask %x\n", irq + i, mask);
823 GIC_SET_PENDING(irq + i, mask);
827 } else if (offset < 0x200) {
828 /* Interrupt Clear Enable. */
829 irq = (offset - 0x180) * 8 + GIC_BASE_IRQ;
830 if (irq >= s->num_irq)
831 goto bad_reg;
832 if (irq < GIC_NR_SGIS) {
833 value = 0;
836 for (i = 0; i < 8; i++) {
837 if (value & (1 << i)) {
838 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
840 if (GIC_TEST_ENABLED(irq + i, cm)) {
841 DPRINTF("Disabled IRQ %d\n", irq + i);
843 GIC_CLEAR_ENABLED(irq + i, cm);
846 } else if (offset < 0x280) {
847 /* Interrupt Set Pending. */
848 irq = (offset - 0x200) * 8 + GIC_BASE_IRQ;
849 if (irq >= s->num_irq)
850 goto bad_reg;
851 if (irq < GIC_NR_SGIS) {
852 value = 0;
855 for (i = 0; i < 8; i++) {
856 if (value & (1 << i)) {
857 GIC_SET_PENDING(irq + i, GIC_TARGET(irq + i));
860 } else if (offset < 0x300) {
861 /* Interrupt Clear Pending. */
862 irq = (offset - 0x280) * 8 + GIC_BASE_IRQ;
863 if (irq >= s->num_irq)
864 goto bad_reg;
865 if (irq < GIC_NR_SGIS) {
866 value = 0;
869 for (i = 0; i < 8; i++) {
870 /* ??? This currently clears the pending bit for all CPUs, even
871 for per-CPU interrupts. It's unclear whether this is the
872 corect behavior. */
873 if (value & (1 << i)) {
874 GIC_CLEAR_PENDING(irq + i, ALL_CPU_MASK);
877 } else if (offset < 0x400) {
878 /* Interrupt Active. */
879 goto bad_reg;
880 } else if (offset < 0x800) {
881 /* Interrupt Priority. */
882 irq = (offset - 0x400) + GIC_BASE_IRQ;
883 if (irq >= s->num_irq)
884 goto bad_reg;
885 gic_set_priority(s, cpu, irq, value, attrs);
886 } else if (offset < 0xc00) {
887 /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the
888 * annoying exception of the 11MPCore's GIC.
890 if (s->num_cpu != 1 || s->revision == REV_11MPCORE) {
891 irq = (offset - 0x800) + GIC_BASE_IRQ;
892 if (irq >= s->num_irq) {
893 goto bad_reg;
895 if (irq < 29) {
896 value = 0;
897 } else if (irq < GIC_INTERNAL) {
898 value = ALL_CPU_MASK;
900 s->irq_target[irq] = value & ALL_CPU_MASK;
902 } else if (offset < 0xf00) {
903 /* Interrupt Configuration. */
904 irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ;
905 if (irq >= s->num_irq)
906 goto bad_reg;
907 if (irq < GIC_NR_SGIS)
908 value |= 0xaa;
909 for (i = 0; i < 4; i++) {
910 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) {
911 if (value & (1 << (i * 2))) {
912 GIC_SET_MODEL(irq + i);
913 } else {
914 GIC_CLEAR_MODEL(irq + i);
917 if (value & (2 << (i * 2))) {
918 GIC_SET_EDGE_TRIGGER(irq + i);
919 } else {
920 GIC_CLEAR_EDGE_TRIGGER(irq + i);
923 } else if (offset < 0xf10) {
924 /* 0xf00 is only handled for 32-bit writes. */
925 goto bad_reg;
926 } else if (offset < 0xf20) {
927 /* GICD_CPENDSGIRn */
928 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) {
929 goto bad_reg;
931 irq = (offset - 0xf10);
933 s->sgi_pending[irq][cpu] &= ~value;
934 if (s->sgi_pending[irq][cpu] == 0) {
935 GIC_CLEAR_PENDING(irq, 1 << cpu);
937 } else if (offset < 0xf30) {
938 /* GICD_SPENDSGIRn */
939 if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) {
940 goto bad_reg;
942 irq = (offset - 0xf20);
944 GIC_SET_PENDING(irq, 1 << cpu);
945 s->sgi_pending[irq][cpu] |= value;
946 } else {
947 goto bad_reg;
949 gic_update(s);
950 return;
951 bad_reg:
952 qemu_log_mask(LOG_GUEST_ERROR,
953 "gic_dist_writeb: Bad offset %x\n", (int)offset);
956 static void gic_dist_writew(void *opaque, hwaddr offset,
957 uint32_t value, MemTxAttrs attrs)
959 gic_dist_writeb(opaque, offset, value & 0xff, attrs);
960 gic_dist_writeb(opaque, offset + 1, value >> 8, attrs);
963 static void gic_dist_writel(void *opaque, hwaddr offset,
964 uint32_t value, MemTxAttrs attrs)
966 GICState *s = (GICState *)opaque;
967 if (offset == 0xf00) {
968 int cpu;
969 int irq;
970 int mask;
971 int target_cpu;
973 cpu = gic_get_current_cpu(s);
974 irq = value & 0x3ff;
975 switch ((value >> 24) & 3) {
976 case 0:
977 mask = (value >> 16) & ALL_CPU_MASK;
978 break;
979 case 1:
980 mask = ALL_CPU_MASK ^ (1 << cpu);
981 break;
982 case 2:
983 mask = 1 << cpu;
984 break;
985 default:
986 DPRINTF("Bad Soft Int target filter\n");
987 mask = ALL_CPU_MASK;
988 break;
990 GIC_SET_PENDING(irq, mask);
991 target_cpu = ctz32(mask);
992 while (target_cpu < GIC_NCPU) {
993 s->sgi_pending[irq][target_cpu] |= (1 << cpu);
994 mask &= ~(1 << target_cpu);
995 target_cpu = ctz32(mask);
997 gic_update(s);
998 return;
1000 gic_dist_writew(opaque, offset, value & 0xffff, attrs);
1001 gic_dist_writew(opaque, offset + 2, value >> 16, attrs);
1004 static MemTxResult gic_dist_write(void *opaque, hwaddr offset, uint64_t data,
1005 unsigned size, MemTxAttrs attrs)
1007 switch (size) {
1008 case 1:
1009 gic_dist_writeb(opaque, offset, data, attrs);
1010 return MEMTX_OK;
1011 case 2:
1012 gic_dist_writew(opaque, offset, data, attrs);
1013 return MEMTX_OK;
1014 case 4:
1015 gic_dist_writel(opaque, offset, data, attrs);
1016 return MEMTX_OK;
1017 default:
1018 return MEMTX_ERROR;
1022 static inline uint32_t gic_apr_ns_view(GICState *s, int cpu, int regno)
1024 /* Return the Nonsecure view of GICC_APR<regno>. This is the
1025 * second half of GICC_NSAPR.
1027 switch (GIC_MIN_BPR) {
1028 case 0:
1029 if (regno < 2) {
1030 return s->nsapr[regno + 2][cpu];
1032 break;
1033 case 1:
1034 if (regno == 0) {
1035 return s->nsapr[regno + 1][cpu];
1037 break;
1038 case 2:
1039 if (regno == 0) {
1040 return extract32(s->nsapr[0][cpu], 16, 16);
1042 break;
1043 case 3:
1044 if (regno == 0) {
1045 return extract32(s->nsapr[0][cpu], 8, 8);
1047 break;
1048 default:
1049 g_assert_not_reached();
1051 return 0;
1054 static inline void gic_apr_write_ns_view(GICState *s, int cpu, int regno,
1055 uint32_t value)
1057 /* Write the Nonsecure view of GICC_APR<regno>. */
1058 switch (GIC_MIN_BPR) {
1059 case 0:
1060 if (regno < 2) {
1061 s->nsapr[regno + 2][cpu] = value;
1063 break;
1064 case 1:
1065 if (regno == 0) {
1066 s->nsapr[regno + 1][cpu] = value;
1068 break;
1069 case 2:
1070 if (regno == 0) {
1071 s->nsapr[0][cpu] = deposit32(s->nsapr[0][cpu], 16, 16, value);
1073 break;
1074 case 3:
1075 if (regno == 0) {
1076 s->nsapr[0][cpu] = deposit32(s->nsapr[0][cpu], 8, 8, value);
1078 break;
1079 default:
1080 g_assert_not_reached();
1084 static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset,
1085 uint64_t *data, MemTxAttrs attrs)
1087 switch (offset) {
1088 case 0x00: /* Control */
1089 *data = gic_get_cpu_control(s, cpu, attrs);
1090 break;
1091 case 0x04: /* Priority mask */
1092 *data = gic_get_priority_mask(s, cpu, attrs);
1093 break;
1094 case 0x08: /* Binary Point */
1095 if (s->security_extn && !attrs.secure) {
1096 /* BPR is banked. Non-secure copy stored in ABPR. */
1097 *data = s->abpr[cpu];
1098 } else {
1099 *data = s->bpr[cpu];
1101 break;
1102 case 0x0c: /* Acknowledge */
1103 *data = gic_acknowledge_irq(s, cpu, attrs);
1104 break;
1105 case 0x14: /* Running Priority */
1106 *data = gic_get_running_priority(s, cpu, attrs);
1107 break;
1108 case 0x18: /* Highest Pending Interrupt */
1109 *data = gic_get_current_pending_irq(s, cpu, attrs);
1110 break;
1111 case 0x1c: /* Aliased Binary Point */
1112 /* GIC v2, no security: ABPR
1113 * GIC v1, no security: not implemented (RAZ/WI)
1114 * With security extensions, secure access: ABPR (alias of NS BPR)
1115 * With security extensions, nonsecure access: RAZ/WI
1117 if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) {
1118 *data = 0;
1119 } else {
1120 *data = s->abpr[cpu];
1122 break;
1123 case 0xd0: case 0xd4: case 0xd8: case 0xdc:
1125 int regno = (offset - 0xd0) / 4;
1127 if (regno >= GIC_NR_APRS || s->revision != 2) {
1128 *data = 0;
1129 } else if (s->security_extn && !attrs.secure) {
1130 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */
1131 *data = gic_apr_ns_view(s, regno, cpu);
1132 } else {
1133 *data = s->apr[regno][cpu];
1135 break;
1137 case 0xe0: case 0xe4: case 0xe8: case 0xec:
1139 int regno = (offset - 0xe0) / 4;
1141 if (regno >= GIC_NR_APRS || s->revision != 2 || !gic_has_groups(s) ||
1142 (s->security_extn && !attrs.secure)) {
1143 *data = 0;
1144 } else {
1145 *data = s->nsapr[regno][cpu];
1147 break;
1149 default:
1150 qemu_log_mask(LOG_GUEST_ERROR,
1151 "gic_cpu_read: Bad offset %x\n", (int)offset);
1152 return MEMTX_ERROR;
1154 return MEMTX_OK;
1157 static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset,
1158 uint32_t value, MemTxAttrs attrs)
1160 switch (offset) {
1161 case 0x00: /* Control */
1162 gic_set_cpu_control(s, cpu, value, attrs);
1163 break;
1164 case 0x04: /* Priority mask */
1165 gic_set_priority_mask(s, cpu, value, attrs);
1166 break;
1167 case 0x08: /* Binary Point */
1168 if (s->security_extn && !attrs.secure) {
1169 s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR);
1170 } else {
1171 s->bpr[cpu] = MAX(value & 0x7, GIC_MIN_BPR);
1173 break;
1174 case 0x10: /* End Of Interrupt */
1175 gic_complete_irq(s, cpu, value & 0x3ff, attrs);
1176 return MEMTX_OK;
1177 case 0x1c: /* Aliased Binary Point */
1178 if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) {
1179 /* unimplemented, or NS access: RAZ/WI */
1180 return MEMTX_OK;
1181 } else {
1182 s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR);
1184 break;
1185 case 0xd0: case 0xd4: case 0xd8: case 0xdc:
1187 int regno = (offset - 0xd0) / 4;
1189 if (regno >= GIC_NR_APRS || s->revision != 2) {
1190 return MEMTX_OK;
1192 if (s->security_extn && !attrs.secure) {
1193 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */
1194 gic_apr_write_ns_view(s, regno, cpu, value);
1195 } else {
1196 s->apr[regno][cpu] = value;
1198 break;
1200 case 0xe0: case 0xe4: case 0xe8: case 0xec:
1202 int regno = (offset - 0xe0) / 4;
1204 if (regno >= GIC_NR_APRS || s->revision != 2) {
1205 return MEMTX_OK;
1207 if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) {
1208 return MEMTX_OK;
1210 s->nsapr[regno][cpu] = value;
1211 break;
1213 default:
1214 qemu_log_mask(LOG_GUEST_ERROR,
1215 "gic_cpu_write: Bad offset %x\n", (int)offset);
1216 return MEMTX_ERROR;
1218 gic_update(s);
1219 return MEMTX_OK;
1222 /* Wrappers to read/write the GIC CPU interface for the current CPU */
1223 static MemTxResult gic_thiscpu_read(void *opaque, hwaddr addr, uint64_t *data,
1224 unsigned size, MemTxAttrs attrs)
1226 GICState *s = (GICState *)opaque;
1227 return gic_cpu_read(s, gic_get_current_cpu(s), addr, data, attrs);
1230 static MemTxResult gic_thiscpu_write(void *opaque, hwaddr addr,
1231 uint64_t value, unsigned size,
1232 MemTxAttrs attrs)
1234 GICState *s = (GICState *)opaque;
1235 return gic_cpu_write(s, gic_get_current_cpu(s), addr, value, attrs);
1238 /* Wrappers to read/write the GIC CPU interface for a specific CPU.
1239 * These just decode the opaque pointer into GICState* + cpu id.
1241 static MemTxResult gic_do_cpu_read(void *opaque, hwaddr addr, uint64_t *data,
1242 unsigned size, MemTxAttrs attrs)
1244 GICState **backref = (GICState **)opaque;
1245 GICState *s = *backref;
1246 int id = (backref - s->backref);
1247 return gic_cpu_read(s, id, addr, data, attrs);
1250 static MemTxResult gic_do_cpu_write(void *opaque, hwaddr addr,
1251 uint64_t value, unsigned size,
1252 MemTxAttrs attrs)
1254 GICState **backref = (GICState **)opaque;
1255 GICState *s = *backref;
1256 int id = (backref - s->backref);
1257 return gic_cpu_write(s, id, addr, value, attrs);
1260 static const MemoryRegionOps gic_ops[2] = {
1262 .read_with_attrs = gic_dist_read,
1263 .write_with_attrs = gic_dist_write,
1264 .endianness = DEVICE_NATIVE_ENDIAN,
1267 .read_with_attrs = gic_thiscpu_read,
1268 .write_with_attrs = gic_thiscpu_write,
1269 .endianness = DEVICE_NATIVE_ENDIAN,
1273 static const MemoryRegionOps gic_cpu_ops = {
1274 .read_with_attrs = gic_do_cpu_read,
1275 .write_with_attrs = gic_do_cpu_write,
1276 .endianness = DEVICE_NATIVE_ENDIAN,
1279 /* This function is used by nvic model */
1280 void gic_init_irqs_and_distributor(GICState *s)
1282 gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops);
1285 static void arm_gic_realize(DeviceState *dev, Error **errp)
1287 /* Device instance realize function for the GIC sysbus device */
1288 int i;
1289 GICState *s = ARM_GIC(dev);
1290 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1291 ARMGICClass *agc = ARM_GIC_GET_CLASS(s);
1292 Error *local_err = NULL;
1294 agc->parent_realize(dev, &local_err);
1295 if (local_err) {
1296 error_propagate(errp, local_err);
1297 return;
1300 /* This creates distributor and main CPU interface (s->cpuiomem[0]) */
1301 gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops);
1303 /* Extra core-specific regions for the CPU interfaces. This is
1304 * necessary for "franken-GIC" implementations, for example on
1305 * Exynos 4.
1306 * NB that the memory region size of 0x100 applies for the 11MPCore
1307 * and also cores following the GIC v1 spec (ie A9).
1308 * GIC v2 defines a larger memory region (0x1000) so this will need
1309 * to be extended when we implement A15.
1311 for (i = 0; i < s->num_cpu; i++) {
1312 s->backref[i] = s;
1313 memory_region_init_io(&s->cpuiomem[i+1], OBJECT(s), &gic_cpu_ops,
1314 &s->backref[i], "gic_cpu", 0x100);
1315 sysbus_init_mmio(sbd, &s->cpuiomem[i+1]);
1319 static void arm_gic_class_init(ObjectClass *klass, void *data)
1321 DeviceClass *dc = DEVICE_CLASS(klass);
1322 ARMGICClass *agc = ARM_GIC_CLASS(klass);
1324 agc->parent_realize = dc->realize;
1325 dc->realize = arm_gic_realize;
1328 static const TypeInfo arm_gic_info = {
1329 .name = TYPE_ARM_GIC,
1330 .parent = TYPE_ARM_GIC_COMMON,
1331 .instance_size = sizeof(GICState),
1332 .class_init = arm_gic_class_init,
1333 .class_size = sizeof(ARMGICClass),
1336 static void arm_gic_register_types(void)
1338 type_register_static(&arm_gic_info);
1341 type_init(arm_gic_register_types)