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target/arm: Check supported KVM features globally (not per vCPU)
[qemu/ar7.git] / hw / arm / xlnx-zynqmp.c
blob1de9d4a89d77f27e0b7f4181bf4652f2ab64bfe5
1 /*
2 * Xilinx Zynq MPSoC emulation
3 *
4 * Copyright (C) 2015 Xilinx Inc
5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 */
17
18 #include "qemu/osdep.h"
19 #include "qapi/error.h"
20 #include "qemu/module.h"
21 #include "cpu.h"
22 #include "hw/arm/xlnx-zynqmp.h"
23 #include "hw/intc/arm_gic_common.h"
24 #include "hw/boards.h"
25 #include "exec/address-spaces.h"
26 #include "sysemu/kvm.h"
27 #include "sysemu/sysemu.h"
28 #include "kvm_arm.h"
29
30 #define GIC_NUM_SPI_INTR 160
31
32 #define ARM_PHYS_TIMER_PPI 30
33 #define ARM_VIRT_TIMER_PPI 27
34 #define ARM_HYP_TIMER_PPI 26
35 #define ARM_SEC_TIMER_PPI 29
36 #define GIC_MAINTENANCE_PPI 25
37
38 #define GEM_REVISION 0x40070106
39
40 #define GIC_BASE_ADDR 0xf9000000
41 #define GIC_DIST_ADDR 0xf9010000
42 #define GIC_CPU_ADDR 0xf9020000
43 #define GIC_VIFACE_ADDR 0xf9040000
44 #define GIC_VCPU_ADDR 0xf9060000
45
46 #define SATA_INTR 133
47 #define SATA_ADDR 0xFD0C0000
48 #define SATA_NUM_PORTS 2
49
50 #define QSPI_ADDR 0xff0f0000
51 #define LQSPI_ADDR 0xc0000000
52 #define QSPI_IRQ 15
53
54 #define DP_ADDR 0xfd4a0000
55 #define DP_IRQ 113
56
57 #define DPDMA_ADDR 0xfd4c0000
58 #define DPDMA_IRQ 116
59
60 #define IPI_ADDR 0xFF300000
61 #define IPI_IRQ 64
62
63 #define RTC_ADDR 0xffa60000
64 #define RTC_IRQ 26
65
66 #define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */
67
68 static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
69 0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
70 };
71
72 static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = {
73 57, 59, 61, 63,
74 };
75
76 static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = {
77 0xFF000000, 0xFF010000,
78 };
79
80 static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
81 21, 22,
82 };
83
84 static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = {
85 0xFF160000, 0xFF170000,
86 };
87
88 static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = {
89 48, 49,
90 };
91
92 static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = {
93 0xFF040000, 0xFF050000,
94 };
95
96 static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = {
97 19, 20,
98 };
99
100 static const uint64_t gdma_ch_addr[XLNX_ZYNQMP_NUM_GDMA_CH] = {
101 0xFD500000, 0xFD510000, 0xFD520000, 0xFD530000,
102 0xFD540000, 0xFD550000, 0xFD560000, 0xFD570000
103 };
104
105 static const int gdma_ch_intr[XLNX_ZYNQMP_NUM_GDMA_CH] = {
106 124, 125, 126, 127, 128, 129, 130, 131
107 };
108
109 static const uint64_t adma_ch_addr[XLNX_ZYNQMP_NUM_ADMA_CH] = {
110 0xFFA80000, 0xFFA90000, 0xFFAA0000, 0xFFAB0000,
111 0xFFAC0000, 0xFFAD0000, 0xFFAE0000, 0xFFAF0000
112 };
113
114 static const int adma_ch_intr[XLNX_ZYNQMP_NUM_ADMA_CH] = {
115 77, 78, 79, 80, 81, 82, 83, 84
116 };
117
118 typedef struct XlnxZynqMPGICRegion {
119 int region_index;
120 uint32_t address;
121 uint32_t offset;
122 bool virt;
123 } XlnxZynqMPGICRegion;
124
125 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = {
126 /* Distributor */
127 {
128 .region_index = 0,
129 .address = GIC_DIST_ADDR,
130 .offset = 0,
131 .virt = false
132 },
133
134 /* CPU interface */
135 {
136 .region_index = 1,
137 .address = GIC_CPU_ADDR,
138 .offset = 0,
139 .virt = false
140 },
141 {
142 .region_index = 1,
143 .address = GIC_CPU_ADDR + 0x10000,
144 .offset = 0x1000,
145 .virt = false
146 },
147
148 /* Virtual interface */
149 {
150 .region_index = 2,
151 .address = GIC_VIFACE_ADDR,
152 .offset = 0,
153 .virt = true
154 },
155
156 /* Virtual CPU interface */
157 {
158 .region_index = 3,
159 .address = GIC_VCPU_ADDR,
160 .offset = 0,
161 .virt = true
162 },
163 {
164 .region_index = 3,
165 .address = GIC_VCPU_ADDR + 0x10000,
166 .offset = 0x1000,
167 .virt = true
168 },
169 };
170
171 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
172 {
173 return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index;
174 }
175
176 static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s,
177 const char *boot_cpu, Error **errp)
178 {
179 Error *err = NULL;
180 int i;
181 int num_rpus = MIN(ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS,
182 XLNX_ZYNQMP_NUM_RPU_CPUS);
183
184 if (num_rpus <= 0) {
185 /* Don't create rpu-cluster object if there's nothing to put in it */
186 return;
187 }
188
189 object_initialize_child(OBJECT(s), "rpu-cluster", &s->rpu_cluster,
190 TYPE_CPU_CLUSTER);
191 qdev_prop_set_uint32(DEVICE(&s->rpu_cluster), "cluster-id", 1);
192
193 for (i = 0; i < num_rpus; i++) {
194 char *name;
195
196 object_initialize_child(OBJECT(&s->rpu_cluster), "rpu-cpu[*]",
197 &s->rpu_cpu[i],
198 ARM_CPU_TYPE_NAME("cortex-r5f"));
199
200 name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i]));
201 if (strcmp(name, boot_cpu)) {
202 /* Secondary CPUs start in PSCI powered-down state */
203 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true,
204 "start-powered-off", &error_abort);
205 } else {
206 s->boot_cpu_ptr = &s->rpu_cpu[i];
207 }
208 g_free(name);
209
210 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs",
211 &error_abort);
212 qdev_realize(DEVICE(&s->rpu_cpu[i]), NULL, &err);
213 if (err) {
214 error_propagate(errp, err);
215 return;
216 }
217 }
218
219 qdev_realize(DEVICE(&s->rpu_cluster), NULL, &error_fatal);
220 }
221
222 static void xlnx_zynqmp_init(Object *obj)
223 {
224 MachineState *ms = MACHINE(qdev_get_machine());
225 XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
226 int i;
227 int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
228
229 object_initialize_child(obj, "apu-cluster", &s->apu_cluster,
230 TYPE_CPU_CLUSTER);
231 qdev_prop_set_uint32(DEVICE(&s->apu_cluster), "cluster-id", 0);
232
233 for (i = 0; i < num_apus; i++) {
234 object_initialize_child(OBJECT(&s->apu_cluster), "apu-cpu[*]",
235 &s->apu_cpu[i],
236 ARM_CPU_TYPE_NAME("cortex-a53"));
237 }
238
239 object_initialize_child(obj, "gic", &s->gic, gic_class_name());
240
241 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
242 object_initialize_child(obj, "gem[*]", &s->gem[i], TYPE_CADENCE_GEM);
243 }
244
245 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
246 object_initialize_child(obj, "uart[*]", &s->uart[i],
247 TYPE_CADENCE_UART);
248 }
249
250 object_initialize_child(obj, "sata", &s->sata, TYPE_SYSBUS_AHCI);
251
252 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
253 object_initialize_child(obj, "sdhci[*]", &s->sdhci[i],
254 TYPE_SYSBUS_SDHCI);
255 }
256
257 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
258 object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_XILINX_SPIPS);
259 }
260
261 object_initialize_child(obj, "qspi", &s->qspi, TYPE_XLNX_ZYNQMP_QSPIPS);
262
263 object_initialize_child(obj, "xxxdp", &s->dp, TYPE_XLNX_DP);
264
265 object_initialize_child(obj, "dp-dma", &s->dpdma, TYPE_XLNX_DPDMA);
266
267 object_initialize_child(obj, "ipi", &s->ipi, TYPE_XLNX_ZYNQMP_IPI);
268
269 object_initialize_child(obj, "rtc", &s->rtc, TYPE_XLNX_ZYNQMP_RTC);
270
271 for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
272 object_initialize_child(obj, "gdma[*]", &s->gdma[i], TYPE_XLNX_ZDMA);
273 }
274
275 for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) {
276 object_initialize_child(obj, "adma[*]", &s->adma[i], TYPE_XLNX_ZDMA);
277 }
278 }
279
280 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
281 {
282 MachineState *ms = MACHINE(qdev_get_machine());
283 XlnxZynqMPState *s = XLNX_ZYNQMP(dev);
284 MemoryRegion *system_memory = get_system_memory();
285 uint8_t i;
286 uint64_t ram_size;
287 int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
288 const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]";
289 ram_addr_t ddr_low_size, ddr_high_size;
290 qemu_irq gic_spi[GIC_NUM_SPI_INTR];
291 Error *err = NULL;
292
293 ram_size = memory_region_size(s->ddr_ram);
294
295 /* Create the DDR Memory Regions. User friendly checks should happen at
296 * the board level
297 */
298 if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) {
299 /* The RAM size is above the maximum available for the low DDR.
300 * Create the high DDR memory region as well.
301 */
302 assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE);
303 ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
304 ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
305
306 memory_region_init_alias(&s->ddr_ram_high, OBJECT(dev),
307 "ddr-ram-high", s->ddr_ram, ddr_low_size,
308 ddr_high_size);
309 memory_region_add_subregion(get_system_memory(),
310 XLNX_ZYNQMP_HIGH_RAM_START,
311 &s->ddr_ram_high);
312 } else {
313 /* RAM must be non-zero */
314 assert(ram_size);
315 ddr_low_size = ram_size;
316 }
317
318 memory_region_init_alias(&s->ddr_ram_low, OBJECT(dev), "ddr-ram-low",
319 s->ddr_ram, 0, ddr_low_size);
320 memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low);
321
322 /* Create the four OCM banks */
323 for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) {
324 char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i);
325
326 memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name,
327 XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal);
328 memory_region_add_subregion(get_system_memory(),
329 XLNX_ZYNQMP_OCM_RAM_0_ADDRESS +
330 i * XLNX_ZYNQMP_OCM_RAM_SIZE,
331 &s->ocm_ram[i]);
332
333 g_free(ocm_name);
334 }
335
336 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
337 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
338 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus);
339 qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", s->secure);
340 qdev_prop_set_bit(DEVICE(&s->gic),
341 "has-virtualization-extensions", s->virt);
342
343 qdev_realize(DEVICE(&s->apu_cluster), NULL, &error_fatal);
344
345 /* Realize APUs before realizing the GIC. KVM requires this. */
346 for (i = 0; i < num_apus; i++) {
347 char *name;
348
349 object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC,
350 "psci-conduit", &error_abort);
351
352 name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i]));
353 if (strcmp(name, boot_cpu)) {
354 /* Secondary CPUs start in PSCI powered-down state */
355 object_property_set_bool(OBJECT(&s->apu_cpu[i]), true,
356 "start-powered-off", &error_abort);
357 } else {
358 s->boot_cpu_ptr = &s->apu_cpu[i];
359 }
360 g_free(name);
361
362 object_property_set_bool(OBJECT(&s->apu_cpu[i]),
363 s->secure, "has_el3", NULL);
364 object_property_set_bool(OBJECT(&s->apu_cpu[i]),
365 s->virt, "has_el2", NULL);
366 object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR,
367 "reset-cbar", &error_abort);
368 object_property_set_int(OBJECT(&s->apu_cpu[i]), num_apus,
369 "core-count", &error_abort);
370 qdev_realize(DEVICE(&s->apu_cpu[i]), NULL, &err);
371 if (err) {
372 error_propagate(errp, err);
373 return;
374 }
375 }
376
377 sysbus_realize(SYS_BUS_DEVICE(&s->gic), &err);
378 if (err) {
379 error_propagate(errp, err);
380 return;
381 }
382
383 assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS);
384 for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) {
385 SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic);
386 const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i];
387 MemoryRegion *mr;
388 uint32_t addr = r->address;
389 int j;
390
391 if (r->virt && !s->virt) {
392 continue;
393 }
394
395 mr = sysbus_mmio_get_region(gic, r->region_index);
396 for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) {
397 MemoryRegion *alias = &s->gic_mr[i][j];
398
399 memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr,
400 r->offset, XLNX_ZYNQMP_GIC_REGION_SIZE);
401 memory_region_add_subregion(system_memory, addr, alias);
402
403 addr += XLNX_ZYNQMP_GIC_REGION_SIZE;
404 }
405 }
406
407 for (i = 0; i < num_apus; i++) {
408 qemu_irq irq;
409
410 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
411 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
412 ARM_CPU_IRQ));
413 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus,
414 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
415 ARM_CPU_FIQ));
416 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 2,
417 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
418 ARM_CPU_VIRQ));
419 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 3,
420 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
421 ARM_CPU_VFIQ));
422 irq = qdev_get_gpio_in(DEVICE(&s->gic),
423 arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
424 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_PHYS, irq);
425 irq = qdev_get_gpio_in(DEVICE(&s->gic),
426 arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
427 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_VIRT, irq);
428 irq = qdev_get_gpio_in(DEVICE(&s->gic),
429 arm_gic_ppi_index(i, ARM_HYP_TIMER_PPI));
430 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_HYP, irq);
431 irq = qdev_get_gpio_in(DEVICE(&s->gic),
432 arm_gic_ppi_index(i, ARM_SEC_TIMER_PPI));
433 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_SEC, irq);
434
435 if (s->virt) {
436 irq = qdev_get_gpio_in(DEVICE(&s->gic),
437 arm_gic_ppi_index(i, GIC_MAINTENANCE_PPI));
438 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 4, irq);
439 }
440 }
441
442 if (s->has_rpu) {
443 info_report("The 'has_rpu' property is no longer required, to use the "
444 "RPUs just use -smp 6.");
445 }
446
447 xlnx_zynqmp_create_rpu(ms, s, boot_cpu, &err);
448 if (err) {
449 error_propagate(errp, err);
450 return;
451 }
452
453 if (!s->boot_cpu_ptr) {
454 error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu);
455 return;
456 }
457
458 for (i = 0; i < GIC_NUM_SPI_INTR; i++) {
459 gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i);
460 }
461
462 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
463 NICInfo *nd = &nd_table[i];
464
465 if (nd->used) {
466 qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
467 qdev_set_nic_properties(DEVICE(&s->gem[i]), nd);
468 }
469 object_property_set_int(OBJECT(&s->gem[i]), GEM_REVISION, "revision",
470 &error_abort);
471 object_property_set_int(OBJECT(&s->gem[i]), 2, "num-priority-queues",
472 &error_abort);
473 sysbus_realize(SYS_BUS_DEVICE(&s->gem[i]), &err);
474 if (err) {
475 error_propagate(errp, err);
476 return;
477 }
478 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]);
479 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0,
480 gic_spi[gem_intr[i]]);
481 }
482
483 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
484 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
485 sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), &err);
486 if (err) {
487 error_propagate(errp, err);
488 return;
489 }
490 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]);
491 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
492 gic_spi[uart_intr[i]]);
493 }
494
495 object_property_set_int(OBJECT(&s->sata), SATA_NUM_PORTS, "num-ports",
496 &error_abort);
497 sysbus_realize(SYS_BUS_DEVICE(&s->sata), &err);
498 if (err) {
499 error_propagate(errp, err);
500 return;
501 }
502
503 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR);
504 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);
505
506 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
507 char *bus_name;
508 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->sdhci[i]);
509 Object *sdhci = OBJECT(&s->sdhci[i]);
510
511 /* Compatible with:
512 * - SD Host Controller Specification Version 3.00
513 * - SDIO Specification Version 3.0
514 * - eMMC Specification Version 4.51
515 */
516 object_property_set_uint(sdhci, 3, "sd-spec-version", &err);
517 if (err) {
518 error_propagate(errp, err);
519 return;
520 }
521 object_property_set_uint(sdhci, SDHCI_CAPABILITIES, "capareg", &err);
522 if (err) {
523 error_propagate(errp, err);
524 return;
525 }
526 object_property_set_uint(sdhci, UHS_I, "uhs", &err);
527 if (err) {
528 error_propagate(errp, err);
529 return;
530 }
531 sysbus_realize(SYS_BUS_DEVICE(sdhci), &err);
532 if (err) {
533 error_propagate(errp, err);
534 return;
535 }
536 sysbus_mmio_map(sbd, 0, sdhci_addr[i]);
537 sysbus_connect_irq(sbd, 0, gic_spi[sdhci_intr[i]]);
538
539 /* Alias controller SD bus to the SoC itself */
540 bus_name = g_strdup_printf("sd-bus%d", i);
541 object_property_add_alias(OBJECT(s), bus_name, sdhci, "sd-bus");
542 g_free(bus_name);
543 }
544
545 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
546 gchar *bus_name;
547
548 sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &err);
549 if (err) {
550 error_propagate(errp, err);
551 return;
552 }
553
554 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
555 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
556 gic_spi[spi_intr[i]]);
557
558 /* Alias controller SPI bus to the SoC itself */
559 bus_name = g_strdup_printf("spi%d", i);
560 object_property_add_alias(OBJECT(s), bus_name,
561 OBJECT(&s->spi[i]), "spi0");
562 g_free(bus_name);
563 }
564
565 sysbus_realize(SYS_BUS_DEVICE(&s->qspi), &err);
566 if (err) {
567 error_propagate(errp, err);
568 return;
569 }
570 sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR);
571 sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR);
572 sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0, gic_spi[QSPI_IRQ]);
573
574 for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_BUS; i++) {
575 gchar *bus_name;
576 gchar *target_bus;
577
578 /* Alias controller SPI bus to the SoC itself */
579 bus_name = g_strdup_printf("qspi%d", i);
580 target_bus = g_strdup_printf("spi%d", i);
581 object_property_add_alias(OBJECT(s), bus_name,
582 OBJECT(&s->qspi), target_bus);
583 g_free(bus_name);
584 g_free(target_bus);
585 }
586
587 sysbus_realize(SYS_BUS_DEVICE(&s->dp), &err);
588 if (err) {
589 error_propagate(errp, err);
590 return;
591 }
592 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR);
593 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]);
594
595 sysbus_realize(SYS_BUS_DEVICE(&s->dpdma), &err);
596 if (err) {
597 error_propagate(errp, err);
598 return;
599 }
600 object_property_set_link(OBJECT(&s->dp), OBJECT(&s->dpdma), "dpdma",
601 &error_abort);
602 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR);
603 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]);
604
605 sysbus_realize(SYS_BUS_DEVICE(&s->ipi), &err);
606 if (err) {
607 error_propagate(errp, err);
608 return;
609 }
610 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi), 0, IPI_ADDR);
611 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi), 0, gic_spi[IPI_IRQ]);
612
613 sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &err);
614 if (err) {
615 error_propagate(errp, err);
616 return;
617 }
618 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR);
619 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]);
620
621 for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
622 object_property_set_uint(OBJECT(&s->gdma[i]), 128, "bus-width", &err);
623 if (err) {
624 error_propagate(errp, err);
625 return;
626 }
627 sysbus_realize(SYS_BUS_DEVICE(&s->gdma[i]), &err);
628 if (err) {
629 error_propagate(errp, err);
630 return;
631 }
632
633 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gdma[i]), 0, gdma_ch_addr[i]);
634 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gdma[i]), 0,
635 gic_spi[gdma_ch_intr[i]]);
636 }
637
638 for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) {
639 sysbus_realize(SYS_BUS_DEVICE(&s->adma[i]), &err);
640 if (err) {
641 error_propagate(errp, err);
642 return;
643 }
644
645 sysbus_mmio_map(SYS_BUS_DEVICE(&s->adma[i]), 0, adma_ch_addr[i]);
646 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adma[i]), 0,
647 gic_spi[adma_ch_intr[i]]);
648 }
649 }
650
651 static Property xlnx_zynqmp_props[] = {
652 DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu),
653 DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false),
654 DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState, virt, false),
655 DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false),
656 DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION,
657 MemoryRegion *),
658 DEFINE_PROP_END_OF_LIST()
659 };
660
661 static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data)
662 {
663 DeviceClass *dc = DEVICE_CLASS(oc);
664
665 device_class_set_props(dc, xlnx_zynqmp_props);
666 dc->realize = xlnx_zynqmp_realize;
667 /* Reason: Uses serial_hds in realize function, thus can't be used twice */
668 dc->user_creatable = false;
669 }
670
671 static const TypeInfo xlnx_zynqmp_type_info = {
672 .name = TYPE_XLNX_ZYNQMP,
673 .parent = TYPE_DEVICE,
674 .instance_size = sizeof(XlnxZynqMPState),
675 .instance_init = xlnx_zynqmp_init,
676 .class_init = xlnx_zynqmp_class_init,
677 };
678
679 static void xlnx_zynqmp_register_types(void)
680 {
681 type_register_static(&xlnx_zynqmp_type_info);
682 }
683
684 type_init(xlnx_zynqmp_register_types)
AR7 emulation for QEMU